lib/librte_pmd_e1000/e1000/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  60                                            u16 *data);
  61 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  62 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  63 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  64                                      u32 offset, u16 *data);
  65 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  66                                       u32 offset, u16 data);
  67 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  68                                           bool active);
  69 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  72                                           bool active);
  73 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  74 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  78 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  79                                             u32 offset, u16 data);
  80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  81 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  82 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  83                                                  u16 *speed, u16 *duplex);
  84 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  87 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  98                                                  u16 offset);
  99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                    u16 offset);
 101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 105
 106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 117
 118 STATIC const u16 e1000_82580_rxpbs_table[] = {
 119         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 120 #define E1000_82580_RXPBS_TABLE_SIZE \
 121         (sizeof(e1000_82580_rxpbs_table) / \
 122          sizeof(e1000_82580_rxpbs_table[0]))
 123
 124
 125 /**
 126  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 127  *  @hw: pointer to the HW structure
 128  *
 129  *  Called to determine if the I2C pins are being used for I2C or as an
 130  *  external MDIO interface since the two options are mutually exclusive.
 131  **/
 132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 133 {
 134         u32 reg = 0;
 135         bool ext_mdio = false;
 136
 137         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 138
 139         switch (hw->mac.type) {
 140         case e1000_82575:
 141         case e1000_82576:
 142                 reg = E1000_READ_REG(hw, E1000_MDIC);
 143                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 144                 break;
 145         case e1000_82580:
 146         case e1000_i350:
 147         case e1000_i354:
 148         case e1000_i210:
 149         case e1000_i211:
 150                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 151                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 152                 break;
 153         default:
 154                 break;
 155         }
 156         return ext_mdio;
 157 }
 158
 159 /**
 160  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 161  *  @hw: pointer to the HW structure
 162  **/
 163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 164 {
 165         struct e1000_phy_info *phy = &hw->phy;
 166         s32 ret_val = E1000_SUCCESS;
 167         u32 ctrl_ext;
 168
 169         DEBUGFUNC("e1000_init_phy_params_82575");
 170
 171         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 172         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 173
 174         if (hw->phy.media_type != e1000_media_type_copper) {
 175                 phy->type = e1000_phy_none;
 176                 goto out;
 177         }
 178
 179         phy->ops.power_up   = e1000_power_up_phy_copper;
 180         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 181
 182         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 183         phy->reset_delay_us     = 100;
 184
 185         phy->ops.acquire        = e1000_acquire_phy_82575;
 186         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 187         phy->ops.commit         = e1000_phy_sw_reset_generic;
 188         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 189         phy->ops.release        = e1000_release_phy_82575;
 190
 191         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 192
 193         if (e1000_sgmii_active_82575(hw)) {
 194                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 195                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 196         } else {
 197                 phy->ops.reset = e1000_phy_hw_reset_generic;
 198                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 199         }
 200
 201         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 202         e1000_reset_mdicnfg_82580(hw);
 203
 204         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 205                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 206                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 207         } else {
 208                 switch (hw->mac.type) {
 209                 case e1000_82580:
 210                 case e1000_i350:
 211                 case e1000_i354:
 212                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 213                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 214                         break;
 215                 case e1000_i210:
 216                 case e1000_i211:
 217                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 218                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 219                         break;
 220                 default:
 221                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 222                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 223                 }
 224         }
 225
 226         /* Set phy->phy_addr and phy->id. */
 227         ret_val = e1000_get_phy_id_82575(hw);
 228
 229         /* Verify phy id and set remaining function pointers */
 230         switch (phy->id) {
 231         case M88E1543_E_PHY_ID:
 232         case M88E1512_E_PHY_ID:
 233         case I347AT4_E_PHY_ID:
 234         case M88E1112_E_PHY_ID:
 235         case M88E1340M_E_PHY_ID:
 236         case M88E1111_I_PHY_ID:
 237                 phy->type               = e1000_phy_m88;
 238                 phy->ops.check_polarity = e1000_check_polarity_m88;
 239                 phy->ops.get_info       = e1000_get_phy_info_m88;
 240                 if (phy->id == I347AT4_E_PHY_ID ||
 241                     phy->id == M88E1112_E_PHY_ID ||
 242                     phy->id == M88E1340M_E_PHY_ID)
 243                         phy->ops.get_cable_length =
 244                                          e1000_get_cable_length_m88_gen2;
 245                 else if (phy->id == M88E1543_E_PHY_ID ||
 246                          phy->id == M88E1512_E_PHY_ID)
 247                         phy->ops.get_cable_length =
 248                                          e1000_get_cable_length_m88_gen2;
 249                 else
 250                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 251                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 252                 /* Check if this PHY is confgured for media swap. */
 253                 if (phy->id == M88E1112_E_PHY_ID) {
 254                         u16 data;
 255
 256                         ret_val = phy->ops.write_reg(hw,
 257                                                      E1000_M88E1112_PAGE_ADDR,
 258                                                      2);
 259                         if (ret_val)
 260                                 goto out;
 261
 262                         ret_val = phy->ops.read_reg(hw,
 263                                                     E1000_M88E1112_MAC_CTRL_1,
 264                                                     &data);
 265                         if (ret_val)
 266                                 goto out;
 267
 268                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 269                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 270                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 271                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 272                                 hw->mac.ops.check_for_link =
 273                                                 e1000_check_for_link_media_swap;
 274                 }
 275                 break;
 276         case IGP03E1000_E_PHY_ID:
 277         case IGP04E1000_E_PHY_ID:
 278                 phy->type = e1000_phy_igp_3;
 279                 phy->ops.check_polarity = e1000_check_polarity_igp;
 280                 phy->ops.get_info = e1000_get_phy_info_igp;
 281                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 282                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 283                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 284                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 285                 break;
 286         case I82580_I_PHY_ID:
 287         case I350_I_PHY_ID:
 288                 phy->type = e1000_phy_82580;
 289                 phy->ops.check_polarity = e1000_check_polarity_82577;
 290                 phy->ops.force_speed_duplex =
 291                                          e1000_phy_force_speed_duplex_82577;
 292                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 293                 phy->ops.get_info = e1000_get_phy_info_82577;
 294                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 295                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 296                 break;
 297         case I210_I_PHY_ID:
 298                 phy->type               = e1000_phy_i210;
 299                 phy->ops.check_polarity = e1000_check_polarity_m88;
 300                 phy->ops.get_info       = e1000_get_phy_info_m88;
 301                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 302                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 303                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 304                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 305                 break;
 306         default:
 307                 ret_val = -E1000_ERR_PHY;
 308                 goto out;
 309         }
 310
 311 out:
 312         return ret_val;
 313 }
 314
 315 /**
 316  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 317  *  @hw: pointer to the HW structure
 318  **/
 319 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 320 {
 321         struct e1000_nvm_info *nvm = &hw->nvm;
 322         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 323         u16 size;
 324
 325         DEBUGFUNC("e1000_init_nvm_params_82575");
 326
 327         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 328                      E1000_EECD_SIZE_EX_SHIFT);
 329         /*
 330          * Added to a constant, "size" becomes the left-shift value
 331          * for setting word_size.
 332          */
 333         size += NVM_WORD_SIZE_BASE_SHIFT;
 334
 335         /* Just in case size is out of range, cap it to the largest
 336          * EEPROM size supported
 337          */
 338         if (size > 15)
 339                 size = 15;
 340
 341         nvm->word_size = 1 << size;
 342         if (hw->mac.type < e1000_i210) {
 343                 nvm->opcode_bits = 8;
 344                 nvm->delay_usec = 1;
 345
 346                 switch (nvm->override) {
 347                 case e1000_nvm_override_spi_large:
 348                         nvm->page_size = 32;
 349                         nvm->address_bits = 16;
 350                         break;
 351                 case e1000_nvm_override_spi_small:
 352                         nvm->page_size = 8;
 353                         nvm->address_bits = 8;
 354                         break;
 355                 default:
 356                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 357                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 358                                             16 : 8;
 359                         break;
 360                 }
 361                 if (nvm->word_size == (1 << 15))
 362                         nvm->page_size = 128;
 363
 364                 nvm->type = e1000_nvm_eeprom_spi;
 365         } else {
 366                 nvm->type = e1000_nvm_flash_hw;
 367         }
 368
 369         /* Function Pointers */
 370         nvm->ops.acquire = e1000_acquire_nvm_82575;
 371         nvm->ops.release = e1000_release_nvm_82575;
 372         if (nvm->word_size < (1 << 15))
 373                 nvm->ops.read = e1000_read_nvm_eerd;
 374         else
 375                 nvm->ops.read = e1000_read_nvm_spi;
 376
 377         nvm->ops.write = e1000_write_nvm_spi;
 378         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 379         nvm->ops.update = e1000_update_nvm_checksum_generic;
 380         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 381
 382         /* override generic family function pointers for specific descendants */
 383         switch (hw->mac.type) {
 384         case e1000_82580:
 385                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 386                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 387                 break;
 388         case e1000_i350:
 389         case e1000_i354:
 390                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 391                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 392                 break;
 393         default:
 394                 break;
 395         }
 396
 397         return E1000_SUCCESS;
 398 }
 399
 400 /**
 401  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 402  *  @hw: pointer to the HW structure
 403  **/
 404 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 405 {
 406         struct e1000_mac_info *mac = &hw->mac;
 407         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 408
 409         DEBUGFUNC("e1000_init_mac_params_82575");
 410
 411         /* Derives media type */
 412         e1000_get_media_type_82575(hw);
 413         /* Set mta register count */
 414         mac->mta_reg_count = 128;
 415         /* Set uta register count */
 416         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 417         /* Set rar entry count */
 418         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 419         if (mac->type == e1000_82576)
 420                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 421         if (mac->type == e1000_82580)
 422                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 423         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 424                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 425
 426         /* Enable EEE default settings for EEE supported devices */
 427         if (mac->type >= e1000_i350)
 428                 dev_spec->eee_disable = false;
 429
 430         /* Allow a single clear of the SW semaphore on I210 and newer */
 431         if (mac->type >= e1000_i210)
 432                 dev_spec->clear_semaphore_once = true;
 433
 434         /* Set if part includes ASF firmware */
 435         mac->asf_firmware_present = true;
 436         /* FWSM register */
 437         mac->has_fwsm = true;
 438         /* ARC supported; valid only if manageability features are enabled. */
 439         mac->arc_subsystem_valid =
 440                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 441
 442         /* Function pointers */
 443
 444         /* bus type/speed/width */
 445         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 446         /* reset */
 447         if (mac->type >= e1000_82580)
 448                 mac->ops.reset_hw = e1000_reset_hw_82580;
 449         else
 450         mac->ops.reset_hw = e1000_reset_hw_82575;
 451         /* hw initialization */
 452         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 453                 mac->ops.init_hw = e1000_init_hw_i210;
 454         else
 455         mac->ops.init_hw = e1000_init_hw_82575;
 456         /* link setup */
 457         mac->ops.setup_link = e1000_setup_link_generic;
 458         /* physical interface link setup */
 459         mac->ops.setup_physical_interface =
 460                 (hw->phy.media_type == e1000_media_type_copper)
 461                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 462         /* physical interface shutdown */
 463         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 464         /* physical interface power up */
 465         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 466         /* check for link */
 467         mac->ops.check_for_link = e1000_check_for_link_82575;
 468         /* read mac address */
 469         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 470         /* configure collision distance */
 471         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 472         /* multicast address update */
 473         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 474         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 475                 /* writing VFTA */
 476                 mac->ops.write_vfta = e1000_write_vfta_i350;
 477                 /* clearing VFTA */
 478                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 479         } else {
 480                 /* writing VFTA */
 481                 mac->ops.write_vfta = e1000_write_vfta_generic;
 482                 /* clearing VFTA */
 483                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 484         }
 485         if (hw->mac.type >= e1000_82580)
 486                 mac->ops.validate_mdi_setting =
 487                                 e1000_validate_mdi_setting_crossover_generic;
 488         /* ID LED init */
 489         mac->ops.id_led_init = e1000_id_led_init_generic;
 490         /* blink LED */
 491         mac->ops.blink_led = e1000_blink_led_generic;
 492         /* setup LED */
 493         mac->ops.setup_led = e1000_setup_led_generic;
 494         /* cleanup LED */
 495         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 496         /* turn on/off LED */
 497         mac->ops.led_on = e1000_led_on_generic;
 498         mac->ops.led_off = e1000_led_off_generic;
 499         /* clear hardware counters */
 500         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 501         /* link info */
 502         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 503         /* acquire SW_FW sync */
 504         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 505         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 506         if (mac->type >= e1000_i210) {
 507                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 508                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 509         }
 510
 511         /* set lan id for port to determine which phy lock to use */
 512         hw->mac.ops.set_lan_id(hw);
 513
 514         return E1000_SUCCESS;
 515 }
 516
 517 /**
 518  *  e1000_init_function_pointers_82575 - Init func ptrs.
 519  *  @hw: pointer to the HW structure
 520  *
 521  *  Called to initialize all function pointers and parameters.
 522  **/
 523 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 524 {
 525         DEBUGFUNC("e1000_init_function_pointers_82575");
 526
 527         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 528         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 529         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 530         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 531 }
 532
 533 /**
 534  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 535  *  @hw: pointer to the HW structure
 536  *
 537  *  Acquire access rights to the correct PHY.
 538  **/
 539 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 540 {
 541         u16 mask = E1000_SWFW_PHY0_SM;
 542
 543         DEBUGFUNC("e1000_acquire_phy_82575");
 544
 545         if (hw->bus.func == E1000_FUNC_1)
 546                 mask = E1000_SWFW_PHY1_SM;
 547         else if (hw->bus.func == E1000_FUNC_2)
 548                 mask = E1000_SWFW_PHY2_SM;
 549         else if (hw->bus.func == E1000_FUNC_3)
 550                 mask = E1000_SWFW_PHY3_SM;
 551
 552         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 553 }
 554
 555 /**
 556  *  e1000_release_phy_82575 - Release rights to access PHY
 557  *  @hw: pointer to the HW structure
 558  *
 559  *  A wrapper to release access rights to the correct PHY.
 560  **/
 561 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 562 {
 563         u16 mask = E1000_SWFW_PHY0_SM;
 564
 565         DEBUGFUNC("e1000_release_phy_82575");
 566
 567         if (hw->bus.func == E1000_FUNC_1)
 568                 mask = E1000_SWFW_PHY1_SM;
 569         else if (hw->bus.func == E1000_FUNC_2)
 570                 mask = E1000_SWFW_PHY2_SM;
 571         else if (hw->bus.func == E1000_FUNC_3)
 572                 mask = E1000_SWFW_PHY3_SM;
 573
 574         hw->mac.ops.release_swfw_sync(hw, mask);
 575 }
 576
 577 /**
 578  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 579  *  @hw: pointer to the HW structure
 580  *  @offset: register offset to be read
 581  *  @data: pointer to the read data
 582  *
 583  *  Reads the PHY register at offset using the serial gigabit media independent
 584  *  interface and stores the retrieved information in data.
 585  **/
 586 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 587                                           u16 *data)
 588 {
 589         s32 ret_val = -E1000_ERR_PARAM;
 590
 591         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 592
 593         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 594                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 595                 goto out;
 596         }
 597
 598         ret_val = hw->phy.ops.acquire(hw);
 599         if (ret_val)
 600                 goto out;
 601
 602         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 603
 604         hw->phy.ops.release(hw);
 605
 606 out:
 607         return ret_val;
 608 }
 609
 610 /**
 611  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 612  *  @hw: pointer to the HW structure
 613  *  @offset: register offset to write to
 614  *  @data: data to write at register offset
 615  *
 616  *  Writes the data to PHY register at the offset using the serial gigabit
 617  *  media independent interface.
 618  **/
 619 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 620                                            u16 data)
 621 {
 622         s32 ret_val = -E1000_ERR_PARAM;
 623
 624         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 625
 626         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 627                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 628                 goto out;
 629         }
 630
 631         ret_val = hw->phy.ops.acquire(hw);
 632         if (ret_val)
 633                 goto out;
 634
 635         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 636
 637         hw->phy.ops.release(hw);
 638
 639 out:
 640         return ret_val;
 641 }
 642
 643 /**
 644  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 645  *  @hw: pointer to the HW structure
 646  *
 647  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 648  *  sgmi interface.
 649  **/
 650 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 651 {
 652         struct e1000_phy_info *phy = &hw->phy;
 653         s32  ret_val = E1000_SUCCESS;
 654         u16 phy_id;
 655         u32 ctrl_ext;
 656         u32 mdic;
 657
 658         DEBUGFUNC("e1000_get_phy_id_82575");
 659
 660         /* some i354 devices need an extra read for phy id */
 661         if (hw->mac.type == e1000_i354)
 662                 e1000_get_phy_id(hw);
 663
 664         /*
 665          * For SGMII PHYs, we try the list of possible addresses until
 666          * we find one that works.  For non-SGMII PHYs
 667          * (e.g. integrated copper PHYs), an address of 1 should
 668          * work.  The result of this function should mean phy->phy_addr
 669          * and phy->id are set correctly.
 670          */
 671         if (!e1000_sgmii_active_82575(hw)) {
 672                 phy->addr = 1;
 673                 ret_val = e1000_get_phy_id(hw);
 674                 goto out;
 675         }
 676
 677         if (e1000_sgmii_uses_mdio_82575(hw)) {
 678                 switch (hw->mac.type) {
 679                 case e1000_82575:
 680                 case e1000_82576:
 681                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 682                         mdic &= E1000_MDIC_PHY_MASK;
 683                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 684                         break;
 685                 case e1000_82580:
 686                 case e1000_i350:
 687                 case e1000_i354:
 688                 case e1000_i210:
 689                 case e1000_i211:
 690                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 691                         mdic &= E1000_MDICNFG_PHY_MASK;
 692                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 693                         break;
 694                 default:
 695                         ret_val = -E1000_ERR_PHY;
 696                         goto out;
 697                         break;
 698                 }
 699                 ret_val = e1000_get_phy_id(hw);
 700                 goto out;
 701         }
 702
 703         /* Power on sgmii phy if it is disabled */
 704         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 705         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 706                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 707         E1000_WRITE_FLUSH(hw);
 708         msec_delay(300);
 709
 710         /*
 711          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 712          * Therefore, we need to test 1-7
 713          */
 714         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 715                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 716                 if (ret_val == E1000_SUCCESS) {
 717                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 718                                   phy_id, phy->addr);
 719                         /*
 720                          * At the time of this writing, The M88 part is
 721                          * the only supported SGMII PHY product.
 722                          */
 723                         if (phy_id == M88_VENDOR)
 724                                 break;
 725                 } else {
 726                         DEBUGOUT1("PHY address %u was unreadable\n",
 727                                   phy->addr);
 728                 }
 729         }
 730
 731         /* A valid PHY type couldn't be found. */
 732         if (phy->addr == 8) {
 733                 phy->addr = 0;
 734                 ret_val = -E1000_ERR_PHY;
 735         } else {
 736                 ret_val = e1000_get_phy_id(hw);
 737         }
 738
 739         /* restore previous sfp cage power state */
 740         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 741
 742 out:
 743         return ret_val;
 744 }
 745
 746 /**
 747  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 748  *  @hw: pointer to the HW structure
 749  *
 750  *  Resets the PHY using the serial gigabit media independent interface.
 751  **/
 752 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 753 {
 754         s32 ret_val = E1000_SUCCESS;
 755
 756         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 757
 758         /*
 759          * This isn't a true "hard" reset, but is the only reset
 760          * available to us at this time.
 761          */
 762
 763         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 764
 765         if (!(hw->phy.ops.write_reg))
 766                 goto out;
 767
 768         /*
 769          * SFP documentation requires the following to configure the SPF module
 770          * to work on SGMII.  No further documentation is given.
 771          */
 772         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 773         if (ret_val)
 774                 goto out;
 775
 776         ret_val = hw->phy.ops.commit(hw);
 777
 778 out:
 779         return ret_val;
 780 }
 781
 782 /**
 783  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 784  *  @hw: pointer to the HW structure
 785  *  @active: true to enable LPLU, false to disable
 786  *
 787  *  Sets the LPLU D0 state according to the active flag.  When
 788  *  activating LPLU this function also disables smart speed
 789  *  and vice versa.  LPLU will not be activated unless the
 790  *  device autonegotiation advertisement meets standards of
 791  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 792  *  This is a function pointer entry point only called by
 793  *  PHY setup routines.
 794  **/
 795 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 796 {
 797         struct e1000_phy_info *phy = &hw->phy;
 798         s32 ret_val = E1000_SUCCESS;
 799         u16 data;
 800
 801         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 802
 803         if (!(hw->phy.ops.read_reg))
 804                 goto out;
 805
 806         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 807         if (ret_val)
 808                 goto out;
 809
 810         if (active) {
 811                 data |= IGP02E1000_PM_D0_LPLU;
 812                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 813                                              data);
 814                 if (ret_val)
 815                         goto out;
 816
 817                 /* When LPLU is enabled, we should disable SmartSpeed */
 818                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 819                                             &data);
 820                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 821                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 822                                              data);
 823                 if (ret_val)
 824                         goto out;
 825         } else {
 826                 data &= ~IGP02E1000_PM_D0_LPLU;
 827                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 828                                              data);
 829                 /*
 830                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 831                  * during Dx states where the power conservation is most
 832                  * important.  During driver activity we should enable
 833                  * SmartSpeed, so performance is maintained.
 834                  */
 835                 if (phy->smart_speed == e1000_smart_speed_on) {
 836                         ret_val = phy->ops.read_reg(hw,
 837                                                     IGP01E1000_PHY_PORT_CONFIG,
 838                                                     &data);
 839                         if (ret_val)
 840                                 goto out;
 841
 842                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 843                         ret_val = phy->ops.write_reg(hw,
 844                                                      IGP01E1000_PHY_PORT_CONFIG,
 845                                                      data);
 846                         if (ret_val)
 847                                 goto out;
 848                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 849                         ret_val = phy->ops.read_reg(hw,
 850                                                     IGP01E1000_PHY_PORT_CONFIG,
 851                                                     &data);
 852                         if (ret_val)
 853                                 goto out;
 854
 855                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 856                         ret_val = phy->ops.write_reg(hw,
 857                                                      IGP01E1000_PHY_PORT_CONFIG,
 858                                                      data);
 859                         if (ret_val)
 860                                 goto out;
 861                 }
 862         }
 863
 864 out:
 865         return ret_val;
 866 }
 867
 868 /**
 869  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 870  *  @hw: pointer to the HW structure
 871  *  @active: true to enable LPLU, false to disable
 872  *
 873  *  Sets the LPLU D0 state according to the active flag.  When
 874  *  activating LPLU this function also disables smart speed
 875  *  and vice versa.  LPLU will not be activated unless the
 876  *  device autonegotiation advertisement meets standards of
 877  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 878  *  This is a function pointer entry point only called by
 879  *  PHY setup routines.
 880  **/
 881 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 882 {
 883         struct e1000_phy_info *phy = &hw->phy;
 884         s32 ret_val = E1000_SUCCESS;
 885         u32 data;
 886
 887         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 888
 889         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 890
 891         if (active) {
 892                 data |= E1000_82580_PM_D0_LPLU;
 893
 894                 /* When LPLU is enabled, we should disable SmartSpeed */
 895                 data &= ~E1000_82580_PM_SPD;
 896         } else {
 897                 data &= ~E1000_82580_PM_D0_LPLU;
 898
 899                 /*
 900                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 901                  * during Dx states where the power conservation is most
 902                  * important.  During driver activity we should enable
 903                  * SmartSpeed, so performance is maintained.
 904                  */
 905                 if (phy->smart_speed == e1000_smart_speed_on)
 906                         data |= E1000_82580_PM_SPD;
 907                 else if (phy->smart_speed == e1000_smart_speed_off)
 908                         data &= ~E1000_82580_PM_SPD;
 909         }
 910
 911         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 912         return ret_val;
 913 }
 914
 915 /**
 916  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 917  *  @hw: pointer to the HW structure
 918  *  @active: boolean used to enable/disable lplu
 919  *
 920  *  Success returns 0, Failure returns 1
 921  *
 922  *  The low power link up (lplu) state is set to the power management level D3
 923  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 924  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 925  *  is used during Dx states where the power conservation is most important.
 926  *  During driver activity, SmartSpeed should be enabled so performance is
 927  *  maintained.
 928  **/
 929 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 930 {
 931         struct e1000_phy_info *phy = &hw->phy;
 932         s32 ret_val = E1000_SUCCESS;
 933         u32 data;
 934
 935         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 936
 937         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 938
 939         if (!active) {
 940                 data &= ~E1000_82580_PM_D3_LPLU;
 941                 /*
 942                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 943                  * during Dx states where the power conservation is most
 944                  * important.  During driver activity we should enable
 945                  * SmartSpeed, so performance is maintained.
 946                  */
 947                 if (phy->smart_speed == e1000_smart_speed_on)
 948                         data |= E1000_82580_PM_SPD;
 949                 else if (phy->smart_speed == e1000_smart_speed_off)
 950                         data &= ~E1000_82580_PM_SPD;
 951         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 952                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 953                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 954                 data |= E1000_82580_PM_D3_LPLU;
 955                 /* When LPLU is enabled, we should disable SmartSpeed */
 956                 data &= ~E1000_82580_PM_SPD;
 957         }
 958
 959         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 960         return ret_val;
 961 }
 962
 963 /**
 964  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 965  *  @hw: pointer to the HW structure
 966  *
 967  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 968  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 969  *  Return successful if access grant bit set, else clear the request for
 970  *  EEPROM access and return -E1000_ERR_NVM (-1).
 971  **/
 972 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 973 {
 974         s32 ret_val;
 975
 976         DEBUGFUNC("e1000_acquire_nvm_82575");
 977
 978         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 979         if (ret_val)
 980                 goto out;
 981
 982         /*
 983          * Check if there is some access
 984          * error this access may hook on
 985          */
 986         if (hw->mac.type == e1000_i350) {
 987                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 988                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 989                     E1000_EECD_TIMEOUT)) {
 990                         /* Clear all access error flags */
 991                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 992                                         E1000_EECD_ERROR_CLR);
 993                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 994                 }
 995         }
 996         if (hw->mac.type == e1000_82580) {
 997                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 998                 if (eecd & E1000_EECD_BLOCKED) {
 999                         /* Clear access error flag */
1000                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1001                                         E1000_EECD_BLOCKED);
1002                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1003                 }
1004         }
1005
1006
1007         ret_val = e1000_acquire_nvm_generic(hw);
1008         if (ret_val)
1009                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1010
1011 out:
1012         return ret_val;
1013 }
1014
1015 /**
1016  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1017  *  @hw: pointer to the HW structure
1018  *
1019  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1020  *  then release the semaphores acquired.
1021  **/
1022 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1023 {
1024         DEBUGFUNC("e1000_release_nvm_82575");
1025
1026         e1000_release_nvm_generic(hw);
1027
1028         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1029 }
1030
1031 /**
1032  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1033  *  @hw: pointer to the HW structure
1034  *  @mask: specifies which semaphore to acquire
1035  *
1036  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1037  *  will also specify which port we're acquiring the lock for.
1038  **/
1039 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1040 {
1041         u32 swfw_sync;
1042         u32 swmask = mask;
1043         u32 fwmask = mask << 16;
1044         s32 ret_val = E1000_SUCCESS;
1045         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1046
1047         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1048
1049         while (i < timeout) {
1050                 if (e1000_get_hw_semaphore_generic(hw)) {
1051                         ret_val = -E1000_ERR_SWFW_SYNC;
1052                         goto out;
1053                 }
1054
1055                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1056                 if (!(swfw_sync & (fwmask | swmask)))
1057                         break;
1058
1059                 /*
1060                  * Firmware currently using resource (fwmask)
1061                  * or other software thread using resource (swmask)
1062                  */
1063                 e1000_put_hw_semaphore_generic(hw);
1064                 msec_delay_irq(5);
1065                 i++;
1066         }
1067
1068         if (i == timeout) {
1069                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1070                 ret_val = -E1000_ERR_SWFW_SYNC;
1071                 goto out;
1072         }
1073
1074         swfw_sync |= swmask;
1075         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1076
1077         e1000_put_hw_semaphore_generic(hw);
1078
1079 out:
1080         return ret_val;
1081 }
1082
1083 /**
1084  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1085  *  @hw: pointer to the HW structure
1086  *  @mask: specifies which semaphore to acquire
1087  *
1088  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1089  *  will also specify which port we're releasing the lock for.
1090  **/
1091 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1092 {
1093         u32 swfw_sync;
1094
1095         DEBUGFUNC("e1000_release_swfw_sync_82575");
1096
1097         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1098                 ; /* Empty */
1099
1100         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1101         swfw_sync &= ~mask;
1102         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1103
1104         e1000_put_hw_semaphore_generic(hw);
1105 }
1106
1107 /**
1108  *  e1000_get_cfg_done_82575 - Read config done bit
1109  *  @hw: pointer to the HW structure
1110  *
1111  *  Read the management control register for the config done bit for
1112  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1113  *  to read the config done bit, so an error is *ONLY* logged and returns
1114  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1115  *  would not be able to be reset or change link.
1116  **/
1117 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1118 {
1119         s32 timeout = PHY_CFG_TIMEOUT;
1120         s32 ret_val = E1000_SUCCESS;
1121         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1122
1123         DEBUGFUNC("e1000_get_cfg_done_82575");
1124
1125         if (hw->bus.func == E1000_FUNC_1)
1126                 mask = E1000_NVM_CFG_DONE_PORT_1;
1127         else if (hw->bus.func == E1000_FUNC_2)
1128                 mask = E1000_NVM_CFG_DONE_PORT_2;
1129         else if (hw->bus.func == E1000_FUNC_3)
1130                 mask = E1000_NVM_CFG_DONE_PORT_3;
1131         while (timeout) {
1132                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1133                         break;
1134                 msec_delay(1);
1135                 timeout--;
1136         }
1137         if (!timeout)
1138                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1139
1140         /* If EEPROM is not marked present, init the PHY manually */
1141         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1142             (hw->phy.type == e1000_phy_igp_3))
1143                 e1000_phy_init_script_igp3(hw);
1144
1145         return ret_val;
1146 }
1147
1148 /**
1149  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1150  *  @hw: pointer to the HW structure
1151  *  @speed: stores the current speed
1152  *  @duplex: stores the current duplex
1153  *
1154  *  This is a wrapper function, if using the serial gigabit media independent
1155  *  interface, use PCS to retrieve the link speed and duplex information.
1156  *  Otherwise, use the generic function to get the link speed and duplex info.
1157  **/
1158 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1159                                         u16 *duplex)
1160 {
1161         s32 ret_val;
1162
1163         DEBUGFUNC("e1000_get_link_up_info_82575");
1164
1165         if (hw->phy.media_type != e1000_media_type_copper)
1166                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1167                                                                duplex);
1168         else
1169                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1170                                                                     duplex);
1171
1172         return ret_val;
1173 }
1174
1175 /**
1176  *  e1000_check_for_link_82575 - Check for link
1177  *  @hw: pointer to the HW structure
1178  *
1179  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1180  *  use the generic interface for determining link.
1181  **/
1182 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1183 {
1184         s32 ret_val;
1185         u16 speed, duplex;
1186
1187         DEBUGFUNC("e1000_check_for_link_82575");
1188
1189         if (hw->phy.media_type != e1000_media_type_copper) {
1190                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1191                                                                &duplex);
1192                 /*
1193                  * Use this flag to determine if link needs to be checked or
1194                  * not.  If we have link clear the flag so that we do not
1195                  * continue to check for link.
1196                  */
1197                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1198
1199                 /*
1200                  * Configure Flow Control now that Auto-Neg has completed.
1201                  * First, we need to restore the desired flow control
1202                  * settings because we may have had to re-autoneg with a
1203                  * different link partner.
1204                  */
1205                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1206                 if (ret_val)
1207                         DEBUGOUT("Error configuring flow control\n");
1208         } else {
1209                 ret_val = e1000_check_for_copper_link_generic(hw);
1210         }
1211
1212         return ret_val;
1213 }
1214
1215 /**
1216  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1217  *  @hw: pointer to the HW structure
1218  *
1219  *  Poll the M88E1112 interfaces to see which interface achieved link.
1220  */
1221 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1222 {
1223         struct e1000_phy_info *phy = &hw->phy;
1224         s32 ret_val;
1225         u16 data;
1226         u8 port = 0;
1227
1228         DEBUGFUNC("e1000_check_for_link_media_swap");
1229
1230         /* Check the copper medium. */
1231         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1232         if (ret_val)
1233                 return ret_val;
1234
1235         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1236         if (ret_val)
1237                 return ret_val;
1238
1239         if (data & E1000_M88E1112_STATUS_LINK)
1240                 port = E1000_MEDIA_PORT_COPPER;
1241
1242         /* Check the other medium. */
1243         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1244         if (ret_val)
1245                 return ret_val;
1246
1247         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1248         if (ret_val)
1249                 return ret_val;
1250
1251         /* reset page to 0 */
1252         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1253         if (ret_val)
1254                 return ret_val;
1255
1256         if (data & E1000_M88E1112_STATUS_LINK)
1257                 port = E1000_MEDIA_PORT_OTHER;
1258
1259         /* Determine if a swap needs to happen. */
1260         if (port && (hw->dev_spec._82575.media_port != port)) {
1261                 hw->dev_spec._82575.media_port = port;
1262                 hw->dev_spec._82575.media_changed = true;
1263         } else {
1264                 ret_val = e1000_check_for_link_82575(hw);
1265         }
1266
1267         return E1000_SUCCESS;
1268 }
1269
1270 /**
1271  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1272  *  @hw: pointer to the HW structure
1273  **/
1274 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1275 {
1276         u32 reg;
1277
1278         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1279
1280         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1281             !e1000_sgmii_active_82575(hw))
1282                 return;
1283
1284         /* Enable PCS to turn on link */
1285         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1286         reg |= E1000_PCS_CFG_PCS_EN;
1287         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1288
1289         /* Power up the laser */
1290         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1291         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1292         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1293
1294         /* flush the write to verify completion */
1295         E1000_WRITE_FLUSH(hw);
1296         msec_delay(1);
1297 }
1298
1299 /**
1300  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1301  *  @hw: pointer to the HW structure
1302  *  @speed: stores the current speed
1303  *  @duplex: stores the current duplex
1304  *
1305  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1306  *  duplex, then store the values in the pointers provided.
1307  **/
1308 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1309                                                 u16 *speed, u16 *duplex)
1310 {
1311         struct e1000_mac_info *mac = &hw->mac;
1312         u32 pcs;
1313         u32 status;
1314
1315         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1316
1317         /*
1318          * Read the PCS Status register for link state. For non-copper mode,
1319          * the status register is not accurate. The PCS status register is
1320          * used instead.
1321          */
1322         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1323
1324         /*
1325          * The link up bit determines when link is up on autoneg.
1326          */
1327         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1328                 mac->serdes_has_link = true;
1329
1330                 /* Detect and store PCS speed */
1331                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1332                         *speed = SPEED_1000;
1333                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1334                         *speed = SPEED_100;
1335                 else
1336                         *speed = SPEED_10;
1337
1338                 /* Detect and store PCS duplex */
1339                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1340                         *duplex = FULL_DUPLEX;
1341                 else
1342                         *duplex = HALF_DUPLEX;
1343
1344                 /* Check if it is an I354 2.5Gb backplane connection. */
1345                 if (mac->type == e1000_i354) {
1346                         status = E1000_READ_REG(hw, E1000_STATUS);
1347                         if ((status & E1000_STATUS_2P5_SKU) &&
1348                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1349                                 *speed = SPEED_2500;
1350                                 *duplex = FULL_DUPLEX;
1351                                 DEBUGOUT("2500 Mbs, ");
1352                                 DEBUGOUT("Full Duplex\n");
1353                         }
1354                 }
1355
1356         } else {
1357                 mac->serdes_has_link = false;
1358                 *speed = 0;
1359                 *duplex = 0;
1360         }
1361
1362         return E1000_SUCCESS;
1363 }
1364
1365 /**
1366  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1367  *  @hw: pointer to the HW structure
1368  *
1369  *  In the case of serdes shut down sfp and PCS on driver unload
1370  *  when management pass thru is not enabled.
1371  **/
1372 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1373 {
1374         u32 reg;
1375
1376         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1377
1378         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1379             !e1000_sgmii_active_82575(hw))
1380                 return;
1381
1382         if (!e1000_enable_mng_pass_thru(hw)) {
1383                 /* Disable PCS to turn off link */
1384                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1385                 reg &= ~E1000_PCS_CFG_PCS_EN;
1386                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1387
1388                 /* shutdown the laser */
1389                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1390                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1391                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1392
1393                 /* flush the write to verify completion */
1394                 E1000_WRITE_FLUSH(hw);
1395                 msec_delay(1);
1396         }
1397
1398         return;
1399 }
1400
1401 /**
1402  *  e1000_reset_hw_82575 - Reset hardware
1403  *  @hw: pointer to the HW structure
1404  *
1405  *  This resets the hardware into a known state.
1406  **/
1407 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1408 {
1409         u32 ctrl;
1410         s32 ret_val;
1411
1412         DEBUGFUNC("e1000_reset_hw_82575");
1413
1414         /*
1415          * Prevent the PCI-E bus from sticking if there is no TLP connection
1416          * on the last TLP read/write transaction when MAC is reset.
1417          */
1418         ret_val = e1000_disable_pcie_master_generic(hw);
1419         if (ret_val)
1420                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1421
1422         /* set the completion timeout for interface */
1423         ret_val = e1000_set_pcie_completion_timeout(hw);
1424         if (ret_val)
1425                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1426
1427         DEBUGOUT("Masking off all interrupts\n");
1428         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1429
1430         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1431         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1432         E1000_WRITE_FLUSH(hw);
1433
1434         msec_delay(10);
1435
1436         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1437
1438         DEBUGOUT("Issuing a global reset to MAC\n");
1439         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1440
1441         ret_val = e1000_get_auto_rd_done_generic(hw);
1442         if (ret_val) {
1443                 /*
1444                  * When auto config read does not complete, do not
1445                  * return with an error. This can happen in situations
1446                  * where there is no eeprom and prevents getting link.
1447                  */
1448                 DEBUGOUT("Auto Read Done did not complete\n");
1449         }
1450
1451         /* If EEPROM is not present, run manual init scripts */
1452         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1453                 e1000_reset_init_script_82575(hw);
1454
1455         /* Clear any pending interrupt events. */
1456         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1457         E1000_READ_REG(hw, E1000_ICR);
1458
1459         /* Install any alternate MAC address into RAR0 */
1460         ret_val = e1000_check_alt_mac_addr_generic(hw);
1461
1462         return ret_val;
1463 }
1464
1465 /**
1466  *  e1000_init_hw_82575 - Initialize hardware
1467  *  @hw: pointer to the HW structure
1468  *
1469  *  This inits the hardware readying it for operation.
1470  **/
1471 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1472 {
1473         struct e1000_mac_info *mac = &hw->mac;
1474         s32 ret_val;
1475         u16 i, rar_count = mac->rar_entry_count;
1476
1477         DEBUGFUNC("e1000_init_hw_82575");
1478
1479         /* Initialize identification LED */
1480         ret_val = mac->ops.id_led_init(hw);
1481         if (ret_val) {
1482                 DEBUGOUT("Error initializing identification LED\n");
1483                 /* This is not fatal and we should not stop init due to this */
1484         }
1485
1486         /* Disabling VLAN filtering */
1487         DEBUGOUT("Initializing the IEEE VLAN\n");
1488         mac->ops.clear_vfta(hw);
1489
1490         /* Setup the receive address */
1491         e1000_init_rx_addrs_generic(hw, rar_count);
1492
1493         /* Zero out the Multicast HASH table */
1494         DEBUGOUT("Zeroing the MTA\n");
1495         for (i = 0; i < mac->mta_reg_count; i++)
1496                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1497
1498         /* Zero out the Unicast HASH table */
1499         DEBUGOUT("Zeroing the UTA\n");
1500         for (i = 0; i < mac->uta_reg_count; i++)
1501                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1502
1503         /* Setup link and flow control */
1504         ret_val = mac->ops.setup_link(hw);
1505
1506         /* Set the default MTU size */
1507         hw->dev_spec._82575.mtu = 1500;
1508
1509         /*
1510          * Clear all of the statistics registers (clear on read).  It is
1511          * important that we do this after we have tried to establish link
1512          * because the symbol error count will increment wildly if there
1513          * is no link.
1514          */
1515         e1000_clear_hw_cntrs_82575(hw);
1516
1517         return ret_val;
1518 }
1519
1520 /**
1521  *  e1000_setup_copper_link_82575 - Configure copper link settings
1522  *  @hw: pointer to the HW structure
1523  *
1524  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1525  *  for link, once link is established calls to configure collision distance
1526  *  and flow control are called.
1527  **/
1528 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1529 {
1530         u32 ctrl;
1531         s32 ret_val;
1532         u32 phpm_reg;
1533
1534         DEBUGFUNC("e1000_setup_copper_link_82575");
1535
1536         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1537         ctrl |= E1000_CTRL_SLU;
1538         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1539         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1540
1541         /* Clear Go Link Disconnect bit on supported devices */
1542         switch (hw->mac.type) {
1543         case e1000_82580:
1544         case e1000_i350:
1545         case e1000_i210:
1546         case e1000_i211:
1547                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1548                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1549                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1550                 break;
1551         default:
1552                 break;
1553         }
1554
1555         ret_val = e1000_setup_serdes_link_82575(hw);
1556         if (ret_val)
1557                 goto out;
1558
1559         if (e1000_sgmii_active_82575(hw)) {
1560                 /* allow time for SFP cage time to power up phy */
1561                 msec_delay(300);
1562
1563                 ret_val = hw->phy.ops.reset(hw);
1564                 if (ret_val) {
1565                         DEBUGOUT("Error resetting the PHY.\n");
1566                         goto out;
1567                 }
1568         }
1569         switch (hw->phy.type) {
1570         case e1000_phy_i210:
1571         case e1000_phy_m88:
1572                 switch (hw->phy.id) {
1573                 case I347AT4_E_PHY_ID:
1574                 case M88E1112_E_PHY_ID:
1575                 case M88E1340M_E_PHY_ID:
1576                 case M88E1543_E_PHY_ID:
1577                 case M88E1512_E_PHY_ID:
1578                 case I210_I_PHY_ID:
1579                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1580                         break;
1581                 default:
1582                         ret_val = e1000_copper_link_setup_m88(hw);
1583                         break;
1584                 }
1585                 break;
1586         case e1000_phy_igp_3:
1587                 ret_val = e1000_copper_link_setup_igp(hw);
1588                 break;
1589         case e1000_phy_82580:
1590                 ret_val = e1000_copper_link_setup_82577(hw);
1591                 break;
1592         default:
1593                 ret_val = -E1000_ERR_PHY;
1594                 break;
1595         }
1596
1597         if (ret_val)
1598                 goto out;
1599
1600         ret_val = e1000_setup_copper_link_generic(hw);
1601 out:
1602         return ret_val;
1603 }
1604
1605 /**
1606  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1607  *  @hw: pointer to the HW structure
1608  *
1609  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1610  *  used on copper connections where the serialized gigabit media independent
1611  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1612  *  for auto-negotiation or forces speed/duplex.
1613  **/
1614 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1615 {
1616         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1617         bool pcs_autoneg;
1618         s32 ret_val = E1000_SUCCESS;
1619         u16 data;
1620
1621         DEBUGFUNC("e1000_setup_serdes_link_82575");
1622
1623         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1624             !e1000_sgmii_active_82575(hw))
1625                 return ret_val;
1626
1627         /*
1628          * On the 82575, SerDes loopback mode persists until it is
1629          * explicitly turned off or a power cycle is performed.  A read to
1630          * the register does not indicate its status.  Therefore, we ensure
1631          * loopback mode is disabled during initialization.
1632          */
1633         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1634
1635         /* power on the sfp cage if present */
1636         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1637         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1638         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1639
1640         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1641         ctrl_reg |= E1000_CTRL_SLU;
1642
1643         /* set both sw defined pins on 82575/82576*/
1644         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1645                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1646
1647         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1648
1649         /* default pcs_autoneg to the same setting as mac autoneg */
1650         pcs_autoneg = hw->mac.autoneg;
1651
1652         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1653         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1654                 /* sgmii mode lets the phy handle forcing speed/duplex */
1655                 pcs_autoneg = true;
1656                 /* autoneg time out should be disabled for SGMII mode */
1657                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1658                 break;
1659         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1660                 /* disable PCS autoneg and support parallel detect only */
1661                 pcs_autoneg = false;
1662                 /* fall through to default case */
1663         default:
1664                 if (hw->mac.type == e1000_82575 ||
1665                     hw->mac.type == e1000_82576) {
1666                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1667                         if (ret_val) {
1668                                 DEBUGOUT("NVM Read Error\n");
1669                                 return ret_val;
1670                         }
1671
1672                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1673                                 pcs_autoneg = false;
1674                 }
1675
1676                 /*
1677                  * non-SGMII modes only supports a speed of 1000/Full for the
1678                  * link so it is best to just force the MAC and let the pcs
1679                  * link either autoneg or be forced to 1000/Full
1680                  */
1681                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1682                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1683
1684                 /* set speed of 1000/Full if speed/duplex is forced */
1685                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1686                 break;
1687         }
1688
1689         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1690
1691         /*
1692          * New SerDes mode allows for forcing speed or autonegotiating speed
1693          * at 1gb. Autoneg should be default set by most drivers. This is the
1694          * mode that will be compatible with older link partners and switches.
1695          * However, both are supported by the hardware and some drivers/tools.
1696          */
1697         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1698                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1699
1700         if (pcs_autoneg) {
1701                 /* Set PCS register for autoneg */
1702                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1703                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1704
1705                 /* Disable force flow control for autoneg */
1706                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1707
1708                 /* Configure flow control advertisement for autoneg */
1709                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1710                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1711
1712                 switch (hw->fc.requested_mode) {
1713                 case e1000_fc_full:
1714                 case e1000_fc_rx_pause:
1715                         anadv_reg |= E1000_TXCW_ASM_DIR;
1716                         anadv_reg |= E1000_TXCW_PAUSE;
1717                         break;
1718                 case e1000_fc_tx_pause:
1719                         anadv_reg |= E1000_TXCW_ASM_DIR;
1720                         break;
1721                 default:
1722                         break;
1723                 }
1724
1725                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1726
1727                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1728         } else {
1729                 /* Set PCS register for forced link */
1730                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1731
1732                 /* Force flow control for forced link */
1733                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1734
1735                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1736         }
1737
1738         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1739
1740         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1741                 e1000_force_mac_fc_generic(hw);
1742
1743         return ret_val;
1744 }
1745
1746 /**
1747  *  e1000_get_media_type_82575 - derives current media type.
1748  *  @hw: pointer to the HW structure
1749  *
1750  *  The media type is chosen reflecting few settings.
1751  *  The following are taken into account:
1752  *  - link mode set in the current port Init Control Word #3
1753  *  - current link mode settings in CSR register
1754  *  - MDIO vs. I2C PHY control interface chosen
1755  *  - SFP module media type
1756  **/
1757 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1758 {
1759         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1760         s32 ret_val = E1000_SUCCESS;
1761         u32 ctrl_ext = 0;
1762         u32 link_mode = 0;
1763
1764         /* Set internal phy as default */
1765         dev_spec->sgmii_active = false;
1766         dev_spec->module_plugged = false;
1767
1768         /* Get CSR setting */
1769         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1770
1771         /* extract link mode setting */
1772         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1773
1774         switch (link_mode) {
1775         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1776                 hw->phy.media_type = e1000_media_type_internal_serdes;
1777                 break;
1778         case E1000_CTRL_EXT_LINK_MODE_GMII:
1779                 hw->phy.media_type = e1000_media_type_copper;
1780                 break;
1781         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1782                 /* Get phy control interface type set (MDIO vs. I2C)*/
1783                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1784                         hw->phy.media_type = e1000_media_type_copper;
1785                         dev_spec->sgmii_active = true;
1786                         break;
1787                 }
1788                 /* fall through for I2C based SGMII */
1789         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1790                 /* read media type from SFP EEPROM */
1791                 ret_val = e1000_set_sfp_media_type_82575(hw);
1792                 if ((ret_val != E1000_SUCCESS) ||
1793                     (hw->phy.media_type == e1000_media_type_unknown)) {
1794                         /*
1795                          * If media type was not identified then return media
1796                          * type defined by the CTRL_EXT settings.
1797                          */
1798                         hw->phy.media_type = e1000_media_type_internal_serdes;
1799
1800                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1801                                 hw->phy.media_type = e1000_media_type_copper;
1802                                 dev_spec->sgmii_active = true;
1803                         }
1804
1805                         break;
1806                 }
1807
1808                 /* do not change link mode for 100BaseFX */
1809                 if (dev_spec->eth_flags.e100_base_fx)
1810                         break;
1811
1812                 /* change current link mode setting */
1813                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1814
1815                 if (hw->phy.media_type == e1000_media_type_copper)
1816                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1817                 else
1818                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1819
1820                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1821
1822                 break;
1823         }
1824
1825         return ret_val;
1826 }
1827
1828 /**
1829  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1830  *  @hw: pointer to the HW structure
1831  *
1832  *  The media type is chosen based on SFP module.
1833  *  compatibility flags retrieved from SFP ID EEPROM.
1834  **/
1835 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1836 {
1837         s32 ret_val = E1000_ERR_CONFIG;
1838         u32 ctrl_ext = 0;
1839         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1840         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1841         u8 tranceiver_type = 0;
1842         s32 timeout = 3;
1843
1844         /* Turn I2C interface ON and power on sfp cage */
1845         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1846         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1847         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1848
1849         E1000_WRITE_FLUSH(hw);
1850
1851         /* Read SFP module data */
1852         while (timeout) {
1853                 ret_val = e1000_read_sfp_data_byte(hw,
1854                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1855                         &tranceiver_type);
1856                 if (ret_val == E1000_SUCCESS)
1857                         break;
1858                 msec_delay(100);
1859                 timeout--;
1860         }
1861         if (ret_val != E1000_SUCCESS)
1862                 goto out;
1863
1864         ret_val = e1000_read_sfp_data_byte(hw,
1865                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1866                         (u8 *)eth_flags);
1867         if (ret_val != E1000_SUCCESS)
1868                 goto out;
1869
1870         /* Check if there is some SFP module plugged and powered */
1871         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1872             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1873                 dev_spec->module_plugged = true;
1874                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1875                         hw->phy.media_type = e1000_media_type_internal_serdes;
1876                 } else if (eth_flags->e100_base_fx) {
1877                         dev_spec->sgmii_active = true;
1878                         hw->phy.media_type = e1000_media_type_internal_serdes;
1879                 } else if (eth_flags->e1000_base_t) {
1880                         dev_spec->sgmii_active = true;
1881                         hw->phy.media_type = e1000_media_type_copper;
1882                 } else {
1883                         hw->phy.media_type = e1000_media_type_unknown;
1884                         DEBUGOUT("PHY module has not been recognized\n");
1885                         goto out;
1886                 }
1887         } else {
1888                 hw->phy.media_type = e1000_media_type_unknown;
1889         }
1890         ret_val = E1000_SUCCESS;
1891 out:
1892         /* Restore I2C interface setting */
1893         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1894         return ret_val;
1895 }
1896
1897 /**
1898  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1899  *  @hw: pointer to the HW structure
1900  *  @data: pointer to the NVM (EEPROM)
1901  *
1902  *  Read the EEPROM for the current default LED configuration.  If the
1903  *  LED configuration is not valid, set to a valid LED configuration.
1904  **/
1905 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1906 {
1907         s32 ret_val;
1908
1909         DEBUGFUNC("e1000_valid_led_default_82575");
1910
1911         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1912         if (ret_val) {
1913                 DEBUGOUT("NVM Read Error\n");
1914                 goto out;
1915         }
1916
1917         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1918                 switch (hw->phy.media_type) {
1919                 case e1000_media_type_internal_serdes:
1920                         *data = ID_LED_DEFAULT_82575_SERDES;
1921                         break;
1922                 case e1000_media_type_copper:
1923                 default:
1924                         *data = ID_LED_DEFAULT;
1925                         break;
1926                 }
1927         }
1928 out:
1929         return ret_val;
1930 }
1931
1932 /**
1933  *  e1000_sgmii_active_82575 - Return sgmii state
1934  *  @hw: pointer to the HW structure
1935  *
1936  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1937  *  which can be enabled for use in the embedded applications.  Simply
1938  *  return the current state of the sgmii interface.
1939  **/
1940 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1941 {
1942         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1943         return dev_spec->sgmii_active;
1944 }
1945
1946 /**
1947  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1948  *  @hw: pointer to the HW structure
1949  *
1950  *  Inits recommended HW defaults after a reset when there is no EEPROM
1951  *  detected. This is only for the 82575.
1952  **/
1953 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1954 {
1955         DEBUGFUNC("e1000_reset_init_script_82575");
1956
1957         if (hw->mac.type == e1000_82575) {
1958                 DEBUGOUT("Running reset init script for 82575\n");
1959                 /* SerDes configuration via SERDESCTRL */
1960                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1961                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1962                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1963                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1964
1965                 /* CCM configuration via CCMCTL register */
1966                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1967                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1968
1969                 /* PCIe lanes configuration */
1970                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1971                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1972                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1973                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1974
1975                 /* PCIe PLL Configuration */
1976                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1977                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1978                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1979         }
1980
1981         return E1000_SUCCESS;
1982 }
1983
1984 /**
1985  *  e1000_read_mac_addr_82575 - Read device MAC address
1986  *  @hw: pointer to the HW structure
1987  **/
1988 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1989 {
1990         s32 ret_val;
1991
1992         DEBUGFUNC("e1000_read_mac_addr_82575");
1993
1994         /*
1995          * If there's an alternate MAC address place it in RAR0
1996          * so that it will override the Si installed default perm
1997          * address.
1998          */
1999         ret_val = e1000_check_alt_mac_addr_generic(hw);
2000         if (ret_val)
2001                 goto out;
2002
2003         ret_val = e1000_read_mac_addr_generic(hw);
2004
2005 out:
2006         return ret_val;
2007 }
2008
2009 /**
2010  *  e1000_config_collision_dist_82575 - Configure collision distance
2011  *  @hw: pointer to the HW structure
2012  *
2013  *  Configures the collision distance to the default value and is used
2014  *  during link setup.
2015  **/
2016 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2017 {
2018         u32 tctl_ext;
2019
2020         DEBUGFUNC("e1000_config_collision_dist_82575");
2021
2022         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2023
2024         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2025         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2026
2027         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2028         E1000_WRITE_FLUSH(hw);
2029 }
2030
2031 /**
2032  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2033  * @hw: pointer to the HW structure
2034  *
2035  * In the case of a PHY power down to save power, or to turn off link during a
2036  * driver unload, or wake on lan is not enabled, remove the link.
2037  **/
2038 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2039 {
2040         struct e1000_phy_info *phy = &hw->phy;
2041
2042         if (!(phy->ops.check_reset_block))
2043                 return;
2044
2045         /* If the management interface is not enabled, then power down */
2046         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2047                 e1000_power_down_phy_copper(hw);
2048
2049         return;
2050 }
2051
2052 /**
2053  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2054  *  @hw: pointer to the HW structure
2055  *
2056  *  Clears the hardware counters by reading the counter registers.
2057  **/
2058 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2059 {
2060         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2061
2062         e1000_clear_hw_cntrs_base_generic(hw);
2063
2064         E1000_READ_REG(hw, E1000_PRC64);
2065         E1000_READ_REG(hw, E1000_PRC127);
2066         E1000_READ_REG(hw, E1000_PRC255);
2067         E1000_READ_REG(hw, E1000_PRC511);
2068         E1000_READ_REG(hw, E1000_PRC1023);
2069         E1000_READ_REG(hw, E1000_PRC1522);
2070         E1000_READ_REG(hw, E1000_PTC64);
2071         E1000_READ_REG(hw, E1000_PTC127);
2072         E1000_READ_REG(hw, E1000_PTC255);
2073         E1000_READ_REG(hw, E1000_PTC511);
2074         E1000_READ_REG(hw, E1000_PTC1023);
2075         E1000_READ_REG(hw, E1000_PTC1522);
2076
2077         E1000_READ_REG(hw, E1000_ALGNERRC);
2078         E1000_READ_REG(hw, E1000_RXERRC);
2079         E1000_READ_REG(hw, E1000_TNCRS);
2080         E1000_READ_REG(hw, E1000_CEXTERR);
2081         E1000_READ_REG(hw, E1000_TSCTC);
2082         E1000_READ_REG(hw, E1000_TSCTFC);
2083
2084         E1000_READ_REG(hw, E1000_MGTPRC);
2085         E1000_READ_REG(hw, E1000_MGTPDC);
2086         E1000_READ_REG(hw, E1000_MGTPTC);
2087
2088         E1000_READ_REG(hw, E1000_IAC);
2089         E1000_READ_REG(hw, E1000_ICRXOC);
2090
2091         E1000_READ_REG(hw, E1000_ICRXPTC);
2092         E1000_READ_REG(hw, E1000_ICRXATC);
2093         E1000_READ_REG(hw, E1000_ICTXPTC);
2094         E1000_READ_REG(hw, E1000_ICTXATC);
2095         E1000_READ_REG(hw, E1000_ICTXQEC);
2096         E1000_READ_REG(hw, E1000_ICTXQMTC);
2097         E1000_READ_REG(hw, E1000_ICRXDMTC);
2098
2099         E1000_READ_REG(hw, E1000_CBTMPC);
2100         E1000_READ_REG(hw, E1000_HTDPMC);
2101         E1000_READ_REG(hw, E1000_CBRMPC);
2102         E1000_READ_REG(hw, E1000_RPTHC);
2103         E1000_READ_REG(hw, E1000_HGPTC);
2104         E1000_READ_REG(hw, E1000_HTCBDPC);
2105         E1000_READ_REG(hw, E1000_HGORCL);
2106         E1000_READ_REG(hw, E1000_HGORCH);
2107         E1000_READ_REG(hw, E1000_HGOTCL);
2108         E1000_READ_REG(hw, E1000_HGOTCH);
2109         E1000_READ_REG(hw, E1000_LENERRS);
2110
2111         /* This register should not be read in copper configurations */
2112         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2113             e1000_sgmii_active_82575(hw))
2114                 E1000_READ_REG(hw, E1000_SCVPC);
2115 }
2116
2117 /**
2118  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2119  *  @hw: pointer to the HW structure
2120  *
2121  *  After rx enable if managability is enabled then there is likely some
2122  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2123  *  function clears the fifos and flushes any packets that came in as rx was
2124  *  being enabled.
2125  **/
2126 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2127 {
2128         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2129         int i, ms_wait;
2130
2131         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2132         if (hw->mac.type != e1000_82575 ||
2133             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2134                 return;
2135
2136         /* Disable all Rx queues */
2137         for (i = 0; i < 4; i++) {
2138                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2139                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2140                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2141         }
2142         /* Poll all queues to verify they have shut down */
2143         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2144                 msec_delay(1);
2145                 rx_enabled = 0;
2146                 for (i = 0; i < 4; i++)
2147                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2148                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2149                         break;
2150         }
2151
2152         if (ms_wait == 10)
2153                 DEBUGOUT("Queue disable timed out after 10ms\n");
2154
2155         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2156          * incoming packets are rejected.  Set enable and wait 2ms so that
2157          * any packet that was coming in as RCTL.EN was set is flushed
2158          */
2159         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2160         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2161
2162         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2163         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2164
2165         rctl = E1000_READ_REG(hw, E1000_RCTL);
2166         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2167         temp_rctl |= E1000_RCTL_LPE;
2168
2169         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2170         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2171         E1000_WRITE_FLUSH(hw);
2172         msec_delay(2);
2173
2174         /* Enable Rx queues that were previously enabled and restore our
2175          * previous state
2176          */
2177         for (i = 0; i < 4; i++)
2178                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2179         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2180         E1000_WRITE_FLUSH(hw);
2181
2182         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2183         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2184
2185         /* Flush receive errors generated by workaround */
2186         E1000_READ_REG(hw, E1000_ROC);
2187         E1000_READ_REG(hw, E1000_RNBC);
2188         E1000_READ_REG(hw, E1000_MPC);
2189 }
2190
2191 /**
2192  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2193  *  @hw: pointer to the HW structure
2194  *
2195  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2196  *  however the hardware default for these parts is 500us to 1ms which is less
2197  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2198  *  increase the value to either 10ms to 200ms for capability version 1 config,
2199  *  or 16ms to 55ms for version 2.
2200  **/
2201 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2202 {
2203         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2204         s32 ret_val = E1000_SUCCESS;
2205         u16 pcie_devctl2;
2206
2207         /* only take action if timeout value is defaulted to 0 */
2208         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2209                 goto out;
2210
2211         /*
2212          * if capababilities version is type 1 we can write the
2213          * timeout of 10ms to 200ms through the GCR register
2214          */
2215         if (!(gcr & E1000_GCR_CAP_VER2)) {
2216                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2217                 goto out;
2218         }
2219
2220         /*
2221          * for version 2 capabilities we need to write the config space
2222          * directly in order to set the completion timeout value for
2223          * 16ms to 55ms
2224          */
2225         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2226                                           &pcie_devctl2);
2227         if (ret_val)
2228                 goto out;
2229
2230         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2231
2232         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2233                                            &pcie_devctl2);
2234 out:
2235         /* disable completion timeout resend */
2236         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2237
2238         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2239         return ret_val;
2240 }
2241
2242 /**
2243  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2244  *  @hw: pointer to the hardware struct
2245  *  @enable: state to enter, either enabled or disabled
2246  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2247  *
2248  *  enables/disables L2 switch anti-spoofing functionality.
2249  **/
2250 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2251 {
2252         u32 reg_val, reg_offset;
2253
2254         switch (hw->mac.type) {
2255         case e1000_82576:
2256                 reg_offset = E1000_DTXSWC;
2257                 break;
2258         case e1000_i350:
2259         case e1000_i354:
2260                 reg_offset = E1000_TXSWC;
2261                 break;
2262         default:
2263                 return;
2264         }
2265
2266         reg_val = E1000_READ_REG(hw, reg_offset);
2267         if (enable) {
2268                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2269                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2270                 /* The PF can spoof - it has to in order to
2271                  * support emulation mode NICs
2272                  */
2273                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2274         } else {
2275                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2276                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2277         }
2278         E1000_WRITE_REG(hw, reg_offset, reg_val);
2279 }
2280
2281 /**
2282  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2283  *  @hw: pointer to the hardware struct
2284  *  @enable: state to enter, either enabled or disabled
2285  *
2286  *  enables/disables L2 switch loopback functionality.
2287  **/
2288 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2289 {
2290         u32 dtxswc;
2291
2292         switch (hw->mac.type) {
2293         case e1000_82576:
2294                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2295                 if (enable)
2296                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2297                 else
2298                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2299                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2300                 break;
2301         case e1000_i350:
2302         case e1000_i354:
2303                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2304                 if (enable)
2305                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2306                 else
2307                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2308                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2309                 break;
2310         default:
2311                 /* Currently no other hardware supports loopback */
2312                 break;
2313         }
2314
2315
2316 }
2317
2318 /**
2319  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2320  *  @hw: pointer to the hardware struct
2321  *  @enable: state to enter, either enabled or disabled
2322  *
2323  *  enables/disables replication of packets across multiple pools.
2324  **/
2325 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2326 {
2327         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2328
2329         if (enable)
2330                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2331         else
2332                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2333
2334         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2335 }
2336
2337 /**
2338  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2339  *  @hw: pointer to the HW structure
2340  *  @offset: register offset to be read
2341  *  @data: pointer to the read data
2342  *
2343  *  Reads the MDI control register in the PHY at offset and stores the
2344  *  information read to data.
2345  **/
2346 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2347 {
2348         s32 ret_val;
2349
2350         DEBUGFUNC("e1000_read_phy_reg_82580");
2351
2352         ret_val = hw->phy.ops.acquire(hw);
2353         if (ret_val)
2354                 goto out;
2355
2356         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2357
2358         hw->phy.ops.release(hw);
2359
2360 out:
2361         return ret_val;
2362 }
2363
2364 /**
2365  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2366  *  @hw: pointer to the HW structure
2367  *  @offset: register offset to write to
2368  *  @data: data to write to register at offset
2369  *
2370  *  Writes data to MDI control register in the PHY at offset.
2371  **/
2372 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2373 {
2374         s32 ret_val;
2375
2376         DEBUGFUNC("e1000_write_phy_reg_82580");
2377
2378         ret_val = hw->phy.ops.acquire(hw);
2379         if (ret_val)
2380                 goto out;
2381
2382         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2383
2384         hw->phy.ops.release(hw);
2385
2386 out:
2387         return ret_val;
2388 }
2389
2390 /**
2391  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2392  *  @hw: pointer to the HW structure
2393  *
2394  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2395  *  the values found in the EEPROM.  This addresses an issue in which these
2396  *  bits are not restored from EEPROM after reset.
2397  **/
2398 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2399 {
2400         s32 ret_val = E1000_SUCCESS;
2401         u32 mdicnfg;
2402         u16 nvm_data = 0;
2403
2404         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2405
2406         if (hw->mac.type != e1000_82580)
2407                 goto out;
2408         if (!e1000_sgmii_active_82575(hw))
2409                 goto out;
2410
2411         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2412                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2413                                    &nvm_data);
2414         if (ret_val) {
2415                 DEBUGOUT("NVM Read Error\n");
2416                 goto out;
2417         }
2418
2419         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2420         if (nvm_data & NVM_WORD24_EXT_MDIO)
2421                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2422         if (nvm_data & NVM_WORD24_COM_MDIO)
2423                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2424         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2425 out:
2426         return ret_val;
2427 }
2428
2429 /**
2430  *  e1000_reset_hw_82580 - Reset hardware
2431  *  @hw: pointer to the HW structure
2432  *
2433  *  This resets function or entire device (all ports, etc.)
2434  *  to a known state.
2435  **/
2436 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2437 {
2438         s32 ret_val = E1000_SUCCESS;
2439         /* BH SW mailbox bit in SW_FW_SYNC */
2440         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2441         u32 ctrl;
2442         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2443
2444         DEBUGFUNC("e1000_reset_hw_82580");
2445
2446         hw->dev_spec._82575.global_device_reset = false;
2447
2448         /* 82580 does not reliably do global_device_reset due to hw errata */
2449         if (hw->mac.type == e1000_82580)
2450                 global_device_reset = false;
2451
2452         /* Get current control state. */
2453         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2454
2455         /*
2456          * Prevent the PCI-E bus from sticking if there is no TLP connection
2457          * on the last TLP read/write transaction when MAC is reset.
2458          */
2459         ret_val = e1000_disable_pcie_master_generic(hw);
2460         if (ret_val)
2461                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2462
2463         DEBUGOUT("Masking off all interrupts\n");
2464         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2465         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2466         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2467         E1000_WRITE_FLUSH(hw);
2468
2469         msec_delay(10);
2470
2471         /* Determine whether or not a global dev reset is requested */
2472         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2473             swmbsw_mask))
2474                         global_device_reset = false;
2475
2476         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2477             E1000_STAT_DEV_RST_SET))
2478                 ctrl |= E1000_CTRL_DEV_RST;
2479         else
2480                 ctrl |= E1000_CTRL_RST;
2481
2482         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2483         E1000_WRITE_FLUSH(hw);
2484
2485         /* Add delay to insure DEV_RST has time to complete */
2486         if (global_device_reset)
2487                 msec_delay(5);
2488
2489         ret_val = e1000_get_auto_rd_done_generic(hw);
2490         if (ret_val) {
2491                 /*
2492                  * When auto config read does not complete, do not
2493                  * return with an error. This can happen in situations
2494                  * where there is no eeprom and prevents getting link.
2495                  */
2496                 DEBUGOUT("Auto Read Done did not complete\n");
2497         }
2498
2499         /* clear global device reset status bit */
2500         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2501
2502         /* Clear any pending interrupt events. */
2503         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2504         E1000_READ_REG(hw, E1000_ICR);
2505
2506         ret_val = e1000_reset_mdicnfg_82580(hw);
2507         if (ret_val)
2508                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2509
2510         /* Install any alternate MAC address into RAR0 */
2511         ret_val = e1000_check_alt_mac_addr_generic(hw);
2512
2513         /* Release semaphore */
2514         if (global_device_reset)
2515                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2516
2517         return ret_val;
2518 }
2519
2520 /**
2521  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2522  *  @data: data received by reading RXPBS register
2523  *
2524  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2525  *  This function converts the retrieved value into the correct table value
2526  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2527  *  0x0 36  72 144   1   2   4   8  16
2528  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2529  */
2530 u16 e1000_rxpbs_adjust_82580(u32 data)
2531 {
2532         u16 ret_val = 0;
2533
2534         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2535                 ret_val = e1000_82580_rxpbs_table[data];
2536
2537         return ret_val;
2538 }
2539
2540 /**
2541  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2542  *  checksum
2543  *  @hw: pointer to the HW structure
2544  *  @offset: offset in words of the checksum protected region
2545  *
2546  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2547  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2548  **/
2549 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2550 {
2551         s32 ret_val = E1000_SUCCESS;
2552         u16 checksum = 0;
2553         u16 i, nvm_data;
2554
2555         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2556
2557         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2558                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2559                 if (ret_val) {
2560                         DEBUGOUT("NVM Read Error\n");
2561                         goto out;
2562                 }
2563                 checksum += nvm_data;
2564         }
2565
2566         if (checksum != (u16) NVM_SUM) {
2567                 DEBUGOUT("NVM Checksum Invalid\n");
2568                 ret_val = -E1000_ERR_NVM;
2569                 goto out;
2570         }
2571
2572 out:
2573         return ret_val;
2574 }
2575
2576 /**
2577  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2578  *  checksum
2579  *  @hw: pointer to the HW structure
2580  *  @offset: offset in words of the checksum protected region
2581  *
2582  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2583  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2584  *  value to the EEPROM.
2585  **/
2586 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2587 {
2588         s32 ret_val;
2589         u16 checksum = 0;
2590         u16 i, nvm_data;
2591
2592         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2593
2594         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2595                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2596                 if (ret_val) {
2597                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2598                         goto out;
2599                 }
2600                 checksum += nvm_data;
2601         }
2602         checksum = (u16) NVM_SUM - checksum;
2603         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2604                                     &checksum);
2605         if (ret_val)
2606                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2607
2608 out:
2609         return ret_val;
2610 }
2611
2612 /**
2613  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2614  *  @hw: pointer to the HW structure
2615  *
2616  *  Calculates the EEPROM section checksum by reading/adding each word of
2617  *  the EEPROM and then verifies that the sum of the EEPROM is
2618  *  equal to 0xBABA.
2619  **/
2620 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2621 {
2622         s32 ret_val;
2623         u16 eeprom_regions_count = 1;
2624         u16 j, nvm_data;
2625         u16 nvm_offset;
2626
2627         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2628
2629         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2630         if (ret_val) {
2631                 DEBUGOUT("NVM Read Error\n");
2632                 goto out;
2633         }
2634
2635         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2636                 /* if chekcsums compatibility bit is set validate checksums
2637                  * for all 4 ports. */
2638                 eeprom_regions_count = 4;
2639         }
2640
2641         for (j = 0; j < eeprom_regions_count; j++) {
2642                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2643                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2644                                                                   nvm_offset);
2645                 if (ret_val != E1000_SUCCESS)
2646                         goto out;
2647         }
2648
2649 out:
2650         return ret_val;
2651 }
2652
2653 /**
2654  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2655  *  @hw: pointer to the HW structure
2656  *
2657  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2658  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2659  *  checksum and writes the value to the EEPROM.
2660  **/
2661 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2662 {
2663         s32 ret_val;
2664         u16 j, nvm_data;
2665         u16 nvm_offset;
2666
2667         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2668
2669         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2670         if (ret_val) {
2671                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2672                 goto out;
2673         }
2674
2675         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2676                 /* set compatibility bit to validate checksums appropriately */
2677                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2678                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2679                                             &nvm_data);
2680                 if (ret_val) {
2681                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2682                         goto out;
2683                 }
2684         }
2685
2686         for (j = 0; j < 4; j++) {
2687                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2688                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2689                 if (ret_val)
2690                         goto out;
2691         }
2692
2693 out:
2694         return ret_val;
2695 }
2696
2697 /**
2698  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2699  *  @hw: pointer to the HW structure
2700  *
2701  *  Calculates the EEPROM section checksum by reading/adding each word of
2702  *  the EEPROM and then verifies that the sum of the EEPROM is
2703  *  equal to 0xBABA.
2704  **/
2705 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2706 {
2707         s32 ret_val = E1000_SUCCESS;
2708         u16 j;
2709         u16 nvm_offset;
2710
2711         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2712
2713         for (j = 0; j < 4; j++) {
2714                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2715                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2716                                                                   nvm_offset);
2717                 if (ret_val != E1000_SUCCESS)
2718                         goto out;
2719         }
2720
2721 out:
2722         return ret_val;
2723 }
2724
2725 /**
2726  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2727  *  @hw: pointer to the HW structure
2728  *
2729  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2730  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2731  *  checksum and writes the value to the EEPROM.
2732  **/
2733 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2734 {
2735         s32 ret_val = E1000_SUCCESS;
2736         u16 j;
2737         u16 nvm_offset;
2738
2739         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2740
2741         for (j = 0; j < 4; j++) {
2742                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2743                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2744                 if (ret_val != E1000_SUCCESS)
2745                         goto out;
2746         }
2747
2748 out:
2749         return ret_val;
2750 }
2751
2752 /**
2753  *  __e1000_access_emi_reg - Read/write EMI register
2754  *  @hw: pointer to the HW structure
2755  *  @addr: EMI address to program
2756  *  @data: pointer to value to read/write from/to the EMI address
2757  *  @read: boolean flag to indicate read or write
2758  **/
2759 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2760                                   u16 *data, bool read)
2761 {
2762         s32 ret_val;
2763
2764         DEBUGFUNC("__e1000_access_emi_reg");
2765
2766         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2767         if (ret_val)
2768                 return ret_val;
2769
2770         if (read)
2771                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2772         else
2773                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2774
2775         return ret_val;
2776 }
2777
2778 /**
2779  *  e1000_read_emi_reg - Read Extended Management Interface register
2780  *  @hw: pointer to the HW structure
2781  *  @addr: EMI address to program
2782  *  @data: value to be read from the EMI address
2783  **/
2784 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2785 {
2786         DEBUGFUNC("e1000_read_emi_reg");
2787
2788         return __e1000_access_emi_reg(hw, addr, data, true);
2789 }
2790
2791 /**
2792  *  e1000_set_eee_i350 - Enable/disable EEE support
2793  *  @hw: pointer to the HW structure
2794  *
2795  *  Enable/disable EEE based on setting in dev_spec structure.
2796  *
2797  **/
2798 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2799 {
2800         s32 ret_val = E1000_SUCCESS;
2801         u32 ipcnfg, eeer;
2802
2803         DEBUGFUNC("e1000_set_eee_i350");
2804
2805         if ((hw->mac.type < e1000_i350) ||
2806             (hw->phy.media_type != e1000_media_type_copper))
2807                 goto out;
2808         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2809         eeer = E1000_READ_REG(hw, E1000_EEER);
2810
2811         /* enable or disable per user setting */
2812         if (!(hw->dev_spec._82575.eee_disable)) {
2813                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2814
2815                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2816                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2817                          E1000_EEER_LPI_FC);
2818
2819                 /* This bit should not be set in normal operation. */
2820                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2821                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2822         } else {
2823                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2824                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2825                           E1000_EEER_LPI_FC);
2826         }
2827         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2828         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2829         E1000_READ_REG(hw, E1000_IPCNFG);
2830         E1000_READ_REG(hw, E1000_EEER);
2831 out:
2832
2833         return ret_val;
2834 }
2835
2836 /**
2837  *  e1000_set_eee_i354 - Enable/disable EEE support
2838  *  @hw: pointer to the HW structure
2839  *
2840  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2841  *
2842  **/
2843 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2844 {
2845         struct e1000_phy_info *phy = &hw->phy;
2846         s32 ret_val = E1000_SUCCESS;
2847         u16 phy_data;
2848
2849         DEBUGFUNC("e1000_set_eee_i354");
2850
2851         if ((hw->phy.media_type != e1000_media_type_copper) ||
2852             ((phy->id != M88E1543_E_PHY_ID) &&
2853             (phy->id != M88E1512_E_PHY_ID)))
2854                 goto out;
2855
2856         if (!hw->dev_spec._82575.eee_disable) {
2857                 /* Switch to PHY page 18. */
2858                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2859                 if (ret_val)
2860                         goto out;
2861
2862                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2863                                             &phy_data);
2864                 if (ret_val)
2865                         goto out;
2866
2867                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2868                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2869                                              phy_data);
2870                 if (ret_val)
2871                         goto out;
2872
2873                 /* Return the PHY to page 0. */
2874                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2875                 if (ret_val)
2876                         goto out;
2877
2878                 /* Turn on EEE advertisement. */
2879                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2880                                                E1000_EEE_ADV_DEV_I354,
2881                                                &phy_data);
2882                 if (ret_val)
2883                         goto out;
2884
2885                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2886                             E1000_EEE_ADV_1000_SUPPORTED;
2887                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2888                                                 E1000_EEE_ADV_DEV_I354,
2889                                                 phy_data);
2890         } else {
2891                 /* Turn off EEE advertisement. */
2892                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2893                                                E1000_EEE_ADV_DEV_I354,
2894                                                &phy_data);
2895                 if (ret_val)
2896                         goto out;
2897
2898                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2899                               E1000_EEE_ADV_1000_SUPPORTED);
2900                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2901                                                 E1000_EEE_ADV_DEV_I354,
2902                                                 phy_data);
2903         }
2904
2905 out:
2906         return ret_val;
2907 }
2908
2909 /**
2910  *  e1000_get_eee_status_i354 - Get EEE status
2911  *  @hw: pointer to the HW structure
2912  *  @status: EEE status
2913  *
2914  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2915  *  been received.
2916  **/
2917 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2918 {
2919         struct e1000_phy_info *phy = &hw->phy;
2920         s32 ret_val = E1000_SUCCESS;
2921         u16 phy_data;
2922
2923         DEBUGFUNC("e1000_get_eee_status_i354");
2924
2925         /* Check if EEE is supported on this device. */
2926         if ((hw->phy.media_type != e1000_media_type_copper) ||
2927             ((phy->id != M88E1543_E_PHY_ID) &&
2928             (phy->id != M88E1512_E_PHY_ID)))
2929                 goto out;
2930
2931         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2932                                        E1000_PCS_STATUS_DEV_I354,
2933                                        &phy_data);
2934         if (ret_val)
2935                 goto out;
2936
2937         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2938                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2939
2940 out:
2941         return ret_val;
2942 }
2943
2944 /* Due to a hw errata, if the host tries to  configure the VFTA register
2945  * while performing queries from the BMC or DMA, then the VFTA in some
2946  * cases won't be written.
2947  */
2948
2949 /**
2950  *  e1000_clear_vfta_i350 - Clear VLAN filter table
2951  *  @hw: pointer to the HW structure
2952  *
2953  *  Clears the register array which contains the VLAN filter table by
2954  *  setting all the values to 0.
2955  **/
2956 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2957 {
2958         u32 offset;
2959         int i;
2960
2961         DEBUGFUNC("e1000_clear_vfta_350");
2962
2963         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2964                 for (i = 0; i < 10; i++)
2965                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2966
2967                 E1000_WRITE_FLUSH(hw);
2968         }
2969 }
2970
2971 /**
2972  *  e1000_write_vfta_i350 - Write value to VLAN filter table
2973  *  @hw: pointer to the HW structure
2974  *  @offset: register offset in VLAN filter table
2975  *  @value: register value written to VLAN filter table
2976  *
2977  *  Writes value at the given offset in the register array which stores
2978  *  the VLAN filter table.
2979  **/
2980 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2981 {
2982         int i;
2983
2984         DEBUGFUNC("e1000_write_vfta_350");
2985
2986         for (i = 0; i < 10; i++)
2987                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2988
2989         E1000_WRITE_FLUSH(hw);
2990 }
2991
2992
2993 /**
2994  *  e1000_set_i2c_bb - Enable I2C bit-bang
2995  *  @hw: pointer to the HW structure
2996  *
2997  *  Enable I2C bit-bang interface
2998  *
2999  **/
3000 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3001 {
3002         s32 ret_val = E1000_SUCCESS;
3003         u32 ctrl_ext, i2cparams;
3004
3005         DEBUGFUNC("e1000_set_i2c_bb");
3006
3007         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3008         ctrl_ext |= E1000_CTRL_I2C_ENA;
3009         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3010         E1000_WRITE_FLUSH(hw);
3011
3012         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3013         i2cparams |= E1000_I2CBB_EN;
3014         i2cparams |= E1000_I2C_DATA_OE_N;
3015         i2cparams |= E1000_I2C_CLK_OE_N;
3016         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3017         E1000_WRITE_FLUSH(hw);
3018
3019         return ret_val;
3020 }
3021
3022 /**
3023  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3024  *  @hw: pointer to hardware structure
3025  *  @byte_offset: byte offset to read
3026  *  @dev_addr: device address
3027  *  @data: value read
3028  *
3029  *  Performs byte read operation over I2C interface at
3030  *  a specified device address.
3031  **/
3032 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3033                                 u8 dev_addr, u8 *data)
3034 {
3035         s32 status = E1000_SUCCESS;
3036         u32 max_retry = 10;
3037         u32 retry = 1;
3038         u16 swfw_mask = 0;
3039
3040         bool nack = true;
3041
3042         DEBUGFUNC("e1000_read_i2c_byte_generic");
3043
3044         swfw_mask = E1000_SWFW_PHY0_SM;
3045
3046         do {
3047                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3048                     != E1000_SUCCESS) {
3049                         status = E1000_ERR_SWFW_SYNC;
3050                         goto read_byte_out;
3051                 }
3052
3053                 e1000_i2c_start(hw);
3054
3055                 /* Device Address and write indication */
3056                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3057                 if (status != E1000_SUCCESS)
3058                         goto fail;
3059
3060                 status = e1000_get_i2c_ack(hw);
3061                 if (status != E1000_SUCCESS)
3062                         goto fail;
3063
3064                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3065                 if (status != E1000_SUCCESS)
3066                         goto fail;
3067
3068                 status = e1000_get_i2c_ack(hw);
3069                 if (status != E1000_SUCCESS)
3070                         goto fail;
3071
3072                 e1000_i2c_start(hw);
3073
3074                 /* Device Address and read indication */
3075                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3076                 if (status != E1000_SUCCESS)
3077                         goto fail;
3078
3079                 status = e1000_get_i2c_ack(hw);
3080                 if (status != E1000_SUCCESS)
3081                         goto fail;
3082
3083                 status = e1000_clock_in_i2c_byte(hw, data);
3084                 if (status != E1000_SUCCESS)
3085                         goto fail;
3086
3087                 status = e1000_clock_out_i2c_bit(hw, nack);
3088                 if (status != E1000_SUCCESS)
3089                         goto fail;
3090
3091                 e1000_i2c_stop(hw);
3092                 break;
3093
3094 fail:
3095                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3096                 msec_delay(100);
3097                 e1000_i2c_bus_clear(hw);
3098                 retry++;
3099                 if (retry < max_retry)
3100                         DEBUGOUT("I2C byte read error - Retrying.\n");
3101                 else
3102                         DEBUGOUT("I2C byte read error.\n");
3103
3104         } while (retry < max_retry);
3105
3106         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3107
3108 read_byte_out:
3109
3110         return status;
3111 }
3112
3113 /**
3114  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3115  *  @hw: pointer to hardware structure
3116  *  @byte_offset: byte offset to write
3117  *  @dev_addr: device address
3118  *  @data: value to write
3119  *
3120  *  Performs byte write operation over I2C interface at
3121  *  a specified device address.
3122  **/
3123 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3124                                  u8 dev_addr, u8 data)
3125 {
3126         s32 status = E1000_SUCCESS;
3127         u32 max_retry = 1;
3128         u32 retry = 0;
3129         u16 swfw_mask = 0;
3130
3131         DEBUGFUNC("e1000_write_i2c_byte_generic");
3132
3133         swfw_mask = E1000_SWFW_PHY0_SM;
3134
3135         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3136                 status = E1000_ERR_SWFW_SYNC;
3137                 goto write_byte_out;
3138         }
3139
3140         do {
3141                 e1000_i2c_start(hw);
3142
3143                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3144                 if (status != E1000_SUCCESS)
3145                         goto fail;
3146
3147                 status = e1000_get_i2c_ack(hw);
3148                 if (status != E1000_SUCCESS)
3149                         goto fail;
3150
3151                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3152                 if (status != E1000_SUCCESS)
3153                         goto fail;
3154
3155                 status = e1000_get_i2c_ack(hw);
3156                 if (status != E1000_SUCCESS)
3157                         goto fail;
3158
3159                 status = e1000_clock_out_i2c_byte(hw, data);
3160                 if (status != E1000_SUCCESS)
3161                         goto fail;
3162
3163                 status = e1000_get_i2c_ack(hw);
3164                 if (status != E1000_SUCCESS)
3165                         goto fail;
3166
3167                 e1000_i2c_stop(hw);
3168                 break;
3169
3170 fail:
3171                 e1000_i2c_bus_clear(hw);
3172                 retry++;
3173                 if (retry < max_retry)
3174                         DEBUGOUT("I2C byte write error - Retrying.\n");
3175                 else
3176                         DEBUGOUT("I2C byte write error.\n");
3177         } while (retry < max_retry);
3178
3179         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3180
3181 write_byte_out:
3182
3183         return status;
3184 }
3185
3186 /**
3187  *  e1000_i2c_start - Sets I2C start condition
3188  *  @hw: pointer to hardware structure
3189  *
3190  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3191  **/
3192 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3193 {
3194         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3195
3196         DEBUGFUNC("e1000_i2c_start");
3197
3198         /* Start condition must begin with data and clock high */
3199         e1000_set_i2c_data(hw, &i2cctl, 1);
3200         e1000_raise_i2c_clk(hw, &i2cctl);
3201
3202         /* Setup time for start condition (4.7us) */
3203         usec_delay(E1000_I2C_T_SU_STA);
3204
3205         e1000_set_i2c_data(hw, &i2cctl, 0);
3206
3207         /* Hold time for start condition (4us) */
3208         usec_delay(E1000_I2C_T_HD_STA);
3209
3210         e1000_lower_i2c_clk(hw, &i2cctl);
3211
3212         /* Minimum low period of clock is 4.7 us */
3213         usec_delay(E1000_I2C_T_LOW);
3214
3215 }
3216
3217 /**
3218  *  e1000_i2c_stop - Sets I2C stop condition
3219  *  @hw: pointer to hardware structure
3220  *
3221  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3222  **/
3223 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3224 {
3225         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3226
3227         DEBUGFUNC("e1000_i2c_stop");
3228
3229         /* Stop condition must begin with data low and clock high */
3230         e1000_set_i2c_data(hw, &i2cctl, 0);
3231         e1000_raise_i2c_clk(hw, &i2cctl);
3232
3233         /* Setup time for stop condition (4us) */
3234         usec_delay(E1000_I2C_T_SU_STO);
3235
3236         e1000_set_i2c_data(hw, &i2cctl, 1);
3237
3238         /* bus free time between stop and start (4.7us)*/
3239         usec_delay(E1000_I2C_T_BUF);
3240 }
3241
3242 /**
3243  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3244  *  @hw: pointer to hardware structure
3245  *  @data: data byte to clock in
3246  *
3247  *  Clocks in one byte data via I2C data/clock
3248  **/
3249 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3250 {
3251         s32 i;
3252         bool bit = 0;
3253
3254         DEBUGFUNC("e1000_clock_in_i2c_byte");
3255
3256         *data = 0;
3257         for (i = 7; i >= 0; i--) {
3258                 e1000_clock_in_i2c_bit(hw, &bit);
3259                 *data |= bit << i;
3260         }
3261
3262         return E1000_SUCCESS;
3263 }
3264
3265 /**
3266  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3267  *  @hw: pointer to hardware structure
3268  *  @data: data byte clocked out
3269  *
3270  *  Clocks out one byte data via I2C data/clock
3271  **/
3272 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3273 {
3274         s32 status = E1000_SUCCESS;
3275         s32 i;
3276         u32 i2cctl;
3277         bool bit = 0;
3278
3279         DEBUGFUNC("e1000_clock_out_i2c_byte");
3280
3281         for (i = 7; i >= 0; i--) {
3282                 bit = (data >> i) & 0x1;
3283                 status = e1000_clock_out_i2c_bit(hw, bit);
3284
3285                 if (status != E1000_SUCCESS)
3286                         break;
3287         }
3288
3289         /* Release SDA line (set high) */
3290         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3291
3292         i2cctl |= E1000_I2C_DATA_OE_N;
3293         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3294         E1000_WRITE_FLUSH(hw);
3295
3296         return status;
3297 }
3298
3299 /**
3300  *  e1000_get_i2c_ack - Polls for I2C ACK
3301  *  @hw: pointer to hardware structure
3302  *
3303  *  Clocks in/out one bit via I2C data/clock
3304  **/
3305 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3306 {
3307         s32 status = E1000_SUCCESS;
3308         u32 i = 0;
3309         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3310         u32 timeout = 10;
3311         bool ack = true;
3312
3313         DEBUGFUNC("e1000_get_i2c_ack");
3314
3315         e1000_raise_i2c_clk(hw, &i2cctl);
3316
3317         /* Minimum high period of clock is 4us */
3318         usec_delay(E1000_I2C_T_HIGH);
3319
3320         /* Wait until SCL returns high */
3321         for (i = 0; i < timeout; i++) {
3322                 usec_delay(1);
3323                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3324                 if (i2cctl & E1000_I2C_CLK_IN)
3325                         break;
3326         }
3327         if (!(i2cctl & E1000_I2C_CLK_IN))
3328                 return E1000_ERR_I2C;
3329
3330         ack = e1000_get_i2c_data(&i2cctl);
3331         if (ack) {
3332                 DEBUGOUT("I2C ack was not received.\n");
3333                 status = E1000_ERR_I2C;
3334         }
3335
3336         e1000_lower_i2c_clk(hw, &i2cctl);
3337
3338         /* Minimum low period of clock is 4.7 us */
3339         usec_delay(E1000_I2C_T_LOW);
3340
3341         return status;
3342 }
3343
3344 /**
3345  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3346  *  @hw: pointer to hardware structure
3347  *  @data: read data value
3348  *
3349  *  Clocks in one bit via I2C data/clock
3350  **/
3351 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3352 {
3353         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3354
3355         DEBUGFUNC("e1000_clock_in_i2c_bit");
3356
3357         e1000_raise_i2c_clk(hw, &i2cctl);
3358
3359         /* Minimum high period of clock is 4us */
3360         usec_delay(E1000_I2C_T_HIGH);
3361
3362         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3363         *data = e1000_get_i2c_data(&i2cctl);
3364
3365         e1000_lower_i2c_clk(hw, &i2cctl);
3366
3367         /* Minimum low period of clock is 4.7 us */
3368         usec_delay(E1000_I2C_T_LOW);
3369
3370         return E1000_SUCCESS;
3371 }
3372
3373 /**
3374  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3375  *  @hw: pointer to hardware structure
3376  *  @data: data value to write
3377  *
3378  *  Clocks out one bit via I2C data/clock
3379  **/
3380 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3381 {
3382         s32 status;
3383         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3384
3385         DEBUGFUNC("e1000_clock_out_i2c_bit");
3386
3387         status = e1000_set_i2c_data(hw, &i2cctl, data);
3388         if (status == E1000_SUCCESS) {
3389                 e1000_raise_i2c_clk(hw, &i2cctl);
3390
3391                 /* Minimum high period of clock is 4us */
3392                 usec_delay(E1000_I2C_T_HIGH);
3393
3394                 e1000_lower_i2c_clk(hw, &i2cctl);
3395
3396                 /* Minimum low period of clock is 4.7 us.
3397                  * This also takes care of the data hold time.
3398                  */
3399                 usec_delay(E1000_I2C_T_LOW);
3400         } else {
3401                 status = E1000_ERR_I2C;
3402                 DEBUGOUT1("I2C data was not set to %X\n", data);
3403         }
3404
3405         return status;
3406 }
3407 /**
3408  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3409  *  @hw: pointer to hardware structure
3410  *  @i2cctl: Current value of I2CCTL register
3411  *
3412  *  Raises the I2C clock line '0'->'1'
3413  **/
3414 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3415 {
3416         DEBUGFUNC("e1000_raise_i2c_clk");
3417
3418         *i2cctl |= E1000_I2C_CLK_OUT;
3419         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3420         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3421         E1000_WRITE_FLUSH(hw);
3422
3423         /* SCL rise time (1000ns) */
3424         usec_delay(E1000_I2C_T_RISE);
3425 }
3426
3427 /**
3428  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3429  *  @hw: pointer to hardware structure
3430  *  @i2cctl: Current value of I2CCTL register
3431  *
3432  *  Lowers the I2C clock line '1'->'0'
3433  **/
3434 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3435 {
3436
3437         DEBUGFUNC("e1000_lower_i2c_clk");
3438
3439         *i2cctl &= ~E1000_I2C_CLK_OUT;
3440         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3441         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3442         E1000_WRITE_FLUSH(hw);
3443
3444         /* SCL fall time (300ns) */
3445         usec_delay(E1000_I2C_T_FALL);
3446 }
3447
3448 /**
3449  *  e1000_set_i2c_data - Sets the I2C data bit
3450  *  @hw: pointer to hardware structure
3451  *  @i2cctl: Current value of I2CCTL register
3452  *  @data: I2C data value (0 or 1) to set
3453  *
3454  *  Sets the I2C data bit
3455  **/
3456 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3457 {
3458         s32 status = E1000_SUCCESS;
3459
3460         DEBUGFUNC("e1000_set_i2c_data");
3461
3462         if (data)
3463                 *i2cctl |= E1000_I2C_DATA_OUT;
3464         else
3465                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3466
3467         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3468         *i2cctl |= E1000_I2C_CLK_OE_N;
3469         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3470         E1000_WRITE_FLUSH(hw);
3471
3472         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3473         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3474
3475         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3476         if (data != e1000_get_i2c_data(i2cctl)) {
3477                 status = E1000_ERR_I2C;
3478                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3479         }
3480
3481         return status;
3482 }
3483
3484 /**
3485  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3486  *  @hw: pointer to hardware structure
3487  *  @i2cctl: Current value of I2CCTL register
3488  *
3489  *  Returns the I2C data bit value
3490  **/
3491 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3492 {
3493         bool data;
3494
3495         DEBUGFUNC("e1000_get_i2c_data");
3496
3497         if (*i2cctl & E1000_I2C_DATA_IN)
3498                 data = 1;
3499         else
3500                 data = 0;
3501
3502         return data;
3503 }
3504
3505 /**
3506  *  e1000_i2c_bus_clear - Clears the I2C bus
3507  *  @hw: pointer to hardware structure
3508  *
3509  *  Clears the I2C bus by sending nine clock pulses.
3510  *  Used when data line is stuck low.
3511  **/
3512 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3513 {
3514         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3515         u32 i;
3516
3517         DEBUGFUNC("e1000_i2c_bus_clear");
3518
3519         e1000_i2c_start(hw);
3520
3521         e1000_set_i2c_data(hw, &i2cctl, 1);
3522
3523         for (i = 0; i < 9; i++) {
3524                 e1000_raise_i2c_clk(hw, &i2cctl);
3525
3526                 /* Min high period of clock is 4us */
3527                 usec_delay(E1000_I2C_T_HIGH);
3528
3529                 e1000_lower_i2c_clk(hw, &i2cctl);
3530
3531                 /* Min low period of clock is 4.7us*/
3532                 usec_delay(E1000_I2C_T_LOW);
3533         }
3534
3535         e1000_i2c_start(hw);
3536
3537         /* Put the i2c bus back to default state */
3538         e1000_i2c_stop(hw);
3539 }
3540