1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
40 * 82580 Gigabit Network Connection
41 * I350 Gigabit Network Connection
44 #include "e1000_api.h"
45 #include "e1000_i210.h"
47 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
49 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
55 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
57 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw);
58 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
69 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
71 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
73 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79 u32 offset, u16 data);
80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
86 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
88 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
118 static const u16 e1000_82580_rxpbs_table[] = {
119 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
120 #define E1000_82580_RXPBS_TABLE_SIZE \
121 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
125 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
126 * @hw: pointer to the HW structure
128 * Called to determine if the I2C pins are being used for I2C or as an
129 * external MDIO interface since the two options are mutually exclusive.
131 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
134 bool ext_mdio = false;
136 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
138 switch (hw->mac.type) {
141 reg = E1000_READ_REG(hw, E1000_MDIC);
142 ext_mdio = !!(reg & E1000_MDIC_DEST);
148 reg = E1000_READ_REG(hw, E1000_MDICNFG);
149 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
158 * e1000_init_phy_params_82575 - Init PHY func ptrs.
159 * @hw: pointer to the HW structure
161 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
163 struct e1000_phy_info *phy = &hw->phy;
164 s32 ret_val = E1000_SUCCESS;
167 DEBUGFUNC("e1000_init_phy_params_82575");
169 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
170 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
172 if (hw->phy.media_type != e1000_media_type_copper) {
173 phy->type = e1000_phy_none;
177 phy->ops.power_up = e1000_power_up_phy_copper;
178 phy->ops.power_down = e1000_power_down_phy_copper_82575;
180 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
181 phy->reset_delay_us = 100;
183 phy->ops.acquire = e1000_acquire_phy_82575;
184 phy->ops.check_reset_block = e1000_check_reset_block_generic;
185 phy->ops.commit = e1000_phy_sw_reset_generic;
186 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
187 phy->ops.release = e1000_release_phy_82575;
189 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
191 if (e1000_sgmii_active_82575(hw)) {
192 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
193 ctrl_ext |= E1000_CTRL_I2C_ENA;
195 phy->ops.reset = e1000_phy_hw_reset_generic;
196 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
199 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
200 e1000_reset_mdicnfg_82580(hw);
202 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
203 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
204 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
206 switch (hw->mac.type) {
209 phy->ops.read_reg = e1000_read_phy_reg_82580;
210 phy->ops.write_reg = e1000_write_phy_reg_82580;
214 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
215 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
218 phy->ops.read_reg = e1000_read_phy_reg_igp;
219 phy->ops.write_reg = e1000_write_phy_reg_igp;
223 /* Set phy->phy_addr and phy->id. */
224 ret_val = e1000_get_phy_id_82575(hw);
226 /* Verify phy id and set remaining function pointers */
228 case I347AT4_E_PHY_ID:
229 case M88E1112_E_PHY_ID:
230 case M88E1340M_E_PHY_ID:
231 case M88E1111_I_PHY_ID:
232 phy->type = e1000_phy_m88;
233 phy->ops.check_polarity = e1000_check_polarity_m88;
234 phy->ops.get_info = e1000_get_phy_info_m88;
235 if (phy->id == I347AT4_E_PHY_ID ||
236 phy->id == M88E1112_E_PHY_ID ||
237 phy->id == M88E1340M_E_PHY_ID)
238 phy->ops.get_cable_length =
239 e1000_get_cable_length_m88_gen2;
241 phy->ops.get_cable_length = e1000_get_cable_length_m88;
242 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
244 case IGP03E1000_E_PHY_ID:
245 case IGP04E1000_E_PHY_ID:
246 phy->type = e1000_phy_igp_3;
247 phy->ops.check_polarity = e1000_check_polarity_igp;
248 phy->ops.get_info = e1000_get_phy_info_igp;
249 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
250 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
251 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
252 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
254 case I82580_I_PHY_ID:
256 phy->type = e1000_phy_82580;
257 phy->ops.check_polarity = e1000_check_polarity_82577;
258 phy->ops.force_speed_duplex =
259 e1000_phy_force_speed_duplex_82577;
260 phy->ops.get_cable_length = e1000_get_cable_length_82577;
261 phy->ops.get_info = e1000_get_phy_info_82577;
262 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
263 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
266 phy->type = e1000_phy_i210;
267 phy->ops.check_polarity = e1000_check_polarity_m88;
268 phy->ops.get_info = e1000_get_phy_info_m88;
269 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
270 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
271 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
272 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
275 ret_val = -E1000_ERR_PHY;
284 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
285 * @hw: pointer to the HW structure
287 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
289 struct e1000_nvm_info *nvm = &hw->nvm;
290 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
293 DEBUGFUNC("e1000_init_nvm_params_82575");
295 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
296 E1000_EECD_SIZE_EX_SHIFT);
298 * Added to a constant, "size" becomes the left-shift value
299 * for setting word_size.
301 size += NVM_WORD_SIZE_BASE_SHIFT;
303 /* Just in case size is out of range, cap it to the largest
304 * EEPROM size supported
309 nvm->word_size = 1 << size;
310 if (hw->mac.type < e1000_i210) {
311 nvm->opcode_bits = 8;
314 switch (nvm->override) {
315 case e1000_nvm_override_spi_large:
317 nvm->address_bits = 16;
319 case e1000_nvm_override_spi_small:
321 nvm->address_bits = 8;
324 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
325 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
329 if (nvm->word_size == (1 << 15))
330 nvm->page_size = 128;
332 nvm->type = e1000_nvm_eeprom_spi;
334 nvm->type = e1000_nvm_flash_hw;
336 /* Function Pointers */
337 nvm->ops.acquire = e1000_acquire_nvm_82575;
338 nvm->ops.release = e1000_release_nvm_82575;
339 if (nvm->word_size < (1 << 15))
340 nvm->ops.read = e1000_read_nvm_eerd;
342 nvm->ops.read = e1000_read_nvm_spi;
344 nvm->ops.write = e1000_write_nvm_spi;
345 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
346 nvm->ops.update = e1000_update_nvm_checksum_generic;
347 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
349 /* override generic family function pointers for specific descendants */
350 switch (hw->mac.type) {
352 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
353 nvm->ops.update = e1000_update_nvm_checksum_82580;
356 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
357 nvm->ops.update = e1000_update_nvm_checksum_i350;
363 return E1000_SUCCESS;
367 * e1000_init_mac_params_82575 - Init MAC func ptrs.
368 * @hw: pointer to the HW structure
370 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
372 struct e1000_mac_info *mac = &hw->mac;
373 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
375 DEBUGFUNC("e1000_init_mac_params_82575");
377 /* Derives media type */
378 e1000_get_media_type_82575(hw);
379 /* Set mta register count */
380 mac->mta_reg_count = 128;
381 /* Set uta register count */
382 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
383 /* Set rar entry count */
384 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
385 if (mac->type == e1000_82576)
386 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
387 if (mac->type == e1000_82580)
388 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
389 if (mac->type == e1000_i350) {
390 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
391 /* Enable EEE default settings for i350 */
392 dev_spec->eee_disable = false;
395 /* Set if part includes ASF firmware */
396 mac->asf_firmware_present = true;
398 mac->has_fwsm = true;
399 /* ARC supported; valid only if manageability features are enabled. */
400 mac->arc_subsystem_valid =
401 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
403 /* Function pointers */
405 /* bus type/speed/width */
406 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
408 if (mac->type >= e1000_82580)
409 mac->ops.reset_hw = e1000_reset_hw_82580;
411 mac->ops.reset_hw = e1000_reset_hw_82575;
412 /* hw initialization */
413 mac->ops.init_hw = e1000_init_hw_82575;
415 mac->ops.setup_link = e1000_setup_link_generic;
416 /* physical interface link setup */
417 mac->ops.setup_physical_interface =
418 (hw->phy.media_type == e1000_media_type_copper)
419 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
420 /* physical interface shutdown */
421 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
422 /* physical interface power up */
423 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
425 mac->ops.check_for_link = e1000_check_for_link_82575;
426 /* read mac address */
427 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
428 /* configure collision distance */
429 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
430 /* multicast address update */
431 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
432 if (mac->type == e1000_i350) {
434 mac->ops.write_vfta = e1000_write_vfta_i350;
436 mac->ops.clear_vfta = e1000_clear_vfta_i350;
439 mac->ops.write_vfta = e1000_write_vfta_generic;
441 mac->ops.clear_vfta = e1000_clear_vfta_generic;
443 if (hw->mac.type >= e1000_82580)
444 mac->ops.validate_mdi_setting =
445 e1000_validate_mdi_setting_crossover_generic;
447 mac->ops.id_led_init = e1000_id_led_init_generic;
449 mac->ops.blink_led = e1000_blink_led_generic;
451 mac->ops.setup_led = e1000_setup_led_generic;
453 mac->ops.cleanup_led = e1000_cleanup_led_generic;
454 /* turn on/off LED */
455 mac->ops.led_on = e1000_led_on_generic;
456 mac->ops.led_off = e1000_led_off_generic;
457 /* clear hardware counters */
458 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
460 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
461 /* acquire SW_FW sync */
462 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
463 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
464 if (mac->type >= e1000_i210) {
465 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
466 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
469 /* set lan id for port to determine which phy lock to use */
470 hw->mac.ops.set_lan_id(hw);
472 return E1000_SUCCESS;
476 * e1000_init_function_pointers_82575 - Init func ptrs.
477 * @hw: pointer to the HW structure
479 * Called to initialize all function pointers and parameters.
481 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
483 DEBUGFUNC("e1000_init_function_pointers_82575");
485 hw->mac.ops.init_params = e1000_init_mac_params_82575;
486 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
487 hw->phy.ops.init_params = e1000_init_phy_params_82575;
488 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
492 * e1000_acquire_phy_82575 - Acquire rights to access PHY
493 * @hw: pointer to the HW structure
495 * Acquire access rights to the correct PHY.
497 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
499 u16 mask = E1000_SWFW_PHY0_SM;
501 DEBUGFUNC("e1000_acquire_phy_82575");
503 if (hw->bus.func == E1000_FUNC_1)
504 mask = E1000_SWFW_PHY1_SM;
505 else if (hw->bus.func == E1000_FUNC_2)
506 mask = E1000_SWFW_PHY2_SM;
507 else if (hw->bus.func == E1000_FUNC_3)
508 mask = E1000_SWFW_PHY3_SM;
510 return hw->mac.ops.acquire_swfw_sync(hw, mask);
514 * e1000_release_phy_82575 - Release rights to access PHY
515 * @hw: pointer to the HW structure
517 * A wrapper to release access rights to the correct PHY.
519 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
521 u16 mask = E1000_SWFW_PHY0_SM;
523 DEBUGFUNC("e1000_release_phy_82575");
525 if (hw->bus.func == E1000_FUNC_1)
526 mask = E1000_SWFW_PHY1_SM;
527 else if (hw->bus.func == E1000_FUNC_2)
528 mask = E1000_SWFW_PHY2_SM;
529 else if (hw->bus.func == E1000_FUNC_3)
530 mask = E1000_SWFW_PHY3_SM;
532 hw->mac.ops.release_swfw_sync(hw, mask);
536 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
537 * @hw: pointer to the HW structure
538 * @offset: register offset to be read
539 * @data: pointer to the read data
541 * Reads the PHY register at offset using the serial gigabit media independent
542 * interface and stores the retrieved information in data.
544 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
547 s32 ret_val = -E1000_ERR_PARAM;
549 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
551 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
552 DEBUGOUT1("PHY Address %u is out of range\n", offset);
556 ret_val = hw->phy.ops.acquire(hw);
560 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
562 hw->phy.ops.release(hw);
569 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
570 * @hw: pointer to the HW structure
571 * @offset: register offset to write to
572 * @data: data to write at register offset
574 * Writes the data to PHY register at the offset using the serial gigabit
575 * media independent interface.
577 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
580 s32 ret_val = -E1000_ERR_PARAM;
582 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
584 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
585 DEBUGOUT1("PHY Address %d is out of range\n", offset);
589 ret_val = hw->phy.ops.acquire(hw);
593 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
595 hw->phy.ops.release(hw);
602 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
603 * @hw: pointer to the HW structure
605 * Retrieves the PHY address and ID for both PHY's which do and do not use
608 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
610 struct e1000_phy_info *phy = &hw->phy;
611 s32 ret_val = E1000_SUCCESS;
616 DEBUGFUNC("e1000_get_phy_id_82575");
619 * For SGMII PHYs, we try the list of possible addresses until
620 * we find one that works. For non-SGMII PHYs
621 * (e.g. integrated copper PHYs), an address of 1 should
622 * work. The result of this function should mean phy->phy_addr
623 * and phy->id are set correctly.
625 if (!e1000_sgmii_active_82575(hw)) {
627 ret_val = e1000_get_phy_id(hw);
631 if (e1000_sgmii_uses_mdio_82575(hw)) {
632 switch (hw->mac.type) {
635 mdic = E1000_READ_REG(hw, E1000_MDIC);
636 mdic &= E1000_MDIC_PHY_MASK;
637 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
643 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
644 mdic &= E1000_MDICNFG_PHY_MASK;
645 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
648 ret_val = -E1000_ERR_PHY;
652 ret_val = e1000_get_phy_id(hw);
656 /* Power on sgmii phy if it is disabled */
657 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
658 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
659 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
660 E1000_WRITE_FLUSH(hw);
664 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
665 * Therefore, we need to test 1-7
667 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
668 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
669 if (ret_val == E1000_SUCCESS) {
670 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
673 * At the time of this writing, The M88 part is
674 * the only supported SGMII PHY product.
676 if (phy_id == M88_VENDOR)
679 DEBUGOUT1("PHY address %u was unreadable\n",
684 /* A valid PHY type couldn't be found. */
685 if (phy->addr == 8) {
687 ret_val = -E1000_ERR_PHY;
689 ret_val = e1000_get_phy_id(hw);
692 /* restore previous sfp cage power state */
693 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
700 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
701 * @hw: pointer to the HW structure
703 * Resets the PHY using the serial gigabit media independent interface.
705 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
707 s32 ret_val = E1000_SUCCESS;
709 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
712 * This isn't a true "hard" reset, but is the only reset
713 * available to us at this time.
716 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
718 if (!(hw->phy.ops.write_reg))
722 * SFP documentation requires the following to configure the SPF module
723 * to work on SGMII. No further documentation is given.
725 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
729 ret_val = hw->phy.ops.commit(hw);
736 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
737 * @hw: pointer to the HW structure
738 * @active: true to enable LPLU, false to disable
740 * Sets the LPLU D0 state according to the active flag. When
741 * activating LPLU this function also disables smart speed
742 * and vice versa. LPLU will not be activated unless the
743 * device autonegotiation advertisement meets standards of
744 * either 10 or 10/100 or 10/100/1000 at all duplexes.
745 * This is a function pointer entry point only called by
746 * PHY setup routines.
748 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
750 struct e1000_phy_info *phy = &hw->phy;
751 s32 ret_val = E1000_SUCCESS;
754 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
756 if (!(hw->phy.ops.read_reg))
759 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
764 data |= IGP02E1000_PM_D0_LPLU;
765 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
770 /* When LPLU is enabled, we should disable SmartSpeed */
771 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
773 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
774 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
779 data &= ~IGP02E1000_PM_D0_LPLU;
780 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
783 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
784 * during Dx states where the power conservation is most
785 * important. During driver activity we should enable
786 * SmartSpeed, so performance is maintained.
788 if (phy->smart_speed == e1000_smart_speed_on) {
789 ret_val = phy->ops.read_reg(hw,
790 IGP01E1000_PHY_PORT_CONFIG,
795 data |= IGP01E1000_PSCFR_SMART_SPEED;
796 ret_val = phy->ops.write_reg(hw,
797 IGP01E1000_PHY_PORT_CONFIG,
801 } else if (phy->smart_speed == e1000_smart_speed_off) {
802 ret_val = phy->ops.read_reg(hw,
803 IGP01E1000_PHY_PORT_CONFIG,
808 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
809 ret_val = phy->ops.write_reg(hw,
810 IGP01E1000_PHY_PORT_CONFIG,
822 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
823 * @hw: pointer to the HW structure
824 * @active: true to enable LPLU, false to disable
826 * Sets the LPLU D0 state according to the active flag. When
827 * activating LPLU this function also disables smart speed
828 * and vice versa. LPLU will not be activated unless the
829 * device autonegotiation advertisement meets standards of
830 * either 10 or 10/100 or 10/100/1000 at all duplexes.
831 * This is a function pointer entry point only called by
832 * PHY setup routines.
834 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
836 struct e1000_phy_info *phy = &hw->phy;
837 s32 ret_val = E1000_SUCCESS;
840 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
842 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
845 data |= E1000_82580_PM_D0_LPLU;
847 /* When LPLU is enabled, we should disable SmartSpeed */
848 data &= ~E1000_82580_PM_SPD;
850 data &= ~E1000_82580_PM_D0_LPLU;
853 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
854 * during Dx states where the power conservation is most
855 * important. During driver activity we should enable
856 * SmartSpeed, so performance is maintained.
858 if (phy->smart_speed == e1000_smart_speed_on)
859 data |= E1000_82580_PM_SPD;
860 else if (phy->smart_speed == e1000_smart_speed_off)
861 data &= ~E1000_82580_PM_SPD;
864 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
869 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
870 * @hw: pointer to the HW structure
871 * @active: boolean used to enable/disable lplu
873 * Success returns 0, Failure returns 1
875 * The low power link up (lplu) state is set to the power management level D3
876 * and SmartSpeed is disabled when active is true, else clear lplu for D3
877 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
878 * is used during Dx states where the power conservation is most important.
879 * During driver activity, SmartSpeed should be enabled so performance is
882 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
884 struct e1000_phy_info *phy = &hw->phy;
885 s32 ret_val = E1000_SUCCESS;
888 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
890 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
893 data &= ~E1000_82580_PM_D3_LPLU;
895 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
896 * during Dx states where the power conservation is most
897 * important. During driver activity we should enable
898 * SmartSpeed, so performance is maintained.
900 if (phy->smart_speed == e1000_smart_speed_on)
901 data |= E1000_82580_PM_SPD;
902 else if (phy->smart_speed == e1000_smart_speed_off)
903 data &= ~E1000_82580_PM_SPD;
904 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
905 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
906 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
907 data |= E1000_82580_PM_D3_LPLU;
908 /* When LPLU is enabled, we should disable SmartSpeed */
909 data &= ~E1000_82580_PM_SPD;
912 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
917 * e1000_acquire_nvm_82575 - Request for access to EEPROM
918 * @hw: pointer to the HW structure
920 * Acquire the necessary semaphores for exclusive access to the EEPROM.
921 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
922 * Return successful if access grant bit set, else clear the request for
923 * EEPROM access and return -E1000_ERR_NVM (-1).
925 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
929 DEBUGFUNC("e1000_acquire_nvm_82575");
931 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
936 * Check if there is some access
937 * error this access may hook on
939 if (hw->mac.type == e1000_i350) {
940 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
941 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
942 E1000_EECD_TIMEOUT)) {
943 /* Clear all access error flags */
944 E1000_WRITE_REG(hw, E1000_EECD, eecd |
945 E1000_EECD_ERROR_CLR);
946 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
949 if (hw->mac.type == e1000_82580) {
950 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
951 if (eecd & E1000_EECD_BLOCKED) {
952 /* Clear access error flag */
953 E1000_WRITE_REG(hw, E1000_EECD, eecd |
955 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
960 ret_val = e1000_acquire_nvm_generic(hw);
962 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
969 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
970 * @hw: pointer to the HW structure
972 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
973 * then release the semaphores acquired.
975 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
977 DEBUGFUNC("e1000_release_nvm_82575");
979 e1000_release_nvm_generic(hw);
981 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
985 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
986 * @hw: pointer to the HW structure
987 * @mask: specifies which semaphore to acquire
989 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
990 * will also specify which port we're acquiring the lock for.
992 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
996 u32 fwmask = mask << 16;
997 s32 ret_val = E1000_SUCCESS;
998 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1000 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1002 while (i < timeout) {
1003 if (e1000_get_hw_semaphore_generic(hw)) {
1004 ret_val = -E1000_ERR_SWFW_SYNC;
1008 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1009 if (!(swfw_sync & (fwmask | swmask)))
1013 * Firmware currently using resource (fwmask)
1014 * or other software thread using resource (swmask)
1016 e1000_put_hw_semaphore_generic(hw);
1022 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1023 ret_val = -E1000_ERR_SWFW_SYNC;
1027 swfw_sync |= swmask;
1028 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1030 e1000_put_hw_semaphore_generic(hw);
1037 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1038 * @hw: pointer to the HW structure
1039 * @mask: specifies which semaphore to acquire
1041 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1042 * will also specify which port we're releasing the lock for.
1044 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1048 DEBUGFUNC("e1000_release_swfw_sync_82575");
1050 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1053 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1055 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1057 e1000_put_hw_semaphore_generic(hw);
1061 * e1000_get_cfg_done_82575 - Read config done bit
1062 * @hw: pointer to the HW structure
1064 * Read the management control register for the config done bit for
1065 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1066 * to read the config done bit, so an error is *ONLY* logged and returns
1067 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1068 * would not be able to be reset or change link.
1070 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1072 s32 timeout = PHY_CFG_TIMEOUT;
1073 s32 ret_val = E1000_SUCCESS;
1074 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1076 DEBUGFUNC("e1000_get_cfg_done_82575");
1078 if (hw->bus.func == E1000_FUNC_1)
1079 mask = E1000_NVM_CFG_DONE_PORT_1;
1080 else if (hw->bus.func == E1000_FUNC_2)
1081 mask = E1000_NVM_CFG_DONE_PORT_2;
1082 else if (hw->bus.func == E1000_FUNC_3)
1083 mask = E1000_NVM_CFG_DONE_PORT_3;
1085 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1091 DEBUGOUT("MNG configuration cycle has not completed.\n");
1093 /* If EEPROM is not marked present, init the PHY manually */
1094 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1095 (hw->phy.type == e1000_phy_igp_3))
1096 e1000_phy_init_script_igp3(hw);
1102 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1103 * @hw: pointer to the HW structure
1104 * @speed: stores the current speed
1105 * @duplex: stores the current duplex
1107 * This is a wrapper function, if using the serial gigabit media independent
1108 * interface, use PCS to retrieve the link speed and duplex information.
1109 * Otherwise, use the generic function to get the link speed and duplex info.
1111 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1116 DEBUGFUNC("e1000_get_link_up_info_82575");
1118 if (hw->phy.media_type != e1000_media_type_copper)
1119 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1122 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1129 * e1000_check_for_link_82575 - Check for link
1130 * @hw: pointer to the HW structure
1132 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1133 * use the generic interface for determining link.
1135 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1140 DEBUGFUNC("e1000_check_for_link_82575");
1142 if (hw->phy.media_type != e1000_media_type_copper) {
1143 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1146 * Use this flag to determine if link needs to be checked or
1147 * not. If we have link clear the flag so that we do not
1148 * continue to check for link.
1150 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1153 * Configure Flow Control now that Auto-Neg has completed.
1154 * First, we need to restore the desired flow control
1155 * settings because we may have had to re-autoneg with a
1156 * different link partner.
1158 ret_val = e1000_config_fc_after_link_up_generic(hw);
1160 DEBUGOUT("Error configuring flow control\n");
1162 ret_val = e1000_check_for_copper_link_generic(hw);
1169 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1170 * @hw: pointer to the HW structure
1172 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1176 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1178 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1179 !e1000_sgmii_active_82575(hw))
1182 /* Enable PCS to turn on link */
1183 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1184 reg |= E1000_PCS_CFG_PCS_EN;
1185 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1187 /* Power up the laser */
1188 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1189 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1190 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1192 /* flush the write to verify completion */
1193 E1000_WRITE_FLUSH(hw);
1198 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1199 * @hw: pointer to the HW structure
1200 * @speed: stores the current speed
1201 * @duplex: stores the current duplex
1203 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1204 * duplex, then store the values in the pointers provided.
1206 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1207 u16 *speed, u16 *duplex)
1209 struct e1000_mac_info *mac = &hw->mac;
1212 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1215 * Read the PCS Status register for link state. For non-copper mode,
1216 * the status register is not accurate. The PCS status register is
1219 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1222 * The link up bit determines when link is up on autoneg.
1224 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1225 mac->serdes_has_link = true;
1227 /* Detect and store PCS speed */
1228 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1229 *speed = SPEED_1000;
1230 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1235 /* Detect and store PCS duplex */
1236 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1237 *duplex = FULL_DUPLEX;
1239 *duplex = HALF_DUPLEX;
1242 mac->serdes_has_link = false;
1247 return E1000_SUCCESS;
1251 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1252 * @hw: pointer to the HW structure
1254 * In the case of serdes shut down sfp and PCS on driver unload
1255 * when management pass thru is not enabled.
1257 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1261 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1263 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1264 !e1000_sgmii_active_82575(hw))
1267 if (!e1000_enable_mng_pass_thru(hw)) {
1268 /* Disable PCS to turn off link */
1269 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1270 reg &= ~E1000_PCS_CFG_PCS_EN;
1271 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1273 /* shutdown the laser */
1274 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1275 reg |= E1000_CTRL_EXT_SDP3_DATA;
1276 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1278 /* flush the write to verify completion */
1279 E1000_WRITE_FLUSH(hw);
1287 * e1000_reset_hw_82575 - Reset hardware
1288 * @hw: pointer to the HW structure
1290 * This resets the hardware into a known state.
1292 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1297 DEBUGFUNC("e1000_reset_hw_82575");
1300 * Prevent the PCI-E bus from sticking if there is no TLP connection
1301 * on the last TLP read/write transaction when MAC is reset.
1303 ret_val = e1000_disable_pcie_master_generic(hw);
1305 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1307 /* set the completion timeout for interface */
1308 ret_val = e1000_set_pcie_completion_timeout(hw);
1310 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1312 DEBUGOUT("Masking off all interrupts\n");
1313 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1315 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1316 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1317 E1000_WRITE_FLUSH(hw);
1321 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1323 DEBUGOUT("Issuing a global reset to MAC\n");
1324 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1326 ret_val = e1000_get_auto_rd_done_generic(hw);
1329 * When auto config read does not complete, do not
1330 * return with an error. This can happen in situations
1331 * where there is no eeprom and prevents getting link.
1333 DEBUGOUT("Auto Read Done did not complete\n");
1336 /* If EEPROM is not present, run manual init scripts */
1337 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1338 e1000_reset_init_script_82575(hw);
1340 /* Clear any pending interrupt events. */
1341 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1342 E1000_READ_REG(hw, E1000_ICR);
1344 /* Install any alternate MAC address into RAR0 */
1345 ret_val = e1000_check_alt_mac_addr_generic(hw);
1351 * e1000_init_hw_82575 - Initialize hardware
1352 * @hw: pointer to the HW structure
1354 * This inits the hardware readying it for operation.
1356 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1358 struct e1000_mac_info *mac = &hw->mac;
1360 u16 i, rar_count = mac->rar_entry_count;
1362 DEBUGFUNC("e1000_init_hw_82575");
1364 /* Initialize identification LED */
1365 ret_val = mac->ops.id_led_init(hw);
1367 DEBUGOUT("Error initializing identification LED\n");
1368 /* This is not fatal and we should not stop init due to this */
1371 /* Disabling VLAN filtering */
1372 DEBUGOUT("Initializing the IEEE VLAN\n");
1373 mac->ops.clear_vfta(hw);
1375 /* Setup the receive address */
1376 e1000_init_rx_addrs_generic(hw, rar_count);
1378 /* Zero out the Multicast HASH table */
1379 DEBUGOUT("Zeroing the MTA\n");
1380 for (i = 0; i < mac->mta_reg_count; i++)
1381 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1383 /* Zero out the Unicast HASH table */
1384 DEBUGOUT("Zeroing the UTA\n");
1385 for (i = 0; i < mac->uta_reg_count; i++)
1386 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1388 /* Setup link and flow control */
1389 ret_val = mac->ops.setup_link(hw);
1391 /* Set the default MTU size */
1392 hw->dev_spec._82575.mtu = 1500;
1395 * Clear all of the statistics registers (clear on read). It is
1396 * important that we do this after we have tried to establish link
1397 * because the symbol error count will increment wildly if there
1400 e1000_clear_hw_cntrs_82575(hw);
1406 * e1000_setup_copper_link_82575 - Configure copper link settings
1407 * @hw: pointer to the HW structure
1409 * Configures the link for auto-neg or forced speed and duplex. Then we check
1410 * for link, once link is established calls to configure collision distance
1411 * and flow control are called.
1413 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1419 DEBUGFUNC("e1000_setup_copper_link_82575");
1421 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1422 ctrl |= E1000_CTRL_SLU;
1423 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1424 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1426 /* Clear Go Link Disconnect bit */
1427 if (hw->mac.type >= e1000_82580) {
1428 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1429 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1430 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1433 ret_val = e1000_setup_serdes_link_82575(hw);
1437 if (e1000_sgmii_active_82575(hw)) {
1438 /* allow time for SFP cage time to power up phy */
1441 ret_val = hw->phy.ops.reset(hw);
1443 DEBUGOUT("Error resetting the PHY.\n");
1447 switch (hw->phy.type) {
1448 case e1000_phy_i210:
1450 if (hw->phy.id == I347AT4_E_PHY_ID ||
1451 hw->phy.id == M88E1112_E_PHY_ID ||
1452 hw->phy.id == M88E1340M_E_PHY_ID)
1453 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1455 ret_val = e1000_copper_link_setup_m88(hw);
1457 case e1000_phy_igp_3:
1458 ret_val = e1000_copper_link_setup_igp(hw);
1460 case e1000_phy_82580:
1461 ret_val = e1000_copper_link_setup_82577(hw);
1464 ret_val = -E1000_ERR_PHY;
1471 ret_val = e1000_setup_copper_link_generic(hw);
1477 * e1000_setup_serdes_link_82575 - Setup link for serdes
1478 * @hw: pointer to the HW structure
1480 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1481 * used on copper connections where the serialized gigabit media independent
1482 * interface (sgmii), or serdes fiber is being used. Configures the link
1483 * for auto-negotiation or forces speed/duplex.
1485 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1487 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1489 s32 ret_val = E1000_SUCCESS;
1492 DEBUGFUNC("e1000_setup_serdes_link_82575");
1494 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1495 !e1000_sgmii_active_82575(hw))
1499 * On the 82575, SerDes loopback mode persists until it is
1500 * explicitly turned off or a power cycle is performed. A read to
1501 * the register does not indicate its status. Therefore, we ensure
1502 * loopback mode is disabled during initialization.
1504 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1506 /* power on the sfp cage if present */
1507 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1508 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1509 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1511 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1512 ctrl_reg |= E1000_CTRL_SLU;
1514 /* set both sw defined pins on 82575/82576*/
1515 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1516 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1518 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1520 /* default pcs_autoneg to the same setting as mac autoneg */
1521 pcs_autoneg = hw->mac.autoneg;
1523 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1524 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1525 /* sgmii mode lets the phy handle forcing speed/duplex */
1527 /* autoneg time out should be disabled for SGMII mode */
1528 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1530 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1531 /* disable PCS autoneg and support parallel detect only */
1532 pcs_autoneg = false;
1533 /* fall through to default case */
1535 if (hw->mac.type == e1000_82575 ||
1536 hw->mac.type == e1000_82576) {
1537 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1539 DEBUGOUT("NVM Read Error\n");
1543 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1544 pcs_autoneg = false;
1548 * non-SGMII modes only supports a speed of 1000/Full for the
1549 * link so it is best to just force the MAC and let the pcs
1550 * link either autoneg or be forced to 1000/Full
1552 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1553 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1555 /* set speed of 1000/Full if speed/duplex is forced */
1556 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1560 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1563 * New SerDes mode allows for forcing speed or autonegotiating speed
1564 * at 1gb. Autoneg should be default set by most drivers. This is the
1565 * mode that will be compatible with older link partners and switches.
1566 * However, both are supported by the hardware and some drivers/tools.
1568 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1569 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1572 /* Set PCS register for autoneg */
1573 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1574 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1576 /* Disable force flow control for autoneg */
1577 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1579 /* Configure flow control advertisement for autoneg */
1580 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1581 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1583 switch (hw->fc.requested_mode) {
1585 case e1000_fc_rx_pause:
1586 anadv_reg |= E1000_TXCW_ASM_DIR;
1587 anadv_reg |= E1000_TXCW_PAUSE;
1589 case e1000_fc_tx_pause:
1590 anadv_reg |= E1000_TXCW_ASM_DIR;
1596 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1598 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1600 /* Set PCS register for forced link */
1601 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1603 /* Force flow control for forced link */
1604 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1606 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1609 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1611 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1612 e1000_force_mac_fc_generic(hw);
1618 * e1000_get_media_type_82575 - derives current media type.
1619 * @hw: pointer to the HW structure
1621 * The media type is chosen reflecting few settings.
1622 * The following are taken into account:
1623 * - link mode set in the current port Init Control Word #3
1624 * - current link mode settings in CSR register
1625 * - MDIO vs. I2C PHY control interface chosen
1626 * - SFP module media type
1628 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1631 s32 ret_val = E1000_ERR_CONFIG;
1632 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1634 u32 current_link_mode = 0;
1635 u16 init_ctrl_wd_3 = 0;
1636 u8 init_ctrl_wd_3_offset = 0;
1637 u8 init_ctrl_wd_3_bit_offset = 0;
1639 /* Set internal phy as default */
1640 dev_spec->sgmii_active = false;
1641 dev_spec->module_plugged = false;
1644 * Check if NVM access method is attached already.
1645 * If it is then Init Control Word #3 is considered
1646 * otherwise runtime CSR register content is taken.
1649 /* Get CSR setting */
1650 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1652 /* Get link mode setting */
1653 if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
1654 /* Take link mode from EEPROM */
1657 * Get LAN port ID to derive its
1658 * adequate Init Control Word #3
1660 lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
1661 E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
1663 * Derive Init Control Word #3 offset
1664 * and mask to pick up link mode setting.
1666 if (hw->mac.type < e1000_82580) {
1667 init_ctrl_wd_3_offset = lan_id ?
1668 NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
1669 init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
1671 init_ctrl_wd_3_offset =
1672 NVM_82580_LAN_FUNC_OFFSET(lan_id) +
1673 NVM_INIT_CONTROL3_PORT_A;
1674 init_ctrl_wd_3_bit_offset =
1675 NVM_WORD24_82580_LNK_MODE_OFFSET;
1677 /* Read Init Control Word #3*/
1678 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
1681 * Align link mode bits to
1682 * their CTRL_EXT location.
1684 current_link_mode = init_ctrl_wd_3;
1685 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1686 init_ctrl_wd_3_bit_offset);
1687 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
1690 * Switch to CSR for all but internal PHY.
1692 if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII)
1693 /* Take link mode from CSR */
1694 current_link_mode = ctrl_ext &
1695 E1000_CTRL_EXT_LINK_MODE_MASK;
1697 /* Take link mode from CSR */
1698 current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1701 switch (current_link_mode) {
1703 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1704 hw->phy.media_type = e1000_media_type_internal_serdes;
1705 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
1707 case E1000_CTRL_EXT_LINK_MODE_GMII:
1708 hw->phy.media_type = e1000_media_type_copper;
1709 current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
1711 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1712 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1713 /* Get phy control interface type set (MDIO vs. I2C)*/
1714 if (e1000_sgmii_uses_mdio_82575(hw)) {
1715 hw->phy.media_type = e1000_media_type_copper;
1716 dev_spec->sgmii_active = true;
1717 current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
1719 ret_val = e1000_set_sfp_media_type_82575(hw);
1720 if (ret_val != E1000_SUCCESS)
1722 if (hw->phy.media_type ==
1723 e1000_media_type_internal_serdes) {
1724 /* Keep Link Mode as SGMII for 100BaseFX */
1725 if (!dev_spec->eth_flags.e100_base_fx) {
1727 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1729 } else if (hw->phy.media_type ==
1730 e1000_media_type_copper) {
1732 E1000_CTRL_EXT_LINK_MODE_SGMII;
1737 DEBUGOUT("Link mode mask doesn't fit bit field size\n");
1741 * Do not change current link mode setting
1742 * if media type is fibre or has not been
1745 if ((hw->phy.media_type != e1000_media_type_unknown) &&
1746 (hw->phy.media_type != e1000_media_type_fiber)) {
1747 /* Update link mode */
1748 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1749 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
1753 ret_val = E1000_SUCCESS;
1756 * If media type was not identified then return media type
1757 * defined by the CTRL_EXT settings.
1759 if (hw->phy.media_type == e1000_media_type_unknown) {
1760 if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
1761 hw->phy.media_type = e1000_media_type_copper;
1763 hw->phy.media_type = e1000_media_type_internal_serdes;
1770 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1771 * @hw: pointer to the HW structure
1773 * The media type is chosen based on SFP module.
1774 * compatibility flags retrieved from SFP ID EEPROM.
1776 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1778 s32 ret_val = E1000_ERR_CONFIG;
1780 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1781 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1782 u8 tranceiver_type = 0;
1785 /* Turn I2C interface ON and power on sfp cage */
1786 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1787 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1788 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1790 E1000_WRITE_FLUSH(hw);
1792 /* Read SFP module data */
1794 ret_val = e1000_read_sfp_data_byte(hw,
1795 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1797 if (ret_val == E1000_SUCCESS)
1802 if (ret_val != E1000_SUCCESS)
1804 ret_val = e1000_read_sfp_data_byte(hw,
1805 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1807 if (ret_val != E1000_SUCCESS)
1810 * Check if there is some SFP
1811 * module plugged and powered
1813 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1814 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1815 dev_spec->module_plugged = true;
1816 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1817 hw->phy.media_type = e1000_media_type_internal_serdes;
1818 } else if (eth_flags->e100_base_fx) {
1819 dev_spec->sgmii_active = true;
1820 hw->phy.media_type = e1000_media_type_internal_serdes;
1821 } else if (eth_flags->e1000_base_t) {
1822 dev_spec->sgmii_active = true;
1823 hw->phy.media_type = e1000_media_type_copper;
1825 hw->phy.media_type = e1000_media_type_unknown;
1826 DEBUGOUT("PHY module has not been recognized\n");
1830 hw->phy.media_type = e1000_media_type_unknown;
1832 ret_val = E1000_SUCCESS;
1834 /* Restore I2C interface setting */
1835 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1840 * e1000_valid_led_default_82575 - Verify a valid default LED config
1841 * @hw: pointer to the HW structure
1842 * @data: pointer to the NVM (EEPROM)
1844 * Read the EEPROM for the current default LED configuration. If the
1845 * LED configuration is not valid, set to a valid LED configuration.
1847 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1851 DEBUGFUNC("e1000_valid_led_default_82575");
1853 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1855 DEBUGOUT("NVM Read Error\n");
1859 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1860 switch (hw->phy.media_type) {
1861 case e1000_media_type_internal_serdes:
1862 *data = ID_LED_DEFAULT_82575_SERDES;
1864 case e1000_media_type_copper:
1866 *data = ID_LED_DEFAULT;
1875 * e1000_sgmii_active_82575 - Return sgmii state
1876 * @hw: pointer to the HW structure
1878 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1879 * which can be enabled for use in the embedded applications. Simply
1880 * return the current state of the sgmii interface.
1882 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1884 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1885 return dev_spec->sgmii_active;
1889 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1890 * @hw: pointer to the HW structure
1892 * Inits recommended HW defaults after a reset when there is no EEPROM
1893 * detected. This is only for the 82575.
1895 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1897 DEBUGFUNC("e1000_reset_init_script_82575");
1899 if (hw->mac.type == e1000_82575) {
1900 DEBUGOUT("Running reset init script for 82575\n");
1901 /* SerDes configuration via SERDESCTRL */
1902 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1903 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1904 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1905 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1907 /* CCM configuration via CCMCTL register */
1908 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1909 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1911 /* PCIe lanes configuration */
1912 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1913 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1914 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1915 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1917 /* PCIe PLL Configuration */
1918 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1919 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1920 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1923 return E1000_SUCCESS;
1927 * e1000_read_mac_addr_82575 - Read device MAC address
1928 * @hw: pointer to the HW structure
1930 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1932 s32 ret_val = E1000_SUCCESS;
1934 DEBUGFUNC("e1000_read_mac_addr_82575");
1937 * If there's an alternate MAC address place it in RAR0
1938 * so that it will override the Si installed default perm
1941 ret_val = e1000_check_alt_mac_addr_generic(hw);
1945 ret_val = e1000_read_mac_addr_generic(hw);
1952 * e1000_config_collision_dist_82575 - Configure collision distance
1953 * @hw: pointer to the HW structure
1955 * Configures the collision distance to the default value and is used
1956 * during link setup.
1958 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1962 DEBUGFUNC("e1000_config_collision_dist_82575");
1964 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1966 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1967 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1969 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1970 E1000_WRITE_FLUSH(hw);
1974 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1975 * @hw: pointer to the HW structure
1977 * In the case of a PHY power down to save power, or to turn off link during a
1978 * driver unload, or wake on lan is not enabled, remove the link.
1980 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1982 struct e1000_phy_info *phy = &hw->phy;
1984 if (!(phy->ops.check_reset_block))
1987 /* If the management interface is not enabled, then power down */
1988 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1989 e1000_power_down_phy_copper(hw);
1995 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1996 * @hw: pointer to the HW structure
1998 * Clears the hardware counters by reading the counter registers.
2000 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2002 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2004 e1000_clear_hw_cntrs_base_generic(hw);
2006 E1000_READ_REG(hw, E1000_PRC64);
2007 E1000_READ_REG(hw, E1000_PRC127);
2008 E1000_READ_REG(hw, E1000_PRC255);
2009 E1000_READ_REG(hw, E1000_PRC511);
2010 E1000_READ_REG(hw, E1000_PRC1023);
2011 E1000_READ_REG(hw, E1000_PRC1522);
2012 E1000_READ_REG(hw, E1000_PTC64);
2013 E1000_READ_REG(hw, E1000_PTC127);
2014 E1000_READ_REG(hw, E1000_PTC255);
2015 E1000_READ_REG(hw, E1000_PTC511);
2016 E1000_READ_REG(hw, E1000_PTC1023);
2017 E1000_READ_REG(hw, E1000_PTC1522);
2019 E1000_READ_REG(hw, E1000_ALGNERRC);
2020 E1000_READ_REG(hw, E1000_RXERRC);
2021 E1000_READ_REG(hw, E1000_TNCRS);
2022 E1000_READ_REG(hw, E1000_CEXTERR);
2023 E1000_READ_REG(hw, E1000_TSCTC);
2024 E1000_READ_REG(hw, E1000_TSCTFC);
2026 E1000_READ_REG(hw, E1000_MGTPRC);
2027 E1000_READ_REG(hw, E1000_MGTPDC);
2028 E1000_READ_REG(hw, E1000_MGTPTC);
2030 E1000_READ_REG(hw, E1000_IAC);
2031 E1000_READ_REG(hw, E1000_ICRXOC);
2033 E1000_READ_REG(hw, E1000_ICRXPTC);
2034 E1000_READ_REG(hw, E1000_ICRXATC);
2035 E1000_READ_REG(hw, E1000_ICTXPTC);
2036 E1000_READ_REG(hw, E1000_ICTXATC);
2037 E1000_READ_REG(hw, E1000_ICTXQEC);
2038 E1000_READ_REG(hw, E1000_ICTXQMTC);
2039 E1000_READ_REG(hw, E1000_ICRXDMTC);
2041 E1000_READ_REG(hw, E1000_CBTMPC);
2042 E1000_READ_REG(hw, E1000_HTDPMC);
2043 E1000_READ_REG(hw, E1000_CBRMPC);
2044 E1000_READ_REG(hw, E1000_RPTHC);
2045 E1000_READ_REG(hw, E1000_HGPTC);
2046 E1000_READ_REG(hw, E1000_HTCBDPC);
2047 E1000_READ_REG(hw, E1000_HGORCL);
2048 E1000_READ_REG(hw, E1000_HGORCH);
2049 E1000_READ_REG(hw, E1000_HGOTCL);
2050 E1000_READ_REG(hw, E1000_HGOTCH);
2051 E1000_READ_REG(hw, E1000_LENERRS);
2053 /* This register should not be read in copper configurations */
2054 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2055 e1000_sgmii_active_82575(hw))
2056 E1000_READ_REG(hw, E1000_SCVPC);
2060 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2061 * @hw: pointer to the HW structure
2063 * After rx enable if managability is enabled then there is likely some
2064 * bad data at the start of the fifo and possibly in the DMA fifo. This
2065 * function clears the fifos and flushes any packets that came in as rx was
2068 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2070 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2073 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2074 if (hw->mac.type != e1000_82575 ||
2075 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2078 /* Disable all Rx queues */
2079 for (i = 0; i < 4; i++) {
2080 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2081 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2082 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2084 /* Poll all queues to verify they have shut down */
2085 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2088 for (i = 0; i < 4; i++)
2089 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2090 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2095 DEBUGOUT("Queue disable timed out after 10ms\n");
2097 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2098 * incoming packets are rejected. Set enable and wait 2ms so that
2099 * any packet that was coming in as RCTL.EN was set is flushed
2101 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2102 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2104 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2105 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2107 rctl = E1000_READ_REG(hw, E1000_RCTL);
2108 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2109 temp_rctl |= E1000_RCTL_LPE;
2111 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2112 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2113 E1000_WRITE_FLUSH(hw);
2116 /* Enable Rx queues that were previously enabled and restore our
2119 for (i = 0; i < 4; i++)
2120 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2121 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2122 E1000_WRITE_FLUSH(hw);
2124 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2125 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2127 /* Flush receive errors generated by workaround */
2128 E1000_READ_REG(hw, E1000_ROC);
2129 E1000_READ_REG(hw, E1000_RNBC);
2130 E1000_READ_REG(hw, E1000_MPC);
2134 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2135 * @hw: pointer to the HW structure
2137 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2138 * however the hardware default for these parts is 500us to 1ms which is less
2139 * than the 10ms recommended by the pci-e spec. To address this we need to
2140 * increase the value to either 10ms to 200ms for capability version 1 config,
2141 * or 16ms to 55ms for version 2.
2143 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2145 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2146 s32 ret_val = E1000_SUCCESS;
2149 /* only take action if timeout value is defaulted to 0 */
2150 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2154 * if capababilities version is type 1 we can write the
2155 * timeout of 10ms to 200ms through the GCR register
2157 if (!(gcr & E1000_GCR_CAP_VER2)) {
2158 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2163 * for version 2 capabilities we need to write the config space
2164 * directly in order to set the completion timeout value for
2167 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2172 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2174 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2177 /* disable completion timeout resend */
2178 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2180 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2185 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2186 * @hw: pointer to the hardware struct
2187 * @enable: state to enter, either enabled or disabled
2188 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2190 * enables/disables L2 switch anti-spoofing functionality.
2192 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2196 switch (hw->mac.type) {
2198 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2200 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2201 E1000_DTXSWC_VLAN_SPOOF_MASK);
2202 /* The PF can spoof - it has to in order to
2203 * support emulation mode NICs */
2204 dtxswc ^= (1 << pf | 1 << (pf +
2205 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2207 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2208 E1000_DTXSWC_VLAN_SPOOF_MASK);
2210 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2213 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2215 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2216 E1000_DTXSWC_VLAN_SPOOF_MASK);
2217 /* The PF can spoof - it has to in order to
2218 * support emulation mode NICs
2220 dtxswc ^= (1 << pf | 1 << (pf +
2221 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2223 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2224 E1000_DTXSWC_VLAN_SPOOF_MASK);
2226 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2233 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2234 * @hw: pointer to the hardware struct
2235 * @enable: state to enter, either enabled or disabled
2237 * enables/disables L2 switch loopback functionality.
2239 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2243 switch (hw->mac.type) {
2245 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2247 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2249 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2250 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2253 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2255 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2257 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2258 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2261 /* Currently no other hardware supports loopback */
2269 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2270 * @hw: pointer to the hardware struct
2271 * @enable: state to enter, either enabled or disabled
2273 * enables/disables replication of packets across multiple pools.
2275 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2277 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2280 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2282 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2284 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2288 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2289 * @hw: pointer to the HW structure
2290 * @offset: register offset to be read
2291 * @data: pointer to the read data
2293 * Reads the MDI control register in the PHY at offset and stores the
2294 * information read to data.
2296 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2300 DEBUGFUNC("e1000_read_phy_reg_82580");
2302 ret_val = hw->phy.ops.acquire(hw);
2306 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2308 hw->phy.ops.release(hw);
2315 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2316 * @hw: pointer to the HW structure
2317 * @offset: register offset to write to
2318 * @data: data to write to register at offset
2320 * Writes data to MDI control register in the PHY at offset.
2322 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2326 DEBUGFUNC("e1000_write_phy_reg_82580");
2328 ret_val = hw->phy.ops.acquire(hw);
2332 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2334 hw->phy.ops.release(hw);
2341 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2342 * @hw: pointer to the HW structure
2344 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2345 * the values found in the EEPROM. This addresses an issue in which these
2346 * bits are not restored from EEPROM after reset.
2348 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2350 s32 ret_val = E1000_SUCCESS;
2354 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2356 if (hw->mac.type != e1000_82580)
2358 if (!e1000_sgmii_active_82575(hw))
2361 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2362 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2365 DEBUGOUT("NVM Read Error\n");
2369 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2370 if (nvm_data & NVM_WORD24_EXT_MDIO)
2371 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2372 if (nvm_data & NVM_WORD24_COM_MDIO)
2373 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2374 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2380 * e1000_reset_hw_82580 - Reset hardware
2381 * @hw: pointer to the HW structure
2383 * This resets function or entire device (all ports, etc.)
2386 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2388 s32 ret_val = E1000_SUCCESS;
2389 /* BH SW mailbox bit in SW_FW_SYNC */
2390 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2392 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2394 DEBUGFUNC("e1000_reset_hw_82580");
2396 hw->dev_spec._82575.global_device_reset = false;
2398 /* Get current control state. */
2399 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2402 * Prevent the PCI-E bus from sticking if there is no TLP connection
2403 * on the last TLP read/write transaction when MAC is reset.
2405 ret_val = e1000_disable_pcie_master_generic(hw);
2407 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2409 DEBUGOUT("Masking off all interrupts\n");
2410 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2411 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2412 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2413 E1000_WRITE_FLUSH(hw);
2417 /* Determine whether or not a global dev reset is requested */
2418 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2420 global_device_reset = false;
2422 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2423 E1000_STAT_DEV_RST_SET))
2424 ctrl |= E1000_CTRL_DEV_RST;
2426 ctrl |= E1000_CTRL_RST;
2428 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2429 E1000_WRITE_FLUSH(hw);
2431 /* Add delay to insure DEV_RST has time to complete */
2432 if (global_device_reset)
2435 ret_val = e1000_get_auto_rd_done_generic(hw);
2438 * When auto config read does not complete, do not
2439 * return with an error. This can happen in situations
2440 * where there is no eeprom and prevents getting link.
2442 DEBUGOUT("Auto Read Done did not complete\n");
2445 /* If EEPROM is not present, run manual init scripts */
2446 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2447 e1000_reset_init_script_82575(hw);
2449 /* clear global device reset status bit */
2450 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2452 /* Clear any pending interrupt events. */
2453 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2454 E1000_READ_REG(hw, E1000_ICR);
2456 ret_val = e1000_reset_mdicnfg_82580(hw);
2458 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2460 /* Install any alternate MAC address into RAR0 */
2461 ret_val = e1000_check_alt_mac_addr_generic(hw);
2463 /* Release semaphore */
2464 if (global_device_reset)
2465 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2471 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2472 * @data: data received by reading RXPBS register
2474 * The 82580 uses a table based approach for packet buffer allocation sizes.
2475 * This function converts the retrieved value into the correct table value
2476 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2477 * 0x0 36 72 144 1 2 4 8 16
2478 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2480 u16 e1000_rxpbs_adjust_82580(u32 data)
2484 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2485 ret_val = e1000_82580_rxpbs_table[data];
2491 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2493 * @hw: pointer to the HW structure
2494 * @offset: offset in words of the checksum protected region
2496 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2497 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2499 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2501 s32 ret_val = E1000_SUCCESS;
2505 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2507 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2508 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2510 DEBUGOUT("NVM Read Error\n");
2513 checksum += nvm_data;
2516 if (checksum != (u16) NVM_SUM) {
2517 DEBUGOUT("NVM Checksum Invalid\n");
2518 ret_val = -E1000_ERR_NVM;
2527 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2529 * @hw: pointer to the HW structure
2530 * @offset: offset in words of the checksum protected region
2532 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2533 * up to the checksum. Then calculates the EEPROM checksum and writes the
2534 * value to the EEPROM.
2536 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2542 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2544 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2545 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2547 DEBUGOUT("NVM Read Error while updating checksum.\n");
2550 checksum += nvm_data;
2552 checksum = (u16) NVM_SUM - checksum;
2553 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2556 DEBUGOUT("NVM Write Error while updating checksum.\n");
2563 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2564 * @hw: pointer to the HW structure
2566 * Calculates the EEPROM section checksum by reading/adding each word of
2567 * the EEPROM and then verifies that the sum of the EEPROM is
2570 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2572 s32 ret_val = E1000_SUCCESS;
2573 u16 eeprom_regions_count = 1;
2577 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2579 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2581 DEBUGOUT("NVM Read Error\n");
2585 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2586 /* if chekcsums compatibility bit is set validate checksums
2587 * for all 4 ports. */
2588 eeprom_regions_count = 4;
2591 for (j = 0; j < eeprom_regions_count; j++) {
2592 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2593 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2595 if (ret_val != E1000_SUCCESS)
2604 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2605 * @hw: pointer to the HW structure
2607 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2608 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2609 * checksum and writes the value to the EEPROM.
2611 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2617 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2619 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2621 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2625 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2626 /* set compatibility bit to validate checksums appropriately */
2627 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2628 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2631 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2636 for (j = 0; j < 4; j++) {
2637 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2638 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2648 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2649 * @hw: pointer to the HW structure
2651 * Calculates the EEPROM section checksum by reading/adding each word of
2652 * the EEPROM and then verifies that the sum of the EEPROM is
2655 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2657 s32 ret_val = E1000_SUCCESS;
2661 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2663 for (j = 0; j < 4; j++) {
2664 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2665 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2667 if (ret_val != E1000_SUCCESS)
2676 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2677 * @hw: pointer to the HW structure
2679 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2680 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2681 * checksum and writes the value to the EEPROM.
2683 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2685 s32 ret_val = E1000_SUCCESS;
2689 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2691 for (j = 0; j < 4; j++) {
2692 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2693 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2694 if (ret_val != E1000_SUCCESS)
2703 * e1000_set_eee_i350 - Enable/disable EEE support
2704 * @hw: pointer to the HW structure
2706 * Enable/disable EEE based on setting in dev_spec structure.
2709 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2711 s32 ret_val = E1000_SUCCESS;
2714 DEBUGFUNC("e1000_set_eee_i350");
2716 if ((hw->mac.type < e1000_i350) ||
2717 (hw->phy.media_type != e1000_media_type_copper))
2719 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2720 eeer = E1000_READ_REG(hw, E1000_EEER);
2722 /* enable or disable per user setting */
2723 if (!(hw->dev_spec._82575.eee_disable)) {
2724 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2726 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2727 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2730 /* This bit should not be set in normal operation. */
2731 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2732 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2734 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2735 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2738 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2739 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2740 E1000_READ_REG(hw, E1000_IPCNFG);
2741 E1000_READ_REG(hw, E1000_EEER);
2747 /* Due to a hw errata, if the host tries to configure the VFTA register
2748 * while performing queries from the BMC or DMA, then the VFTA in some
2749 * cases won't be written.
2753 * e1000_clear_vfta_i350 - Clear VLAN filter table
2754 * @hw: pointer to the HW structure
2756 * Clears the register array which contains the VLAN filter table by
2757 * setting all the values to 0.
2759 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2764 DEBUGFUNC("e1000_clear_vfta_350");
2766 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2767 for (i = 0; i < 10; i++)
2768 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2770 E1000_WRITE_FLUSH(hw);
2775 * e1000_write_vfta_i350 - Write value to VLAN filter table
2776 * @hw: pointer to the HW structure
2777 * @offset: register offset in VLAN filter table
2778 * @value: register value written to VLAN filter table
2780 * Writes value at the given offset in the register array which stores
2781 * the VLAN filter table.
2783 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2787 DEBUGFUNC("e1000_write_vfta_350");
2789 for (i = 0; i < 10; i++)
2790 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2792 E1000_WRITE_FLUSH(hw);
2797 * e1000_set_i2c_bb - Enable I2C bit-bang
2798 * @hw: pointer to the HW structure
2800 * Enable I2C bit-bang interface
2803 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2805 s32 ret_val = E1000_SUCCESS;
2806 u32 ctrl_ext, i2cparams;
2808 DEBUGFUNC("e1000_set_i2c_bb");
2810 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2811 ctrl_ext |= E1000_CTRL_I2C_ENA;
2812 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2813 E1000_WRITE_FLUSH(hw);
2815 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2816 i2cparams |= E1000_I2CBB_EN;
2817 i2cparams |= E1000_I2C_DATA_OE_N;
2818 i2cparams |= E1000_I2C_CLK_OE_N;
2819 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2820 E1000_WRITE_FLUSH(hw);
2826 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2827 * @hw: pointer to hardware structure
2828 * @byte_offset: byte offset to read
2829 * @dev_addr: device address
2832 * Performs byte read operation over I2C interface at
2833 * a specified device address.
2835 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2836 u8 dev_addr, u8 *data)
2838 s32 status = E1000_SUCCESS;
2845 DEBUGFUNC("e1000_read_i2c_byte_generic");
2847 swfw_mask = E1000_SWFW_PHY0_SM;
2850 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2852 status = E1000_ERR_SWFW_SYNC;
2856 e1000_i2c_start(hw);
2858 /* Device Address and write indication */
2859 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2860 if (status != E1000_SUCCESS)
2863 status = e1000_get_i2c_ack(hw);
2864 if (status != E1000_SUCCESS)
2867 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2868 if (status != E1000_SUCCESS)
2871 status = e1000_get_i2c_ack(hw);
2872 if (status != E1000_SUCCESS)
2875 e1000_i2c_start(hw);
2877 /* Device Address and read indication */
2878 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2879 if (status != E1000_SUCCESS)
2882 status = e1000_get_i2c_ack(hw);
2883 if (status != E1000_SUCCESS)
2886 status = e1000_clock_in_i2c_byte(hw, data);
2887 if (status != E1000_SUCCESS)
2890 status = e1000_clock_out_i2c_bit(hw, nack);
2891 if (status != E1000_SUCCESS)
2898 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2900 e1000_i2c_bus_clear(hw);
2902 if (retry < max_retry)
2903 DEBUGOUT("I2C byte read error - Retrying.\n");
2905 DEBUGOUT("I2C byte read error.\n");
2907 } while (retry < max_retry);
2909 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2917 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2918 * @hw: pointer to hardware structure
2919 * @byte_offset: byte offset to write
2920 * @dev_addr: device address
2921 * @data: value to write
2923 * Performs byte write operation over I2C interface at
2924 * a specified device address.
2926 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2927 u8 dev_addr, u8 data)
2929 s32 status = E1000_SUCCESS;
2934 DEBUGFUNC("e1000_write_i2c_byte_generic");
2936 swfw_mask = E1000_SWFW_PHY0_SM;
2938 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2939 status = E1000_ERR_SWFW_SYNC;
2940 goto write_byte_out;
2944 e1000_i2c_start(hw);
2946 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2947 if (status != E1000_SUCCESS)
2950 status = e1000_get_i2c_ack(hw);
2951 if (status != E1000_SUCCESS)
2954 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2955 if (status != E1000_SUCCESS)
2958 status = e1000_get_i2c_ack(hw);
2959 if (status != E1000_SUCCESS)
2962 status = e1000_clock_out_i2c_byte(hw, data);
2963 if (status != E1000_SUCCESS)
2966 status = e1000_get_i2c_ack(hw);
2967 if (status != E1000_SUCCESS)
2974 e1000_i2c_bus_clear(hw);
2976 if (retry < max_retry)
2977 DEBUGOUT("I2C byte write error - Retrying.\n");
2979 DEBUGOUT("I2C byte write error.\n");
2980 } while (retry < max_retry);
2982 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2990 * e1000_i2c_start - Sets I2C start condition
2991 * @hw: pointer to hardware structure
2993 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2995 STATIC void e1000_i2c_start(struct e1000_hw *hw)
2997 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2999 DEBUGFUNC("e1000_i2c_start");
3001 /* Start condition must begin with data and clock high */
3002 e1000_set_i2c_data(hw, &i2cctl, 1);
3003 e1000_raise_i2c_clk(hw, &i2cctl);
3005 /* Setup time for start condition (4.7us) */
3006 usec_delay(E1000_I2C_T_SU_STA);
3008 e1000_set_i2c_data(hw, &i2cctl, 0);
3010 /* Hold time for start condition (4us) */
3011 usec_delay(E1000_I2C_T_HD_STA);
3013 e1000_lower_i2c_clk(hw, &i2cctl);
3015 /* Minimum low period of clock is 4.7 us */
3016 usec_delay(E1000_I2C_T_LOW);
3021 * e1000_i2c_stop - Sets I2C stop condition
3022 * @hw: pointer to hardware structure
3024 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3026 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3028 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3030 DEBUGFUNC("e1000_i2c_stop");
3032 /* Stop condition must begin with data low and clock high */
3033 e1000_set_i2c_data(hw, &i2cctl, 0);
3034 e1000_raise_i2c_clk(hw, &i2cctl);
3036 /* Setup time for stop condition (4us) */
3037 usec_delay(E1000_I2C_T_SU_STO);
3039 e1000_set_i2c_data(hw, &i2cctl, 1);
3041 /* bus free time between stop and start (4.7us)*/
3042 usec_delay(E1000_I2C_T_BUF);
3046 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3047 * @hw: pointer to hardware structure
3048 * @data: data byte to clock in
3050 * Clocks in one byte data via I2C data/clock
3052 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3057 DEBUGFUNC("e1000_clock_in_i2c_byte");
3060 for (i = 7; i >= 0; i--) {
3061 e1000_clock_in_i2c_bit(hw, &bit);
3065 return E1000_SUCCESS;
3069 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3070 * @hw: pointer to hardware structure
3071 * @data: data byte clocked out
3073 * Clocks out one byte data via I2C data/clock
3075 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3077 s32 status = E1000_SUCCESS;
3082 DEBUGFUNC("e1000_clock_out_i2c_byte");
3084 for (i = 7; i >= 0; i--) {
3085 bit = (data >> i) & 0x1;
3086 status = e1000_clock_out_i2c_bit(hw, bit);
3088 if (status != E1000_SUCCESS)
3092 /* Release SDA line (set high) */
3093 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3095 i2cctl |= E1000_I2C_DATA_OE_N;
3096 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3097 E1000_WRITE_FLUSH(hw);
3103 * e1000_get_i2c_ack - Polls for I2C ACK
3104 * @hw: pointer to hardware structure
3106 * Clocks in/out one bit via I2C data/clock
3108 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3110 s32 status = E1000_SUCCESS;
3112 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3116 DEBUGFUNC("e1000_get_i2c_ack");
3118 e1000_raise_i2c_clk(hw, &i2cctl);
3120 /* Minimum high period of clock is 4us */
3121 usec_delay(E1000_I2C_T_HIGH);
3123 /* Wait until SCL returns high */
3124 for (i = 0; i < timeout; i++) {
3126 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3127 if (i2cctl & E1000_I2C_CLK_IN)
3130 if (!(i2cctl & E1000_I2C_CLK_IN))
3131 return E1000_ERR_I2C;
3133 ack = e1000_get_i2c_data(&i2cctl);
3135 DEBUGOUT("I2C ack was not received.\n");
3136 status = E1000_ERR_I2C;
3139 e1000_lower_i2c_clk(hw, &i2cctl);
3141 /* Minimum low period of clock is 4.7 us */
3142 usec_delay(E1000_I2C_T_LOW);
3148 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3149 * @hw: pointer to hardware structure
3150 * @data: read data value
3152 * Clocks in one bit via I2C data/clock
3154 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3156 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3158 DEBUGFUNC("e1000_clock_in_i2c_bit");
3160 e1000_raise_i2c_clk(hw, &i2cctl);
3162 /* Minimum high period of clock is 4us */
3163 usec_delay(E1000_I2C_T_HIGH);
3165 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3166 *data = e1000_get_i2c_data(&i2cctl);
3168 e1000_lower_i2c_clk(hw, &i2cctl);
3170 /* Minimum low period of clock is 4.7 us */
3171 usec_delay(E1000_I2C_T_LOW);
3173 return E1000_SUCCESS;
3177 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3178 * @hw: pointer to hardware structure
3179 * @data: data value to write
3181 * Clocks out one bit via I2C data/clock
3183 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3186 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3188 DEBUGFUNC("e1000_clock_out_i2c_bit");
3190 status = e1000_set_i2c_data(hw, &i2cctl, data);
3191 if (status == E1000_SUCCESS) {
3192 e1000_raise_i2c_clk(hw, &i2cctl);
3194 /* Minimum high period of clock is 4us */
3195 usec_delay(E1000_I2C_T_HIGH);
3197 e1000_lower_i2c_clk(hw, &i2cctl);
3199 /* Minimum low period of clock is 4.7 us.
3200 * This also takes care of the data hold time.
3202 usec_delay(E1000_I2C_T_LOW);
3204 status = E1000_ERR_I2C;
3205 DEBUGOUT1("I2C data was not set to %X\n", data);
3211 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3212 * @hw: pointer to hardware structure
3213 * @i2cctl: Current value of I2CCTL register
3215 * Raises the I2C clock line '0'->'1'
3217 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3219 DEBUGFUNC("e1000_raise_i2c_clk");
3221 *i2cctl |= E1000_I2C_CLK_OUT;
3222 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3223 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3224 E1000_WRITE_FLUSH(hw);
3226 /* SCL rise time (1000ns) */
3227 usec_delay(E1000_I2C_T_RISE);
3231 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3232 * @hw: pointer to hardware structure
3233 * @i2cctl: Current value of I2CCTL register
3235 * Lowers the I2C clock line '1'->'0'
3237 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3240 DEBUGFUNC("e1000_lower_i2c_clk");
3242 *i2cctl &= ~E1000_I2C_CLK_OUT;
3243 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3244 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3245 E1000_WRITE_FLUSH(hw);
3247 /* SCL fall time (300ns) */
3248 usec_delay(E1000_I2C_T_FALL);
3252 * e1000_set_i2c_data - Sets the I2C data bit
3253 * @hw: pointer to hardware structure
3254 * @i2cctl: Current value of I2CCTL register
3255 * @data: I2C data value (0 or 1) to set
3257 * Sets the I2C data bit
3259 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3261 s32 status = E1000_SUCCESS;
3263 DEBUGFUNC("e1000_set_i2c_data");
3266 *i2cctl |= E1000_I2C_DATA_OUT;
3268 *i2cctl &= ~E1000_I2C_DATA_OUT;
3270 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3271 *i2cctl |= E1000_I2C_CLK_OE_N;
3272 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3273 E1000_WRITE_FLUSH(hw);
3275 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3276 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3278 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3279 if (data != e1000_get_i2c_data(i2cctl)) {
3280 status = E1000_ERR_I2C;
3281 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3288 * e1000_get_i2c_data - Reads the I2C SDA data bit
3289 * @hw: pointer to hardware structure
3290 * @i2cctl: Current value of I2CCTL register
3292 * Returns the I2C data bit value
3294 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3298 DEBUGFUNC("e1000_get_i2c_data");
3300 if (*i2cctl & E1000_I2C_DATA_IN)
3309 * e1000_i2c_bus_clear - Clears the I2C bus
3310 * @hw: pointer to hardware structure
3312 * Clears the I2C bus by sending nine clock pulses.
3313 * Used when data line is stuck low.
3315 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3317 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3320 DEBUGFUNC("e1000_i2c_bus_clear");
3322 e1000_i2c_start(hw);
3324 e1000_set_i2c_data(hw, &i2cctl, 1);
3326 for (i = 0; i < 9; i++) {
3327 e1000_raise_i2c_clk(hw, &i2cctl);
3329 /* Min high period of clock is 4us */
3330 usec_delay(E1000_I2C_T_HIGH);
3332 e1000_lower_i2c_clk(hw, &i2cctl);
3334 /* Min low period of clock is 4.7us*/
3335 usec_delay(E1000_I2C_T_LOW);
3338 e1000_i2c_start(hw);
3340 /* Put the i2c bus back to default state */