lib/librte_pmd_e1000/e1000/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_init_hw_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  60 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  61                                            u16 *data);
  62 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  63 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  64 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  65                                      u32 offset, u16 *data);
  66 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  67                                       u32 offset, u16 data);
  68 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  69                                           bool active);
  70 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  71                                           bool active);
  72 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  73                                           bool active);
  74 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  78 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  79 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  80                                             u32 offset, u16 data);
  81 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  82 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  83 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  84                                                  u16 *speed, u16 *duplex);
  85 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  86 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  87 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  89 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  90 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  91 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  92 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  94 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  95 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  98 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  99                                                  u16 offset);
 100 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 101                                                    u16 offset);
 102 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 104 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 105 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 106
 107 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 108 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 109 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 110 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 111 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 112 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 113 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 114 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 116 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 117 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 118
 119 STATIC const u16 e1000_82580_rxpbs_table[] = {
 120         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 121 #define E1000_82580_RXPBS_TABLE_SIZE \
 122         (sizeof(e1000_82580_rxpbs_table) / \
 123          sizeof(e1000_82580_rxpbs_table[0]))
 124
 125
 126 /**
 127  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 128  *  @hw: pointer to the HW structure
 129  *
 130  *  Called to determine if the I2C pins are being used for I2C or as an
 131  *  external MDIO interface since the two options are mutually exclusive.
 132  **/
 133 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 134 {
 135         u32 reg = 0;
 136         bool ext_mdio = false;
 137
 138         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 139
 140         switch (hw->mac.type) {
 141         case e1000_82575:
 142         case e1000_82576:
 143                 reg = E1000_READ_REG(hw, E1000_MDIC);
 144                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 145                 break;
 146         case e1000_82580:
 147         case e1000_i350:
 148         case e1000_i354:
 149         case e1000_i210:
 150         case e1000_i211:
 151                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 152                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 153                 break;
 154         default:
 155                 break;
 156         }
 157         return ext_mdio;
 158 }
 159
 160 /**
 161  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 162  *  @hw: pointer to the HW structure
 163  **/
 164 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 165 {
 166         struct e1000_phy_info *phy = &hw->phy;
 167         s32 ret_val = E1000_SUCCESS;
 168         u32 ctrl_ext;
 169
 170         DEBUGFUNC("e1000_init_phy_params_82575");
 171
 172         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 173         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 174
 175         if (hw->phy.media_type != e1000_media_type_copper) {
 176                 phy->type = e1000_phy_none;
 177                 goto out;
 178         }
 179
 180         phy->ops.power_up   = e1000_power_up_phy_copper;
 181         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 182
 183         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 184         phy->reset_delay_us     = 100;
 185
 186         phy->ops.acquire        = e1000_acquire_phy_82575;
 187         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 188         phy->ops.commit         = e1000_phy_sw_reset_generic;
 189         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 190         phy->ops.release        = e1000_release_phy_82575;
 191
 192         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 193
 194         if (e1000_sgmii_active_82575(hw)) {
 195                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 196                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 197         } else {
 198                 phy->ops.reset = e1000_phy_hw_reset_generic;
 199                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 200         }
 201
 202         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 203         e1000_reset_mdicnfg_82580(hw);
 204
 205         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 206                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 207                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 208         } else {
 209                 switch (hw->mac.type) {
 210                 case e1000_82580:
 211                 case e1000_i350:
 212                 case e1000_i354:
 213                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 214                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 215                         break;
 216                 case e1000_i210:
 217                 case e1000_i211:
 218                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 219                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 220                         break;
 221                 default:
 222                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 223                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 224                 }
 225         }
 226
 227         /* Set phy->phy_addr and phy->id. */
 228         ret_val = e1000_get_phy_id_82575(hw);
 229
 230         /* Verify phy id and set remaining function pointers */
 231         switch (phy->id) {
 232         case M88E1543_E_PHY_ID:
 233         case M88E1512_E_PHY_ID:
 234         case I347AT4_E_PHY_ID:
 235         case M88E1112_E_PHY_ID:
 236         case M88E1340M_E_PHY_ID:
 237         case M88E1111_I_PHY_ID:
 238                 phy->type               = e1000_phy_m88;
 239                 phy->ops.check_polarity = e1000_check_polarity_m88;
 240                 phy->ops.get_info       = e1000_get_phy_info_m88;
 241                 if (phy->id == I347AT4_E_PHY_ID ||
 242                     phy->id == M88E1112_E_PHY_ID ||
 243                     phy->id == M88E1340M_E_PHY_ID)
 244                         phy->ops.get_cable_length =
 245                                          e1000_get_cable_length_m88_gen2;
 246                 else if (phy->id == M88E1543_E_PHY_ID ||
 247                          phy->id == M88E1512_E_PHY_ID)
 248                         phy->ops.get_cable_length =
 249                                          e1000_get_cable_length_m88_gen2;
 250                 else
 251                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 252                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 253                 /* Check if this PHY is confgured for media swap. */
 254                 if (phy->id == M88E1112_E_PHY_ID) {
 255                         u16 data;
 256
 257                         ret_val = phy->ops.write_reg(hw,
 258                                                      E1000_M88E1112_PAGE_ADDR,
 259                                                      2);
 260                         if (ret_val)
 261                                 goto out;
 262
 263                         ret_val = phy->ops.read_reg(hw,
 264                                                     E1000_M88E1112_MAC_CTRL_1,
 265                                                     &data);
 266                         if (ret_val)
 267                                 goto out;
 268
 269                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 270                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 271                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 272                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 273                                 hw->mac.ops.check_for_link =
 274                                                 e1000_check_for_link_media_swap;
 275                 }
 276                 break;
 277         case IGP03E1000_E_PHY_ID:
 278         case IGP04E1000_E_PHY_ID:
 279                 phy->type = e1000_phy_igp_3;
 280                 phy->ops.check_polarity = e1000_check_polarity_igp;
 281                 phy->ops.get_info = e1000_get_phy_info_igp;
 282                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 283                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 284                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 285                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 286                 break;
 287         case I82580_I_PHY_ID:
 288         case I350_I_PHY_ID:
 289                 phy->type = e1000_phy_82580;
 290                 phy->ops.check_polarity = e1000_check_polarity_82577;
 291                 phy->ops.force_speed_duplex =
 292                                          e1000_phy_force_speed_duplex_82577;
 293                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 294                 phy->ops.get_info = e1000_get_phy_info_82577;
 295                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 296                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 297                 break;
 298         case I210_I_PHY_ID:
 299                 phy->type               = e1000_phy_i210;
 300                 phy->ops.check_polarity = e1000_check_polarity_m88;
 301                 phy->ops.get_info       = e1000_get_phy_info_m88;
 302                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 303                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 304                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 305                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 306                 break;
 307         default:
 308                 ret_val = -E1000_ERR_PHY;
 309                 goto out;
 310         }
 311
 312 out:
 313         return ret_val;
 314 }
 315
 316 /**
 317  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 318  *  @hw: pointer to the HW structure
 319  **/
 320 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 321 {
 322         struct e1000_nvm_info *nvm = &hw->nvm;
 323         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 324         u16 size;
 325
 326         DEBUGFUNC("e1000_init_nvm_params_82575");
 327
 328         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 329                      E1000_EECD_SIZE_EX_SHIFT);
 330         /*
 331          * Added to a constant, "size" becomes the left-shift value
 332          * for setting word_size.
 333          */
 334         size += NVM_WORD_SIZE_BASE_SHIFT;
 335
 336         /* Just in case size is out of range, cap it to the largest
 337          * EEPROM size supported
 338          */
 339         if (size > 15)
 340                 size = 15;
 341
 342         nvm->word_size = 1 << size;
 343         if (hw->mac.type < e1000_i210) {
 344                 nvm->opcode_bits = 8;
 345                 nvm->delay_usec = 1;
 346
 347                 switch (nvm->override) {
 348                 case e1000_nvm_override_spi_large:
 349                         nvm->page_size = 32;
 350                         nvm->address_bits = 16;
 351                         break;
 352                 case e1000_nvm_override_spi_small:
 353                         nvm->page_size = 8;
 354                         nvm->address_bits = 8;
 355                         break;
 356                 default:
 357                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 358                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 359                                             16 : 8;
 360                         break;
 361                 }
 362                 if (nvm->word_size == (1 << 15))
 363                         nvm->page_size = 128;
 364
 365                 nvm->type = e1000_nvm_eeprom_spi;
 366         } else {
 367                 nvm->type = e1000_nvm_flash_hw;
 368         }
 369
 370         /* Function Pointers */
 371         nvm->ops.acquire = e1000_acquire_nvm_82575;
 372         nvm->ops.release = e1000_release_nvm_82575;
 373         if (nvm->word_size < (1 << 15))
 374                 nvm->ops.read = e1000_read_nvm_eerd;
 375         else
 376                 nvm->ops.read = e1000_read_nvm_spi;
 377
 378         nvm->ops.write = e1000_write_nvm_spi;
 379         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 380         nvm->ops.update = e1000_update_nvm_checksum_generic;
 381         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 382
 383         /* override generic family function pointers for specific descendants */
 384         switch (hw->mac.type) {
 385         case e1000_82580:
 386                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 387                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 388                 break;
 389         case e1000_i350:
 390                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 391                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 392                 break;
 393         default:
 394                 break;
 395         }
 396
 397         return E1000_SUCCESS;
 398 }
 399
 400 /**
 401  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 402  *  @hw: pointer to the HW structure
 403  **/
 404 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 405 {
 406         struct e1000_mac_info *mac = &hw->mac;
 407         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 408
 409         DEBUGFUNC("e1000_init_mac_params_82575");
 410
 411         /* Derives media type */
 412         e1000_get_media_type_82575(hw);
 413         /* Set mta register count */
 414         mac->mta_reg_count = 128;
 415         /* Set uta register count */
 416         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 417         /* Set rar entry count */
 418         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 419         if (mac->type == e1000_82576)
 420                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 421         if (mac->type == e1000_82580)
 422                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 423         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 424                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 425
 426         /* Enable EEE default settings for EEE supported devices */
 427         if (mac->type >= e1000_i350)
 428                 dev_spec->eee_disable = false;
 429
 430         /* Allow a single clear of the SW semaphore on I210 and newer */
 431         if (mac->type >= e1000_i210)
 432                 dev_spec->clear_semaphore_once = true;
 433
 434         /* Set if part includes ASF firmware */
 435         mac->asf_firmware_present = true;
 436         /* FWSM register */
 437         mac->has_fwsm = true;
 438         /* ARC supported; valid only if manageability features are enabled. */
 439         mac->arc_subsystem_valid =
 440                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 441
 442         /* Function pointers */
 443
 444         /* bus type/speed/width */
 445         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 446         /* reset */
 447         if (mac->type >= e1000_82580)
 448                 mac->ops.reset_hw = e1000_reset_hw_82580;
 449         else
 450         mac->ops.reset_hw = e1000_reset_hw_82575;
 451         /* hw initialization */
 452         mac->ops.init_hw = e1000_init_hw_82575;
 453         /* link setup */
 454         mac->ops.setup_link = e1000_setup_link_generic;
 455         /* physical interface link setup */
 456         mac->ops.setup_physical_interface =
 457                 (hw->phy.media_type == e1000_media_type_copper)
 458                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 459         /* physical interface shutdown */
 460         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 461         /* physical interface power up */
 462         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 463         /* check for link */
 464         mac->ops.check_for_link = e1000_check_for_link_82575;
 465         /* read mac address */
 466         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 467         /* configure collision distance */
 468         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 469         /* multicast address update */
 470         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 471         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 472                 /* writing VFTA */
 473                 mac->ops.write_vfta = e1000_write_vfta_i350;
 474                 /* clearing VFTA */
 475                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 476         } else {
 477                 /* writing VFTA */
 478                 mac->ops.write_vfta = e1000_write_vfta_generic;
 479                 /* clearing VFTA */
 480                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 481         }
 482         if (hw->mac.type >= e1000_82580)
 483                 mac->ops.validate_mdi_setting =
 484                                 e1000_validate_mdi_setting_crossover_generic;
 485         /* ID LED init */
 486         mac->ops.id_led_init = e1000_id_led_init_generic;
 487         /* blink LED */
 488         mac->ops.blink_led = e1000_blink_led_generic;
 489         /* setup LED */
 490         mac->ops.setup_led = e1000_setup_led_generic;
 491         /* cleanup LED */
 492         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 493         /* turn on/off LED */
 494         mac->ops.led_on = e1000_led_on_generic;
 495         mac->ops.led_off = e1000_led_off_generic;
 496         /* clear hardware counters */
 497         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 498         /* link info */
 499         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 500         /* acquire SW_FW sync */
 501         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 502         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 503         if (mac->type >= e1000_i210) {
 504                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 505                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 506         }
 507
 508         /* set lan id for port to determine which phy lock to use */
 509         hw->mac.ops.set_lan_id(hw);
 510
 511         return E1000_SUCCESS;
 512 }
 513
 514 /**
 515  *  e1000_init_function_pointers_82575 - Init func ptrs.
 516  *  @hw: pointer to the HW structure
 517  *
 518  *  Called to initialize all function pointers and parameters.
 519  **/
 520 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 521 {
 522         DEBUGFUNC("e1000_init_function_pointers_82575");
 523
 524         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 525         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 526         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 527         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 528 }
 529
 530 /**
 531  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 532  *  @hw: pointer to the HW structure
 533  *
 534  *  Acquire access rights to the correct PHY.
 535  **/
 536 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 537 {
 538         u16 mask = E1000_SWFW_PHY0_SM;
 539
 540         DEBUGFUNC("e1000_acquire_phy_82575");
 541
 542         if (hw->bus.func == E1000_FUNC_1)
 543                 mask = E1000_SWFW_PHY1_SM;
 544         else if (hw->bus.func == E1000_FUNC_2)
 545                 mask = E1000_SWFW_PHY2_SM;
 546         else if (hw->bus.func == E1000_FUNC_3)
 547                 mask = E1000_SWFW_PHY3_SM;
 548
 549         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 550 }
 551
 552 /**
 553  *  e1000_release_phy_82575 - Release rights to access PHY
 554  *  @hw: pointer to the HW structure
 555  *
 556  *  A wrapper to release access rights to the correct PHY.
 557  **/
 558 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 559 {
 560         u16 mask = E1000_SWFW_PHY0_SM;
 561
 562         DEBUGFUNC("e1000_release_phy_82575");
 563
 564         if (hw->bus.func == E1000_FUNC_1)
 565                 mask = E1000_SWFW_PHY1_SM;
 566         else if (hw->bus.func == E1000_FUNC_2)
 567                 mask = E1000_SWFW_PHY2_SM;
 568         else if (hw->bus.func == E1000_FUNC_3)
 569                 mask = E1000_SWFW_PHY3_SM;
 570
 571         hw->mac.ops.release_swfw_sync(hw, mask);
 572 }
 573
 574 /**
 575  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 576  *  @hw: pointer to the HW structure
 577  *  @offset: register offset to be read
 578  *  @data: pointer to the read data
 579  *
 580  *  Reads the PHY register at offset using the serial gigabit media independent
 581  *  interface and stores the retrieved information in data.
 582  **/
 583 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 584                                           u16 *data)
 585 {
 586         s32 ret_val = -E1000_ERR_PARAM;
 587
 588         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 589
 590         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 591                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 592                 goto out;
 593         }
 594
 595         ret_val = hw->phy.ops.acquire(hw);
 596         if (ret_val)
 597                 goto out;
 598
 599         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 600
 601         hw->phy.ops.release(hw);
 602
 603 out:
 604         return ret_val;
 605 }
 606
 607 /**
 608  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 609  *  @hw: pointer to the HW structure
 610  *  @offset: register offset to write to
 611  *  @data: data to write at register offset
 612  *
 613  *  Writes the data to PHY register at the offset using the serial gigabit
 614  *  media independent interface.
 615  **/
 616 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 617                                            u16 data)
 618 {
 619         s32 ret_val = -E1000_ERR_PARAM;
 620
 621         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 622
 623         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 624                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 625                 goto out;
 626         }
 627
 628         ret_val = hw->phy.ops.acquire(hw);
 629         if (ret_val)
 630                 goto out;
 631
 632         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 633
 634         hw->phy.ops.release(hw);
 635
 636 out:
 637         return ret_val;
 638 }
 639
 640 /**
 641  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 642  *  @hw: pointer to the HW structure
 643  *
 644  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 645  *  sgmi interface.
 646  **/
 647 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 648 {
 649         struct e1000_phy_info *phy = &hw->phy;
 650         s32  ret_val = E1000_SUCCESS;
 651         u16 phy_id;
 652         u32 ctrl_ext;
 653         u32 mdic;
 654
 655         DEBUGFUNC("e1000_get_phy_id_82575");
 656
 657         /* some i354 devices need an extra read for phy id */
 658         if (hw->mac.type == e1000_i354)
 659                 e1000_get_phy_id(hw);
 660
 661         /*
 662          * For SGMII PHYs, we try the list of possible addresses until
 663          * we find one that works.  For non-SGMII PHYs
 664          * (e.g. integrated copper PHYs), an address of 1 should
 665          * work.  The result of this function should mean phy->phy_addr
 666          * and phy->id are set correctly.
 667          */
 668         if (!e1000_sgmii_active_82575(hw)) {
 669                 phy->addr = 1;
 670                 ret_val = e1000_get_phy_id(hw);
 671                 goto out;
 672         }
 673
 674         if (e1000_sgmii_uses_mdio_82575(hw)) {
 675                 switch (hw->mac.type) {
 676                 case e1000_82575:
 677                 case e1000_82576:
 678                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 679                         mdic &= E1000_MDIC_PHY_MASK;
 680                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 681                         break;
 682                 case e1000_82580:
 683                 case e1000_i350:
 684                 case e1000_i354:
 685                 case e1000_i210:
 686                 case e1000_i211:
 687                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 688                         mdic &= E1000_MDICNFG_PHY_MASK;
 689                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 690                         break;
 691                 default:
 692                         ret_val = -E1000_ERR_PHY;
 693                         goto out;
 694                         break;
 695                 }
 696                 ret_val = e1000_get_phy_id(hw);
 697                 goto out;
 698         }
 699
 700         /* Power on sgmii phy if it is disabled */
 701         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 702         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 703                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 704         E1000_WRITE_FLUSH(hw);
 705         msec_delay(300);
 706
 707         /*
 708          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 709          * Therefore, we need to test 1-7
 710          */
 711         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 712                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 713                 if (ret_val == E1000_SUCCESS) {
 714                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 715                                   phy_id, phy->addr);
 716                         /*
 717                          * At the time of this writing, The M88 part is
 718                          * the only supported SGMII PHY product.
 719                          */
 720                         if (phy_id == M88_VENDOR)
 721                                 break;
 722                 } else {
 723                         DEBUGOUT1("PHY address %u was unreadable\n",
 724                                   phy->addr);
 725                 }
 726         }
 727
 728         /* A valid PHY type couldn't be found. */
 729         if (phy->addr == 8) {
 730                 phy->addr = 0;
 731                 ret_val = -E1000_ERR_PHY;
 732         } else {
 733                 ret_val = e1000_get_phy_id(hw);
 734         }
 735
 736         /* restore previous sfp cage power state */
 737         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 738
 739 out:
 740         return ret_val;
 741 }
 742
 743 /**
 744  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 745  *  @hw: pointer to the HW structure
 746  *
 747  *  Resets the PHY using the serial gigabit media independent interface.
 748  **/
 749 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 750 {
 751         s32 ret_val = E1000_SUCCESS;
 752
 753         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 754
 755         /*
 756          * This isn't a true "hard" reset, but is the only reset
 757          * available to us at this time.
 758          */
 759
 760         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 761
 762         if (!(hw->phy.ops.write_reg))
 763                 goto out;
 764
 765         /*
 766          * SFP documentation requires the following to configure the SPF module
 767          * to work on SGMII.  No further documentation is given.
 768          */
 769         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 770         if (ret_val)
 771                 goto out;
 772
 773         ret_val = hw->phy.ops.commit(hw);
 774
 775 out:
 776         return ret_val;
 777 }
 778
 779 /**
 780  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 781  *  @hw: pointer to the HW structure
 782  *  @active: true to enable LPLU, false to disable
 783  *
 784  *  Sets the LPLU D0 state according to the active flag.  When
 785  *  activating LPLU this function also disables smart speed
 786  *  and vice versa.  LPLU will not be activated unless the
 787  *  device autonegotiation advertisement meets standards of
 788  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 789  *  This is a function pointer entry point only called by
 790  *  PHY setup routines.
 791  **/
 792 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 793 {
 794         struct e1000_phy_info *phy = &hw->phy;
 795         s32 ret_val = E1000_SUCCESS;
 796         u16 data;
 797
 798         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 799
 800         if (!(hw->phy.ops.read_reg))
 801                 goto out;
 802
 803         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 804         if (ret_val)
 805                 goto out;
 806
 807         if (active) {
 808                 data |= IGP02E1000_PM_D0_LPLU;
 809                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 810                                              data);
 811                 if (ret_val)
 812                         goto out;
 813
 814                 /* When LPLU is enabled, we should disable SmartSpeed */
 815                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 816                                             &data);
 817                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 818                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 819                                              data);
 820                 if (ret_val)
 821                         goto out;
 822         } else {
 823                 data &= ~IGP02E1000_PM_D0_LPLU;
 824                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 825                                              data);
 826                 /*
 827                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 828                  * during Dx states where the power conservation is most
 829                  * important.  During driver activity we should enable
 830                  * SmartSpeed, so performance is maintained.
 831                  */
 832                 if (phy->smart_speed == e1000_smart_speed_on) {
 833                         ret_val = phy->ops.read_reg(hw,
 834                                                     IGP01E1000_PHY_PORT_CONFIG,
 835                                                     &data);
 836                         if (ret_val)
 837                                 goto out;
 838
 839                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 840                         ret_val = phy->ops.write_reg(hw,
 841                                                      IGP01E1000_PHY_PORT_CONFIG,
 842                                                      data);
 843                         if (ret_val)
 844                                 goto out;
 845                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 846                         ret_val = phy->ops.read_reg(hw,
 847                                                     IGP01E1000_PHY_PORT_CONFIG,
 848                                                     &data);
 849                         if (ret_val)
 850                                 goto out;
 851
 852                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 853                         ret_val = phy->ops.write_reg(hw,
 854                                                      IGP01E1000_PHY_PORT_CONFIG,
 855                                                      data);
 856                         if (ret_val)
 857                                 goto out;
 858                 }
 859         }
 860
 861 out:
 862         return ret_val;
 863 }
 864
 865 /**
 866  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 867  *  @hw: pointer to the HW structure
 868  *  @active: true to enable LPLU, false to disable
 869  *
 870  *  Sets the LPLU D0 state according to the active flag.  When
 871  *  activating LPLU this function also disables smart speed
 872  *  and vice versa.  LPLU will not be activated unless the
 873  *  device autonegotiation advertisement meets standards of
 874  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 875  *  This is a function pointer entry point only called by
 876  *  PHY setup routines.
 877  **/
 878 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 879 {
 880         struct e1000_phy_info *phy = &hw->phy;
 881         s32 ret_val = E1000_SUCCESS;
 882         u32 data;
 883
 884         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 885
 886         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 887
 888         if (active) {
 889                 data |= E1000_82580_PM_D0_LPLU;
 890
 891                 /* When LPLU is enabled, we should disable SmartSpeed */
 892                 data &= ~E1000_82580_PM_SPD;
 893         } else {
 894                 data &= ~E1000_82580_PM_D0_LPLU;
 895
 896                 /*
 897                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 898                  * during Dx states where the power conservation is most
 899                  * important.  During driver activity we should enable
 900                  * SmartSpeed, so performance is maintained.
 901                  */
 902                 if (phy->smart_speed == e1000_smart_speed_on)
 903                         data |= E1000_82580_PM_SPD;
 904                 else if (phy->smart_speed == e1000_smart_speed_off)
 905                         data &= ~E1000_82580_PM_SPD;
 906         }
 907
 908         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 909         return ret_val;
 910 }
 911
 912 /**
 913  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 914  *  @hw: pointer to the HW structure
 915  *  @active: boolean used to enable/disable lplu
 916  *
 917  *  Success returns 0, Failure returns 1
 918  *
 919  *  The low power link up (lplu) state is set to the power management level D3
 920  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 921  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 922  *  is used during Dx states where the power conservation is most important.
 923  *  During driver activity, SmartSpeed should be enabled so performance is
 924  *  maintained.
 925  **/
 926 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 927 {
 928         struct e1000_phy_info *phy = &hw->phy;
 929         s32 ret_val = E1000_SUCCESS;
 930         u32 data;
 931
 932         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 933
 934         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 935
 936         if (!active) {
 937                 data &= ~E1000_82580_PM_D3_LPLU;
 938                 /*
 939                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 940                  * during Dx states where the power conservation is most
 941                  * important.  During driver activity we should enable
 942                  * SmartSpeed, so performance is maintained.
 943                  */
 944                 if (phy->smart_speed == e1000_smart_speed_on)
 945                         data |= E1000_82580_PM_SPD;
 946                 else if (phy->smart_speed == e1000_smart_speed_off)
 947                         data &= ~E1000_82580_PM_SPD;
 948         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 949                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 950                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 951                 data |= E1000_82580_PM_D3_LPLU;
 952                 /* When LPLU is enabled, we should disable SmartSpeed */
 953                 data &= ~E1000_82580_PM_SPD;
 954         }
 955
 956         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 957         return ret_val;
 958 }
 959
 960 /**
 961  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 962  *  @hw: pointer to the HW structure
 963  *
 964  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 965  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 966  *  Return successful if access grant bit set, else clear the request for
 967  *  EEPROM access and return -E1000_ERR_NVM (-1).
 968  **/
 969 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 970 {
 971         s32 ret_val;
 972
 973         DEBUGFUNC("e1000_acquire_nvm_82575");
 974
 975         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 976         if (ret_val)
 977                 goto out;
 978
 979         /*
 980          * Check if there is some access
 981          * error this access may hook on
 982          */
 983         if (hw->mac.type == e1000_i350) {
 984                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 985                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 986                     E1000_EECD_TIMEOUT)) {
 987                         /* Clear all access error flags */
 988                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 989                                         E1000_EECD_ERROR_CLR);
 990                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 991                 }
 992         }
 993         if (hw->mac.type == e1000_82580) {
 994                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 995                 if (eecd & E1000_EECD_BLOCKED) {
 996                         /* Clear access error flag */
 997                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 998                                         E1000_EECD_BLOCKED);
 999                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1000                 }
1001         }
1002
1003
1004         ret_val = e1000_acquire_nvm_generic(hw);
1005         if (ret_val)
1006                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1007
1008 out:
1009         return ret_val;
1010 }
1011
1012 /**
1013  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1014  *  @hw: pointer to the HW structure
1015  *
1016  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1017  *  then release the semaphores acquired.
1018  **/
1019 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1020 {
1021         DEBUGFUNC("e1000_release_nvm_82575");
1022
1023         e1000_release_nvm_generic(hw);
1024
1025         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1026 }
1027
1028 /**
1029  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1030  *  @hw: pointer to the HW structure
1031  *  @mask: specifies which semaphore to acquire
1032  *
1033  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1034  *  will also specify which port we're acquiring the lock for.
1035  **/
1036 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1037 {
1038         u32 swfw_sync;
1039         u32 swmask = mask;
1040         u32 fwmask = mask << 16;
1041         s32 ret_val = E1000_SUCCESS;
1042         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1043
1044         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1045
1046         while (i < timeout) {
1047                 if (e1000_get_hw_semaphore_generic(hw)) {
1048                         ret_val = -E1000_ERR_SWFW_SYNC;
1049                         goto out;
1050                 }
1051
1052                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1053                 if (!(swfw_sync & (fwmask | swmask)))
1054                         break;
1055
1056                 /*
1057                  * Firmware currently using resource (fwmask)
1058                  * or other software thread using resource (swmask)
1059                  */
1060                 e1000_put_hw_semaphore_generic(hw);
1061                 msec_delay_irq(5);
1062                 i++;
1063         }
1064
1065         if (i == timeout) {
1066                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1067                 ret_val = -E1000_ERR_SWFW_SYNC;
1068                 goto out;
1069         }
1070
1071         swfw_sync |= swmask;
1072         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1073
1074         e1000_put_hw_semaphore_generic(hw);
1075
1076 out:
1077         return ret_val;
1078 }
1079
1080 /**
1081  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1082  *  @hw: pointer to the HW structure
1083  *  @mask: specifies which semaphore to acquire
1084  *
1085  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1086  *  will also specify which port we're releasing the lock for.
1087  **/
1088 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1089 {
1090         u32 swfw_sync;
1091
1092         DEBUGFUNC("e1000_release_swfw_sync_82575");
1093
1094         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1095                 ; /* Empty */
1096
1097         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1098         swfw_sync &= ~mask;
1099         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1100
1101         e1000_put_hw_semaphore_generic(hw);
1102 }
1103
1104 /**
1105  *  e1000_get_cfg_done_82575 - Read config done bit
1106  *  @hw: pointer to the HW structure
1107  *
1108  *  Read the management control register for the config done bit for
1109  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1110  *  to read the config done bit, so an error is *ONLY* logged and returns
1111  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1112  *  would not be able to be reset or change link.
1113  **/
1114 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1115 {
1116         s32 timeout = PHY_CFG_TIMEOUT;
1117         s32 ret_val = E1000_SUCCESS;
1118         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1119
1120         DEBUGFUNC("e1000_get_cfg_done_82575");
1121
1122         if (hw->bus.func == E1000_FUNC_1)
1123                 mask = E1000_NVM_CFG_DONE_PORT_1;
1124         else if (hw->bus.func == E1000_FUNC_2)
1125                 mask = E1000_NVM_CFG_DONE_PORT_2;
1126         else if (hw->bus.func == E1000_FUNC_3)
1127                 mask = E1000_NVM_CFG_DONE_PORT_3;
1128         while (timeout) {
1129                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1130                         break;
1131                 msec_delay(1);
1132                 timeout--;
1133         }
1134         if (!timeout)
1135                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1136
1137         /* If EEPROM is not marked present, init the PHY manually */
1138         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1139             (hw->phy.type == e1000_phy_igp_3))
1140                 e1000_phy_init_script_igp3(hw);
1141
1142         return ret_val;
1143 }
1144
1145 /**
1146  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1147  *  @hw: pointer to the HW structure
1148  *  @speed: stores the current speed
1149  *  @duplex: stores the current duplex
1150  *
1151  *  This is a wrapper function, if using the serial gigabit media independent
1152  *  interface, use PCS to retrieve the link speed and duplex information.
1153  *  Otherwise, use the generic function to get the link speed and duplex info.
1154  **/
1155 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1156                                         u16 *duplex)
1157 {
1158         s32 ret_val;
1159
1160         DEBUGFUNC("e1000_get_link_up_info_82575");
1161
1162         if (hw->phy.media_type != e1000_media_type_copper)
1163                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1164                                                                duplex);
1165         else
1166                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1167                                                                     duplex);
1168
1169         return ret_val;
1170 }
1171
1172 /**
1173  *  e1000_check_for_link_82575 - Check for link
1174  *  @hw: pointer to the HW structure
1175  *
1176  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1177  *  use the generic interface for determining link.
1178  **/
1179 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1180 {
1181         s32 ret_val;
1182         u16 speed, duplex;
1183
1184         DEBUGFUNC("e1000_check_for_link_82575");
1185
1186         if (hw->phy.media_type != e1000_media_type_copper) {
1187                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1188                                                                &duplex);
1189                 /*
1190                  * Use this flag to determine if link needs to be checked or
1191                  * not.  If we have link clear the flag so that we do not
1192                  * continue to check for link.
1193                  */
1194                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1195
1196                 /*
1197                  * Configure Flow Control now that Auto-Neg has completed.
1198                  * First, we need to restore the desired flow control
1199                  * settings because we may have had to re-autoneg with a
1200                  * different link partner.
1201                  */
1202                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1203                 if (ret_val)
1204                         DEBUGOUT("Error configuring flow control\n");
1205         } else {
1206                 ret_val = e1000_check_for_copper_link_generic(hw);
1207         }
1208
1209         return ret_val;
1210 }
1211
1212 /**
1213  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1214  *  @hw: pointer to the HW structure
1215  *
1216  *  Poll the M88E1112 interfaces to see which interface achieved link.
1217  */
1218 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1219 {
1220         struct e1000_phy_info *phy = &hw->phy;
1221         s32 ret_val;
1222         u16 data;
1223         u8 port = 0;
1224
1225         DEBUGFUNC("e1000_check_for_link_media_swap");
1226
1227         /* Check the copper medium. */
1228         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1229         if (ret_val)
1230                 return ret_val;
1231
1232         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1233         if (ret_val)
1234                 return ret_val;
1235
1236         if (data & E1000_M88E1112_STATUS_LINK)
1237                 port = E1000_MEDIA_PORT_COPPER;
1238
1239         /* Check the other medium. */
1240         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1241         if (ret_val)
1242                 return ret_val;
1243
1244         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1245         if (ret_val)
1246                 return ret_val;
1247
1248         if (data & E1000_M88E1112_STATUS_LINK)
1249                 port = E1000_MEDIA_PORT_OTHER;
1250
1251         /* Determine if a swap needs to happen. */
1252         if (port && (hw->dev_spec._82575.media_port != port)) {
1253                 hw->dev_spec._82575.media_port = port;
1254                 hw->dev_spec._82575.media_changed = true;
1255         } else {
1256                 ret_val = e1000_check_for_link_82575(hw);
1257         }
1258
1259         return E1000_SUCCESS;
1260 }
1261
1262 /**
1263  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1264  *  @hw: pointer to the HW structure
1265  **/
1266 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1267 {
1268         u32 reg;
1269
1270         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1271
1272         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1273             !e1000_sgmii_active_82575(hw))
1274                 return;
1275
1276         /* Enable PCS to turn on link */
1277         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1278         reg |= E1000_PCS_CFG_PCS_EN;
1279         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1280
1281         /* Power up the laser */
1282         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1283         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1284         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1285
1286         /* flush the write to verify completion */
1287         E1000_WRITE_FLUSH(hw);
1288         msec_delay(1);
1289 }
1290
1291 /**
1292  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1293  *  @hw: pointer to the HW structure
1294  *  @speed: stores the current speed
1295  *  @duplex: stores the current duplex
1296  *
1297  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1298  *  duplex, then store the values in the pointers provided.
1299  **/
1300 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1301                                                 u16 *speed, u16 *duplex)
1302 {
1303         struct e1000_mac_info *mac = &hw->mac;
1304         u32 pcs;
1305         u32 status;
1306
1307         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1308
1309         /*
1310          * Read the PCS Status register for link state. For non-copper mode,
1311          * the status register is not accurate. The PCS status register is
1312          * used instead.
1313          */
1314         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1315
1316         /*
1317          * The link up bit determines when link is up on autoneg.
1318          */
1319         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1320                 mac->serdes_has_link = true;
1321
1322                 /* Detect and store PCS speed */
1323                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1324                         *speed = SPEED_1000;
1325                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1326                         *speed = SPEED_100;
1327                 else
1328                         *speed = SPEED_10;
1329
1330                 /* Detect and store PCS duplex */
1331                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1332                         *duplex = FULL_DUPLEX;
1333                 else
1334                         *duplex = HALF_DUPLEX;
1335
1336                 /* Check if it is an I354 2.5Gb backplane connection. */
1337                 if (mac->type == e1000_i354) {
1338                         status = E1000_READ_REG(hw, E1000_STATUS);
1339                         if ((status & E1000_STATUS_2P5_SKU) &&
1340                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1341                                 *speed = SPEED_2500;
1342                                 *duplex = FULL_DUPLEX;
1343                                 DEBUGOUT("2500 Mbs, ");
1344                                 DEBUGOUT("Full Duplex\n");
1345                         }
1346                 }
1347
1348         } else {
1349                 mac->serdes_has_link = false;
1350                 *speed = 0;
1351                 *duplex = 0;
1352         }
1353
1354         return E1000_SUCCESS;
1355 }
1356
1357 /**
1358  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1359  *  @hw: pointer to the HW structure
1360  *
1361  *  In the case of serdes shut down sfp and PCS on driver unload
1362  *  when management pass thru is not enabled.
1363  **/
1364 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1365 {
1366         u32 reg;
1367
1368         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1369
1370         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1371             !e1000_sgmii_active_82575(hw))
1372                 return;
1373
1374         if (!e1000_enable_mng_pass_thru(hw)) {
1375                 /* Disable PCS to turn off link */
1376                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1377                 reg &= ~E1000_PCS_CFG_PCS_EN;
1378                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1379
1380                 /* shutdown the laser */
1381                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1382                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1383                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1384
1385                 /* flush the write to verify completion */
1386                 E1000_WRITE_FLUSH(hw);
1387                 msec_delay(1);
1388         }
1389
1390         return;
1391 }
1392
1393 /**
1394  *  e1000_reset_hw_82575 - Reset hardware
1395  *  @hw: pointer to the HW structure
1396  *
1397  *  This resets the hardware into a known state.
1398  **/
1399 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1400 {
1401         u32 ctrl;
1402         s32 ret_val;
1403
1404         DEBUGFUNC("e1000_reset_hw_82575");
1405
1406         /*
1407          * Prevent the PCI-E bus from sticking if there is no TLP connection
1408          * on the last TLP read/write transaction when MAC is reset.
1409          */
1410         ret_val = e1000_disable_pcie_master_generic(hw);
1411         if (ret_val)
1412                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1413
1414         /* set the completion timeout for interface */
1415         ret_val = e1000_set_pcie_completion_timeout(hw);
1416         if (ret_val)
1417                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1418
1419         DEBUGOUT("Masking off all interrupts\n");
1420         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1421
1422         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1423         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1424         E1000_WRITE_FLUSH(hw);
1425
1426         msec_delay(10);
1427
1428         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1429
1430         DEBUGOUT("Issuing a global reset to MAC\n");
1431         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1432
1433         ret_val = e1000_get_auto_rd_done_generic(hw);
1434         if (ret_val) {
1435                 /*
1436                  * When auto config read does not complete, do not
1437                  * return with an error. This can happen in situations
1438                  * where there is no eeprom and prevents getting link.
1439                  */
1440                 DEBUGOUT("Auto Read Done did not complete\n");
1441         }
1442
1443         /* If EEPROM is not present, run manual init scripts */
1444         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1445                 e1000_reset_init_script_82575(hw);
1446
1447         /* Clear any pending interrupt events. */
1448         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1449         E1000_READ_REG(hw, E1000_ICR);
1450
1451         /* Install any alternate MAC address into RAR0 */
1452         ret_val = e1000_check_alt_mac_addr_generic(hw);
1453
1454         return ret_val;
1455 }
1456
1457 /**
1458  *  e1000_init_hw_82575 - Initialize hardware
1459  *  @hw: pointer to the HW structure
1460  *
1461  *  This inits the hardware readying it for operation.
1462  **/
1463 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1464 {
1465         struct e1000_mac_info *mac = &hw->mac;
1466         s32 ret_val;
1467         u16 i, rar_count = mac->rar_entry_count;
1468
1469         DEBUGFUNC("e1000_init_hw_82575");
1470
1471         /* Initialize identification LED */
1472         ret_val = mac->ops.id_led_init(hw);
1473         if (ret_val) {
1474                 DEBUGOUT("Error initializing identification LED\n");
1475                 /* This is not fatal and we should not stop init due to this */
1476         }
1477
1478         /* Disabling VLAN filtering */
1479         DEBUGOUT("Initializing the IEEE VLAN\n");
1480         mac->ops.clear_vfta(hw);
1481
1482         /* Setup the receive address */
1483         e1000_init_rx_addrs_generic(hw, rar_count);
1484
1485         /* Zero out the Multicast HASH table */
1486         DEBUGOUT("Zeroing the MTA\n");
1487         for (i = 0; i < mac->mta_reg_count; i++)
1488                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1489
1490         /* Zero out the Unicast HASH table */
1491         DEBUGOUT("Zeroing the UTA\n");
1492         for (i = 0; i < mac->uta_reg_count; i++)
1493                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1494
1495         /* Setup link and flow control */
1496         ret_val = mac->ops.setup_link(hw);
1497
1498         /* Set the default MTU size */
1499         hw->dev_spec._82575.mtu = 1500;
1500
1501         /*
1502          * Clear all of the statistics registers (clear on read).  It is
1503          * important that we do this after we have tried to establish link
1504          * because the symbol error count will increment wildly if there
1505          * is no link.
1506          */
1507         e1000_clear_hw_cntrs_82575(hw);
1508
1509         return ret_val;
1510 }
1511
1512 /**
1513  *  e1000_setup_copper_link_82575 - Configure copper link settings
1514  *  @hw: pointer to the HW structure
1515  *
1516  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1517  *  for link, once link is established calls to configure collision distance
1518  *  and flow control are called.
1519  **/
1520 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1521 {
1522         u32 ctrl;
1523         s32 ret_val;
1524         u32 phpm_reg;
1525
1526         DEBUGFUNC("e1000_setup_copper_link_82575");
1527
1528         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1529         ctrl |= E1000_CTRL_SLU;
1530         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1531         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1532
1533         /* Clear Go Link Disconnect bit on supported devices */
1534         switch (hw->mac.type) {
1535         case e1000_82580:
1536         case e1000_i350:
1537         case e1000_i210:
1538         case e1000_i211:
1539                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1540                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1541                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1542                 break;
1543         default:
1544                 break;
1545         }
1546
1547         ret_val = e1000_setup_serdes_link_82575(hw);
1548         if (ret_val)
1549                 goto out;
1550
1551         if (e1000_sgmii_active_82575(hw)) {
1552                 /* allow time for SFP cage time to power up phy */
1553                 msec_delay(300);
1554
1555                 ret_val = hw->phy.ops.reset(hw);
1556                 if (ret_val) {
1557                         DEBUGOUT("Error resetting the PHY.\n");
1558                         goto out;
1559                 }
1560         }
1561         switch (hw->phy.type) {
1562         case e1000_phy_i210:
1563         case e1000_phy_m88:
1564                 switch (hw->phy.id) {
1565                 case I347AT4_E_PHY_ID:
1566                 case M88E1112_E_PHY_ID:
1567                 case M88E1340M_E_PHY_ID:
1568                 case M88E1543_E_PHY_ID:
1569                 case M88E1512_E_PHY_ID:
1570                 case I210_I_PHY_ID:
1571                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1572                         break;
1573                 default:
1574                         ret_val = e1000_copper_link_setup_m88(hw);
1575                         break;
1576                 }
1577                 break;
1578         case e1000_phy_igp_3:
1579                 ret_val = e1000_copper_link_setup_igp(hw);
1580                 break;
1581         case e1000_phy_82580:
1582                 ret_val = e1000_copper_link_setup_82577(hw);
1583                 break;
1584         default:
1585                 ret_val = -E1000_ERR_PHY;
1586                 break;
1587         }
1588
1589         if (ret_val)
1590                 goto out;
1591
1592         ret_val = e1000_setup_copper_link_generic(hw);
1593 out:
1594         return ret_val;
1595 }
1596
1597 /**
1598  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1599  *  @hw: pointer to the HW structure
1600  *
1601  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1602  *  used on copper connections where the serialized gigabit media independent
1603  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1604  *  for auto-negotiation or forces speed/duplex.
1605  **/
1606 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1607 {
1608         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1609         bool pcs_autoneg;
1610         s32 ret_val = E1000_SUCCESS;
1611         u16 data;
1612
1613         DEBUGFUNC("e1000_setup_serdes_link_82575");
1614
1615         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1616             !e1000_sgmii_active_82575(hw))
1617                 return ret_val;
1618
1619         /*
1620          * On the 82575, SerDes loopback mode persists until it is
1621          * explicitly turned off or a power cycle is performed.  A read to
1622          * the register does not indicate its status.  Therefore, we ensure
1623          * loopback mode is disabled during initialization.
1624          */
1625         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1626
1627         /* power on the sfp cage if present */
1628         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1629         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1630         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1631
1632         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1633         ctrl_reg |= E1000_CTRL_SLU;
1634
1635         /* set both sw defined pins on 82575/82576*/
1636         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1637                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1638
1639         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1640
1641         /* default pcs_autoneg to the same setting as mac autoneg */
1642         pcs_autoneg = hw->mac.autoneg;
1643
1644         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1645         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1646                 /* sgmii mode lets the phy handle forcing speed/duplex */
1647                 pcs_autoneg = true;
1648                 /* autoneg time out should be disabled for SGMII mode */
1649                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1650                 break;
1651         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1652                 /* disable PCS autoneg and support parallel detect only */
1653                 pcs_autoneg = false;
1654                 /* fall through to default case */
1655         default:
1656                 if (hw->mac.type == e1000_82575 ||
1657                     hw->mac.type == e1000_82576) {
1658                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1659                         if (ret_val) {
1660                                 DEBUGOUT("NVM Read Error\n");
1661                                 return ret_val;
1662                         }
1663
1664                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1665                                 pcs_autoneg = false;
1666                 }
1667
1668                 /*
1669                  * non-SGMII modes only supports a speed of 1000/Full for the
1670                  * link so it is best to just force the MAC and let the pcs
1671                  * link either autoneg or be forced to 1000/Full
1672                  */
1673                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1674                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1675
1676                 /* set speed of 1000/Full if speed/duplex is forced */
1677                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1678                 break;
1679         }
1680
1681         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1682
1683         /*
1684          * New SerDes mode allows for forcing speed or autonegotiating speed
1685          * at 1gb. Autoneg should be default set by most drivers. This is the
1686          * mode that will be compatible with older link partners and switches.
1687          * However, both are supported by the hardware and some drivers/tools.
1688          */
1689         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1690                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1691
1692         if (pcs_autoneg) {
1693                 /* Set PCS register for autoneg */
1694                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1695                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1696
1697                 /* Disable force flow control for autoneg */
1698                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1699
1700                 /* Configure flow control advertisement for autoneg */
1701                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1702                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1703
1704                 switch (hw->fc.requested_mode) {
1705                 case e1000_fc_full:
1706                 case e1000_fc_rx_pause:
1707                         anadv_reg |= E1000_TXCW_ASM_DIR;
1708                         anadv_reg |= E1000_TXCW_PAUSE;
1709                         break;
1710                 case e1000_fc_tx_pause:
1711                         anadv_reg |= E1000_TXCW_ASM_DIR;
1712                         break;
1713                 default:
1714                         break;
1715                 }
1716
1717                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1718
1719                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1720         } else {
1721                 /* Set PCS register for forced link */
1722                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1723
1724                 /* Force flow control for forced link */
1725                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1726
1727                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1728         }
1729
1730         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1731
1732         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1733                 e1000_force_mac_fc_generic(hw);
1734
1735         return ret_val;
1736 }
1737
1738 /**
1739  *  e1000_get_media_type_82575 - derives current media type.
1740  *  @hw: pointer to the HW structure
1741  *
1742  *  The media type is chosen reflecting few settings.
1743  *  The following are taken into account:
1744  *  - link mode set in the current port Init Control Word #3
1745  *  - current link mode settings in CSR register
1746  *  - MDIO vs. I2C PHY control interface chosen
1747  *  - SFP module media type
1748  **/
1749 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1750 {
1751         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1752         s32 ret_val = E1000_SUCCESS;
1753         u32 ctrl_ext = 0;
1754         u32 link_mode = 0;
1755
1756         /* Set internal phy as default */
1757         dev_spec->sgmii_active = false;
1758         dev_spec->module_plugged = false;
1759
1760         /* Get CSR setting */
1761         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1762
1763         /* extract link mode setting */
1764         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1765
1766         switch (link_mode) {
1767         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1768                 hw->phy.media_type = e1000_media_type_internal_serdes;
1769                 break;
1770         case E1000_CTRL_EXT_LINK_MODE_GMII:
1771                 hw->phy.media_type = e1000_media_type_copper;
1772                 break;
1773         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1774                 /* Get phy control interface type set (MDIO vs. I2C)*/
1775                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1776                         hw->phy.media_type = e1000_media_type_copper;
1777                         dev_spec->sgmii_active = true;
1778                         break;
1779                 }
1780                 /* fall through for I2C based SGMII */
1781         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1782                 /* read media type from SFP EEPROM */
1783                 ret_val = e1000_set_sfp_media_type_82575(hw);
1784                 if ((ret_val != E1000_SUCCESS) ||
1785                     (hw->phy.media_type == e1000_media_type_unknown)) {
1786                         /*
1787                          * If media type was not identified then return media
1788                          * type defined by the CTRL_EXT settings.
1789                          */
1790                         hw->phy.media_type = e1000_media_type_internal_serdes;
1791
1792                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1793                                 hw->phy.media_type = e1000_media_type_copper;
1794                                 dev_spec->sgmii_active = true;
1795                         }
1796
1797                         break;
1798                 }
1799
1800                 /* do not change link mode for 100BaseFX */
1801                 if (dev_spec->eth_flags.e100_base_fx)
1802                         break;
1803
1804                 /* change current link mode setting */
1805                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1806
1807                 if (hw->phy.media_type == e1000_media_type_copper)
1808                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1809                 else
1810                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1811
1812                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1813
1814                 break;
1815         }
1816
1817         return ret_val;
1818 }
1819
1820 /**
1821  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1822  *  @hw: pointer to the HW structure
1823  *
1824  *  The media type is chosen based on SFP module.
1825  *  compatibility flags retrieved from SFP ID EEPROM.
1826  **/
1827 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1828 {
1829         s32 ret_val = E1000_ERR_CONFIG;
1830         u32 ctrl_ext = 0;
1831         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1832         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1833         u8 tranceiver_type = 0;
1834         s32 timeout = 3;
1835
1836         /* Turn I2C interface ON and power on sfp cage */
1837         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1838         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1839         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1840
1841         E1000_WRITE_FLUSH(hw);
1842
1843         /* Read SFP module data */
1844         while (timeout) {
1845                 ret_val = e1000_read_sfp_data_byte(hw,
1846                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1847                         &tranceiver_type);
1848                 if (ret_val == E1000_SUCCESS)
1849                         break;
1850                 msec_delay(100);
1851                 timeout--;
1852         }
1853         if (ret_val != E1000_SUCCESS)
1854                 goto out;
1855
1856         ret_val = e1000_read_sfp_data_byte(hw,
1857                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1858                         (u8 *)eth_flags);
1859         if (ret_val != E1000_SUCCESS)
1860                 goto out;
1861
1862         /* Check if there is some SFP module plugged and powered */
1863         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1864             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1865                 dev_spec->module_plugged = true;
1866                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1867                         hw->phy.media_type = e1000_media_type_internal_serdes;
1868                 } else if (eth_flags->e100_base_fx) {
1869                         dev_spec->sgmii_active = true;
1870                         hw->phy.media_type = e1000_media_type_internal_serdes;
1871                 } else if (eth_flags->e1000_base_t) {
1872                         dev_spec->sgmii_active = true;
1873                         hw->phy.media_type = e1000_media_type_copper;
1874                 } else {
1875                         hw->phy.media_type = e1000_media_type_unknown;
1876                         DEBUGOUT("PHY module has not been recognized\n");
1877                         goto out;
1878                 }
1879         } else {
1880                 hw->phy.media_type = e1000_media_type_unknown;
1881         }
1882         ret_val = E1000_SUCCESS;
1883 out:
1884         /* Restore I2C interface setting */
1885         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1886         return ret_val;
1887 }
1888
1889 /**
1890  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1891  *  @hw: pointer to the HW structure
1892  *  @data: pointer to the NVM (EEPROM)
1893  *
1894  *  Read the EEPROM for the current default LED configuration.  If the
1895  *  LED configuration is not valid, set to a valid LED configuration.
1896  **/
1897 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1898 {
1899         s32 ret_val;
1900
1901         DEBUGFUNC("e1000_valid_led_default_82575");
1902
1903         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1904         if (ret_val) {
1905                 DEBUGOUT("NVM Read Error\n");
1906                 goto out;
1907         }
1908
1909         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1910                 switch (hw->phy.media_type) {
1911                 case e1000_media_type_internal_serdes:
1912                         *data = ID_LED_DEFAULT_82575_SERDES;
1913                         break;
1914                 case e1000_media_type_copper:
1915                 default:
1916                         *data = ID_LED_DEFAULT;
1917                         break;
1918                 }
1919         }
1920 out:
1921         return ret_val;
1922 }
1923
1924 /**
1925  *  e1000_sgmii_active_82575 - Return sgmii state
1926  *  @hw: pointer to the HW structure
1927  *
1928  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1929  *  which can be enabled for use in the embedded applications.  Simply
1930  *  return the current state of the sgmii interface.
1931  **/
1932 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1933 {
1934         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1935         return dev_spec->sgmii_active;
1936 }
1937
1938 /**
1939  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1940  *  @hw: pointer to the HW structure
1941  *
1942  *  Inits recommended HW defaults after a reset when there is no EEPROM
1943  *  detected. This is only for the 82575.
1944  **/
1945 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1946 {
1947         DEBUGFUNC("e1000_reset_init_script_82575");
1948
1949         if (hw->mac.type == e1000_82575) {
1950                 DEBUGOUT("Running reset init script for 82575\n");
1951                 /* SerDes configuration via SERDESCTRL */
1952                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1953                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1954                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1955                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1956
1957                 /* CCM configuration via CCMCTL register */
1958                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1959                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1960
1961                 /* PCIe lanes configuration */
1962                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1963                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1964                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1965                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1966
1967                 /* PCIe PLL Configuration */
1968                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1969                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1970                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1971         }
1972
1973         return E1000_SUCCESS;
1974 }
1975
1976 /**
1977  *  e1000_read_mac_addr_82575 - Read device MAC address
1978  *  @hw: pointer to the HW structure
1979  **/
1980 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1981 {
1982         s32 ret_val;
1983
1984         DEBUGFUNC("e1000_read_mac_addr_82575");
1985
1986         /*
1987          * If there's an alternate MAC address place it in RAR0
1988          * so that it will override the Si installed default perm
1989          * address.
1990          */
1991         ret_val = e1000_check_alt_mac_addr_generic(hw);
1992         if (ret_val)
1993                 goto out;
1994
1995         ret_val = e1000_read_mac_addr_generic(hw);
1996
1997 out:
1998         return ret_val;
1999 }
2000
2001 /**
2002  *  e1000_config_collision_dist_82575 - Configure collision distance
2003  *  @hw: pointer to the HW structure
2004  *
2005  *  Configures the collision distance to the default value and is used
2006  *  during link setup.
2007  **/
2008 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2009 {
2010         u32 tctl_ext;
2011
2012         DEBUGFUNC("e1000_config_collision_dist_82575");
2013
2014         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2015
2016         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2017         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2018
2019         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2020         E1000_WRITE_FLUSH(hw);
2021 }
2022
2023 /**
2024  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2025  * @hw: pointer to the HW structure
2026  *
2027  * In the case of a PHY power down to save power, or to turn off link during a
2028  * driver unload, or wake on lan is not enabled, remove the link.
2029  **/
2030 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2031 {
2032         struct e1000_phy_info *phy = &hw->phy;
2033
2034         if (!(phy->ops.check_reset_block))
2035                 return;
2036
2037         /* If the management interface is not enabled, then power down */
2038         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2039                 e1000_power_down_phy_copper(hw);
2040
2041         return;
2042 }
2043
2044 /**
2045  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2046  *  @hw: pointer to the HW structure
2047  *
2048  *  Clears the hardware counters by reading the counter registers.
2049  **/
2050 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2051 {
2052         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2053
2054         e1000_clear_hw_cntrs_base_generic(hw);
2055
2056         E1000_READ_REG(hw, E1000_PRC64);
2057         E1000_READ_REG(hw, E1000_PRC127);
2058         E1000_READ_REG(hw, E1000_PRC255);
2059         E1000_READ_REG(hw, E1000_PRC511);
2060         E1000_READ_REG(hw, E1000_PRC1023);
2061         E1000_READ_REG(hw, E1000_PRC1522);
2062         E1000_READ_REG(hw, E1000_PTC64);
2063         E1000_READ_REG(hw, E1000_PTC127);
2064         E1000_READ_REG(hw, E1000_PTC255);
2065         E1000_READ_REG(hw, E1000_PTC511);
2066         E1000_READ_REG(hw, E1000_PTC1023);
2067         E1000_READ_REG(hw, E1000_PTC1522);
2068
2069         E1000_READ_REG(hw, E1000_ALGNERRC);
2070         E1000_READ_REG(hw, E1000_RXERRC);
2071         E1000_READ_REG(hw, E1000_TNCRS);
2072         E1000_READ_REG(hw, E1000_CEXTERR);
2073         E1000_READ_REG(hw, E1000_TSCTC);
2074         E1000_READ_REG(hw, E1000_TSCTFC);
2075
2076         E1000_READ_REG(hw, E1000_MGTPRC);
2077         E1000_READ_REG(hw, E1000_MGTPDC);
2078         E1000_READ_REG(hw, E1000_MGTPTC);
2079
2080         E1000_READ_REG(hw, E1000_IAC);
2081         E1000_READ_REG(hw, E1000_ICRXOC);
2082
2083         E1000_READ_REG(hw, E1000_ICRXPTC);
2084         E1000_READ_REG(hw, E1000_ICRXATC);
2085         E1000_READ_REG(hw, E1000_ICTXPTC);
2086         E1000_READ_REG(hw, E1000_ICTXATC);
2087         E1000_READ_REG(hw, E1000_ICTXQEC);
2088         E1000_READ_REG(hw, E1000_ICTXQMTC);
2089         E1000_READ_REG(hw, E1000_ICRXDMTC);
2090
2091         E1000_READ_REG(hw, E1000_CBTMPC);
2092         E1000_READ_REG(hw, E1000_HTDPMC);
2093         E1000_READ_REG(hw, E1000_CBRMPC);
2094         E1000_READ_REG(hw, E1000_RPTHC);
2095         E1000_READ_REG(hw, E1000_HGPTC);
2096         E1000_READ_REG(hw, E1000_HTCBDPC);
2097         E1000_READ_REG(hw, E1000_HGORCL);
2098         E1000_READ_REG(hw, E1000_HGORCH);
2099         E1000_READ_REG(hw, E1000_HGOTCL);
2100         E1000_READ_REG(hw, E1000_HGOTCH);
2101         E1000_READ_REG(hw, E1000_LENERRS);
2102
2103         /* This register should not be read in copper configurations */
2104         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2105             e1000_sgmii_active_82575(hw))
2106                 E1000_READ_REG(hw, E1000_SCVPC);
2107 }
2108
2109 /**
2110  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2111  *  @hw: pointer to the HW structure
2112  *
2113  *  After rx enable if managability is enabled then there is likely some
2114  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2115  *  function clears the fifos and flushes any packets that came in as rx was
2116  *  being enabled.
2117  **/
2118 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2119 {
2120         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2121         int i, ms_wait;
2122
2123         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2124         if (hw->mac.type != e1000_82575 ||
2125             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2126                 return;
2127
2128         /* Disable all Rx queues */
2129         for (i = 0; i < 4; i++) {
2130                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2131                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2132                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2133         }
2134         /* Poll all queues to verify they have shut down */
2135         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2136                 msec_delay(1);
2137                 rx_enabled = 0;
2138                 for (i = 0; i < 4; i++)
2139                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2140                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2141                         break;
2142         }
2143
2144         if (ms_wait == 10)
2145                 DEBUGOUT("Queue disable timed out after 10ms\n");
2146
2147         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2148          * incoming packets are rejected.  Set enable and wait 2ms so that
2149          * any packet that was coming in as RCTL.EN was set is flushed
2150          */
2151         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2152         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2153
2154         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2155         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2156
2157         rctl = E1000_READ_REG(hw, E1000_RCTL);
2158         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2159         temp_rctl |= E1000_RCTL_LPE;
2160
2161         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2162         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2163         E1000_WRITE_FLUSH(hw);
2164         msec_delay(2);
2165
2166         /* Enable Rx queues that were previously enabled and restore our
2167          * previous state
2168          */
2169         for (i = 0; i < 4; i++)
2170                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2171         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2172         E1000_WRITE_FLUSH(hw);
2173
2174         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2175         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2176
2177         /* Flush receive errors generated by workaround */
2178         E1000_READ_REG(hw, E1000_ROC);
2179         E1000_READ_REG(hw, E1000_RNBC);
2180         E1000_READ_REG(hw, E1000_MPC);
2181 }
2182
2183 /**
2184  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2185  *  @hw: pointer to the HW structure
2186  *
2187  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2188  *  however the hardware default for these parts is 500us to 1ms which is less
2189  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2190  *  increase the value to either 10ms to 200ms for capability version 1 config,
2191  *  or 16ms to 55ms for version 2.
2192  **/
2193 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2194 {
2195         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2196         s32 ret_val = E1000_SUCCESS;
2197         u16 pcie_devctl2;
2198
2199         /* only take action if timeout value is defaulted to 0 */
2200         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2201                 goto out;
2202
2203         /*
2204          * if capababilities version is type 1 we can write the
2205          * timeout of 10ms to 200ms through the GCR register
2206          */
2207         if (!(gcr & E1000_GCR_CAP_VER2)) {
2208                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2209                 goto out;
2210         }
2211
2212         /*
2213          * for version 2 capabilities we need to write the config space
2214          * directly in order to set the completion timeout value for
2215          * 16ms to 55ms
2216          */
2217         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2218                                           &pcie_devctl2);
2219         if (ret_val)
2220                 goto out;
2221
2222         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2223
2224         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2225                                            &pcie_devctl2);
2226 out:
2227         /* disable completion timeout resend */
2228         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2229
2230         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2231         return ret_val;
2232 }
2233
2234 /**
2235  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2236  *  @hw: pointer to the hardware struct
2237  *  @enable: state to enter, either enabled or disabled
2238  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2239  *
2240  *  enables/disables L2 switch anti-spoofing functionality.
2241  **/
2242 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2243 {
2244         u32 reg_val, reg_offset;
2245
2246         switch (hw->mac.type) {
2247         case e1000_82576:
2248                 reg_offset = E1000_DTXSWC;
2249                 break;
2250         case e1000_i350:
2251         case e1000_i354:
2252                 reg_offset = E1000_TXSWC;
2253                 break;
2254         default:
2255                 return;
2256         }
2257
2258         reg_val = E1000_READ_REG(hw, reg_offset);
2259         if (enable) {
2260                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2261                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2262                 /* The PF can spoof - it has to in order to
2263                  * support emulation mode NICs
2264                  */
2265                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2266         } else {
2267                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2268                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2269         }
2270         E1000_WRITE_REG(hw, reg_offset, reg_val);
2271 }
2272
2273 /**
2274  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2275  *  @hw: pointer to the hardware struct
2276  *  @enable: state to enter, either enabled or disabled
2277  *
2278  *  enables/disables L2 switch loopback functionality.
2279  **/
2280 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2281 {
2282         u32 dtxswc;
2283
2284         switch (hw->mac.type) {
2285         case e1000_82576:
2286                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2287                 if (enable)
2288                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2289                 else
2290                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2291                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2292                 break;
2293         case e1000_i350:
2294         case e1000_i354:
2295                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2296                 if (enable)
2297                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2298                 else
2299                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2300                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2301                 break;
2302         default:
2303                 /* Currently no other hardware supports loopback */
2304                 break;
2305         }
2306
2307
2308 }
2309
2310 /**
2311  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2312  *  @hw: pointer to the hardware struct
2313  *  @enable: state to enter, either enabled or disabled
2314  *
2315  *  enables/disables replication of packets across multiple pools.
2316  **/
2317 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2318 {
2319         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2320
2321         if (enable)
2322                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2323         else
2324                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2325
2326         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2327 }
2328
2329 /**
2330  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2331  *  @hw: pointer to the HW structure
2332  *  @offset: register offset to be read
2333  *  @data: pointer to the read data
2334  *
2335  *  Reads the MDI control register in the PHY at offset and stores the
2336  *  information read to data.
2337  **/
2338 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2339 {
2340         s32 ret_val;
2341
2342         DEBUGFUNC("e1000_read_phy_reg_82580");
2343
2344         ret_val = hw->phy.ops.acquire(hw);
2345         if (ret_val)
2346                 goto out;
2347
2348         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2349
2350         hw->phy.ops.release(hw);
2351
2352 out:
2353         return ret_val;
2354 }
2355
2356 /**
2357  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2358  *  @hw: pointer to the HW structure
2359  *  @offset: register offset to write to
2360  *  @data: data to write to register at offset
2361  *
2362  *  Writes data to MDI control register in the PHY at offset.
2363  **/
2364 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2365 {
2366         s32 ret_val;
2367
2368         DEBUGFUNC("e1000_write_phy_reg_82580");
2369
2370         ret_val = hw->phy.ops.acquire(hw);
2371         if (ret_val)
2372                 goto out;
2373
2374         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2375
2376         hw->phy.ops.release(hw);
2377
2378 out:
2379         return ret_val;
2380 }
2381
2382 /**
2383  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2384  *  @hw: pointer to the HW structure
2385  *
2386  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2387  *  the values found in the EEPROM.  This addresses an issue in which these
2388  *  bits are not restored from EEPROM after reset.
2389  **/
2390 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2391 {
2392         s32 ret_val = E1000_SUCCESS;
2393         u32 mdicnfg;
2394         u16 nvm_data = 0;
2395
2396         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2397
2398         if (hw->mac.type != e1000_82580)
2399                 goto out;
2400         if (!e1000_sgmii_active_82575(hw))
2401                 goto out;
2402
2403         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2404                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2405                                    &nvm_data);
2406         if (ret_val) {
2407                 DEBUGOUT("NVM Read Error\n");
2408                 goto out;
2409         }
2410
2411         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2412         if (nvm_data & NVM_WORD24_EXT_MDIO)
2413                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2414         if (nvm_data & NVM_WORD24_COM_MDIO)
2415                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2416         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2417 out:
2418         return ret_val;
2419 }
2420
2421 /**
2422  *  e1000_reset_hw_82580 - Reset hardware
2423  *  @hw: pointer to the HW structure
2424  *
2425  *  This resets function or entire device (all ports, etc.)
2426  *  to a known state.
2427  **/
2428 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2429 {
2430         s32 ret_val = E1000_SUCCESS;
2431         /* BH SW mailbox bit in SW_FW_SYNC */
2432         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2433         u32 ctrl;
2434         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2435
2436         DEBUGFUNC("e1000_reset_hw_82580");
2437
2438         hw->dev_spec._82575.global_device_reset = false;
2439
2440         /* 82580 does not reliably do global_device_reset due to hw errata */
2441         if (hw->mac.type == e1000_82580)
2442                 global_device_reset = false;
2443
2444         /* Get current control state. */
2445         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2446
2447         /*
2448          * Prevent the PCI-E bus from sticking if there is no TLP connection
2449          * on the last TLP read/write transaction when MAC is reset.
2450          */
2451         ret_val = e1000_disable_pcie_master_generic(hw);
2452         if (ret_val)
2453                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2454
2455         DEBUGOUT("Masking off all interrupts\n");
2456         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2457         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2458         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2459         E1000_WRITE_FLUSH(hw);
2460
2461         msec_delay(10);
2462
2463         /* Determine whether or not a global dev reset is requested */
2464         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2465             swmbsw_mask))
2466                         global_device_reset = false;
2467
2468         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2469             E1000_STAT_DEV_RST_SET))
2470                 ctrl |= E1000_CTRL_DEV_RST;
2471         else
2472                 ctrl |= E1000_CTRL_RST;
2473
2474         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2475         E1000_WRITE_FLUSH(hw);
2476
2477         /* Add delay to insure DEV_RST has time to complete */
2478         if (global_device_reset)
2479                 msec_delay(5);
2480
2481         ret_val = e1000_get_auto_rd_done_generic(hw);
2482         if (ret_val) {
2483                 /*
2484                  * When auto config read does not complete, do not
2485                  * return with an error. This can happen in situations
2486                  * where there is no eeprom and prevents getting link.
2487                  */
2488                 DEBUGOUT("Auto Read Done did not complete\n");
2489         }
2490
2491         /* clear global device reset status bit */
2492         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2493
2494         /* Clear any pending interrupt events. */
2495         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2496         E1000_READ_REG(hw, E1000_ICR);
2497
2498         ret_val = e1000_reset_mdicnfg_82580(hw);
2499         if (ret_val)
2500                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2501
2502         /* Install any alternate MAC address into RAR0 */
2503         ret_val = e1000_check_alt_mac_addr_generic(hw);
2504
2505         /* Release semaphore */
2506         if (global_device_reset)
2507                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2508
2509         return ret_val;
2510 }
2511
2512 /**
2513  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2514  *  @data: data received by reading RXPBS register
2515  *
2516  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2517  *  This function converts the retrieved value into the correct table value
2518  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2519  *  0x0 36  72 144   1   2   4   8  16
2520  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2521  */
2522 u16 e1000_rxpbs_adjust_82580(u32 data)
2523 {
2524         u16 ret_val = 0;
2525
2526         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2527                 ret_val = e1000_82580_rxpbs_table[data];
2528
2529         return ret_val;
2530 }
2531
2532 /**
2533  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2534  *  checksum
2535  *  @hw: pointer to the HW structure
2536  *  @offset: offset in words of the checksum protected region
2537  *
2538  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2539  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2540  **/
2541 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2542 {
2543         s32 ret_val = E1000_SUCCESS;
2544         u16 checksum = 0;
2545         u16 i, nvm_data;
2546
2547         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2548
2549         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2550                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2551                 if (ret_val) {
2552                         DEBUGOUT("NVM Read Error\n");
2553                         goto out;
2554                 }
2555                 checksum += nvm_data;
2556         }
2557
2558         if (checksum != (u16) NVM_SUM) {
2559                 DEBUGOUT("NVM Checksum Invalid\n");
2560                 ret_val = -E1000_ERR_NVM;
2561                 goto out;
2562         }
2563
2564 out:
2565         return ret_val;
2566 }
2567
2568 /**
2569  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2570  *  checksum
2571  *  @hw: pointer to the HW structure
2572  *  @offset: offset in words of the checksum protected region
2573  *
2574  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2575  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2576  *  value to the EEPROM.
2577  **/
2578 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2579 {
2580         s32 ret_val;
2581         u16 checksum = 0;
2582         u16 i, nvm_data;
2583
2584         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2585
2586         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2587                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2588                 if (ret_val) {
2589                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2590                         goto out;
2591                 }
2592                 checksum += nvm_data;
2593         }
2594         checksum = (u16) NVM_SUM - checksum;
2595         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2596                                     &checksum);
2597         if (ret_val)
2598                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2599
2600 out:
2601         return ret_val;
2602 }
2603
2604 /**
2605  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2606  *  @hw: pointer to the HW structure
2607  *
2608  *  Calculates the EEPROM section checksum by reading/adding each word of
2609  *  the EEPROM and then verifies that the sum of the EEPROM is
2610  *  equal to 0xBABA.
2611  **/
2612 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2613 {
2614         s32 ret_val;
2615         u16 eeprom_regions_count = 1;
2616         u16 j, nvm_data;
2617         u16 nvm_offset;
2618
2619         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2620
2621         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2622         if (ret_val) {
2623                 DEBUGOUT("NVM Read Error\n");
2624                 goto out;
2625         }
2626
2627         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2628                 /* if chekcsums compatibility bit is set validate checksums
2629                  * for all 4 ports. */
2630                 eeprom_regions_count = 4;
2631         }
2632
2633         for (j = 0; j < eeprom_regions_count; j++) {
2634                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2635                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2636                                                                   nvm_offset);
2637                 if (ret_val != E1000_SUCCESS)
2638                         goto out;
2639         }
2640
2641 out:
2642         return ret_val;
2643 }
2644
2645 /**
2646  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2647  *  @hw: pointer to the HW structure
2648  *
2649  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2650  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2651  *  checksum and writes the value to the EEPROM.
2652  **/
2653 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2654 {
2655         s32 ret_val;
2656         u16 j, nvm_data;
2657         u16 nvm_offset;
2658
2659         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2660
2661         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2662         if (ret_val) {
2663                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2664                 goto out;
2665         }
2666
2667         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2668                 /* set compatibility bit to validate checksums appropriately */
2669                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2670                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2671                                             &nvm_data);
2672                 if (ret_val) {
2673                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2674                         goto out;
2675                 }
2676         }
2677
2678         for (j = 0; j < 4; j++) {
2679                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2680                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2681                 if (ret_val)
2682                         goto out;
2683         }
2684
2685 out:
2686         return ret_val;
2687 }
2688
2689 /**
2690  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2691  *  @hw: pointer to the HW structure
2692  *
2693  *  Calculates the EEPROM section checksum by reading/adding each word of
2694  *  the EEPROM and then verifies that the sum of the EEPROM is
2695  *  equal to 0xBABA.
2696  **/
2697 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2698 {
2699         s32 ret_val = E1000_SUCCESS;
2700         u16 j;
2701         u16 nvm_offset;
2702
2703         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2704
2705         for (j = 0; j < 4; j++) {
2706                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2707                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2708                                                                   nvm_offset);
2709                 if (ret_val != E1000_SUCCESS)
2710                         goto out;
2711         }
2712
2713 out:
2714         return ret_val;
2715 }
2716
2717 /**
2718  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2719  *  @hw: pointer to the HW structure
2720  *
2721  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2722  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2723  *  checksum and writes the value to the EEPROM.
2724  **/
2725 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2726 {
2727         s32 ret_val = E1000_SUCCESS;
2728         u16 j;
2729         u16 nvm_offset;
2730
2731         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2732
2733         for (j = 0; j < 4; j++) {
2734                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2735                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2736                 if (ret_val != E1000_SUCCESS)
2737                         goto out;
2738         }
2739
2740 out:
2741         return ret_val;
2742 }
2743
2744 /**
2745  *  __e1000_access_emi_reg - Read/write EMI register
2746  *  @hw: pointer to the HW structure
2747  *  @addr: EMI address to program
2748  *  @data: pointer to value to read/write from/to the EMI address
2749  *  @read: boolean flag to indicate read or write
2750  **/
2751 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2752                                   u16 *data, bool read)
2753 {
2754         s32 ret_val;
2755
2756         DEBUGFUNC("__e1000_access_emi_reg");
2757
2758         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2759         if (ret_val)
2760                 return ret_val;
2761
2762         if (read)
2763                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2764         else
2765                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2766
2767         return ret_val;
2768 }
2769
2770 /**
2771  *  e1000_read_emi_reg - Read Extended Management Interface register
2772  *  @hw: pointer to the HW structure
2773  *  @addr: EMI address to program
2774  *  @data: value to be read from the EMI address
2775  **/
2776 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2777 {
2778         DEBUGFUNC("e1000_read_emi_reg");
2779
2780         return __e1000_access_emi_reg(hw, addr, data, true);
2781 }
2782
2783 /**
2784  *  e1000_set_eee_i350 - Enable/disable EEE support
2785  *  @hw: pointer to the HW structure
2786  *
2787  *  Enable/disable EEE based on setting in dev_spec structure.
2788  *
2789  **/
2790 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2791 {
2792         s32 ret_val = E1000_SUCCESS;
2793         u32 ipcnfg, eeer;
2794
2795         DEBUGFUNC("e1000_set_eee_i350");
2796
2797         if ((hw->mac.type < e1000_i350) ||
2798             (hw->phy.media_type != e1000_media_type_copper))
2799                 goto out;
2800         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2801         eeer = E1000_READ_REG(hw, E1000_EEER);
2802
2803         /* enable or disable per user setting */
2804         if (!(hw->dev_spec._82575.eee_disable)) {
2805                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2806
2807                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2808                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2809                          E1000_EEER_LPI_FC);
2810
2811                 /* This bit should not be set in normal operation. */
2812                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2813                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2814         } else {
2815                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2816                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2817                           E1000_EEER_LPI_FC);
2818         }
2819         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2820         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2821         E1000_READ_REG(hw, E1000_IPCNFG);
2822         E1000_READ_REG(hw, E1000_EEER);
2823 out:
2824
2825         return ret_val;
2826 }
2827
2828 /**
2829  *  e1000_set_eee_i354 - Enable/disable EEE support
2830  *  @hw: pointer to the HW structure
2831  *
2832  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2833  *
2834  **/
2835 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2836 {
2837         struct e1000_phy_info *phy = &hw->phy;
2838         s32 ret_val = E1000_SUCCESS;
2839         u16 phy_data;
2840
2841         DEBUGFUNC("e1000_set_eee_i354");
2842
2843         if ((hw->phy.media_type != e1000_media_type_copper) ||
2844             ((phy->id != M88E1543_E_PHY_ID) &&
2845             (phy->id != M88E1512_E_PHY_ID)))
2846                 goto out;
2847
2848         if (!hw->dev_spec._82575.eee_disable) {
2849                 /* Switch to PHY page 18. */
2850                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2851                 if (ret_val)
2852                         goto out;
2853
2854                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2855                                             &phy_data);
2856                 if (ret_val)
2857                         goto out;
2858
2859                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2860                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2861                                              phy_data);
2862                 if (ret_val)
2863                         goto out;
2864
2865                 /* Return the PHY to page 0. */
2866                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2867                 if (ret_val)
2868                         goto out;
2869
2870                 /* Turn on EEE advertisement. */
2871                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2872                                                E1000_EEE_ADV_DEV_I354,
2873                                                &phy_data);
2874                 if (ret_val)
2875                         goto out;
2876
2877                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2878                             E1000_EEE_ADV_1000_SUPPORTED;
2879                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2880                                                 E1000_EEE_ADV_DEV_I354,
2881                                                 phy_data);
2882         } else {
2883                 /* Turn off EEE advertisement. */
2884                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2885                                                E1000_EEE_ADV_DEV_I354,
2886                                                &phy_data);
2887                 if (ret_val)
2888                         goto out;
2889
2890                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2891                               E1000_EEE_ADV_1000_SUPPORTED);
2892                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2893                                                 E1000_EEE_ADV_DEV_I354,
2894                                                 phy_data);
2895         }
2896
2897 out:
2898         return ret_val;
2899 }
2900
2901 /**
2902  *  e1000_get_eee_status_i354 - Get EEE status
2903  *  @hw: pointer to the HW structure
2904  *  @status: EEE status
2905  *
2906  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2907  *  been received.
2908  **/
2909 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2910 {
2911         struct e1000_phy_info *phy = &hw->phy;
2912         s32 ret_val = E1000_SUCCESS;
2913         u16 phy_data;
2914
2915         DEBUGFUNC("e1000_get_eee_status_i354");
2916
2917         /* Check if EEE is supported on this device. */
2918         if ((hw->phy.media_type != e1000_media_type_copper) ||
2919             ((phy->id != M88E1543_E_PHY_ID) &&
2920             (phy->id != M88E1512_E_PHY_ID)))
2921                 goto out;
2922
2923         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2924                                        E1000_PCS_STATUS_DEV_I354,
2925                                        &phy_data);
2926         if (ret_val)
2927                 goto out;
2928
2929         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2930                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2931
2932 out:
2933         return ret_val;
2934 }
2935
2936 /* Due to a hw errata, if the host tries to  configure the VFTA register
2937  * while performing queries from the BMC or DMA, then the VFTA in some
2938  * cases won't be written.
2939  */
2940
2941 /**
2942  *  e1000_clear_vfta_i350 - Clear VLAN filter table
2943  *  @hw: pointer to the HW structure
2944  *
2945  *  Clears the register array which contains the VLAN filter table by
2946  *  setting all the values to 0.
2947  **/
2948 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2949 {
2950         u32 offset;
2951         int i;
2952
2953         DEBUGFUNC("e1000_clear_vfta_350");
2954
2955         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2956                 for (i = 0; i < 10; i++)
2957                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2958
2959                 E1000_WRITE_FLUSH(hw);
2960         }
2961 }
2962
2963 /**
2964  *  e1000_write_vfta_i350 - Write value to VLAN filter table
2965  *  @hw: pointer to the HW structure
2966  *  @offset: register offset in VLAN filter table
2967  *  @value: register value written to VLAN filter table
2968  *
2969  *  Writes value at the given offset in the register array which stores
2970  *  the VLAN filter table.
2971  **/
2972 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2973 {
2974         int i;
2975
2976         DEBUGFUNC("e1000_write_vfta_350");
2977
2978         for (i = 0; i < 10; i++)
2979                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2980
2981         E1000_WRITE_FLUSH(hw);
2982 }
2983
2984
2985 /**
2986  *  e1000_set_i2c_bb - Enable I2C bit-bang
2987  *  @hw: pointer to the HW structure
2988  *
2989  *  Enable I2C bit-bang interface
2990  *
2991  **/
2992 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2993 {
2994         s32 ret_val = E1000_SUCCESS;
2995         u32 ctrl_ext, i2cparams;
2996
2997         DEBUGFUNC("e1000_set_i2c_bb");
2998
2999         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3000         ctrl_ext |= E1000_CTRL_I2C_ENA;
3001         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3002         E1000_WRITE_FLUSH(hw);
3003
3004         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3005         i2cparams |= E1000_I2CBB_EN;
3006         i2cparams |= E1000_I2C_DATA_OE_N;
3007         i2cparams |= E1000_I2C_CLK_OE_N;
3008         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3009         E1000_WRITE_FLUSH(hw);
3010
3011         return ret_val;
3012 }
3013
3014 /**
3015  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3016  *  @hw: pointer to hardware structure
3017  *  @byte_offset: byte offset to read
3018  *  @dev_addr: device address
3019  *  @data: value read
3020  *
3021  *  Performs byte read operation over I2C interface at
3022  *  a specified device address.
3023  **/
3024 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3025                                 u8 dev_addr, u8 *data)
3026 {
3027         s32 status = E1000_SUCCESS;
3028         u32 max_retry = 10;
3029         u32 retry = 1;
3030         u16 swfw_mask = 0;
3031
3032         bool nack = true;
3033
3034         DEBUGFUNC("e1000_read_i2c_byte_generic");
3035
3036         swfw_mask = E1000_SWFW_PHY0_SM;
3037
3038         do {
3039                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3040                     != E1000_SUCCESS) {
3041                         status = E1000_ERR_SWFW_SYNC;
3042                         goto read_byte_out;
3043                 }
3044
3045                 e1000_i2c_start(hw);
3046
3047                 /* Device Address and write indication */
3048                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3049                 if (status != E1000_SUCCESS)
3050                         goto fail;
3051
3052                 status = e1000_get_i2c_ack(hw);
3053                 if (status != E1000_SUCCESS)
3054                         goto fail;
3055
3056                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3057                 if (status != E1000_SUCCESS)
3058                         goto fail;
3059
3060                 status = e1000_get_i2c_ack(hw);
3061                 if (status != E1000_SUCCESS)
3062                         goto fail;
3063
3064                 e1000_i2c_start(hw);
3065
3066                 /* Device Address and read indication */
3067                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3068                 if (status != E1000_SUCCESS)
3069                         goto fail;
3070
3071                 status = e1000_get_i2c_ack(hw);
3072                 if (status != E1000_SUCCESS)
3073                         goto fail;
3074
3075                 status = e1000_clock_in_i2c_byte(hw, data);
3076                 if (status != E1000_SUCCESS)
3077                         goto fail;
3078
3079                 status = e1000_clock_out_i2c_bit(hw, nack);
3080                 if (status != E1000_SUCCESS)
3081                         goto fail;
3082
3083                 e1000_i2c_stop(hw);
3084                 break;
3085
3086 fail:
3087                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3088                 msec_delay(100);
3089                 e1000_i2c_bus_clear(hw);
3090                 retry++;
3091                 if (retry < max_retry)
3092                         DEBUGOUT("I2C byte read error - Retrying.\n");
3093                 else
3094                         DEBUGOUT("I2C byte read error.\n");
3095
3096         } while (retry < max_retry);
3097
3098         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3099
3100 read_byte_out:
3101
3102         return status;
3103 }
3104
3105 /**
3106  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3107  *  @hw: pointer to hardware structure
3108  *  @byte_offset: byte offset to write
3109  *  @dev_addr: device address
3110  *  @data: value to write
3111  *
3112  *  Performs byte write operation over I2C interface at
3113  *  a specified device address.
3114  **/
3115 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3116                                  u8 dev_addr, u8 data)
3117 {
3118         s32 status = E1000_SUCCESS;
3119         u32 max_retry = 1;
3120         u32 retry = 0;
3121         u16 swfw_mask = 0;
3122
3123         DEBUGFUNC("e1000_write_i2c_byte_generic");
3124
3125         swfw_mask = E1000_SWFW_PHY0_SM;
3126
3127         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3128                 status = E1000_ERR_SWFW_SYNC;
3129                 goto write_byte_out;
3130         }
3131
3132         do {
3133                 e1000_i2c_start(hw);
3134
3135                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3136                 if (status != E1000_SUCCESS)
3137                         goto fail;
3138
3139                 status = e1000_get_i2c_ack(hw);
3140                 if (status != E1000_SUCCESS)
3141                         goto fail;
3142
3143                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3144                 if (status != E1000_SUCCESS)
3145                         goto fail;
3146
3147                 status = e1000_get_i2c_ack(hw);
3148                 if (status != E1000_SUCCESS)
3149                         goto fail;
3150
3151                 status = e1000_clock_out_i2c_byte(hw, data);
3152                 if (status != E1000_SUCCESS)
3153                         goto fail;
3154
3155                 status = e1000_get_i2c_ack(hw);
3156                 if (status != E1000_SUCCESS)
3157                         goto fail;
3158
3159                 e1000_i2c_stop(hw);
3160                 break;
3161
3162 fail:
3163                 e1000_i2c_bus_clear(hw);
3164                 retry++;
3165                 if (retry < max_retry)
3166                         DEBUGOUT("I2C byte write error - Retrying.\n");
3167                 else
3168                         DEBUGOUT("I2C byte write error.\n");
3169         } while (retry < max_retry);
3170
3171         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3172
3173 write_byte_out:
3174
3175         return status;
3176 }
3177
3178 /**
3179  *  e1000_i2c_start - Sets I2C start condition
3180  *  @hw: pointer to hardware structure
3181  *
3182  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3183  **/
3184 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3185 {
3186         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3187
3188         DEBUGFUNC("e1000_i2c_start");
3189
3190         /* Start condition must begin with data and clock high */
3191         e1000_set_i2c_data(hw, &i2cctl, 1);
3192         e1000_raise_i2c_clk(hw, &i2cctl);
3193
3194         /* Setup time for start condition (4.7us) */
3195         usec_delay(E1000_I2C_T_SU_STA);
3196
3197         e1000_set_i2c_data(hw, &i2cctl, 0);
3198
3199         /* Hold time for start condition (4us) */
3200         usec_delay(E1000_I2C_T_HD_STA);
3201
3202         e1000_lower_i2c_clk(hw, &i2cctl);
3203
3204         /* Minimum low period of clock is 4.7 us */
3205         usec_delay(E1000_I2C_T_LOW);
3206
3207 }
3208
3209 /**
3210  *  e1000_i2c_stop - Sets I2C stop condition
3211  *  @hw: pointer to hardware structure
3212  *
3213  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3214  **/
3215 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3216 {
3217         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3218
3219         DEBUGFUNC("e1000_i2c_stop");
3220
3221         /* Stop condition must begin with data low and clock high */
3222         e1000_set_i2c_data(hw, &i2cctl, 0);
3223         e1000_raise_i2c_clk(hw, &i2cctl);
3224
3225         /* Setup time for stop condition (4us) */
3226         usec_delay(E1000_I2C_T_SU_STO);
3227
3228         e1000_set_i2c_data(hw, &i2cctl, 1);
3229
3230         /* bus free time between stop and start (4.7us)*/
3231         usec_delay(E1000_I2C_T_BUF);
3232 }
3233
3234 /**
3235  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3236  *  @hw: pointer to hardware structure
3237  *  @data: data byte to clock in
3238  *
3239  *  Clocks in one byte data via I2C data/clock
3240  **/
3241 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3242 {
3243         s32 i;
3244         bool bit = 0;
3245
3246         DEBUGFUNC("e1000_clock_in_i2c_byte");
3247
3248         *data = 0;
3249         for (i = 7; i >= 0; i--) {
3250                 e1000_clock_in_i2c_bit(hw, &bit);
3251                 *data |= bit << i;
3252         }
3253
3254         return E1000_SUCCESS;
3255 }
3256
3257 /**
3258  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3259  *  @hw: pointer to hardware structure
3260  *  @data: data byte clocked out
3261  *
3262  *  Clocks out one byte data via I2C data/clock
3263  **/
3264 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3265 {
3266         s32 status = E1000_SUCCESS;
3267         s32 i;
3268         u32 i2cctl;
3269         bool bit = 0;
3270
3271         DEBUGFUNC("e1000_clock_out_i2c_byte");
3272
3273         for (i = 7; i >= 0; i--) {
3274                 bit = (data >> i) & 0x1;
3275                 status = e1000_clock_out_i2c_bit(hw, bit);
3276
3277                 if (status != E1000_SUCCESS)
3278                         break;
3279         }
3280
3281         /* Release SDA line (set high) */
3282         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3283
3284         i2cctl |= E1000_I2C_DATA_OE_N;
3285         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3286         E1000_WRITE_FLUSH(hw);
3287
3288         return status;
3289 }
3290
3291 /**
3292  *  e1000_get_i2c_ack - Polls for I2C ACK
3293  *  @hw: pointer to hardware structure
3294  *
3295  *  Clocks in/out one bit via I2C data/clock
3296  **/
3297 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3298 {
3299         s32 status = E1000_SUCCESS;
3300         u32 i = 0;
3301         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3302         u32 timeout = 10;
3303         bool ack = true;
3304
3305         DEBUGFUNC("e1000_get_i2c_ack");
3306
3307         e1000_raise_i2c_clk(hw, &i2cctl);
3308
3309         /* Minimum high period of clock is 4us */
3310         usec_delay(E1000_I2C_T_HIGH);
3311
3312         /* Wait until SCL returns high */
3313         for (i = 0; i < timeout; i++) {
3314                 usec_delay(1);
3315                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3316                 if (i2cctl & E1000_I2C_CLK_IN)
3317                         break;
3318         }
3319         if (!(i2cctl & E1000_I2C_CLK_IN))
3320                 return E1000_ERR_I2C;
3321
3322         ack = e1000_get_i2c_data(&i2cctl);
3323         if (ack) {
3324                 DEBUGOUT("I2C ack was not received.\n");
3325                 status = E1000_ERR_I2C;
3326         }
3327
3328         e1000_lower_i2c_clk(hw, &i2cctl);
3329
3330         /* Minimum low period of clock is 4.7 us */
3331         usec_delay(E1000_I2C_T_LOW);
3332
3333         return status;
3334 }
3335
3336 /**
3337  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3338  *  @hw: pointer to hardware structure
3339  *  @data: read data value
3340  *
3341  *  Clocks in one bit via I2C data/clock
3342  **/
3343 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3344 {
3345         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3346
3347         DEBUGFUNC("e1000_clock_in_i2c_bit");
3348
3349         e1000_raise_i2c_clk(hw, &i2cctl);
3350
3351         /* Minimum high period of clock is 4us */
3352         usec_delay(E1000_I2C_T_HIGH);
3353
3354         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3355         *data = e1000_get_i2c_data(&i2cctl);
3356
3357         e1000_lower_i2c_clk(hw, &i2cctl);
3358
3359         /* Minimum low period of clock is 4.7 us */
3360         usec_delay(E1000_I2C_T_LOW);
3361
3362         return E1000_SUCCESS;
3363 }
3364
3365 /**
3366  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3367  *  @hw: pointer to hardware structure
3368  *  @data: data value to write
3369  *
3370  *  Clocks out one bit via I2C data/clock
3371  **/
3372 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3373 {
3374         s32 status;
3375         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3376
3377         DEBUGFUNC("e1000_clock_out_i2c_bit");
3378
3379         status = e1000_set_i2c_data(hw, &i2cctl, data);
3380         if (status == E1000_SUCCESS) {
3381                 e1000_raise_i2c_clk(hw, &i2cctl);
3382
3383                 /* Minimum high period of clock is 4us */
3384                 usec_delay(E1000_I2C_T_HIGH);
3385
3386                 e1000_lower_i2c_clk(hw, &i2cctl);
3387
3388                 /* Minimum low period of clock is 4.7 us.
3389                  * This also takes care of the data hold time.
3390                  */
3391                 usec_delay(E1000_I2C_T_LOW);
3392         } else {
3393                 status = E1000_ERR_I2C;
3394                 DEBUGOUT1("I2C data was not set to %X\n", data);
3395         }
3396
3397         return status;
3398 }
3399 /**
3400  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3401  *  @hw: pointer to hardware structure
3402  *  @i2cctl: Current value of I2CCTL register
3403  *
3404  *  Raises the I2C clock line '0'->'1'
3405  **/
3406 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3407 {
3408         DEBUGFUNC("e1000_raise_i2c_clk");
3409
3410         *i2cctl |= E1000_I2C_CLK_OUT;
3411         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3412         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3413         E1000_WRITE_FLUSH(hw);
3414
3415         /* SCL rise time (1000ns) */
3416         usec_delay(E1000_I2C_T_RISE);
3417 }
3418
3419 /**
3420  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3421  *  @hw: pointer to hardware structure
3422  *  @i2cctl: Current value of I2CCTL register
3423  *
3424  *  Lowers the I2C clock line '1'->'0'
3425  **/
3426 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3427 {
3428
3429         DEBUGFUNC("e1000_lower_i2c_clk");
3430
3431         *i2cctl &= ~E1000_I2C_CLK_OUT;
3432         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3433         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3434         E1000_WRITE_FLUSH(hw);
3435
3436         /* SCL fall time (300ns) */
3437         usec_delay(E1000_I2C_T_FALL);
3438 }
3439
3440 /**
3441  *  e1000_set_i2c_data - Sets the I2C data bit
3442  *  @hw: pointer to hardware structure
3443  *  @i2cctl: Current value of I2CCTL register
3444  *  @data: I2C data value (0 or 1) to set
3445  *
3446  *  Sets the I2C data bit
3447  **/
3448 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3449 {
3450         s32 status = E1000_SUCCESS;
3451
3452         DEBUGFUNC("e1000_set_i2c_data");
3453
3454         if (data)
3455                 *i2cctl |= E1000_I2C_DATA_OUT;
3456         else
3457                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3458
3459         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3460         *i2cctl |= E1000_I2C_CLK_OE_N;
3461         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3462         E1000_WRITE_FLUSH(hw);
3463
3464         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3465         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3466
3467         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3468         if (data != e1000_get_i2c_data(i2cctl)) {
3469                 status = E1000_ERR_I2C;
3470                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3471         }
3472
3473         return status;
3474 }
3475
3476 /**
3477  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3478  *  @hw: pointer to hardware structure
3479  *  @i2cctl: Current value of I2CCTL register
3480  *
3481  *  Returns the I2C data bit value
3482  **/
3483 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3484 {
3485         bool data;
3486
3487         DEBUGFUNC("e1000_get_i2c_data");
3488
3489         if (*i2cctl & E1000_I2C_DATA_IN)
3490                 data = 1;
3491         else
3492                 data = 0;
3493
3494         return data;
3495 }
3496
3497 /**
3498  *  e1000_i2c_bus_clear - Clears the I2C bus
3499  *  @hw: pointer to hardware structure
3500  *
3501  *  Clears the I2C bus by sending nine clock pulses.
3502  *  Used when data line is stuck low.
3503  **/
3504 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3505 {
3506         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3507         u32 i;
3508
3509         DEBUGFUNC("e1000_i2c_bus_clear");
3510
3511         e1000_i2c_start(hw);
3512
3513         e1000_set_i2c_data(hw, &i2cctl, 1);
3514
3515         for (i = 0; i < 9; i++) {
3516                 e1000_raise_i2c_clk(hw, &i2cctl);
3517
3518                 /* Min high period of clock is 4us */
3519                 usec_delay(E1000_I2C_T_HIGH);
3520
3521                 e1000_lower_i2c_clk(hw, &i2cctl);
3522
3523                 /* Min low period of clock is 4.7us*/
3524                 usec_delay(E1000_I2C_T_LOW);
3525         }
3526
3527         e1000_i2c_start(hw);
3528
3529         /* Put the i2c bus back to default state */
3530         e1000_i2c_stop(hw);
3531 }
3532