lib/librte_pmd_e1000/e1000/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_init_hw_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  60 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  61                                            u16 *data);
  62 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  63 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  64 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  65                                      u32 offset, u16 *data);
  66 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  67                                       u32 offset, u16 data);
  68 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  69                                           bool active);
  70 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  71                                           bool active);
  72 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  73                                           bool active);
  74 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  78 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  79 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  80                                             u32 offset, u16 data);
  81 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  82 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  83 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  84                                                  u16 *speed, u16 *duplex);
  85 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  86 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  89 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  90 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  91 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  92 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  94 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  95 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  98 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  99                                                  u16 offset);
 100 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 101                                                    u16 offset);
 102 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 104 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 105 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 106
 107 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 108 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 109 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 110 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 111 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 112 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 113 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 114 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 116 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 117 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 118
 119 static const u16 e1000_82580_rxpbs_table[] = {
 120         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 121 #define E1000_82580_RXPBS_TABLE_SIZE \
 122         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
 123
 124
 125 /**
 126  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 127  *  @hw: pointer to the HW structure
 128  *
 129  *  Called to determine if the I2C pins are being used for I2C or as an
 130  *  external MDIO interface since the two options are mutually exclusive.
 131  **/
 132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 133 {
 134         u32 reg = 0;
 135         bool ext_mdio = false;
 136
 137         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 138
 139         switch (hw->mac.type) {
 140         case e1000_82575:
 141         case e1000_82576:
 142                 reg = E1000_READ_REG(hw, E1000_MDIC);
 143                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 144                 break;
 145         case e1000_82580:
 146         case e1000_i350:
 147         case e1000_i354:
 148         case e1000_i210:
 149         case e1000_i211:
 150                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 151                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 152                 break;
 153         default:
 154                 break;
 155         }
 156         return ext_mdio;
 157 }
 158
 159 /**
 160  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 161  *  @hw: pointer to the HW structure
 162  **/
 163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 164 {
 165         struct e1000_phy_info *phy = &hw->phy;
 166         s32 ret_val = E1000_SUCCESS;
 167         u32 ctrl_ext;
 168
 169         DEBUGFUNC("e1000_init_phy_params_82575");
 170
 171         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 172         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 173
 174         if (hw->phy.media_type != e1000_media_type_copper) {
 175                 phy->type = e1000_phy_none;
 176                 goto out;
 177         }
 178
 179         phy->ops.power_up   = e1000_power_up_phy_copper;
 180         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 181
 182         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 183         phy->reset_delay_us     = 100;
 184
 185         phy->ops.acquire        = e1000_acquire_phy_82575;
 186         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 187         phy->ops.commit         = e1000_phy_sw_reset_generic;
 188         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 189         phy->ops.release        = e1000_release_phy_82575;
 190
 191         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 192
 193         if (e1000_sgmii_active_82575(hw)) {
 194                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 195                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 196         } else {
 197                 phy->ops.reset = e1000_phy_hw_reset_generic;
 198                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 199         }
 200
 201         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 202         e1000_reset_mdicnfg_82580(hw);
 203
 204         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 205                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 206                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 207         } else {
 208                 switch (hw->mac.type) {
 209                 case e1000_82580:
 210                 case e1000_i350:
 211                 case e1000_i354:
 212                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 213                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 214                         break;
 215                 case e1000_i210:
 216                 case e1000_i211:
 217                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 218                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 219                         break;
 220                 default:
 221                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 222                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 223                 }
 224         }
 225
 226         /* Set phy->phy_addr and phy->id. */
 227         ret_val = e1000_get_phy_id_82575(hw);
 228
 229         /* Verify phy id and set remaining function pointers */
 230         switch (phy->id) {
 231         case M88E1543_E_PHY_ID:
 232         case M88E1512_E_PHY_ID:
 233         case I347AT4_E_PHY_ID:
 234         case M88E1112_E_PHY_ID:
 235         case M88E1340M_E_PHY_ID:
 236         case M88E1111_I_PHY_ID:
 237                 phy->type               = e1000_phy_m88;
 238                 phy->ops.check_polarity = e1000_check_polarity_m88;
 239                 phy->ops.get_info       = e1000_get_phy_info_m88;
 240                 if (phy->id == I347AT4_E_PHY_ID ||
 241                     phy->id == M88E1112_E_PHY_ID ||
 242                     phy->id == M88E1340M_E_PHY_ID)
 243                         phy->ops.get_cable_length =
 244                                          e1000_get_cable_length_m88_gen2;
 245                 else if (phy->id == M88E1543_E_PHY_ID ||
 246                          phy->id == M88E1512_E_PHY_ID)
 247                         phy->ops.get_cable_length =
 248                                          e1000_get_cable_length_m88_gen2;
 249                 else
 250                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 251                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 252                 /* Check if this PHY is confgured for media swap. */
 253                 if (phy->id == M88E1112_E_PHY_ID) {
 254                         u16 data;
 255
 256                         ret_val = phy->ops.write_reg(hw,
 257                                                      E1000_M88E1112_PAGE_ADDR,
 258                                                      2);
 259                         if (ret_val)
 260                                 goto out;
 261
 262                         ret_val = phy->ops.read_reg(hw,
 263                                                     E1000_M88E1112_MAC_CTRL_1,
 264                                                     &data);
 265                         if (ret_val)
 266                                 goto out;
 267
 268                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 269                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 270                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 271                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 272                                 hw->mac.ops.check_for_link =
 273                                                 e1000_check_for_link_media_swap;
 274                 }
 275                 break;
 276         case IGP03E1000_E_PHY_ID:
 277         case IGP04E1000_E_PHY_ID:
 278                 phy->type = e1000_phy_igp_3;
 279                 phy->ops.check_polarity = e1000_check_polarity_igp;
 280                 phy->ops.get_info = e1000_get_phy_info_igp;
 281                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 282                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 283                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 284                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 285                 break;
 286         case I82580_I_PHY_ID:
 287         case I350_I_PHY_ID:
 288                 phy->type = e1000_phy_82580;
 289                 phy->ops.check_polarity = e1000_check_polarity_82577;
 290                 phy->ops.force_speed_duplex =
 291                                          e1000_phy_force_speed_duplex_82577;
 292                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 293                 phy->ops.get_info = e1000_get_phy_info_82577;
 294                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 295                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 296                 break;
 297         case I210_I_PHY_ID:
 298                 phy->type               = e1000_phy_i210;
 299                 phy->ops.check_polarity = e1000_check_polarity_m88;
 300                 phy->ops.get_info       = e1000_get_phy_info_m88;
 301                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 302                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 303                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 304                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 305                 break;
 306         default:
 307                 ret_val = -E1000_ERR_PHY;
 308                 goto out;
 309         }
 310
 311 out:
 312         return ret_val;
 313 }
 314
 315 /**
 316  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 317  *  @hw: pointer to the HW structure
 318  **/
 319 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 320 {
 321         struct e1000_nvm_info *nvm = &hw->nvm;
 322         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 323         u16 size;
 324
 325         DEBUGFUNC("e1000_init_nvm_params_82575");
 326
 327         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 328                      E1000_EECD_SIZE_EX_SHIFT);
 329         /*
 330          * Added to a constant, "size" becomes the left-shift value
 331          * for setting word_size.
 332          */
 333         size += NVM_WORD_SIZE_BASE_SHIFT;
 334
 335         /* Just in case size is out of range, cap it to the largest
 336          * EEPROM size supported
 337          */
 338         if (size > 15)
 339                 size = 15;
 340
 341         nvm->word_size = 1 << size;
 342         if (hw->mac.type < e1000_i210) {
 343                 nvm->opcode_bits = 8;
 344                 nvm->delay_usec = 1;
 345
 346                 switch (nvm->override) {
 347                 case e1000_nvm_override_spi_large:
 348                         nvm->page_size = 32;
 349                         nvm->address_bits = 16;
 350                         break;
 351                 case e1000_nvm_override_spi_small:
 352                         nvm->page_size = 8;
 353                         nvm->address_bits = 8;
 354                         break;
 355                 default:
 356                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 357                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 358                                             16 : 8;
 359                         break;
 360                 }
 361                 if (nvm->word_size == (1 << 15))
 362                         nvm->page_size = 128;
 363
 364                 nvm->type = e1000_nvm_eeprom_spi;
 365         } else {
 366                 nvm->type = e1000_nvm_flash_hw;
 367         }
 368
 369         /* Function Pointers */
 370         nvm->ops.acquire = e1000_acquire_nvm_82575;
 371         nvm->ops.release = e1000_release_nvm_82575;
 372         if (nvm->word_size < (1 << 15))
 373                 nvm->ops.read = e1000_read_nvm_eerd;
 374         else
 375                 nvm->ops.read = e1000_read_nvm_spi;
 376
 377         nvm->ops.write = e1000_write_nvm_spi;
 378         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 379         nvm->ops.update = e1000_update_nvm_checksum_generic;
 380         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 381
 382         /* override generic family function pointers for specific descendants */
 383         switch (hw->mac.type) {
 384         case e1000_82580:
 385                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 386                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 387                 break;
 388         case e1000_i350:
 389                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 390                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 391                 break;
 392         default:
 393                 break;
 394         }
 395
 396         return E1000_SUCCESS;
 397 }
 398
 399 /**
 400  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 401  *  @hw: pointer to the HW structure
 402  **/
 403 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 404 {
 405         struct e1000_mac_info *mac = &hw->mac;
 406         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 407
 408         DEBUGFUNC("e1000_init_mac_params_82575");
 409
 410         /* Derives media type */
 411         e1000_get_media_type_82575(hw);
 412         /* Set mta register count */
 413         mac->mta_reg_count = 128;
 414         /* Set uta register count */
 415         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 416         /* Set rar entry count */
 417         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 418         if (mac->type == e1000_82576)
 419                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 420         if (mac->type == e1000_82580)
 421                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 422         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 423                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 424
 425         /* Enable EEE default settings for EEE supported devices */
 426         if (mac->type >= e1000_i350)
 427                 dev_spec->eee_disable = false;
 428
 429         /* Allow a single clear of the SW semaphore on I210 and newer */
 430         if (mac->type >= e1000_i210)
 431                 dev_spec->clear_semaphore_once = true;
 432
 433         /* Set if part includes ASF firmware */
 434         mac->asf_firmware_present = true;
 435         /* FWSM register */
 436         mac->has_fwsm = true;
 437         /* ARC supported; valid only if manageability features are enabled. */
 438         mac->arc_subsystem_valid =
 439                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 440
 441         /* Function pointers */
 442
 443         /* bus type/speed/width */
 444         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 445         /* reset */
 446         if (mac->type >= e1000_82580)
 447                 mac->ops.reset_hw = e1000_reset_hw_82580;
 448         else
 449         mac->ops.reset_hw = e1000_reset_hw_82575;
 450         /* hw initialization */
 451         mac->ops.init_hw = e1000_init_hw_82575;
 452         /* link setup */
 453         mac->ops.setup_link = e1000_setup_link_generic;
 454         /* physical interface link setup */
 455         mac->ops.setup_physical_interface =
 456                 (hw->phy.media_type == e1000_media_type_copper)
 457                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 458         /* physical interface shutdown */
 459         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 460         /* physical interface power up */
 461         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 462         /* check for link */
 463         mac->ops.check_for_link = e1000_check_for_link_82575;
 464         /* read mac address */
 465         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 466         /* configure collision distance */
 467         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 468         /* multicast address update */
 469         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 470         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 471                 /* writing VFTA */
 472                 mac->ops.write_vfta = e1000_write_vfta_i350;
 473                 /* clearing VFTA */
 474                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 475         } else {
 476                 /* writing VFTA */
 477                 mac->ops.write_vfta = e1000_write_vfta_generic;
 478                 /* clearing VFTA */
 479                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 480         }
 481         if (hw->mac.type >= e1000_82580)
 482                 mac->ops.validate_mdi_setting =
 483                                 e1000_validate_mdi_setting_crossover_generic;
 484         /* ID LED init */
 485         mac->ops.id_led_init = e1000_id_led_init_generic;
 486         /* blink LED */
 487         mac->ops.blink_led = e1000_blink_led_generic;
 488         /* setup LED */
 489         mac->ops.setup_led = e1000_setup_led_generic;
 490         /* cleanup LED */
 491         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 492         /* turn on/off LED */
 493         mac->ops.led_on = e1000_led_on_generic;
 494         mac->ops.led_off = e1000_led_off_generic;
 495         /* clear hardware counters */
 496         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 497         /* link info */
 498         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 499         /* acquire SW_FW sync */
 500         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 501         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 502         if (mac->type >= e1000_i210) {
 503                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 504                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 505         }
 506
 507         /* set lan id for port to determine which phy lock to use */
 508         hw->mac.ops.set_lan_id(hw);
 509
 510         return E1000_SUCCESS;
 511 }
 512
 513 /**
 514  *  e1000_init_function_pointers_82575 - Init func ptrs.
 515  *  @hw: pointer to the HW structure
 516  *
 517  *  Called to initialize all function pointers and parameters.
 518  **/
 519 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 520 {
 521         DEBUGFUNC("e1000_init_function_pointers_82575");
 522
 523         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 524         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 525         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 526         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 527 }
 528
 529 /**
 530  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 531  *  @hw: pointer to the HW structure
 532  *
 533  *  Acquire access rights to the correct PHY.
 534  **/
 535 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 536 {
 537         u16 mask = E1000_SWFW_PHY0_SM;
 538
 539         DEBUGFUNC("e1000_acquire_phy_82575");
 540
 541         if (hw->bus.func == E1000_FUNC_1)
 542                 mask = E1000_SWFW_PHY1_SM;
 543         else if (hw->bus.func == E1000_FUNC_2)
 544                 mask = E1000_SWFW_PHY2_SM;
 545         else if (hw->bus.func == E1000_FUNC_3)
 546                 mask = E1000_SWFW_PHY3_SM;
 547
 548         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 549 }
 550
 551 /**
 552  *  e1000_release_phy_82575 - Release rights to access PHY
 553  *  @hw: pointer to the HW structure
 554  *
 555  *  A wrapper to release access rights to the correct PHY.
 556  **/
 557 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 558 {
 559         u16 mask = E1000_SWFW_PHY0_SM;
 560
 561         DEBUGFUNC("e1000_release_phy_82575");
 562
 563         if (hw->bus.func == E1000_FUNC_1)
 564                 mask = E1000_SWFW_PHY1_SM;
 565         else if (hw->bus.func == E1000_FUNC_2)
 566                 mask = E1000_SWFW_PHY2_SM;
 567         else if (hw->bus.func == E1000_FUNC_3)
 568                 mask = E1000_SWFW_PHY3_SM;
 569
 570         hw->mac.ops.release_swfw_sync(hw, mask);
 571 }
 572
 573 /**
 574  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 575  *  @hw: pointer to the HW structure
 576  *  @offset: register offset to be read
 577  *  @data: pointer to the read data
 578  *
 579  *  Reads the PHY register at offset using the serial gigabit media independent
 580  *  interface and stores the retrieved information in data.
 581  **/
 582 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 583                                           u16 *data)
 584 {
 585         s32 ret_val = -E1000_ERR_PARAM;
 586
 587         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 588
 589         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 590                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 591                 goto out;
 592         }
 593
 594         ret_val = hw->phy.ops.acquire(hw);
 595         if (ret_val)
 596                 goto out;
 597
 598         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 599
 600         hw->phy.ops.release(hw);
 601
 602 out:
 603         return ret_val;
 604 }
 605
 606 /**
 607  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 608  *  @hw: pointer to the HW structure
 609  *  @offset: register offset to write to
 610  *  @data: data to write at register offset
 611  *
 612  *  Writes the data to PHY register at the offset using the serial gigabit
 613  *  media independent interface.
 614  **/
 615 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 616                                            u16 data)
 617 {
 618         s32 ret_val = -E1000_ERR_PARAM;
 619
 620         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 621
 622         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 623                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 624                 goto out;
 625         }
 626
 627         ret_val = hw->phy.ops.acquire(hw);
 628         if (ret_val)
 629                 goto out;
 630
 631         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 632
 633         hw->phy.ops.release(hw);
 634
 635 out:
 636         return ret_val;
 637 }
 638
 639 /**
 640  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 641  *  @hw: pointer to the HW structure
 642  *
 643  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 644  *  sgmi interface.
 645  **/
 646 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 647 {
 648         struct e1000_phy_info *phy = &hw->phy;
 649         s32  ret_val = E1000_SUCCESS;
 650         u16 phy_id;
 651         u32 ctrl_ext;
 652         u32 mdic;
 653
 654         DEBUGFUNC("e1000_get_phy_id_82575");
 655
 656         /* some i354 devices need an extra read for phy id */
 657         if (hw->mac.type == e1000_i354)
 658                 e1000_get_phy_id(hw);
 659
 660         /*
 661          * For SGMII PHYs, we try the list of possible addresses until
 662          * we find one that works.  For non-SGMII PHYs
 663          * (e.g. integrated copper PHYs), an address of 1 should
 664          * work.  The result of this function should mean phy->phy_addr
 665          * and phy->id are set correctly.
 666          */
 667         if (!e1000_sgmii_active_82575(hw)) {
 668                 phy->addr = 1;
 669                 ret_val = e1000_get_phy_id(hw);
 670                 goto out;
 671         }
 672
 673         if (e1000_sgmii_uses_mdio_82575(hw)) {
 674                 switch (hw->mac.type) {
 675                 case e1000_82575:
 676                 case e1000_82576:
 677                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 678                         mdic &= E1000_MDIC_PHY_MASK;
 679                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 680                         break;
 681                 case e1000_82580:
 682                 case e1000_i350:
 683                 case e1000_i354:
 684                 case e1000_i210:
 685                 case e1000_i211:
 686                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 687                         mdic &= E1000_MDICNFG_PHY_MASK;
 688                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 689                         break;
 690                 default:
 691                         ret_val = -E1000_ERR_PHY;
 692                         goto out;
 693                         break;
 694                 }
 695                 ret_val = e1000_get_phy_id(hw);
 696                 goto out;
 697         }
 698
 699         /* Power on sgmii phy if it is disabled */
 700         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 701         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 702                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 703         E1000_WRITE_FLUSH(hw);
 704         msec_delay(300);
 705
 706         /*
 707          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 708          * Therefore, we need to test 1-7
 709          */
 710         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 711                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 712                 if (ret_val == E1000_SUCCESS) {
 713                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 714                                   phy_id, phy->addr);
 715                         /*
 716                          * At the time of this writing, The M88 part is
 717                          * the only supported SGMII PHY product.
 718                          */
 719                         if (phy_id == M88_VENDOR)
 720                                 break;
 721                 } else {
 722                         DEBUGOUT1("PHY address %u was unreadable\n",
 723                                   phy->addr);
 724                 }
 725         }
 726
 727         /* A valid PHY type couldn't be found. */
 728         if (phy->addr == 8) {
 729                 phy->addr = 0;
 730                 ret_val = -E1000_ERR_PHY;
 731         } else {
 732                 ret_val = e1000_get_phy_id(hw);
 733         }
 734
 735         /* restore previous sfp cage power state */
 736         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 737
 738 out:
 739         return ret_val;
 740 }
 741
 742 /**
 743  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 744  *  @hw: pointer to the HW structure
 745  *
 746  *  Resets the PHY using the serial gigabit media independent interface.
 747  **/
 748 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 749 {
 750         s32 ret_val = E1000_SUCCESS;
 751
 752         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 753
 754         /*
 755          * This isn't a true "hard" reset, but is the only reset
 756          * available to us at this time.
 757          */
 758
 759         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 760
 761         if (!(hw->phy.ops.write_reg))
 762                 goto out;
 763
 764         /*
 765          * SFP documentation requires the following to configure the SPF module
 766          * to work on SGMII.  No further documentation is given.
 767          */
 768         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 769         if (ret_val)
 770                 goto out;
 771
 772         ret_val = hw->phy.ops.commit(hw);
 773
 774 out:
 775         return ret_val;
 776 }
 777
 778 /**
 779  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 780  *  @hw: pointer to the HW structure
 781  *  @active: true to enable LPLU, false to disable
 782  *
 783  *  Sets the LPLU D0 state according to the active flag.  When
 784  *  activating LPLU this function also disables smart speed
 785  *  and vice versa.  LPLU will not be activated unless the
 786  *  device autonegotiation advertisement meets standards of
 787  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 788  *  This is a function pointer entry point only called by
 789  *  PHY setup routines.
 790  **/
 791 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 792 {
 793         struct e1000_phy_info *phy = &hw->phy;
 794         s32 ret_val = E1000_SUCCESS;
 795         u16 data;
 796
 797         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 798
 799         if (!(hw->phy.ops.read_reg))
 800                 goto out;
 801
 802         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 803         if (ret_val)
 804                 goto out;
 805
 806         if (active) {
 807                 data |= IGP02E1000_PM_D0_LPLU;
 808                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 809                                              data);
 810                 if (ret_val)
 811                         goto out;
 812
 813                 /* When LPLU is enabled, we should disable SmartSpeed */
 814                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 815                                             &data);
 816                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 817                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 818                                              data);
 819                 if (ret_val)
 820                         goto out;
 821         } else {
 822                 data &= ~IGP02E1000_PM_D0_LPLU;
 823                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 824                                              data);
 825                 /*
 826                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 827                  * during Dx states where the power conservation is most
 828                  * important.  During driver activity we should enable
 829                  * SmartSpeed, so performance is maintained.
 830                  */
 831                 if (phy->smart_speed == e1000_smart_speed_on) {
 832                         ret_val = phy->ops.read_reg(hw,
 833                                                     IGP01E1000_PHY_PORT_CONFIG,
 834                                                     &data);
 835                         if (ret_val)
 836                                 goto out;
 837
 838                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 839                         ret_val = phy->ops.write_reg(hw,
 840                                                      IGP01E1000_PHY_PORT_CONFIG,
 841                                                      data);
 842                         if (ret_val)
 843                                 goto out;
 844                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 845                         ret_val = phy->ops.read_reg(hw,
 846                                                     IGP01E1000_PHY_PORT_CONFIG,
 847                                                     &data);
 848                         if (ret_val)
 849                                 goto out;
 850
 851                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 852                         ret_val = phy->ops.write_reg(hw,
 853                                                      IGP01E1000_PHY_PORT_CONFIG,
 854                                                      data);
 855                         if (ret_val)
 856                                 goto out;
 857                 }
 858         }
 859
 860 out:
 861         return ret_val;
 862 }
 863
 864 /**
 865  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 866  *  @hw: pointer to the HW structure
 867  *  @active: true to enable LPLU, false to disable
 868  *
 869  *  Sets the LPLU D0 state according to the active flag.  When
 870  *  activating LPLU this function also disables smart speed
 871  *  and vice versa.  LPLU will not be activated unless the
 872  *  device autonegotiation advertisement meets standards of
 873  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 874  *  This is a function pointer entry point only called by
 875  *  PHY setup routines.
 876  **/
 877 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 878 {
 879         struct e1000_phy_info *phy = &hw->phy;
 880         s32 ret_val = E1000_SUCCESS;
 881         u32 data;
 882
 883         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 884
 885         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 886
 887         if (active) {
 888                 data |= E1000_82580_PM_D0_LPLU;
 889
 890                 /* When LPLU is enabled, we should disable SmartSpeed */
 891                 data &= ~E1000_82580_PM_SPD;
 892         } else {
 893                 data &= ~E1000_82580_PM_D0_LPLU;
 894
 895                 /*
 896                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 897                  * during Dx states where the power conservation is most
 898                  * important.  During driver activity we should enable
 899                  * SmartSpeed, so performance is maintained.
 900                  */
 901                 if (phy->smart_speed == e1000_smart_speed_on)
 902                         data |= E1000_82580_PM_SPD;
 903                 else if (phy->smart_speed == e1000_smart_speed_off)
 904                         data &= ~E1000_82580_PM_SPD;
 905         }
 906
 907         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 908         return ret_val;
 909 }
 910
 911 /**
 912  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 913  *  @hw: pointer to the HW structure
 914  *  @active: boolean used to enable/disable lplu
 915  *
 916  *  Success returns 0, Failure returns 1
 917  *
 918  *  The low power link up (lplu) state is set to the power management level D3
 919  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 920  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 921  *  is used during Dx states where the power conservation is most important.
 922  *  During driver activity, SmartSpeed should be enabled so performance is
 923  *  maintained.
 924  **/
 925 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 926 {
 927         struct e1000_phy_info *phy = &hw->phy;
 928         s32 ret_val = E1000_SUCCESS;
 929         u32 data;
 930
 931         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 932
 933         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 934
 935         if (!active) {
 936                 data &= ~E1000_82580_PM_D3_LPLU;
 937                 /*
 938                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 939                  * during Dx states where the power conservation is most
 940                  * important.  During driver activity we should enable
 941                  * SmartSpeed, so performance is maintained.
 942                  */
 943                 if (phy->smart_speed == e1000_smart_speed_on)
 944                         data |= E1000_82580_PM_SPD;
 945                 else if (phy->smart_speed == e1000_smart_speed_off)
 946                         data &= ~E1000_82580_PM_SPD;
 947         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 948                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 949                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 950                 data |= E1000_82580_PM_D3_LPLU;
 951                 /* When LPLU is enabled, we should disable SmartSpeed */
 952                 data &= ~E1000_82580_PM_SPD;
 953         }
 954
 955         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 956         return ret_val;
 957 }
 958
 959 /**
 960  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 961  *  @hw: pointer to the HW structure
 962  *
 963  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 964  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 965  *  Return successful if access grant bit set, else clear the request for
 966  *  EEPROM access and return -E1000_ERR_NVM (-1).
 967  **/
 968 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 969 {
 970         s32 ret_val;
 971
 972         DEBUGFUNC("e1000_acquire_nvm_82575");
 973
 974         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 975         if (ret_val)
 976                 goto out;
 977
 978         /*
 979          * Check if there is some access
 980          * error this access may hook on
 981          */
 982         if (hw->mac.type == e1000_i350) {
 983                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 984                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 985                     E1000_EECD_TIMEOUT)) {
 986                         /* Clear all access error flags */
 987                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 988                                         E1000_EECD_ERROR_CLR);
 989                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 990                 }
 991         }
 992         if (hw->mac.type == e1000_82580) {
 993                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 994                 if (eecd & E1000_EECD_BLOCKED) {
 995                         /* Clear access error flag */
 996                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 997                                         E1000_EECD_BLOCKED);
 998                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 999                 }
1000         }
1001
1002
1003         ret_val = e1000_acquire_nvm_generic(hw);
1004         if (ret_val)
1005                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1006
1007 out:
1008         return ret_val;
1009 }
1010
1011 /**
1012  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1013  *  @hw: pointer to the HW structure
1014  *
1015  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1016  *  then release the semaphores acquired.
1017  **/
1018 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1019 {
1020         DEBUGFUNC("e1000_release_nvm_82575");
1021
1022         e1000_release_nvm_generic(hw);
1023
1024         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1025 }
1026
1027 /**
1028  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1029  *  @hw: pointer to the HW structure
1030  *  @mask: specifies which semaphore to acquire
1031  *
1032  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1033  *  will also specify which port we're acquiring the lock for.
1034  **/
1035 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1036 {
1037         u32 swfw_sync;
1038         u32 swmask = mask;
1039         u32 fwmask = mask << 16;
1040         s32 ret_val = E1000_SUCCESS;
1041         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1042
1043         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1044
1045         while (i < timeout) {
1046                 if (e1000_get_hw_semaphore_generic(hw)) {
1047                         ret_val = -E1000_ERR_SWFW_SYNC;
1048                         goto out;
1049                 }
1050
1051                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1052                 if (!(swfw_sync & (fwmask | swmask)))
1053                         break;
1054
1055                 /*
1056                  * Firmware currently using resource (fwmask)
1057                  * or other software thread using resource (swmask)
1058                  */
1059                 e1000_put_hw_semaphore_generic(hw);
1060                 msec_delay_irq(5);
1061                 i++;
1062         }
1063
1064         if (i == timeout) {
1065                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1066                 ret_val = -E1000_ERR_SWFW_SYNC;
1067                 goto out;
1068         }
1069
1070         swfw_sync |= swmask;
1071         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1072
1073         e1000_put_hw_semaphore_generic(hw);
1074
1075 out:
1076         return ret_val;
1077 }
1078
1079 /**
1080  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1081  *  @hw: pointer to the HW structure
1082  *  @mask: specifies which semaphore to acquire
1083  *
1084  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1085  *  will also specify which port we're releasing the lock for.
1086  **/
1087 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1088 {
1089         u32 swfw_sync;
1090
1091         DEBUGFUNC("e1000_release_swfw_sync_82575");
1092
1093         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1094                 ; /* Empty */
1095
1096         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1097         swfw_sync &= ~mask;
1098         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1099
1100         e1000_put_hw_semaphore_generic(hw);
1101 }
1102
1103 /**
1104  *  e1000_get_cfg_done_82575 - Read config done bit
1105  *  @hw: pointer to the HW structure
1106  *
1107  *  Read the management control register for the config done bit for
1108  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1109  *  to read the config done bit, so an error is *ONLY* logged and returns
1110  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1111  *  would not be able to be reset or change link.
1112  **/
1113 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1114 {
1115         s32 timeout = PHY_CFG_TIMEOUT;
1116         s32 ret_val = E1000_SUCCESS;
1117         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1118
1119         DEBUGFUNC("e1000_get_cfg_done_82575");
1120
1121         if (hw->bus.func == E1000_FUNC_1)
1122                 mask = E1000_NVM_CFG_DONE_PORT_1;
1123         else if (hw->bus.func == E1000_FUNC_2)
1124                 mask = E1000_NVM_CFG_DONE_PORT_2;
1125         else if (hw->bus.func == E1000_FUNC_3)
1126                 mask = E1000_NVM_CFG_DONE_PORT_3;
1127         while (timeout) {
1128                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1129                         break;
1130                 msec_delay(1);
1131                 timeout--;
1132         }
1133         if (!timeout)
1134                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1135
1136         /* If EEPROM is not marked present, init the PHY manually */
1137         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1138             (hw->phy.type == e1000_phy_igp_3))
1139                 e1000_phy_init_script_igp3(hw);
1140
1141         return ret_val;
1142 }
1143
1144 /**
1145  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1146  *  @hw: pointer to the HW structure
1147  *  @speed: stores the current speed
1148  *  @duplex: stores the current duplex
1149  *
1150  *  This is a wrapper function, if using the serial gigabit media independent
1151  *  interface, use PCS to retrieve the link speed and duplex information.
1152  *  Otherwise, use the generic function to get the link speed and duplex info.
1153  **/
1154 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1155                                         u16 *duplex)
1156 {
1157         s32 ret_val;
1158
1159         DEBUGFUNC("e1000_get_link_up_info_82575");
1160
1161         if (hw->phy.media_type != e1000_media_type_copper)
1162                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1163                                                                duplex);
1164         else
1165                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1166                                                                     duplex);
1167
1168         return ret_val;
1169 }
1170
1171 /**
1172  *  e1000_check_for_link_82575 - Check for link
1173  *  @hw: pointer to the HW structure
1174  *
1175  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1176  *  use the generic interface for determining link.
1177  **/
1178 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1179 {
1180         s32 ret_val;
1181         u16 speed, duplex;
1182
1183         DEBUGFUNC("e1000_check_for_link_82575");
1184
1185         if (hw->phy.media_type != e1000_media_type_copper) {
1186                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1187                                                                &duplex);
1188                 /*
1189                  * Use this flag to determine if link needs to be checked or
1190                  * not.  If we have link clear the flag so that we do not
1191                  * continue to check for link.
1192                  */
1193                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1194
1195                 /*
1196                  * Configure Flow Control now that Auto-Neg has completed.
1197                  * First, we need to restore the desired flow control
1198                  * settings because we may have had to re-autoneg with a
1199                  * different link partner.
1200                  */
1201                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1202                 if (ret_val)
1203                         DEBUGOUT("Error configuring flow control\n");
1204         } else {
1205                 ret_val = e1000_check_for_copper_link_generic(hw);
1206         }
1207
1208         return ret_val;
1209 }
1210
1211 /**
1212  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1213  *  @hw: pointer to the HW structure
1214  *
1215  *  Poll the M88E1112 interfaces to see which interface achieved link.
1216  */
1217 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1218 {
1219         struct e1000_phy_info *phy = &hw->phy;
1220         s32 ret_val;
1221         u16 data;
1222         u8 port = 0;
1223
1224         DEBUGFUNC("e1000_check_for_link_media_swap");
1225
1226         /* Check the copper medium. */
1227         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1228         if (ret_val)
1229                 return ret_val;
1230
1231         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1232         if (ret_val)
1233                 return ret_val;
1234
1235         if (data & E1000_M88E1112_STATUS_LINK)
1236                 port = E1000_MEDIA_PORT_COPPER;
1237
1238         /* Check the other medium. */
1239         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1240         if (ret_val)
1241                 return ret_val;
1242
1243         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1244         if (ret_val)
1245                 return ret_val;
1246
1247         if (data & E1000_M88E1112_STATUS_LINK)
1248                 port = E1000_MEDIA_PORT_OTHER;
1249
1250         /* Determine if a swap needs to happen. */
1251         if (port && (hw->dev_spec._82575.media_port != port)) {
1252                 hw->dev_spec._82575.media_port = port;
1253                 hw->dev_spec._82575.media_changed = true;
1254         } else {
1255                 ret_val = e1000_check_for_link_82575(hw);
1256         }
1257
1258         return E1000_SUCCESS;
1259 }
1260
1261 /**
1262  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1263  *  @hw: pointer to the HW structure
1264  **/
1265 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1266 {
1267         u32 reg;
1268
1269         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1270
1271         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1272             !e1000_sgmii_active_82575(hw))
1273                 return;
1274
1275         /* Enable PCS to turn on link */
1276         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1277         reg |= E1000_PCS_CFG_PCS_EN;
1278         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1279
1280         /* Power up the laser */
1281         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1282         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1283         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1284
1285         /* flush the write to verify completion */
1286         E1000_WRITE_FLUSH(hw);
1287         msec_delay(1);
1288 }
1289
1290 /**
1291  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1292  *  @hw: pointer to the HW structure
1293  *  @speed: stores the current speed
1294  *  @duplex: stores the current duplex
1295  *
1296  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1297  *  duplex, then store the values in the pointers provided.
1298  **/
1299 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1300                                                 u16 *speed, u16 *duplex)
1301 {
1302         struct e1000_mac_info *mac = &hw->mac;
1303         u32 pcs;
1304         u32 status;
1305
1306         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1307
1308         /*
1309          * Read the PCS Status register for link state. For non-copper mode,
1310          * the status register is not accurate. The PCS status register is
1311          * used instead.
1312          */
1313         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1314
1315         /*
1316          * The link up bit determines when link is up on autoneg.
1317          */
1318         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1319                 mac->serdes_has_link = true;
1320
1321                 /* Detect and store PCS speed */
1322                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1323                         *speed = SPEED_1000;
1324                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1325                         *speed = SPEED_100;
1326                 else
1327                         *speed = SPEED_10;
1328
1329                 /* Detect and store PCS duplex */
1330                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1331                         *duplex = FULL_DUPLEX;
1332                 else
1333                         *duplex = HALF_DUPLEX;
1334
1335                 /* Check if it is an I354 2.5Gb backplane connection. */
1336                 if (mac->type == e1000_i354) {
1337                         status = E1000_READ_REG(hw, E1000_STATUS);
1338                         if ((status & E1000_STATUS_2P5_SKU) &&
1339                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1340                                 *speed = SPEED_2500;
1341                                 *duplex = FULL_DUPLEX;
1342                                 DEBUGOUT("2500 Mbs, ");
1343                                 DEBUGOUT("Full Duplex\n");
1344                         }
1345                 }
1346
1347         } else {
1348                 mac->serdes_has_link = false;
1349                 *speed = 0;
1350                 *duplex = 0;
1351         }
1352
1353         return E1000_SUCCESS;
1354 }
1355
1356 /**
1357  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1358  *  @hw: pointer to the HW structure
1359  *
1360  *  In the case of serdes shut down sfp and PCS on driver unload
1361  *  when management pass thru is not enabled.
1362  **/
1363 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1364 {
1365         u32 reg;
1366
1367         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1368
1369         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1370             !e1000_sgmii_active_82575(hw))
1371                 return;
1372
1373         if (!e1000_enable_mng_pass_thru(hw)) {
1374                 /* Disable PCS to turn off link */
1375                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1376                 reg &= ~E1000_PCS_CFG_PCS_EN;
1377                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1378
1379                 /* shutdown the laser */
1380                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1381                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1382                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1383
1384                 /* flush the write to verify completion */
1385                 E1000_WRITE_FLUSH(hw);
1386                 msec_delay(1);
1387         }
1388
1389         return;
1390 }
1391
1392 /**
1393  *  e1000_reset_hw_82575 - Reset hardware
1394  *  @hw: pointer to the HW structure
1395  *
1396  *  This resets the hardware into a known state.
1397  **/
1398 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1399 {
1400         u32 ctrl;
1401         s32 ret_val;
1402
1403         DEBUGFUNC("e1000_reset_hw_82575");
1404
1405         /*
1406          * Prevent the PCI-E bus from sticking if there is no TLP connection
1407          * on the last TLP read/write transaction when MAC is reset.
1408          */
1409         ret_val = e1000_disable_pcie_master_generic(hw);
1410         if (ret_val)
1411                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1412
1413         /* set the completion timeout for interface */
1414         ret_val = e1000_set_pcie_completion_timeout(hw);
1415         if (ret_val)
1416                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1417
1418         DEBUGOUT("Masking off all interrupts\n");
1419         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1420
1421         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1422         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1423         E1000_WRITE_FLUSH(hw);
1424
1425         msec_delay(10);
1426
1427         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1428
1429         DEBUGOUT("Issuing a global reset to MAC\n");
1430         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1431
1432         ret_val = e1000_get_auto_rd_done_generic(hw);
1433         if (ret_val) {
1434                 /*
1435                  * When auto config read does not complete, do not
1436                  * return with an error. This can happen in situations
1437                  * where there is no eeprom and prevents getting link.
1438                  */
1439                 DEBUGOUT("Auto Read Done did not complete\n");
1440         }
1441
1442         /* If EEPROM is not present, run manual init scripts */
1443         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1444                 e1000_reset_init_script_82575(hw);
1445
1446         /* Clear any pending interrupt events. */
1447         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1448         E1000_READ_REG(hw, E1000_ICR);
1449
1450         /* Install any alternate MAC address into RAR0 */
1451         ret_val = e1000_check_alt_mac_addr_generic(hw);
1452
1453         return ret_val;
1454 }
1455
1456 /**
1457  *  e1000_init_hw_82575 - Initialize hardware
1458  *  @hw: pointer to the HW structure
1459  *
1460  *  This inits the hardware readying it for operation.
1461  **/
1462 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1463 {
1464         struct e1000_mac_info *mac = &hw->mac;
1465         s32 ret_val;
1466         u16 i, rar_count = mac->rar_entry_count;
1467
1468         DEBUGFUNC("e1000_init_hw_82575");
1469
1470         /* Initialize identification LED */
1471         ret_val = mac->ops.id_led_init(hw);
1472         if (ret_val) {
1473                 DEBUGOUT("Error initializing identification LED\n");
1474                 /* This is not fatal and we should not stop init due to this */
1475         }
1476
1477         /* Disabling VLAN filtering */
1478         DEBUGOUT("Initializing the IEEE VLAN\n");
1479         mac->ops.clear_vfta(hw);
1480
1481         /* Setup the receive address */
1482         e1000_init_rx_addrs_generic(hw, rar_count);
1483
1484         /* Zero out the Multicast HASH table */
1485         DEBUGOUT("Zeroing the MTA\n");
1486         for (i = 0; i < mac->mta_reg_count; i++)
1487                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1488
1489         /* Zero out the Unicast HASH table */
1490         DEBUGOUT("Zeroing the UTA\n");
1491         for (i = 0; i < mac->uta_reg_count; i++)
1492                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1493
1494         /* Setup link and flow control */
1495         ret_val = mac->ops.setup_link(hw);
1496
1497         /* Set the default MTU size */
1498         hw->dev_spec._82575.mtu = 1500;
1499
1500         /*
1501          * Clear all of the statistics registers (clear on read).  It is
1502          * important that we do this after we have tried to establish link
1503          * because the symbol error count will increment wildly if there
1504          * is no link.
1505          */
1506         e1000_clear_hw_cntrs_82575(hw);
1507
1508         return ret_val;
1509 }
1510
1511 /**
1512  *  e1000_setup_copper_link_82575 - Configure copper link settings
1513  *  @hw: pointer to the HW structure
1514  *
1515  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1516  *  for link, once link is established calls to configure collision distance
1517  *  and flow control are called.
1518  **/
1519 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1520 {
1521         u32 ctrl;
1522         s32 ret_val;
1523         u32 phpm_reg;
1524
1525         DEBUGFUNC("e1000_setup_copper_link_82575");
1526
1527         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1528         ctrl |= E1000_CTRL_SLU;
1529         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1530         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1531
1532         /* Clear Go Link Disconnect bit on supported devices */
1533         switch (hw->mac.type) {
1534         case e1000_82580:
1535         case e1000_i350:
1536         case e1000_i210:
1537         case e1000_i211:
1538                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1539                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1540                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1541                 break;
1542         default:
1543                 break;
1544         }
1545
1546         ret_val = e1000_setup_serdes_link_82575(hw);
1547         if (ret_val)
1548                 goto out;
1549
1550         if (e1000_sgmii_active_82575(hw)) {
1551                 /* allow time for SFP cage time to power up phy */
1552                 msec_delay(300);
1553
1554                 ret_val = hw->phy.ops.reset(hw);
1555                 if (ret_val) {
1556                         DEBUGOUT("Error resetting the PHY.\n");
1557                         goto out;
1558                 }
1559         }
1560         switch (hw->phy.type) {
1561         case e1000_phy_i210:
1562         case e1000_phy_m88:
1563                 switch (hw->phy.id) {
1564                 case I347AT4_E_PHY_ID:
1565                 case M88E1112_E_PHY_ID:
1566                 case M88E1340M_E_PHY_ID:
1567                 case M88E1543_E_PHY_ID:
1568                 case M88E1512_E_PHY_ID:
1569                 case I210_I_PHY_ID:
1570                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1571                         break;
1572                 default:
1573                         ret_val = e1000_copper_link_setup_m88(hw);
1574                         break;
1575                 }
1576                 break;
1577         case e1000_phy_igp_3:
1578                 ret_val = e1000_copper_link_setup_igp(hw);
1579                 break;
1580         case e1000_phy_82580:
1581                 ret_val = e1000_copper_link_setup_82577(hw);
1582                 break;
1583         default:
1584                 ret_val = -E1000_ERR_PHY;
1585                 break;
1586         }
1587
1588         if (ret_val)
1589                 goto out;
1590
1591         ret_val = e1000_setup_copper_link_generic(hw);
1592 out:
1593         return ret_val;
1594 }
1595
1596 /**
1597  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1598  *  @hw: pointer to the HW structure
1599  *
1600  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1601  *  used on copper connections where the serialized gigabit media independent
1602  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1603  *  for auto-negotiation or forces speed/duplex.
1604  **/
1605 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1606 {
1607         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1608         bool pcs_autoneg;
1609         s32 ret_val = E1000_SUCCESS;
1610         u16 data;
1611
1612         DEBUGFUNC("e1000_setup_serdes_link_82575");
1613
1614         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1615             !e1000_sgmii_active_82575(hw))
1616                 return ret_val;
1617
1618         /*
1619          * On the 82575, SerDes loopback mode persists until it is
1620          * explicitly turned off or a power cycle is performed.  A read to
1621          * the register does not indicate its status.  Therefore, we ensure
1622          * loopback mode is disabled during initialization.
1623          */
1624         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1625
1626         /* power on the sfp cage if present */
1627         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1628         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1629         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1630
1631         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1632         ctrl_reg |= E1000_CTRL_SLU;
1633
1634         /* set both sw defined pins on 82575/82576*/
1635         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1636                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1637
1638         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1639
1640         /* default pcs_autoneg to the same setting as mac autoneg */
1641         pcs_autoneg = hw->mac.autoneg;
1642
1643         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1644         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1645                 /* sgmii mode lets the phy handle forcing speed/duplex */
1646                 pcs_autoneg = true;
1647                 /* autoneg time out should be disabled for SGMII mode */
1648                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1649                 break;
1650         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1651                 /* disable PCS autoneg and support parallel detect only */
1652                 pcs_autoneg = false;
1653                 /* fall through to default case */
1654         default:
1655                 if (hw->mac.type == e1000_82575 ||
1656                     hw->mac.type == e1000_82576) {
1657                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1658                         if (ret_val) {
1659                                 DEBUGOUT("NVM Read Error\n");
1660                                 return ret_val;
1661                         }
1662
1663                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1664                                 pcs_autoneg = false;
1665                 }
1666
1667                 /*
1668                  * non-SGMII modes only supports a speed of 1000/Full for the
1669                  * link so it is best to just force the MAC and let the pcs
1670                  * link either autoneg or be forced to 1000/Full
1671                  */
1672                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1673                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1674
1675                 /* set speed of 1000/Full if speed/duplex is forced */
1676                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1677                 break;
1678         }
1679
1680         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1681
1682         /*
1683          * New SerDes mode allows for forcing speed or autonegotiating speed
1684          * at 1gb. Autoneg should be default set by most drivers. This is the
1685          * mode that will be compatible with older link partners and switches.
1686          * However, both are supported by the hardware and some drivers/tools.
1687          */
1688         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1689                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1690
1691         if (pcs_autoneg) {
1692                 /* Set PCS register for autoneg */
1693                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1694                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1695
1696                 /* Disable force flow control for autoneg */
1697                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1698
1699                 /* Configure flow control advertisement for autoneg */
1700                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1701                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1702
1703                 switch (hw->fc.requested_mode) {
1704                 case e1000_fc_full:
1705                 case e1000_fc_rx_pause:
1706                         anadv_reg |= E1000_TXCW_ASM_DIR;
1707                         anadv_reg |= E1000_TXCW_PAUSE;
1708                         break;
1709                 case e1000_fc_tx_pause:
1710                         anadv_reg |= E1000_TXCW_ASM_DIR;
1711                         break;
1712                 default:
1713                         break;
1714                 }
1715
1716                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1717
1718                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1719         } else {
1720                 /* Set PCS register for forced link */
1721                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1722
1723                 /* Force flow control for forced link */
1724                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1725
1726                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1727         }
1728
1729         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1730
1731         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1732                 e1000_force_mac_fc_generic(hw);
1733
1734         return ret_val;
1735 }
1736
1737 /**
1738  *  e1000_get_media_type_82575 - derives current media type.
1739  *  @hw: pointer to the HW structure
1740  *
1741  *  The media type is chosen reflecting few settings.
1742  *  The following are taken into account:
1743  *  - link mode set in the current port Init Control Word #3
1744  *  - current link mode settings in CSR register
1745  *  - MDIO vs. I2C PHY control interface chosen
1746  *  - SFP module media type
1747  **/
1748 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1749 {
1750         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1751         s32 ret_val = E1000_SUCCESS;
1752         u32 ctrl_ext = 0;
1753         u32 link_mode = 0;
1754
1755         /* Set internal phy as default */
1756         dev_spec->sgmii_active = false;
1757         dev_spec->module_plugged = false;
1758
1759         /* Get CSR setting */
1760         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1761
1762         /* extract link mode setting */
1763         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1764
1765         switch (link_mode) {
1766         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1767                 hw->phy.media_type = e1000_media_type_internal_serdes;
1768                 break;
1769         case E1000_CTRL_EXT_LINK_MODE_GMII:
1770                 hw->phy.media_type = e1000_media_type_copper;
1771                 break;
1772         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1773                 /* Get phy control interface type set (MDIO vs. I2C)*/
1774                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1775                         hw->phy.media_type = e1000_media_type_copper;
1776                         dev_spec->sgmii_active = true;
1777                         break;
1778                 }
1779                 /* fall through for I2C based SGMII */
1780         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1781                 /* read media type from SFP EEPROM */
1782                 ret_val = e1000_set_sfp_media_type_82575(hw);
1783                 if ((ret_val != E1000_SUCCESS) ||
1784                     (hw->phy.media_type == e1000_media_type_unknown)) {
1785                         /*
1786                          * If media type was not identified then return media
1787                          * type defined by the CTRL_EXT settings.
1788                          */
1789                         hw->phy.media_type = e1000_media_type_internal_serdes;
1790
1791                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1792                                 hw->phy.media_type = e1000_media_type_copper;
1793                                 dev_spec->sgmii_active = true;
1794                         }
1795
1796                         break;
1797                 }
1798
1799                 /* do not change link mode for 100BaseFX */
1800                 if (dev_spec->eth_flags.e100_base_fx)
1801                         break;
1802
1803                 /* change current link mode setting */
1804                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1805
1806                 if (hw->phy.media_type == e1000_media_type_copper)
1807                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1808                 else
1809                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1810
1811                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1812
1813                 break;
1814         }
1815
1816         return ret_val;
1817 }
1818
1819 /**
1820  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1821  *  @hw: pointer to the HW structure
1822  *
1823  *  The media type is chosen based on SFP module.
1824  *  compatibility flags retrieved from SFP ID EEPROM.
1825  **/
1826 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1827 {
1828         s32 ret_val = E1000_ERR_CONFIG;
1829         u32 ctrl_ext = 0;
1830         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1831         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1832         u8 tranceiver_type = 0;
1833         s32 timeout = 3;
1834
1835         /* Turn I2C interface ON and power on sfp cage */
1836         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1837         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1838         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1839
1840         E1000_WRITE_FLUSH(hw);
1841
1842         /* Read SFP module data */
1843         while (timeout) {
1844                 ret_val = e1000_read_sfp_data_byte(hw,
1845                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1846                         &tranceiver_type);
1847                 if (ret_val == E1000_SUCCESS)
1848                         break;
1849                 msec_delay(100);
1850                 timeout--;
1851         }
1852         if (ret_val != E1000_SUCCESS)
1853                 goto out;
1854
1855         ret_val = e1000_read_sfp_data_byte(hw,
1856                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1857                         (u8 *)eth_flags);
1858         if (ret_val != E1000_SUCCESS)
1859                 goto out;
1860
1861         /* Check if there is some SFP module plugged and powered */
1862         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1863             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1864                 dev_spec->module_plugged = true;
1865                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1866                         hw->phy.media_type = e1000_media_type_internal_serdes;
1867                 } else if (eth_flags->e100_base_fx) {
1868                         dev_spec->sgmii_active = true;
1869                         hw->phy.media_type = e1000_media_type_internal_serdes;
1870                 } else if (eth_flags->e1000_base_t) {
1871                         dev_spec->sgmii_active = true;
1872                         hw->phy.media_type = e1000_media_type_copper;
1873                 } else {
1874                         hw->phy.media_type = e1000_media_type_unknown;
1875                         DEBUGOUT("PHY module has not been recognized\n");
1876                         goto out;
1877                 }
1878         } else {
1879                 hw->phy.media_type = e1000_media_type_unknown;
1880         }
1881         ret_val = E1000_SUCCESS;
1882 out:
1883         /* Restore I2C interface setting */
1884         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1885         return ret_val;
1886 }
1887
1888 /**
1889  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1890  *  @hw: pointer to the HW structure
1891  *  @data: pointer to the NVM (EEPROM)
1892  *
1893  *  Read the EEPROM for the current default LED configuration.  If the
1894  *  LED configuration is not valid, set to a valid LED configuration.
1895  **/
1896 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1897 {
1898         s32 ret_val;
1899
1900         DEBUGFUNC("e1000_valid_led_default_82575");
1901
1902         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1903         if (ret_val) {
1904                 DEBUGOUT("NVM Read Error\n");
1905                 goto out;
1906         }
1907
1908         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1909                 switch (hw->phy.media_type) {
1910                 case e1000_media_type_internal_serdes:
1911                         *data = ID_LED_DEFAULT_82575_SERDES;
1912                         break;
1913                 case e1000_media_type_copper:
1914                 default:
1915                         *data = ID_LED_DEFAULT;
1916                         break;
1917                 }
1918         }
1919 out:
1920         return ret_val;
1921 }
1922
1923 /**
1924  *  e1000_sgmii_active_82575 - Return sgmii state
1925  *  @hw: pointer to the HW structure
1926  *
1927  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1928  *  which can be enabled for use in the embedded applications.  Simply
1929  *  return the current state of the sgmii interface.
1930  **/
1931 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1932 {
1933         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1934         return dev_spec->sgmii_active;
1935 }
1936
1937 /**
1938  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1939  *  @hw: pointer to the HW structure
1940  *
1941  *  Inits recommended HW defaults after a reset when there is no EEPROM
1942  *  detected. This is only for the 82575.
1943  **/
1944 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1945 {
1946         DEBUGFUNC("e1000_reset_init_script_82575");
1947
1948         if (hw->mac.type == e1000_82575) {
1949                 DEBUGOUT("Running reset init script for 82575\n");
1950                 /* SerDes configuration via SERDESCTRL */
1951                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1952                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1953                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1954                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1955
1956                 /* CCM configuration via CCMCTL register */
1957                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1958                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1959
1960                 /* PCIe lanes configuration */
1961                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1962                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1963                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1964                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1965
1966                 /* PCIe PLL Configuration */
1967                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1968                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1969                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1970         }
1971
1972         return E1000_SUCCESS;
1973 }
1974
1975 /**
1976  *  e1000_read_mac_addr_82575 - Read device MAC address
1977  *  @hw: pointer to the HW structure
1978  **/
1979 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1980 {
1981         s32 ret_val = E1000_SUCCESS;
1982
1983         DEBUGFUNC("e1000_read_mac_addr_82575");
1984
1985         /*
1986          * If there's an alternate MAC address place it in RAR0
1987          * so that it will override the Si installed default perm
1988          * address.
1989          */
1990         ret_val = e1000_check_alt_mac_addr_generic(hw);
1991         if (ret_val)
1992                 goto out;
1993
1994         ret_val = e1000_read_mac_addr_generic(hw);
1995
1996 out:
1997         return ret_val;
1998 }
1999
2000 /**
2001  *  e1000_config_collision_dist_82575 - Configure collision distance
2002  *  @hw: pointer to the HW structure
2003  *
2004  *  Configures the collision distance to the default value and is used
2005  *  during link setup.
2006  **/
2007 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2008 {
2009         u32 tctl_ext;
2010
2011         DEBUGFUNC("e1000_config_collision_dist_82575");
2012
2013         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2014
2015         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2016         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2017
2018         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2019         E1000_WRITE_FLUSH(hw);
2020 }
2021
2022 /**
2023  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2024  * @hw: pointer to the HW structure
2025  *
2026  * In the case of a PHY power down to save power, or to turn off link during a
2027  * driver unload, or wake on lan is not enabled, remove the link.
2028  **/
2029 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2030 {
2031         struct e1000_phy_info *phy = &hw->phy;
2032
2033         if (!(phy->ops.check_reset_block))
2034                 return;
2035
2036         /* If the management interface is not enabled, then power down */
2037         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2038                 e1000_power_down_phy_copper(hw);
2039
2040         return;
2041 }
2042
2043 /**
2044  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2045  *  @hw: pointer to the HW structure
2046  *
2047  *  Clears the hardware counters by reading the counter registers.
2048  **/
2049 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2050 {
2051         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2052
2053         e1000_clear_hw_cntrs_base_generic(hw);
2054
2055         E1000_READ_REG(hw, E1000_PRC64);
2056         E1000_READ_REG(hw, E1000_PRC127);
2057         E1000_READ_REG(hw, E1000_PRC255);
2058         E1000_READ_REG(hw, E1000_PRC511);
2059         E1000_READ_REG(hw, E1000_PRC1023);
2060         E1000_READ_REG(hw, E1000_PRC1522);
2061         E1000_READ_REG(hw, E1000_PTC64);
2062         E1000_READ_REG(hw, E1000_PTC127);
2063         E1000_READ_REG(hw, E1000_PTC255);
2064         E1000_READ_REG(hw, E1000_PTC511);
2065         E1000_READ_REG(hw, E1000_PTC1023);
2066         E1000_READ_REG(hw, E1000_PTC1522);
2067
2068         E1000_READ_REG(hw, E1000_ALGNERRC);
2069         E1000_READ_REG(hw, E1000_RXERRC);
2070         E1000_READ_REG(hw, E1000_TNCRS);
2071         E1000_READ_REG(hw, E1000_CEXTERR);
2072         E1000_READ_REG(hw, E1000_TSCTC);
2073         E1000_READ_REG(hw, E1000_TSCTFC);
2074
2075         E1000_READ_REG(hw, E1000_MGTPRC);
2076         E1000_READ_REG(hw, E1000_MGTPDC);
2077         E1000_READ_REG(hw, E1000_MGTPTC);
2078
2079         E1000_READ_REG(hw, E1000_IAC);
2080         E1000_READ_REG(hw, E1000_ICRXOC);
2081
2082         E1000_READ_REG(hw, E1000_ICRXPTC);
2083         E1000_READ_REG(hw, E1000_ICRXATC);
2084         E1000_READ_REG(hw, E1000_ICTXPTC);
2085         E1000_READ_REG(hw, E1000_ICTXATC);
2086         E1000_READ_REG(hw, E1000_ICTXQEC);
2087         E1000_READ_REG(hw, E1000_ICTXQMTC);
2088         E1000_READ_REG(hw, E1000_ICRXDMTC);
2089
2090         E1000_READ_REG(hw, E1000_CBTMPC);
2091         E1000_READ_REG(hw, E1000_HTDPMC);
2092         E1000_READ_REG(hw, E1000_CBRMPC);
2093         E1000_READ_REG(hw, E1000_RPTHC);
2094         E1000_READ_REG(hw, E1000_HGPTC);
2095         E1000_READ_REG(hw, E1000_HTCBDPC);
2096         E1000_READ_REG(hw, E1000_HGORCL);
2097         E1000_READ_REG(hw, E1000_HGORCH);
2098         E1000_READ_REG(hw, E1000_HGOTCL);
2099         E1000_READ_REG(hw, E1000_HGOTCH);
2100         E1000_READ_REG(hw, E1000_LENERRS);
2101
2102         /* This register should not be read in copper configurations */
2103         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2104             e1000_sgmii_active_82575(hw))
2105                 E1000_READ_REG(hw, E1000_SCVPC);
2106 }
2107
2108 /**
2109  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2110  *  @hw: pointer to the HW structure
2111  *
2112  *  After rx enable if managability is enabled then there is likely some
2113  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2114  *  function clears the fifos and flushes any packets that came in as rx was
2115  *  being enabled.
2116  **/
2117 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2118 {
2119         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2120         int i, ms_wait;
2121
2122         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2123         if (hw->mac.type != e1000_82575 ||
2124             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2125                 return;
2126
2127         /* Disable all Rx queues */
2128         for (i = 0; i < 4; i++) {
2129                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2130                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2131                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2132         }
2133         /* Poll all queues to verify they have shut down */
2134         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2135                 msec_delay(1);
2136                 rx_enabled = 0;
2137                 for (i = 0; i < 4; i++)
2138                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2139                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2140                         break;
2141         }
2142
2143         if (ms_wait == 10)
2144                 DEBUGOUT("Queue disable timed out after 10ms\n");
2145
2146         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2147          * incoming packets are rejected.  Set enable and wait 2ms so that
2148          * any packet that was coming in as RCTL.EN was set is flushed
2149          */
2150         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2151         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2152
2153         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2154         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2155
2156         rctl = E1000_READ_REG(hw, E1000_RCTL);
2157         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2158         temp_rctl |= E1000_RCTL_LPE;
2159
2160         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2161         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2162         E1000_WRITE_FLUSH(hw);
2163         msec_delay(2);
2164
2165         /* Enable Rx queues that were previously enabled and restore our
2166          * previous state
2167          */
2168         for (i = 0; i < 4; i++)
2169                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2170         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2171         E1000_WRITE_FLUSH(hw);
2172
2173         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2174         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2175
2176         /* Flush receive errors generated by workaround */
2177         E1000_READ_REG(hw, E1000_ROC);
2178         E1000_READ_REG(hw, E1000_RNBC);
2179         E1000_READ_REG(hw, E1000_MPC);
2180 }
2181
2182 /**
2183  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2184  *  @hw: pointer to the HW structure
2185  *
2186  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2187  *  however the hardware default for these parts is 500us to 1ms which is less
2188  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2189  *  increase the value to either 10ms to 200ms for capability version 1 config,
2190  *  or 16ms to 55ms for version 2.
2191  **/
2192 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2193 {
2194         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2195         s32 ret_val = E1000_SUCCESS;
2196         u16 pcie_devctl2;
2197
2198         /* only take action if timeout value is defaulted to 0 */
2199         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2200                 goto out;
2201
2202         /*
2203          * if capababilities version is type 1 we can write the
2204          * timeout of 10ms to 200ms through the GCR register
2205          */
2206         if (!(gcr & E1000_GCR_CAP_VER2)) {
2207                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2208                 goto out;
2209         }
2210
2211         /*
2212          * for version 2 capabilities we need to write the config space
2213          * directly in order to set the completion timeout value for
2214          * 16ms to 55ms
2215          */
2216         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2217                                           &pcie_devctl2);
2218         if (ret_val)
2219                 goto out;
2220
2221         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2222
2223         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2224                                            &pcie_devctl2);
2225 out:
2226         /* disable completion timeout resend */
2227         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2228
2229         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2230         return ret_val;
2231 }
2232
2233 /**
2234  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2235  *  @hw: pointer to the hardware struct
2236  *  @enable: state to enter, either enabled or disabled
2237  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2238  *
2239  *  enables/disables L2 switch anti-spoofing functionality.
2240  **/
2241 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2242 {
2243         u32 reg_val, reg_offset;
2244
2245         switch (hw->mac.type) {
2246         case e1000_82576:
2247                 reg_offset = E1000_DTXSWC;
2248                 break;
2249         case e1000_i350:
2250         case e1000_i354:
2251                 reg_offset = E1000_TXSWC;
2252                 break;
2253         default:
2254                 return;
2255         }
2256
2257         reg_val = E1000_READ_REG(hw, reg_offset);
2258         if (enable) {
2259                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2260                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2261                 /* The PF can spoof - it has to in order to
2262                  * support emulation mode NICs
2263                  */
2264                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2265         } else {
2266                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2267                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2268         }
2269         E1000_WRITE_REG(hw, reg_offset, reg_val);
2270 }
2271
2272 /**
2273  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2274  *  @hw: pointer to the hardware struct
2275  *  @enable: state to enter, either enabled or disabled
2276  *
2277  *  enables/disables L2 switch loopback functionality.
2278  **/
2279 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2280 {
2281         u32 dtxswc;
2282
2283         switch (hw->mac.type) {
2284         case e1000_82576:
2285                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2286                 if (enable)
2287                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2288                 else
2289                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2290                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2291                 break;
2292         case e1000_i350:
2293         case e1000_i354:
2294                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2295                 if (enable)
2296                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2297                 else
2298                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2299                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2300                 break;
2301         default:
2302                 /* Currently no other hardware supports loopback */
2303                 break;
2304         }
2305
2306
2307 }
2308
2309 /**
2310  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2311  *  @hw: pointer to the hardware struct
2312  *  @enable: state to enter, either enabled or disabled
2313  *
2314  *  enables/disables replication of packets across multiple pools.
2315  **/
2316 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2317 {
2318         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2319
2320         if (enable)
2321                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2322         else
2323                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2324
2325         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2326 }
2327
2328 /**
2329  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2330  *  @hw: pointer to the HW structure
2331  *  @offset: register offset to be read
2332  *  @data: pointer to the read data
2333  *
2334  *  Reads the MDI control register in the PHY at offset and stores the
2335  *  information read to data.
2336  **/
2337 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2338 {
2339         s32 ret_val;
2340
2341         DEBUGFUNC("e1000_read_phy_reg_82580");
2342
2343         ret_val = hw->phy.ops.acquire(hw);
2344         if (ret_val)
2345                 goto out;
2346
2347         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2348
2349         hw->phy.ops.release(hw);
2350
2351 out:
2352         return ret_val;
2353 }
2354
2355 /**
2356  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2357  *  @hw: pointer to the HW structure
2358  *  @offset: register offset to write to
2359  *  @data: data to write to register at offset
2360  *
2361  *  Writes data to MDI control register in the PHY at offset.
2362  **/
2363 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2364 {
2365         s32 ret_val;
2366
2367         DEBUGFUNC("e1000_write_phy_reg_82580");
2368
2369         ret_val = hw->phy.ops.acquire(hw);
2370         if (ret_val)
2371                 goto out;
2372
2373         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2374
2375         hw->phy.ops.release(hw);
2376
2377 out:
2378         return ret_val;
2379 }
2380
2381 /**
2382  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2383  *  @hw: pointer to the HW structure
2384  *
2385  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2386  *  the values found in the EEPROM.  This addresses an issue in which these
2387  *  bits are not restored from EEPROM after reset.
2388  **/
2389 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2390 {
2391         s32 ret_val = E1000_SUCCESS;
2392         u32 mdicnfg;
2393         u16 nvm_data = 0;
2394
2395         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2396
2397         if (hw->mac.type != e1000_82580)
2398                 goto out;
2399         if (!e1000_sgmii_active_82575(hw))
2400                 goto out;
2401
2402         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2403                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2404                                    &nvm_data);
2405         if (ret_val) {
2406                 DEBUGOUT("NVM Read Error\n");
2407                 goto out;
2408         }
2409
2410         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2411         if (nvm_data & NVM_WORD24_EXT_MDIO)
2412                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2413         if (nvm_data & NVM_WORD24_COM_MDIO)
2414                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2415         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2416 out:
2417         return ret_val;
2418 }
2419
2420 /**
2421  *  e1000_reset_hw_82580 - Reset hardware
2422  *  @hw: pointer to the HW structure
2423  *
2424  *  This resets function or entire device (all ports, etc.)
2425  *  to a known state.
2426  **/
2427 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2428 {
2429         s32 ret_val = E1000_SUCCESS;
2430         /* BH SW mailbox bit in SW_FW_SYNC */
2431         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2432         u32 ctrl;
2433         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2434
2435         DEBUGFUNC("e1000_reset_hw_82580");
2436
2437         hw->dev_spec._82575.global_device_reset = false;
2438
2439         /* 82580 does not reliably do global_device_reset due to hw errata */
2440         if (hw->mac.type == e1000_82580)
2441                 global_device_reset = false;
2442
2443         /* Get current control state. */
2444         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2445
2446         /*
2447          * Prevent the PCI-E bus from sticking if there is no TLP connection
2448          * on the last TLP read/write transaction when MAC is reset.
2449          */
2450         ret_val = e1000_disable_pcie_master_generic(hw);
2451         if (ret_val)
2452                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2453
2454         DEBUGOUT("Masking off all interrupts\n");
2455         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2456         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2457         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2458         E1000_WRITE_FLUSH(hw);
2459
2460         msec_delay(10);
2461
2462         /* Determine whether or not a global dev reset is requested */
2463         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2464             swmbsw_mask))
2465                         global_device_reset = false;
2466
2467         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2468             E1000_STAT_DEV_RST_SET))
2469                 ctrl |= E1000_CTRL_DEV_RST;
2470         else
2471                 ctrl |= E1000_CTRL_RST;
2472
2473         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2474         E1000_WRITE_FLUSH(hw);
2475
2476         /* Add delay to insure DEV_RST has time to complete */
2477         if (global_device_reset)
2478                 msec_delay(5);
2479
2480         ret_val = e1000_get_auto_rd_done_generic(hw);
2481         if (ret_val) {
2482                 /*
2483                  * When auto config read does not complete, do not
2484                  * return with an error. This can happen in situations
2485                  * where there is no eeprom and prevents getting link.
2486                  */
2487                 DEBUGOUT("Auto Read Done did not complete\n");
2488         }
2489
2490         /* clear global device reset status bit */
2491         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2492
2493         /* Clear any pending interrupt events. */
2494         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2495         E1000_READ_REG(hw, E1000_ICR);
2496
2497         ret_val = e1000_reset_mdicnfg_82580(hw);
2498         if (ret_val)
2499                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2500
2501         /* Install any alternate MAC address into RAR0 */
2502         ret_val = e1000_check_alt_mac_addr_generic(hw);
2503
2504         /* Release semaphore */
2505         if (global_device_reset)
2506                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2507
2508         return ret_val;
2509 }
2510
2511 /**
2512  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2513  *  @data: data received by reading RXPBS register
2514  *
2515  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2516  *  This function converts the retrieved value into the correct table value
2517  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2518  *  0x0 36  72 144   1   2   4   8  16
2519  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2520  */
2521 u16 e1000_rxpbs_adjust_82580(u32 data)
2522 {
2523         u16 ret_val = 0;
2524
2525         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2526                 ret_val = e1000_82580_rxpbs_table[data];
2527
2528         return ret_val;
2529 }
2530
2531 /**
2532  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2533  *  checksum
2534  *  @hw: pointer to the HW structure
2535  *  @offset: offset in words of the checksum protected region
2536  *
2537  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2538  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2539  **/
2540 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2541 {
2542         s32 ret_val = E1000_SUCCESS;
2543         u16 checksum = 0;
2544         u16 i, nvm_data;
2545
2546         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2547
2548         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2549                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2550                 if (ret_val) {
2551                         DEBUGOUT("NVM Read Error\n");
2552                         goto out;
2553                 }
2554                 checksum += nvm_data;
2555         }
2556
2557         if (checksum != (u16) NVM_SUM) {
2558                 DEBUGOUT("NVM Checksum Invalid\n");
2559                 ret_val = -E1000_ERR_NVM;
2560                 goto out;
2561         }
2562
2563 out:
2564         return ret_val;
2565 }
2566
2567 /**
2568  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2569  *  checksum
2570  *  @hw: pointer to the HW structure
2571  *  @offset: offset in words of the checksum protected region
2572  *
2573  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2574  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2575  *  value to the EEPROM.
2576  **/
2577 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2578 {
2579         s32 ret_val;
2580         u16 checksum = 0;
2581         u16 i, nvm_data;
2582
2583         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2584
2585         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2586                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2587                 if (ret_val) {
2588                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2589                         goto out;
2590                 }
2591                 checksum += nvm_data;
2592         }
2593         checksum = (u16) NVM_SUM - checksum;
2594         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2595                                     &checksum);
2596         if (ret_val)
2597                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2598
2599 out:
2600         return ret_val;
2601 }
2602
2603 /**
2604  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2605  *  @hw: pointer to the HW structure
2606  *
2607  *  Calculates the EEPROM section checksum by reading/adding each word of
2608  *  the EEPROM and then verifies that the sum of the EEPROM is
2609  *  equal to 0xBABA.
2610  **/
2611 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2612 {
2613         s32 ret_val = E1000_SUCCESS;
2614         u16 eeprom_regions_count = 1;
2615         u16 j, nvm_data;
2616         u16 nvm_offset;
2617
2618         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2619
2620         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2621         if (ret_val) {
2622                 DEBUGOUT("NVM Read Error\n");
2623                 goto out;
2624         }
2625
2626         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2627                 /* if chekcsums compatibility bit is set validate checksums
2628                  * for all 4 ports. */
2629                 eeprom_regions_count = 4;
2630         }
2631
2632         for (j = 0; j < eeprom_regions_count; j++) {
2633                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2634                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2635                                                                   nvm_offset);
2636                 if (ret_val != E1000_SUCCESS)
2637                         goto out;
2638         }
2639
2640 out:
2641         return ret_val;
2642 }
2643
2644 /**
2645  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2646  *  @hw: pointer to the HW structure
2647  *
2648  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2649  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2650  *  checksum and writes the value to the EEPROM.
2651  **/
2652 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2653 {
2654         s32 ret_val;
2655         u16 j, nvm_data;
2656         u16 nvm_offset;
2657
2658         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2659
2660         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2661         if (ret_val) {
2662                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2663                 goto out;
2664         }
2665
2666         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2667                 /* set compatibility bit to validate checksums appropriately */
2668                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2669                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2670                                             &nvm_data);
2671                 if (ret_val) {
2672                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2673                         goto out;
2674                 }
2675         }
2676
2677         for (j = 0; j < 4; j++) {
2678                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2679                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2680                 if (ret_val)
2681                         goto out;
2682         }
2683
2684 out:
2685         return ret_val;
2686 }
2687
2688 /**
2689  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2690  *  @hw: pointer to the HW structure
2691  *
2692  *  Calculates the EEPROM section checksum by reading/adding each word of
2693  *  the EEPROM and then verifies that the sum of the EEPROM is
2694  *  equal to 0xBABA.
2695  **/
2696 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2697 {
2698         s32 ret_val = E1000_SUCCESS;
2699         u16 j;
2700         u16 nvm_offset;
2701
2702         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2703
2704         for (j = 0; j < 4; j++) {
2705                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2706                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2707                                                                   nvm_offset);
2708                 if (ret_val != E1000_SUCCESS)
2709                         goto out;
2710         }
2711
2712 out:
2713         return ret_val;
2714 }
2715
2716 /**
2717  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2718  *  @hw: pointer to the HW structure
2719  *
2720  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2721  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2722  *  checksum and writes the value to the EEPROM.
2723  **/
2724 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2725 {
2726         s32 ret_val = E1000_SUCCESS;
2727         u16 j;
2728         u16 nvm_offset;
2729
2730         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2731
2732         for (j = 0; j < 4; j++) {
2733                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2734                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2735                 if (ret_val != E1000_SUCCESS)
2736                         goto out;
2737         }
2738
2739 out:
2740         return ret_val;
2741 }
2742
2743 /**
2744  *  __e1000_access_emi_reg - Read/write EMI register
2745  *  @hw: pointer to the HW structure
2746  *  @addr: EMI address to program
2747  *  @data: pointer to value to read/write from/to the EMI address
2748  *  @read: boolean flag to indicate read or write
2749  **/
2750 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2751                                   u16 *data, bool read)
2752 {
2753         s32 ret_val = E1000_SUCCESS;
2754
2755         DEBUGFUNC("__e1000_access_emi_reg");
2756
2757         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2758         if (ret_val)
2759                 return ret_val;
2760
2761         if (read)
2762                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2763         else
2764                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2765
2766         return ret_val;
2767 }
2768
2769 /**
2770  *  e1000_read_emi_reg - Read Extended Management Interface register
2771  *  @hw: pointer to the HW structure
2772  *  @addr: EMI address to program
2773  *  @data: value to be read from the EMI address
2774  **/
2775 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2776 {
2777         DEBUGFUNC("e1000_read_emi_reg");
2778
2779         return __e1000_access_emi_reg(hw, addr, data, true);
2780 }
2781
2782 /**
2783  *  e1000_set_eee_i350 - Enable/disable EEE support
2784  *  @hw: pointer to the HW structure
2785  *
2786  *  Enable/disable EEE based on setting in dev_spec structure.
2787  *
2788  **/
2789 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2790 {
2791         s32 ret_val = E1000_SUCCESS;
2792         u32 ipcnfg, eeer;
2793
2794         DEBUGFUNC("e1000_set_eee_i350");
2795
2796         if ((hw->mac.type < e1000_i350) ||
2797             (hw->phy.media_type != e1000_media_type_copper))
2798                 goto out;
2799         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2800         eeer = E1000_READ_REG(hw, E1000_EEER);
2801
2802         /* enable or disable per user setting */
2803         if (!(hw->dev_spec._82575.eee_disable)) {
2804                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2805
2806                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2807                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2808                          E1000_EEER_LPI_FC);
2809
2810                 /* This bit should not be set in normal operation. */
2811                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2812                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2813         } else {
2814                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2815                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2816                           E1000_EEER_LPI_FC);
2817         }
2818         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2819         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2820         E1000_READ_REG(hw, E1000_IPCNFG);
2821         E1000_READ_REG(hw, E1000_EEER);
2822 out:
2823
2824         return ret_val;
2825 }
2826
2827 /**
2828  *  e1000_set_eee_i354 - Enable/disable EEE support
2829  *  @hw: pointer to the HW structure
2830  *
2831  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2832  *
2833  **/
2834 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2835 {
2836         struct e1000_phy_info *phy = &hw->phy;
2837         s32 ret_val = E1000_SUCCESS;
2838         u16 phy_data;
2839
2840         DEBUGFUNC("e1000_set_eee_i354");
2841
2842         if ((hw->phy.media_type != e1000_media_type_copper) ||
2843             ((phy->id != M88E1543_E_PHY_ID) &&
2844             (phy->id != M88E1512_E_PHY_ID)))
2845                 goto out;
2846
2847         if (!hw->dev_spec._82575.eee_disable) {
2848                 /* Switch to PHY page 18. */
2849                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2850                 if (ret_val)
2851                         goto out;
2852
2853                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2854                                             &phy_data);
2855                 if (ret_val)
2856                         goto out;
2857
2858                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2859                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2860                                              phy_data);
2861                 if (ret_val)
2862                         goto out;
2863
2864                 /* Return the PHY to page 0. */
2865                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2866                 if (ret_val)
2867                         goto out;
2868
2869                 /* Turn on EEE advertisement. */
2870                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2871                                                E1000_EEE_ADV_DEV_I354,
2872                                                &phy_data);
2873                 if (ret_val)
2874                         goto out;
2875
2876                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2877                             E1000_EEE_ADV_1000_SUPPORTED;
2878                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2879                                                 E1000_EEE_ADV_DEV_I354,
2880                                                 phy_data);
2881         } else {
2882                 /* Turn off EEE advertisement. */
2883                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2884                                                E1000_EEE_ADV_DEV_I354,
2885                                                &phy_data);
2886                 if (ret_val)
2887                         goto out;
2888
2889                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2890                               E1000_EEE_ADV_1000_SUPPORTED);
2891                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2892                                                 E1000_EEE_ADV_DEV_I354,
2893                                                 phy_data);
2894         }
2895
2896 out:
2897         return ret_val;
2898 }
2899
2900 /**
2901  *  e1000_get_eee_status_i354 - Get EEE status
2902  *  @hw: pointer to the HW structure
2903  *  @status: EEE status
2904  *
2905  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2906  *  been received.
2907  **/
2908 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2909 {
2910         struct e1000_phy_info *phy = &hw->phy;
2911         s32 ret_val = E1000_SUCCESS;
2912         u16 phy_data;
2913
2914         DEBUGFUNC("e1000_get_eee_status_i354");
2915
2916         /* Check if EEE is supported on this device. */
2917         if ((hw->phy.media_type != e1000_media_type_copper) ||
2918             ((phy->id != M88E1543_E_PHY_ID) &&
2919             (phy->id != M88E1512_E_PHY_ID)))
2920                 goto out;
2921
2922         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2923                                        E1000_PCS_STATUS_DEV_I354,
2924                                        &phy_data);
2925         if (ret_val)
2926                 goto out;
2927
2928         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2929                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2930
2931 out:
2932         return ret_val;
2933 }
2934
2935 /* Due to a hw errata, if the host tries to  configure the VFTA register
2936  * while performing queries from the BMC or DMA, then the VFTA in some
2937  * cases won't be written.
2938  */
2939
2940 /**
2941  *  e1000_clear_vfta_i350 - Clear VLAN filter table
2942  *  @hw: pointer to the HW structure
2943  *
2944  *  Clears the register array which contains the VLAN filter table by
2945  *  setting all the values to 0.
2946  **/
2947 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2948 {
2949         u32 offset;
2950         int i;
2951
2952         DEBUGFUNC("e1000_clear_vfta_350");
2953
2954         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2955                 for (i = 0; i < 10; i++)
2956                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2957
2958                 E1000_WRITE_FLUSH(hw);
2959         }
2960 }
2961
2962 /**
2963  *  e1000_write_vfta_i350 - Write value to VLAN filter table
2964  *  @hw: pointer to the HW structure
2965  *  @offset: register offset in VLAN filter table
2966  *  @value: register value written to VLAN filter table
2967  *
2968  *  Writes value at the given offset in the register array which stores
2969  *  the VLAN filter table.
2970  **/
2971 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2972 {
2973         int i;
2974
2975         DEBUGFUNC("e1000_write_vfta_350");
2976
2977         for (i = 0; i < 10; i++)
2978                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2979
2980         E1000_WRITE_FLUSH(hw);
2981 }
2982
2983
2984 /**
2985  *  e1000_set_i2c_bb - Enable I2C bit-bang
2986  *  @hw: pointer to the HW structure
2987  *
2988  *  Enable I2C bit-bang interface
2989  *
2990  **/
2991 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2992 {
2993         s32 ret_val = E1000_SUCCESS;
2994         u32 ctrl_ext, i2cparams;
2995
2996         DEBUGFUNC("e1000_set_i2c_bb");
2997
2998         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2999         ctrl_ext |= E1000_CTRL_I2C_ENA;
3000         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3001         E1000_WRITE_FLUSH(hw);
3002
3003         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3004         i2cparams |= E1000_I2CBB_EN;
3005         i2cparams |= E1000_I2C_DATA_OE_N;
3006         i2cparams |= E1000_I2C_CLK_OE_N;
3007         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3008         E1000_WRITE_FLUSH(hw);
3009
3010         return ret_val;
3011 }
3012
3013 /**
3014  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3015  *  @hw: pointer to hardware structure
3016  *  @byte_offset: byte offset to read
3017  *  @dev_addr: device address
3018  *  @data: value read
3019  *
3020  *  Performs byte read operation over I2C interface at
3021  *  a specified device address.
3022  **/
3023 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3024                                 u8 dev_addr, u8 *data)
3025 {
3026         s32 status = E1000_SUCCESS;
3027         u32 max_retry = 10;
3028         u32 retry = 1;
3029         u16 swfw_mask = 0;
3030
3031         bool nack = true;
3032
3033         DEBUGFUNC("e1000_read_i2c_byte_generic");
3034
3035         swfw_mask = E1000_SWFW_PHY0_SM;
3036
3037         do {
3038                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3039                     != E1000_SUCCESS) {
3040                         status = E1000_ERR_SWFW_SYNC;
3041                         goto read_byte_out;
3042                 }
3043
3044                 e1000_i2c_start(hw);
3045
3046                 /* Device Address and write indication */
3047                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3048                 if (status != E1000_SUCCESS)
3049                         goto fail;
3050
3051                 status = e1000_get_i2c_ack(hw);
3052                 if (status != E1000_SUCCESS)
3053                         goto fail;
3054
3055                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3056                 if (status != E1000_SUCCESS)
3057                         goto fail;
3058
3059                 status = e1000_get_i2c_ack(hw);
3060                 if (status != E1000_SUCCESS)
3061                         goto fail;
3062
3063                 e1000_i2c_start(hw);
3064
3065                 /* Device Address and read indication */
3066                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3067                 if (status != E1000_SUCCESS)
3068                         goto fail;
3069
3070                 status = e1000_get_i2c_ack(hw);
3071                 if (status != E1000_SUCCESS)
3072                         goto fail;
3073
3074                 status = e1000_clock_in_i2c_byte(hw, data);
3075                 if (status != E1000_SUCCESS)
3076                         goto fail;
3077
3078                 status = e1000_clock_out_i2c_bit(hw, nack);
3079                 if (status != E1000_SUCCESS)
3080                         goto fail;
3081
3082                 e1000_i2c_stop(hw);
3083                 break;
3084
3085 fail:
3086                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3087                 msec_delay(100);
3088                 e1000_i2c_bus_clear(hw);
3089                 retry++;
3090                 if (retry < max_retry)
3091                         DEBUGOUT("I2C byte read error - Retrying.\n");
3092                 else
3093                         DEBUGOUT("I2C byte read error.\n");
3094
3095         } while (retry < max_retry);
3096
3097         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3098
3099 read_byte_out:
3100
3101         return status;
3102 }
3103
3104 /**
3105  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3106  *  @hw: pointer to hardware structure
3107  *  @byte_offset: byte offset to write
3108  *  @dev_addr: device address
3109  *  @data: value to write
3110  *
3111  *  Performs byte write operation over I2C interface at
3112  *  a specified device address.
3113  **/
3114 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3115                                  u8 dev_addr, u8 data)
3116 {
3117         s32 status = E1000_SUCCESS;
3118         u32 max_retry = 1;
3119         u32 retry = 0;
3120         u16 swfw_mask = 0;
3121
3122         DEBUGFUNC("e1000_write_i2c_byte_generic");
3123
3124         swfw_mask = E1000_SWFW_PHY0_SM;
3125
3126         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3127                 status = E1000_ERR_SWFW_SYNC;
3128                 goto write_byte_out;
3129         }
3130
3131         do {
3132                 e1000_i2c_start(hw);
3133
3134                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3135                 if (status != E1000_SUCCESS)
3136                         goto fail;
3137
3138                 status = e1000_get_i2c_ack(hw);
3139                 if (status != E1000_SUCCESS)
3140                         goto fail;
3141
3142                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3143                 if (status != E1000_SUCCESS)
3144                         goto fail;
3145
3146                 status = e1000_get_i2c_ack(hw);
3147                 if (status != E1000_SUCCESS)
3148                         goto fail;
3149
3150                 status = e1000_clock_out_i2c_byte(hw, data);
3151                 if (status != E1000_SUCCESS)
3152                         goto fail;
3153
3154                 status = e1000_get_i2c_ack(hw);
3155                 if (status != E1000_SUCCESS)
3156                         goto fail;
3157
3158                 e1000_i2c_stop(hw);
3159                 break;
3160
3161 fail:
3162                 e1000_i2c_bus_clear(hw);
3163                 retry++;
3164                 if (retry < max_retry)
3165                         DEBUGOUT("I2C byte write error - Retrying.\n");
3166                 else
3167                         DEBUGOUT("I2C byte write error.\n");
3168         } while (retry < max_retry);
3169
3170         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3171
3172 write_byte_out:
3173
3174         return status;
3175 }
3176
3177 /**
3178  *  e1000_i2c_start - Sets I2C start condition
3179  *  @hw: pointer to hardware structure
3180  *
3181  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3182  **/
3183 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3184 {
3185         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3186
3187         DEBUGFUNC("e1000_i2c_start");
3188
3189         /* Start condition must begin with data and clock high */
3190         e1000_set_i2c_data(hw, &i2cctl, 1);
3191         e1000_raise_i2c_clk(hw, &i2cctl);
3192
3193         /* Setup time for start condition (4.7us) */
3194         usec_delay(E1000_I2C_T_SU_STA);
3195
3196         e1000_set_i2c_data(hw, &i2cctl, 0);
3197
3198         /* Hold time for start condition (4us) */
3199         usec_delay(E1000_I2C_T_HD_STA);
3200
3201         e1000_lower_i2c_clk(hw, &i2cctl);
3202
3203         /* Minimum low period of clock is 4.7 us */
3204         usec_delay(E1000_I2C_T_LOW);
3205
3206 }
3207
3208 /**
3209  *  e1000_i2c_stop - Sets I2C stop condition
3210  *  @hw: pointer to hardware structure
3211  *
3212  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3213  **/
3214 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3215 {
3216         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3217
3218         DEBUGFUNC("e1000_i2c_stop");
3219
3220         /* Stop condition must begin with data low and clock high */
3221         e1000_set_i2c_data(hw, &i2cctl, 0);
3222         e1000_raise_i2c_clk(hw, &i2cctl);
3223
3224         /* Setup time for stop condition (4us) */
3225         usec_delay(E1000_I2C_T_SU_STO);
3226
3227         e1000_set_i2c_data(hw, &i2cctl, 1);
3228
3229         /* bus free time between stop and start (4.7us)*/
3230         usec_delay(E1000_I2C_T_BUF);
3231 }
3232
3233 /**
3234  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3235  *  @hw: pointer to hardware structure
3236  *  @data: data byte to clock in
3237  *
3238  *  Clocks in one byte data via I2C data/clock
3239  **/
3240 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3241 {
3242         s32 i;
3243         bool bit = 0;
3244
3245         DEBUGFUNC("e1000_clock_in_i2c_byte");
3246
3247         *data = 0;
3248         for (i = 7; i >= 0; i--) {
3249                 e1000_clock_in_i2c_bit(hw, &bit);
3250                 *data |= bit << i;
3251         }
3252
3253         return E1000_SUCCESS;
3254 }
3255
3256 /**
3257  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3258  *  @hw: pointer to hardware structure
3259  *  @data: data byte clocked out
3260  *
3261  *  Clocks out one byte data via I2C data/clock
3262  **/
3263 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3264 {
3265         s32 status = E1000_SUCCESS;
3266         s32 i;
3267         u32 i2cctl;
3268         bool bit = 0;
3269
3270         DEBUGFUNC("e1000_clock_out_i2c_byte");
3271
3272         for (i = 7; i >= 0; i--) {
3273                 bit = (data >> i) & 0x1;
3274                 status = e1000_clock_out_i2c_bit(hw, bit);
3275
3276                 if (status != E1000_SUCCESS)
3277                         break;
3278         }
3279
3280         /* Release SDA line (set high) */
3281         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3282
3283         i2cctl |= E1000_I2C_DATA_OE_N;
3284         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3285         E1000_WRITE_FLUSH(hw);
3286
3287         return status;
3288 }
3289
3290 /**
3291  *  e1000_get_i2c_ack - Polls for I2C ACK
3292  *  @hw: pointer to hardware structure
3293  *
3294  *  Clocks in/out one bit via I2C data/clock
3295  **/
3296 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3297 {
3298         s32 status = E1000_SUCCESS;
3299         u32 i = 0;
3300         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3301         u32 timeout = 10;
3302         bool ack = true;
3303
3304         DEBUGFUNC("e1000_get_i2c_ack");
3305
3306         e1000_raise_i2c_clk(hw, &i2cctl);
3307
3308         /* Minimum high period of clock is 4us */
3309         usec_delay(E1000_I2C_T_HIGH);
3310
3311         /* Wait until SCL returns high */
3312         for (i = 0; i < timeout; i++) {
3313                 usec_delay(1);
3314                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3315                 if (i2cctl & E1000_I2C_CLK_IN)
3316                         break;
3317         }
3318         if (!(i2cctl & E1000_I2C_CLK_IN))
3319                 return E1000_ERR_I2C;
3320
3321         ack = e1000_get_i2c_data(&i2cctl);
3322         if (ack) {
3323                 DEBUGOUT("I2C ack was not received.\n");
3324                 status = E1000_ERR_I2C;
3325         }
3326
3327         e1000_lower_i2c_clk(hw, &i2cctl);
3328
3329         /* Minimum low period of clock is 4.7 us */
3330         usec_delay(E1000_I2C_T_LOW);
3331
3332         return status;
3333 }
3334
3335 /**
3336  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3337  *  @hw: pointer to hardware structure
3338  *  @data: read data value
3339  *
3340  *  Clocks in one bit via I2C data/clock
3341  **/
3342 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3343 {
3344         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3345
3346         DEBUGFUNC("e1000_clock_in_i2c_bit");
3347
3348         e1000_raise_i2c_clk(hw, &i2cctl);
3349
3350         /* Minimum high period of clock is 4us */
3351         usec_delay(E1000_I2C_T_HIGH);
3352
3353         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3354         *data = e1000_get_i2c_data(&i2cctl);
3355
3356         e1000_lower_i2c_clk(hw, &i2cctl);
3357
3358         /* Minimum low period of clock is 4.7 us */
3359         usec_delay(E1000_I2C_T_LOW);
3360
3361         return E1000_SUCCESS;
3362 }
3363
3364 /**
3365  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3366  *  @hw: pointer to hardware structure
3367  *  @data: data value to write
3368  *
3369  *  Clocks out one bit via I2C data/clock
3370  **/
3371 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3372 {
3373         s32 status;
3374         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3375
3376         DEBUGFUNC("e1000_clock_out_i2c_bit");
3377
3378         status = e1000_set_i2c_data(hw, &i2cctl, data);
3379         if (status == E1000_SUCCESS) {
3380                 e1000_raise_i2c_clk(hw, &i2cctl);
3381
3382                 /* Minimum high period of clock is 4us */
3383                 usec_delay(E1000_I2C_T_HIGH);
3384
3385                 e1000_lower_i2c_clk(hw, &i2cctl);
3386
3387                 /* Minimum low period of clock is 4.7 us.
3388                  * This also takes care of the data hold time.
3389                  */
3390                 usec_delay(E1000_I2C_T_LOW);
3391         } else {
3392                 status = E1000_ERR_I2C;
3393                 DEBUGOUT1("I2C data was not set to %X\n", data);
3394         }
3395
3396         return status;
3397 }
3398 /**
3399  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3400  *  @hw: pointer to hardware structure
3401  *  @i2cctl: Current value of I2CCTL register
3402  *
3403  *  Raises the I2C clock line '0'->'1'
3404  **/
3405 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3406 {
3407         DEBUGFUNC("e1000_raise_i2c_clk");
3408
3409         *i2cctl |= E1000_I2C_CLK_OUT;
3410         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3411         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3412         E1000_WRITE_FLUSH(hw);
3413
3414         /* SCL rise time (1000ns) */
3415         usec_delay(E1000_I2C_T_RISE);
3416 }
3417
3418 /**
3419  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3420  *  @hw: pointer to hardware structure
3421  *  @i2cctl: Current value of I2CCTL register
3422  *
3423  *  Lowers the I2C clock line '1'->'0'
3424  **/
3425 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3426 {
3427
3428         DEBUGFUNC("e1000_lower_i2c_clk");
3429
3430         *i2cctl &= ~E1000_I2C_CLK_OUT;
3431         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3432         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3433         E1000_WRITE_FLUSH(hw);
3434
3435         /* SCL fall time (300ns) */
3436         usec_delay(E1000_I2C_T_FALL);
3437 }
3438
3439 /**
3440  *  e1000_set_i2c_data - Sets the I2C data bit
3441  *  @hw: pointer to hardware structure
3442  *  @i2cctl: Current value of I2CCTL register
3443  *  @data: I2C data value (0 or 1) to set
3444  *
3445  *  Sets the I2C data bit
3446  **/
3447 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3448 {
3449         s32 status = E1000_SUCCESS;
3450
3451         DEBUGFUNC("e1000_set_i2c_data");
3452
3453         if (data)
3454                 *i2cctl |= E1000_I2C_DATA_OUT;
3455         else
3456                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3457
3458         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3459         *i2cctl |= E1000_I2C_CLK_OE_N;
3460         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3461         E1000_WRITE_FLUSH(hw);
3462
3463         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3464         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3465
3466         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3467         if (data != e1000_get_i2c_data(i2cctl)) {
3468                 status = E1000_ERR_I2C;
3469                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3470         }
3471
3472         return status;
3473 }
3474
3475 /**
3476  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3477  *  @hw: pointer to hardware structure
3478  *  @i2cctl: Current value of I2CCTL register
3479  *
3480  *  Returns the I2C data bit value
3481  **/
3482 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3483 {
3484         bool data;
3485
3486         DEBUGFUNC("e1000_get_i2c_data");
3487
3488         if (*i2cctl & E1000_I2C_DATA_IN)
3489                 data = 1;
3490         else
3491                 data = 0;
3492
3493         return data;
3494 }
3495
3496 /**
3497  *  e1000_i2c_bus_clear - Clears the I2C bus
3498  *  @hw: pointer to hardware structure
3499  *
3500  *  Clears the I2C bus by sending nine clock pulses.
3501  *  Used when data line is stuck low.
3502  **/
3503 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3504 {
3505         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3506         u32 i;
3507
3508         DEBUGFUNC("e1000_i2c_bus_clear");
3509
3510         e1000_i2c_start(hw);
3511
3512         e1000_set_i2c_data(hw, &i2cctl, 1);
3513
3514         for (i = 0; i < 9; i++) {
3515                 e1000_raise_i2c_clk(hw, &i2cctl);
3516
3517                 /* Min high period of clock is 4us */
3518                 usec_delay(E1000_I2C_T_HIGH);
3519
3520                 e1000_lower_i2c_clk(hw, &i2cctl);
3521
3522                 /* Min low period of clock is 4.7us*/
3523                 usec_delay(E1000_I2C_T_LOW);
3524         }
3525
3526         e1000_i2c_start(hw);
3527
3528         /* Put the i2c bus back to default state */
3529         e1000_i2c_stop(hw);
3530 }
3531