lib/librte_pmd_e1000/e1000/e1000_hw.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _E1000_HW_H_
  35 #define _E1000_HW_H_
  36
  37 #include "e1000_osdep.h"
  38 #include "e1000_regs.h"
  39 #include "e1000_defines.h"
  40
  41 struct e1000_hw;
  42
  43 #define E1000_DEV_ID_82576                    0x10C9
  44 #define E1000_DEV_ID_82576_FIBER              0x10E6
  45 #define E1000_DEV_ID_82576_SERDES             0x10E7
  46 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
  47 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
  48 #define E1000_DEV_ID_82576_NS                 0x150A
  49 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
  50 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
  51 #define E1000_DEV_ID_82576_VF                 0x10CA
  52 #define E1000_DEV_ID_I350_VF                  0x1520
  53 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
  54 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
  55 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
  56 #define E1000_DEV_ID_82580_COPPER             0x150E
  57 #define E1000_DEV_ID_82580_FIBER              0x150F
  58 #define E1000_DEV_ID_82580_SERDES             0x1510
  59 #define E1000_DEV_ID_82580_SGMII              0x1511
  60 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
  61 #define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
  62 #define E1000_DEV_ID_I350_COPPER              0x1521
  63 #define E1000_DEV_ID_I350_FIBER               0x1522
  64 #define E1000_DEV_ID_I350_SERDES              0x1523
  65 #define E1000_DEV_ID_I350_SGMII               0x1524
  66 #define E1000_DEV_ID_I350_DA4                 0x1546
  67 #define E1000_DEV_ID_DH89XXCC_SGMII           0x0438
  68 #define E1000_DEV_ID_DH89XXCC_SERDES          0x043A
  69 #define E1000_DEV_ID_DH89XXCC_BACKPLANE       0x043C
  70 #define E1000_DEV_ID_DH89XXCC_SFP             0x0440
  71 #define E1000_REVISION_0 0
  72 #define E1000_REVISION_1 1
  73 #define E1000_REVISION_2 2
  74 #define E1000_REVISION_3 3
  75 #define E1000_REVISION_4 4
  76
  77 #define E1000_FUNC_0     0
  78 #define E1000_FUNC_1     1
  79 #define E1000_FUNC_2     2
  80 #define E1000_FUNC_3     3
  81
  82 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
  83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  84 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
  85 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
  86
  87 enum e1000_mac_type {
  88         e1000_undefined = 0,
  89         e1000_82575,
  90         e1000_82576,
  91         e1000_82580,
  92         e1000_i350,
  93         e1000_vfadapt,
  94         e1000_vfadapt_i350,
  95         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
  96 };
  97
  98 enum e1000_media_type {
  99         e1000_media_type_unknown = 0,
 100         e1000_media_type_copper = 1,
 101         e1000_media_type_fiber = 2,
 102         e1000_media_type_internal_serdes = 3,
 103         e1000_num_media_types
 104 };
 105
 106 enum e1000_nvm_type {
 107         e1000_nvm_unknown = 0,
 108         e1000_nvm_none,
 109         e1000_nvm_eeprom_spi,
 110         e1000_nvm_eeprom_microwire,
 111         e1000_nvm_flash_hw,
 112         e1000_nvm_flash_sw
 113 };
 114
 115 enum e1000_nvm_override {
 116         e1000_nvm_override_none = 0,
 117         e1000_nvm_override_spi_small,
 118         e1000_nvm_override_spi_large,
 119         e1000_nvm_override_microwire_small,
 120         e1000_nvm_override_microwire_large
 121 };
 122
 123 enum e1000_phy_type {
 124         e1000_phy_unknown = 0,
 125         e1000_phy_none,
 126         e1000_phy_m88,
 127         e1000_phy_igp,
 128         e1000_phy_igp_2,
 129         e1000_phy_gg82563,
 130         e1000_phy_igp_3,
 131         e1000_phy_ife,
 132         e1000_phy_82580,
 133         e1000_phy_vf,
 134 };
 135
 136 enum e1000_bus_type {
 137         e1000_bus_type_unknown = 0,
 138         e1000_bus_type_pci,
 139         e1000_bus_type_pcix,
 140         e1000_bus_type_pci_express,
 141         e1000_bus_type_reserved
 142 };
 143
 144 enum e1000_bus_speed {
 145         e1000_bus_speed_unknown = 0,
 146         e1000_bus_speed_33,
 147         e1000_bus_speed_66,
 148         e1000_bus_speed_100,
 149         e1000_bus_speed_120,
 150         e1000_bus_speed_133,
 151         e1000_bus_speed_2500,
 152         e1000_bus_speed_5000,
 153         e1000_bus_speed_reserved
 154 };
 155
 156 enum e1000_bus_width {
 157         e1000_bus_width_unknown = 0,
 158         e1000_bus_width_pcie_x1,
 159         e1000_bus_width_pcie_x2,
 160         e1000_bus_width_pcie_x4 = 4,
 161         e1000_bus_width_pcie_x8 = 8,
 162         e1000_bus_width_32,
 163         e1000_bus_width_64,
 164         e1000_bus_width_reserved
 165 };
 166
 167 enum e1000_1000t_rx_status {
 168         e1000_1000t_rx_status_not_ok = 0,
 169         e1000_1000t_rx_status_ok,
 170         e1000_1000t_rx_status_undefined = 0xFF
 171 };
 172
 173 enum e1000_rev_polarity {
 174         e1000_rev_polarity_normal = 0,
 175         e1000_rev_polarity_reversed,
 176         e1000_rev_polarity_undefined = 0xFF
 177 };
 178
 179 enum e1000_fc_mode {
 180         e1000_fc_none = 0,
 181         e1000_fc_rx_pause,
 182         e1000_fc_tx_pause,
 183         e1000_fc_full,
 184         e1000_fc_default = 0xFF
 185 };
 186
 187 enum e1000_ms_type {
 188         e1000_ms_hw_default = 0,
 189         e1000_ms_force_master,
 190         e1000_ms_force_slave,
 191         e1000_ms_auto
 192 };
 193
 194 enum e1000_smart_speed {
 195         e1000_smart_speed_default = 0,
 196         e1000_smart_speed_on,
 197         e1000_smart_speed_off
 198 };
 199
 200 enum e1000_serdes_link_state {
 201         e1000_serdes_link_down = 0,
 202         e1000_serdes_link_autoneg_progress,
 203         e1000_serdes_link_autoneg_complete,
 204         e1000_serdes_link_forced_up
 205 };
 206
 207 #define __le16 u16
 208 #define __le32 u32
 209 #define __le64 u64
 210 /* Receive Descriptor */
 211 struct e1000_rx_desc {
 212         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 213         __le16 length;      /* Length of data DMAed into data buffer */
 214         __le16 csum;        /* Packet checksum */
 215         u8  status;         /* Descriptor status */
 216         u8  errors;         /* Descriptor Errors */
 217         __le16 special;
 218 };
 219
 220 /* Receive Descriptor - Extended */
 221 union e1000_rx_desc_extended {
 222         struct {
 223                 __le64 buffer_addr;
 224                 __le64 reserved;
 225         } read;
 226         struct {
 227                 struct {
 228                         __le32 mrq;           /* Multiple Rx Queues */
 229                         union {
 230                                 __le32 rss;         /* RSS Hash */
 231                                 struct {
 232                                         __le16 ip_id;  /* IP id */
 233                                         __le16 csum;   /* Packet Checksum */
 234                                 } csum_ip;
 235                         } hi_dword;
 236                 } lower;
 237                 struct {
 238                         __le32 status_error;  /* ext status/error */
 239                         __le16 length;
 240                         __le16 vlan;          /* VLAN tag */
 241                 } upper;
 242         } wb;  /* writeback */
 243 };
 244
 245 #define MAX_PS_BUFFERS 4
 246 /* Receive Descriptor - Packet Split */
 247 union e1000_rx_desc_packet_split {
 248         struct {
 249                 /* one buffer for protocol header(s), three data buffers */
 250                 __le64 buffer_addr[MAX_PS_BUFFERS];
 251         } read;
 252         struct {
 253                 struct {
 254                         __le32 mrq;           /* Multiple Rx Queues */
 255                         union {
 256                                 __le32 rss;           /* RSS Hash */
 257                                 struct {
 258                                         __le16 ip_id;    /* IP id */
 259                                         __le16 csum;     /* Packet Checksum */
 260                                 } csum_ip;
 261                         } hi_dword;
 262                 } lower;
 263                 struct {
 264                         __le32 status_error;  /* ext status/error */
 265                         __le16 length0;       /* length of buffer 0 */
 266                         __le16 vlan;          /* VLAN tag */
 267                 } middle;
 268                 struct {
 269                         __le16 header_status;
 270                         __le16 length[3];     /* length of buffers 1-3 */
 271                 } upper;
 272                 __le64 reserved;
 273         } wb; /* writeback */
 274 };
 275
 276 /* Transmit Descriptor */
 277 struct e1000_tx_desc {
 278         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 279         union {
 280                 __le32 data;
 281                 struct {
 282                         __le16 length;    /* Data buffer length */
 283                         u8 cso;           /* Checksum offset */
 284                         u8 cmd;           /* Descriptor control */
 285                 } flags;
 286         } lower;
 287         union {
 288                 __le32 data;
 289                 struct {
 290                         u8 status;        /* Descriptor status */
 291                         u8 css;           /* Checksum start */
 292                         __le16 special;
 293                 } fields;
 294         } upper;
 295 };
 296
 297 /* Offload Context Descriptor */
 298 struct e1000_context_desc {
 299         union {
 300                 __le32 ip_config;
 301                 struct {
 302                         u8 ipcss;         /* IP checksum start */
 303                         u8 ipcso;         /* IP checksum offset */
 304                         __le16 ipcse;     /* IP checksum end */
 305                 } ip_fields;
 306         } lower_setup;
 307         union {
 308                 __le32 tcp_config;
 309                 struct {
 310                         u8 tucss;         /* TCP checksum start */
 311                         u8 tucso;         /* TCP checksum offset */
 312                         __le16 tucse;     /* TCP checksum end */
 313                 } tcp_fields;
 314         } upper_setup;
 315         __le32 cmd_and_length;
 316         union {
 317                 __le32 data;
 318                 struct {
 319                         u8 status;        /* Descriptor status */
 320                         u8 hdr_len;       /* Header length */
 321                         __le16 mss;       /* Maximum segment size */
 322                 } fields;
 323         } tcp_seg_setup;
 324 };
 325
 326 /* Offload data descriptor */
 327 struct e1000_data_desc {
 328         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 329         union {
 330                 __le32 data;
 331                 struct {
 332                         __le16 length;    /* Data buffer length */
 333                         u8 typ_len_ext;
 334                         u8 cmd;
 335                 } flags;
 336         } lower;
 337         union {
 338                 __le32 data;
 339                 struct {
 340                         u8 status;        /* Descriptor status */
 341                         u8 popts;         /* Packet Options */
 342                         __le16 special;
 343                 } fields;
 344         } upper;
 345 };
 346
 347 /* Statistics counters collected by the MAC */
 348 struct e1000_hw_stats {
 349         u64 crcerrs;
 350         u64 algnerrc;
 351         u64 symerrs;
 352         u64 rxerrc;
 353         u64 mpc;
 354         u64 scc;
 355         u64 ecol;
 356         u64 mcc;
 357         u64 latecol;
 358         u64 colc;
 359         u64 dc;
 360         u64 tncrs;
 361         u64 sec;
 362         u64 cexterr;
 363         u64 rlec;
 364         u64 xonrxc;
 365         u64 xontxc;
 366         u64 xoffrxc;
 367         u64 xofftxc;
 368         u64 fcruc;
 369         u64 prc64;
 370         u64 prc127;
 371         u64 prc255;
 372         u64 prc511;
 373         u64 prc1023;
 374         u64 prc1522;
 375         u64 gprc;
 376         u64 bprc;
 377         u64 mprc;
 378         u64 gptc;
 379         u64 gorc;
 380         u64 gotc;
 381         u64 rnbc;
 382         u64 ruc;
 383         u64 rfc;
 384         u64 roc;
 385         u64 rjc;
 386         u64 mgprc;
 387         u64 mgpdc;
 388         u64 mgptc;
 389         u64 tor;
 390         u64 tot;
 391         u64 tpr;
 392         u64 tpt;
 393         u64 ptc64;
 394         u64 ptc127;
 395         u64 ptc255;
 396         u64 ptc511;
 397         u64 ptc1023;
 398         u64 ptc1522;
 399         u64 mptc;
 400         u64 bptc;
 401         u64 tsctc;
 402         u64 tsctfc;
 403         u64 iac;
 404         u64 icrxptc;
 405         u64 icrxatc;
 406         u64 ictxptc;
 407         u64 ictxatc;
 408         u64 ictxqec;
 409         u64 ictxqmtc;
 410         u64 icrxdmtc;
 411         u64 icrxoc;
 412         u64 cbtmpc;
 413         u64 htdpmc;
 414         u64 cbrdpc;
 415         u64 cbrmpc;
 416         u64 rpthc;
 417         u64 hgptc;
 418         u64 htcbdpc;
 419         u64 hgorc;
 420         u64 hgotc;
 421         u64 lenerrs;
 422         u64 scvpc;
 423         u64 hrmpc;
 424         u64 doosync;
 425 };
 426
 427 struct e1000_vf_stats {
 428         u64 base_gprc;
 429         u64 base_gptc;
 430         u64 base_gorc;
 431         u64 base_gotc;
 432         u64 base_mprc;
 433         u64 base_gotlbc;
 434         u64 base_gptlbc;
 435         u64 base_gorlbc;
 436         u64 base_gprlbc;
 437
 438         u32 last_gprc;
 439         u32 last_gptc;
 440         u32 last_gorc;
 441         u32 last_gotc;
 442         u32 last_mprc;
 443         u32 last_gotlbc;
 444         u32 last_gptlbc;
 445         u32 last_gorlbc;
 446         u32 last_gprlbc;
 447
 448         u64 gprc;
 449         u64 gptc;
 450         u64 gorc;
 451         u64 gotc;
 452         u64 mprc;
 453         u64 gotlbc;
 454         u64 gptlbc;
 455         u64 gorlbc;
 456         u64 gprlbc;
 457 };
 458
 459 struct e1000_phy_stats {
 460         u32 idle_errors;
 461         u32 receive_errors;
 462 };
 463
 464 struct e1000_host_mng_dhcp_cookie {
 465         u32 signature;
 466         u8  status;
 467         u8  reserved0;
 468         u16 vlan_id;
 469         u32 reserved1;
 470         u16 reserved2;
 471         u8  reserved3;
 472         u8  checksum;
 473 };
 474
 475 /* Host Interface "Rev 1" */
 476 struct e1000_host_command_header {
 477         u8 command_id;
 478         u8 command_length;
 479         u8 command_options;
 480         u8 checksum;
 481 };
 482
 483 #define E1000_HI_MAX_DATA_LENGTH     252
 484 struct e1000_host_command_info {
 485         struct e1000_host_command_header command_header;
 486         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 487 };
 488
 489 /* Host Interface "Rev 2" */
 490 struct e1000_host_mng_command_header {
 491         u8  command_id;
 492         u8  checksum;
 493         u16 reserved1;
 494         u16 reserved2;
 495         u16 command_length;
 496 };
 497
 498 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 499 struct e1000_host_mng_command_info {
 500         struct e1000_host_mng_command_header command_header;
 501         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 502 };
 503
 504 #include "e1000_mac.h"
 505 #include "e1000_phy.h"
 506 #include "e1000_nvm.h"
 507 #include "e1000_manage.h"
 508 #include "e1000_mbx.h"
 509
 510 struct e1000_mac_operations {
 511         /* Function pointers for the MAC. */
 512         s32  (*init_params)(struct e1000_hw *);
 513         s32  (*id_led_init)(struct e1000_hw *);
 514         s32  (*blink_led)(struct e1000_hw *);
 515         s32  (*check_for_link)(struct e1000_hw *);
 516         bool (*check_mng_mode)(struct e1000_hw *hw);
 517         s32  (*cleanup_led)(struct e1000_hw *);
 518         void (*clear_hw_cntrs)(struct e1000_hw *);
 519         void (*clear_vfta)(struct e1000_hw *);
 520         s32  (*get_bus_info)(struct e1000_hw *);
 521         void (*set_lan_id)(struct e1000_hw *);
 522         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 523         s32  (*led_on)(struct e1000_hw *);
 524         s32  (*led_off)(struct e1000_hw *);
 525         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 526         s32  (*reset_hw)(struct e1000_hw *);
 527         s32  (*init_hw)(struct e1000_hw *);
 528         void (*shutdown_serdes)(struct e1000_hw *);
 529         void (*power_up_serdes)(struct e1000_hw *);
 530         s32  (*setup_link)(struct e1000_hw *);
 531         s32  (*setup_physical_interface)(struct e1000_hw *);
 532         s32  (*setup_led)(struct e1000_hw *);
 533         void (*write_vfta)(struct e1000_hw *, u32, u32);
 534         void (*config_collision_dist)(struct e1000_hw *);
 535         void (*rar_set)(struct e1000_hw *, u8*, u32);
 536         s32  (*read_mac_addr)(struct e1000_hw *);
 537         s32  (*validate_mdi_setting)(struct e1000_hw *);
 538         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 539         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 540                       struct e1000_host_mng_command_header*);
 541         s32  (*mng_enable_host_if)(struct e1000_hw *);
 542         s32  (*wait_autoneg)(struct e1000_hw *);
 543 };
 544
 545 struct e1000_phy_operations {
 546         s32  (*init_params)(struct e1000_hw *);
 547         s32  (*acquire)(struct e1000_hw *);
 548         s32  (*check_polarity)(struct e1000_hw *);
 549         s32  (*check_reset_block)(struct e1000_hw *);
 550         s32  (*commit)(struct e1000_hw *);
 551         s32  (*force_speed_duplex)(struct e1000_hw *);
 552         s32  (*get_cfg_done)(struct e1000_hw *hw);
 553         s32  (*get_cable_length)(struct e1000_hw *);
 554         s32  (*get_info)(struct e1000_hw *);
 555         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 556         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 557         void (*release)(struct e1000_hw *);
 558         s32  (*reset)(struct e1000_hw *);
 559         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 560         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 561         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 562         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 563         void (*power_up)(struct e1000_hw *);
 564         void (*power_down)(struct e1000_hw *);
 565 };
 566
 567 struct e1000_nvm_operations {
 568         s32  (*init_params)(struct e1000_hw *);
 569         s32  (*acquire)(struct e1000_hw *);
 570         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 571         void (*release)(struct e1000_hw *);
 572         void (*reload)(struct e1000_hw *);
 573         s32  (*update)(struct e1000_hw *);
 574         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 575         s32  (*validate)(struct e1000_hw *);
 576         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 577 };
 578
 579 struct e1000_mac_info {
 580         struct e1000_mac_operations ops;
 581         u8 addr[ETH_ADDR_LEN];
 582         u8 perm_addr[ETH_ADDR_LEN];
 583
 584         enum e1000_mac_type type;
 585
 586         u32 collision_delta;
 587         u32 ledctl_default;
 588         u32 ledctl_mode1;
 589         u32 ledctl_mode2;
 590         u32 mc_filter_type;
 591         u32 tx_packet_delta;
 592         u32 txcw;
 593
 594         u16 current_ifs_val;
 595         u16 ifs_max_val;
 596         u16 ifs_min_val;
 597         u16 ifs_ratio;
 598         u16 ifs_step_size;
 599         u16 mta_reg_count;
 600         u16 uta_reg_count;
 601
 602         /* Maximum size of the MTA register table in all supported adapters */
 603         #define MAX_MTA_REG 128
 604         u32 mta_shadow[MAX_MTA_REG];
 605         u16 rar_entry_count;
 606
 607         u8  forced_speed_duplex;
 608
 609         bool adaptive_ifs;
 610         bool has_fwsm;
 611         bool arc_subsystem_valid;
 612         bool asf_firmware_present;
 613         bool autoneg;
 614         bool autoneg_failed;
 615         bool get_link_status;
 616         bool in_ifs_mode;
 617         enum e1000_serdes_link_state serdes_link_state;
 618         bool serdes_has_link;
 619         bool tx_pkt_filtering;
 620 };
 621
 622 struct e1000_phy_info {
 623         struct e1000_phy_operations ops;
 624         enum e1000_phy_type type;
 625
 626         enum e1000_1000t_rx_status local_rx;
 627         enum e1000_1000t_rx_status remote_rx;
 628         enum e1000_ms_type ms_type;
 629         enum e1000_ms_type original_ms_type;
 630         enum e1000_rev_polarity cable_polarity;
 631         enum e1000_smart_speed smart_speed;
 632
 633         u32 addr;
 634         u32 id;
 635         u32 reset_delay_us; /* in usec */
 636         u32 revision;
 637
 638         enum e1000_media_type media_type;
 639
 640         u16 autoneg_advertised;
 641         u16 autoneg_mask;
 642         u16 cable_length;
 643         u16 max_cable_length;
 644         u16 min_cable_length;
 645
 646         u8 mdix;
 647
 648         bool disable_polarity_correction;
 649         bool is_mdix;
 650         bool polarity_correction;
 651         bool reset_disable;
 652         bool speed_downgraded;
 653         bool autoneg_wait_to_complete;
 654 };
 655
 656 struct e1000_nvm_info {
 657         struct e1000_nvm_operations ops;
 658         enum e1000_nvm_type type;
 659         enum e1000_nvm_override override;
 660
 661         u32 flash_bank_size;
 662         u32 flash_base_addr;
 663
 664         u16 word_size;
 665         u16 delay_usec;
 666         u16 address_bits;
 667         u16 opcode_bits;
 668         u16 page_size;
 669 };
 670
 671 struct e1000_bus_info {
 672         enum e1000_bus_type type;
 673         enum e1000_bus_speed speed;
 674         enum e1000_bus_width width;
 675
 676         u16 func;
 677         u16 pci_cmd_word;
 678 };
 679
 680 struct e1000_fc_info {
 681         u32 high_water;          /* Flow control high-water mark */
 682         u32 low_water;           /* Flow control low-water mark */
 683         u16 pause_time;          /* Flow control pause timer */
 684         u16 refresh_time;        /* Flow control refresh timer */
 685         bool send_xon;           /* Flow control send XON */
 686         bool strict_ieee;        /* Strict IEEE mode */
 687         enum e1000_fc_mode current_mode; /* FC mode in effect */
 688         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 689 };
 690
 691 struct e1000_mbx_operations {
 692         s32 (*init_params)(struct e1000_hw *hw);
 693         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 694         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 695         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 696         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 697         s32 (*check_for_msg)(struct e1000_hw *, u16);
 698         s32 (*check_for_ack)(struct e1000_hw *, u16);
 699         s32 (*check_for_rst)(struct e1000_hw *, u16);
 700 };
 701
 702 struct e1000_mbx_stats {
 703         u32 msgs_tx;
 704         u32 msgs_rx;
 705
 706         u32 acks;
 707         u32 reqs;
 708         u32 rsts;
 709 };
 710
 711 struct e1000_mbx_info {
 712         struct e1000_mbx_operations ops;
 713         struct e1000_mbx_stats stats;
 714         u32 timeout;
 715         u32 usec_delay;
 716         u16 size;
 717 };
 718
 719 struct e1000_dev_spec_82575 {
 720         bool sgmii_active;
 721         bool global_device_reset;
 722         bool eee_disable;
 723 };
 724
 725 struct e1000_dev_spec_vf {
 726         u32 vf_number;
 727         u32 v2p_mailbox;
 728 };
 729
 730 struct e1000_hw {
 731         void *back;
 732
 733         u8 *hw_addr;
 734         u8 *flash_address;
 735         unsigned long io_base;
 736
 737         struct e1000_mac_info  mac;
 738         struct e1000_fc_info   fc;
 739         struct e1000_phy_info  phy;
 740         struct e1000_nvm_info  nvm;
 741         struct e1000_bus_info  bus;
 742         struct e1000_mbx_info mbx;
 743         struct e1000_host_mng_dhcp_cookie mng_cookie;
 744
 745         union {
 746                 struct e1000_dev_spec_82575 _82575;
 747                 struct e1000_dev_spec_vf vf;
 748         } dev_spec;
 749
 750         u16 device_id;
 751         u16 subsystem_vendor_id;
 752         u16 subsystem_device_id;
 753         u16 vendor_id;
 754
 755         u8  revision_id;
 756 };
 757
 758 #include "e1000_82575.h"
 759
 760 /* These functions must be implemented by drivers */
 761 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 762 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 763 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 764 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 765
 766 #endif