1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "e1000_osdep.h"
38 #include "e1000_regs.h"
39 #include "e1000_defines.h"
43 #define E1000_DEV_ID_82576 0x10C9
44 #define E1000_DEV_ID_82576_FIBER 0x10E6
45 #define E1000_DEV_ID_82576_SERDES 0x10E7
46 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
47 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
48 #define E1000_DEV_ID_82576_NS 0x150A
49 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
50 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
51 #define E1000_DEV_ID_82576_VF 0x10CA
52 #define E1000_DEV_ID_I350_VF 0x1520
53 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
54 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
55 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
56 #define E1000_DEV_ID_82580_COPPER 0x150E
57 #define E1000_DEV_ID_82580_FIBER 0x150F
58 #define E1000_DEV_ID_82580_SERDES 0x1510
59 #define E1000_DEV_ID_82580_SGMII 0x1511
60 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
61 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
62 #define E1000_DEV_ID_I350_COPPER 0x1521
63 #define E1000_DEV_ID_I350_FIBER 0x1522
64 #define E1000_DEV_ID_I350_SERDES 0x1523
65 #define E1000_DEV_ID_I350_SGMII 0x1524
66 #define E1000_DEV_ID_I350_DA4 0x1546
67 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
68 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
69 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
70 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
71 #define E1000_REVISION_0 0
72 #define E1000_REVISION_1 1
73 #define E1000_REVISION_2 2
74 #define E1000_REVISION_3 3
75 #define E1000_REVISION_4 4
77 #define E1000_FUNC_0 0
78 #define E1000_FUNC_1 1
79 #define E1000_FUNC_2 2
80 #define E1000_FUNC_3 3
82 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
84 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
85 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
95 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
98 enum e1000_media_type {
99 e1000_media_type_unknown = 0,
100 e1000_media_type_copper = 1,
101 e1000_media_type_fiber = 2,
102 e1000_media_type_internal_serdes = 3,
103 e1000_num_media_types
106 enum e1000_nvm_type {
107 e1000_nvm_unknown = 0,
109 e1000_nvm_eeprom_spi,
110 e1000_nvm_eeprom_microwire,
115 enum e1000_nvm_override {
116 e1000_nvm_override_none = 0,
117 e1000_nvm_override_spi_small,
118 e1000_nvm_override_spi_large,
119 e1000_nvm_override_microwire_small,
120 e1000_nvm_override_microwire_large
123 enum e1000_phy_type {
124 e1000_phy_unknown = 0,
136 enum e1000_bus_type {
137 e1000_bus_type_unknown = 0,
140 e1000_bus_type_pci_express,
141 e1000_bus_type_reserved
144 enum e1000_bus_speed {
145 e1000_bus_speed_unknown = 0,
151 e1000_bus_speed_2500,
152 e1000_bus_speed_5000,
153 e1000_bus_speed_reserved
156 enum e1000_bus_width {
157 e1000_bus_width_unknown = 0,
158 e1000_bus_width_pcie_x1,
159 e1000_bus_width_pcie_x2,
160 e1000_bus_width_pcie_x4 = 4,
161 e1000_bus_width_pcie_x8 = 8,
164 e1000_bus_width_reserved
167 enum e1000_1000t_rx_status {
168 e1000_1000t_rx_status_not_ok = 0,
169 e1000_1000t_rx_status_ok,
170 e1000_1000t_rx_status_undefined = 0xFF
173 enum e1000_rev_polarity {
174 e1000_rev_polarity_normal = 0,
175 e1000_rev_polarity_reversed,
176 e1000_rev_polarity_undefined = 0xFF
184 e1000_fc_default = 0xFF
188 e1000_ms_hw_default = 0,
189 e1000_ms_force_master,
190 e1000_ms_force_slave,
194 enum e1000_smart_speed {
195 e1000_smart_speed_default = 0,
196 e1000_smart_speed_on,
197 e1000_smart_speed_off
200 enum e1000_serdes_link_state {
201 e1000_serdes_link_down = 0,
202 e1000_serdes_link_autoneg_progress,
203 e1000_serdes_link_autoneg_complete,
204 e1000_serdes_link_forced_up
210 /* Receive Descriptor */
211 struct e1000_rx_desc {
212 __le64 buffer_addr; /* Address of the descriptor's data buffer */
213 __le16 length; /* Length of data DMAed into data buffer */
214 __le16 csum; /* Packet checksum */
215 u8 status; /* Descriptor status */
216 u8 errors; /* Descriptor Errors */
220 /* Receive Descriptor - Extended */
221 union e1000_rx_desc_extended {
228 __le32 mrq; /* Multiple Rx Queues */
230 __le32 rss; /* RSS Hash */
232 __le16 ip_id; /* IP id */
233 __le16 csum; /* Packet Checksum */
238 __le32 status_error; /* ext status/error */
240 __le16 vlan; /* VLAN tag */
242 } wb; /* writeback */
245 #define MAX_PS_BUFFERS 4
246 /* Receive Descriptor - Packet Split */
247 union e1000_rx_desc_packet_split {
249 /* one buffer for protocol header(s), three data buffers */
250 __le64 buffer_addr[MAX_PS_BUFFERS];
254 __le32 mrq; /* Multiple Rx Queues */
256 __le32 rss; /* RSS Hash */
258 __le16 ip_id; /* IP id */
259 __le16 csum; /* Packet Checksum */
264 __le32 status_error; /* ext status/error */
265 __le16 length0; /* length of buffer 0 */
266 __le16 vlan; /* VLAN tag */
269 __le16 header_status;
270 __le16 length[3]; /* length of buffers 1-3 */
273 } wb; /* writeback */
276 /* Transmit Descriptor */
277 struct e1000_tx_desc {
278 __le64 buffer_addr; /* Address of the descriptor's data buffer */
282 __le16 length; /* Data buffer length */
283 u8 cso; /* Checksum offset */
284 u8 cmd; /* Descriptor control */
290 u8 status; /* Descriptor status */
291 u8 css; /* Checksum start */
297 /* Offload Context Descriptor */
298 struct e1000_context_desc {
302 u8 ipcss; /* IP checksum start */
303 u8 ipcso; /* IP checksum offset */
304 __le16 ipcse; /* IP checksum end */
310 u8 tucss; /* TCP checksum start */
311 u8 tucso; /* TCP checksum offset */
312 __le16 tucse; /* TCP checksum end */
315 __le32 cmd_and_length;
319 u8 status; /* Descriptor status */
320 u8 hdr_len; /* Header length */
321 __le16 mss; /* Maximum segment size */
326 /* Offload data descriptor */
327 struct e1000_data_desc {
328 __le64 buffer_addr; /* Address of the descriptor's buffer address */
332 __le16 length; /* Data buffer length */
340 u8 status; /* Descriptor status */
341 u8 popts; /* Packet Options */
347 /* Statistics counters collected by the MAC */
348 struct e1000_hw_stats {
427 struct e1000_vf_stats {
459 struct e1000_phy_stats {
464 struct e1000_host_mng_dhcp_cookie {
475 /* Host Interface "Rev 1" */
476 struct e1000_host_command_header {
483 #define E1000_HI_MAX_DATA_LENGTH 252
484 struct e1000_host_command_info {
485 struct e1000_host_command_header command_header;
486 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
489 /* Host Interface "Rev 2" */
490 struct e1000_host_mng_command_header {
498 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
499 struct e1000_host_mng_command_info {
500 struct e1000_host_mng_command_header command_header;
501 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
504 #include "e1000_mac.h"
505 #include "e1000_phy.h"
506 #include "e1000_nvm.h"
507 #include "e1000_manage.h"
508 #include "e1000_mbx.h"
510 struct e1000_mac_operations {
511 /* Function pointers for the MAC. */
512 s32 (*init_params)(struct e1000_hw *);
513 s32 (*id_led_init)(struct e1000_hw *);
514 s32 (*blink_led)(struct e1000_hw *);
515 s32 (*check_for_link)(struct e1000_hw *);
516 bool (*check_mng_mode)(struct e1000_hw *hw);
517 s32 (*cleanup_led)(struct e1000_hw *);
518 void (*clear_hw_cntrs)(struct e1000_hw *);
519 void (*clear_vfta)(struct e1000_hw *);
520 s32 (*get_bus_info)(struct e1000_hw *);
521 void (*set_lan_id)(struct e1000_hw *);
522 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
523 s32 (*led_on)(struct e1000_hw *);
524 s32 (*led_off)(struct e1000_hw *);
525 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
526 s32 (*reset_hw)(struct e1000_hw *);
527 s32 (*init_hw)(struct e1000_hw *);
528 void (*shutdown_serdes)(struct e1000_hw *);
529 void (*power_up_serdes)(struct e1000_hw *);
530 s32 (*setup_link)(struct e1000_hw *);
531 s32 (*setup_physical_interface)(struct e1000_hw *);
532 s32 (*setup_led)(struct e1000_hw *);
533 void (*write_vfta)(struct e1000_hw *, u32, u32);
534 void (*config_collision_dist)(struct e1000_hw *);
535 void (*rar_set)(struct e1000_hw *, u8*, u32);
536 s32 (*read_mac_addr)(struct e1000_hw *);
537 s32 (*validate_mdi_setting)(struct e1000_hw *);
538 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
539 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
540 struct e1000_host_mng_command_header*);
541 s32 (*mng_enable_host_if)(struct e1000_hw *);
542 s32 (*wait_autoneg)(struct e1000_hw *);
545 struct e1000_phy_operations {
546 s32 (*init_params)(struct e1000_hw *);
547 s32 (*acquire)(struct e1000_hw *);
548 s32 (*check_polarity)(struct e1000_hw *);
549 s32 (*check_reset_block)(struct e1000_hw *);
550 s32 (*commit)(struct e1000_hw *);
551 s32 (*force_speed_duplex)(struct e1000_hw *);
552 s32 (*get_cfg_done)(struct e1000_hw *hw);
553 s32 (*get_cable_length)(struct e1000_hw *);
554 s32 (*get_info)(struct e1000_hw *);
555 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
556 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
557 void (*release)(struct e1000_hw *);
558 s32 (*reset)(struct e1000_hw *);
559 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
560 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
561 s32 (*write_reg)(struct e1000_hw *, u32, u16);
562 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
563 void (*power_up)(struct e1000_hw *);
564 void (*power_down)(struct e1000_hw *);
567 struct e1000_nvm_operations {
568 s32 (*init_params)(struct e1000_hw *);
569 s32 (*acquire)(struct e1000_hw *);
570 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
571 void (*release)(struct e1000_hw *);
572 void (*reload)(struct e1000_hw *);
573 s32 (*update)(struct e1000_hw *);
574 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
575 s32 (*validate)(struct e1000_hw *);
576 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
579 struct e1000_mac_info {
580 struct e1000_mac_operations ops;
581 u8 addr[ETH_ADDR_LEN];
582 u8 perm_addr[ETH_ADDR_LEN];
584 enum e1000_mac_type type;
602 /* Maximum size of the MTA register table in all supported adapters */
603 #define MAX_MTA_REG 128
604 u32 mta_shadow[MAX_MTA_REG];
607 u8 forced_speed_duplex;
611 bool arc_subsystem_valid;
612 bool asf_firmware_present;
615 bool get_link_status;
617 enum e1000_serdes_link_state serdes_link_state;
618 bool serdes_has_link;
619 bool tx_pkt_filtering;
622 struct e1000_phy_info {
623 struct e1000_phy_operations ops;
624 enum e1000_phy_type type;
626 enum e1000_1000t_rx_status local_rx;
627 enum e1000_1000t_rx_status remote_rx;
628 enum e1000_ms_type ms_type;
629 enum e1000_ms_type original_ms_type;
630 enum e1000_rev_polarity cable_polarity;
631 enum e1000_smart_speed smart_speed;
635 u32 reset_delay_us; /* in usec */
638 enum e1000_media_type media_type;
640 u16 autoneg_advertised;
643 u16 max_cable_length;
644 u16 min_cable_length;
648 bool disable_polarity_correction;
650 bool polarity_correction;
652 bool speed_downgraded;
653 bool autoneg_wait_to_complete;
656 struct e1000_nvm_info {
657 struct e1000_nvm_operations ops;
658 enum e1000_nvm_type type;
659 enum e1000_nvm_override override;
671 struct e1000_bus_info {
672 enum e1000_bus_type type;
673 enum e1000_bus_speed speed;
674 enum e1000_bus_width width;
680 struct e1000_fc_info {
681 u32 high_water; /* Flow control high-water mark */
682 u32 low_water; /* Flow control low-water mark */
683 u16 pause_time; /* Flow control pause timer */
684 u16 refresh_time; /* Flow control refresh timer */
685 bool send_xon; /* Flow control send XON */
686 bool strict_ieee; /* Strict IEEE mode */
687 enum e1000_fc_mode current_mode; /* FC mode in effect */
688 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
691 struct e1000_mbx_operations {
692 s32 (*init_params)(struct e1000_hw *hw);
693 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
694 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
695 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
696 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
697 s32 (*check_for_msg)(struct e1000_hw *, u16);
698 s32 (*check_for_ack)(struct e1000_hw *, u16);
699 s32 (*check_for_rst)(struct e1000_hw *, u16);
702 struct e1000_mbx_stats {
711 struct e1000_mbx_info {
712 struct e1000_mbx_operations ops;
713 struct e1000_mbx_stats stats;
719 struct e1000_dev_spec_82575 {
721 bool global_device_reset;
725 struct e1000_dev_spec_vf {
735 unsigned long io_base;
737 struct e1000_mac_info mac;
738 struct e1000_fc_info fc;
739 struct e1000_phy_info phy;
740 struct e1000_nvm_info nvm;
741 struct e1000_bus_info bus;
742 struct e1000_mbx_info mbx;
743 struct e1000_host_mng_dhcp_cookie mng_cookie;
746 struct e1000_dev_spec_82575 _82575;
747 struct e1000_dev_spec_vf vf;
751 u16 subsystem_vendor_id;
752 u16 subsystem_device_id;
758 #include "e1000_82575.h"
760 /* These functions must be implemented by drivers */
761 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
762 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
763 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
764 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);