lib/librte_pmd_e1000/e1000/e1000_hw.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _E1000_HW_H_
  35 #define _E1000_HW_H_
  36
  37 #include "e1000_osdep.h"
  38 #include "e1000_regs.h"
  39 #include "e1000_defines.h"
  40
  41 struct e1000_hw;
  42
  43 #define E1000_DEV_ID_82542                      0x1000
  44 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  45 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  46 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  47 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  48 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  49 #define E1000_DEV_ID_82544GC_LOM                0x100D
  50 #define E1000_DEV_ID_82540EM                    0x100E
  51 #define E1000_DEV_ID_82540EM_LOM                0x1015
  52 #define E1000_DEV_ID_82540EP_LOM                0x1016
  53 #define E1000_DEV_ID_82540EP                    0x1017
  54 #define E1000_DEV_ID_82540EP_LP                 0x101E
  55 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  56 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  57 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  58 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  59 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  60 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  61 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  62 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  63 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  64 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  65 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  66 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  67 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  69 #define E1000_DEV_ID_82541EI                    0x1013
  70 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  71 #define E1000_DEV_ID_82541ER_LOM                0x1014
  72 #define E1000_DEV_ID_82541ER                    0x1078
  73 #define E1000_DEV_ID_82541GI                    0x1076
  74 #define E1000_DEV_ID_82541GI_LF                 0x107C
  75 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  76 #define E1000_DEV_ID_82547EI                    0x1019
  77 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  78 #define E1000_DEV_ID_82547GI                    0x1075
  79 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  80 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  81 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  82 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  83 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  84 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  85 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  86 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  87 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  88 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  89 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  90 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  91 #define E1000_DEV_ID_82572EI                    0x10B9
  92 #define E1000_DEV_ID_82573E                     0x108B
  93 #define E1000_DEV_ID_82573E_IAMT                0x108C
  94 #define E1000_DEV_ID_82573L                     0x109A
  95 #define E1000_DEV_ID_82574L                     0x10D3
  96 #define E1000_DEV_ID_82574LA                    0x10F6
  97 #define E1000_DEV_ID_82583V                     0x150C
  98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 102 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 103 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 104 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 105 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 106 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 107 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 108 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 109 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 110 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 111 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 112 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 113 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 114 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 115 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 116 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 117 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 118 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 119 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 120 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 121 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 122 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 123 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 124 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 125 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 126 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 127 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 128 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 129 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 130 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 131 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 132 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 133 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 134 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 135 #ifdef NAHUM6_LPTH_I218_HW
 136 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 137 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 138 #endif /* NAHUM6_LPTH_I218_HW */
 139 #ifdef NAHUM6_WPT_HW
 140 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 141 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 142 #endif /* NAHUM6_WPT_HW */
 143 #define E1000_DEV_ID_82576                      0x10C9
 144 #define E1000_DEV_ID_82576_FIBER                0x10E6
 145 #define E1000_DEV_ID_82576_SERDES               0x10E7
 146 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 147 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 148 #define E1000_DEV_ID_82576_NS                   0x150A
 149 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 150 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 151 #define E1000_DEV_ID_82576_VF                   0x10CA
 152 #define E1000_DEV_ID_82576_VF_HV                0x152D
 153 #define E1000_DEV_ID_I350_VF                    0x1520
 154 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 155 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 156 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 157 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 158 #define E1000_DEV_ID_82580_COPPER               0x150E
 159 #define E1000_DEV_ID_82580_FIBER                0x150F
 160 #define E1000_DEV_ID_82580_SERDES               0x1510
 161 #define E1000_DEV_ID_82580_SGMII                0x1511
 162 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 163 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 164 #define E1000_DEV_ID_I350_COPPER                0x1521
 165 #define E1000_DEV_ID_I350_FIBER                 0x1522
 166 #define E1000_DEV_ID_I350_SERDES                0x1523
 167 #define E1000_DEV_ID_I350_SGMII                 0x1524
 168 #define E1000_DEV_ID_I350_DA4                   0x1546
 169 #define E1000_DEV_ID_I210_COPPER                0x1533
 170 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 171 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 172 #define E1000_DEV_ID_I210_FIBER                 0x1536
 173 #define E1000_DEV_ID_I210_SERDES                0x1537
 174 #define E1000_DEV_ID_I210_SGMII                 0x1538
 175 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 176 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 177 #define E1000_DEV_ID_I211_COPPER                0x1539
 178 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 179 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 180 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 181 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 182 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 183 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 184 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 185
 186 #define E1000_REVISION_0        0
 187 #define E1000_REVISION_1        1
 188 #define E1000_REVISION_2        2
 189 #define E1000_REVISION_3        3
 190 #define E1000_REVISION_4        4
 191
 192 #define E1000_FUNC_0            0
 193 #define E1000_FUNC_1            1
 194 #define E1000_FUNC_2            2
 195 #define E1000_FUNC_3            3
 196
 197 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 198 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 199 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 200 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 201
 202 enum e1000_mac_type {
 203         e1000_undefined = 0,
 204         e1000_82542,
 205         e1000_82543,
 206         e1000_82544,
 207         e1000_82540,
 208         e1000_82545,
 209         e1000_82545_rev_3,
 210         e1000_82546,
 211         e1000_82546_rev_3,
 212         e1000_82541,
 213         e1000_82541_rev_2,
 214         e1000_82547,
 215         e1000_82547_rev_2,
 216         e1000_82571,
 217         e1000_82572,
 218         e1000_82573,
 219         e1000_82574,
 220         e1000_82583,
 221         e1000_80003es2lan,
 222         e1000_ich8lan,
 223         e1000_ich9lan,
 224         e1000_ich10lan,
 225         e1000_pchlan,
 226         e1000_pch2lan,
 227         e1000_pch_lpt,
 228         e1000_82575,
 229         e1000_82576,
 230         e1000_82580,
 231         e1000_i350,
 232         e1000_i354,
 233         e1000_i210,
 234         e1000_i211,
 235         e1000_vfadapt,
 236         e1000_vfadapt_i350,
 237         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 238 };
 239
 240 enum e1000_media_type {
 241         e1000_media_type_unknown = 0,
 242         e1000_media_type_copper = 1,
 243         e1000_media_type_fiber = 2,
 244         e1000_media_type_internal_serdes = 3,
 245         e1000_num_media_types
 246 };
 247
 248 enum e1000_nvm_type {
 249         e1000_nvm_unknown = 0,
 250         e1000_nvm_none,
 251         e1000_nvm_eeprom_spi,
 252         e1000_nvm_eeprom_microwire,
 253         e1000_nvm_flash_hw,
 254         e1000_nvm_invm,
 255         e1000_nvm_flash_sw
 256 };
 257
 258 enum e1000_nvm_override {
 259         e1000_nvm_override_none = 0,
 260         e1000_nvm_override_spi_small,
 261         e1000_nvm_override_spi_large,
 262         e1000_nvm_override_microwire_small,
 263         e1000_nvm_override_microwire_large
 264 };
 265
 266 enum e1000_phy_type {
 267         e1000_phy_unknown = 0,
 268         e1000_phy_none,
 269         e1000_phy_m88,
 270         e1000_phy_igp,
 271         e1000_phy_igp_2,
 272         e1000_phy_gg82563,
 273         e1000_phy_igp_3,
 274         e1000_phy_ife,
 275         e1000_phy_bm,
 276         e1000_phy_82578,
 277         e1000_phy_82577,
 278         e1000_phy_82579,
 279         e1000_phy_i217,
 280         e1000_phy_82580,
 281         e1000_phy_vf,
 282         e1000_phy_i210,
 283 };
 284
 285 enum e1000_bus_type {
 286         e1000_bus_type_unknown = 0,
 287         e1000_bus_type_pci,
 288         e1000_bus_type_pcix,
 289         e1000_bus_type_pci_express,
 290         e1000_bus_type_reserved
 291 };
 292
 293 enum e1000_bus_speed {
 294         e1000_bus_speed_unknown = 0,
 295         e1000_bus_speed_33,
 296         e1000_bus_speed_66,
 297         e1000_bus_speed_100,
 298         e1000_bus_speed_120,
 299         e1000_bus_speed_133,
 300         e1000_bus_speed_2500,
 301         e1000_bus_speed_5000,
 302         e1000_bus_speed_reserved
 303 };
 304
 305 enum e1000_bus_width {
 306         e1000_bus_width_unknown = 0,
 307         e1000_bus_width_pcie_x1,
 308         e1000_bus_width_pcie_x2,
 309         e1000_bus_width_pcie_x4 = 4,
 310         e1000_bus_width_pcie_x8 = 8,
 311         e1000_bus_width_32,
 312         e1000_bus_width_64,
 313         e1000_bus_width_reserved
 314 };
 315
 316 enum e1000_1000t_rx_status {
 317         e1000_1000t_rx_status_not_ok = 0,
 318         e1000_1000t_rx_status_ok,
 319         e1000_1000t_rx_status_undefined = 0xFF
 320 };
 321
 322 enum e1000_rev_polarity {
 323         e1000_rev_polarity_normal = 0,
 324         e1000_rev_polarity_reversed,
 325         e1000_rev_polarity_undefined = 0xFF
 326 };
 327
 328 enum e1000_fc_mode {
 329         e1000_fc_none = 0,
 330         e1000_fc_rx_pause,
 331         e1000_fc_tx_pause,
 332         e1000_fc_full,
 333         e1000_fc_default = 0xFF
 334 };
 335
 336 enum e1000_ffe_config {
 337         e1000_ffe_config_enabled = 0,
 338         e1000_ffe_config_active,
 339         e1000_ffe_config_blocked
 340 };
 341
 342 enum e1000_dsp_config {
 343         e1000_dsp_config_disabled = 0,
 344         e1000_dsp_config_enabled,
 345         e1000_dsp_config_activated,
 346         e1000_dsp_config_undefined = 0xFF
 347 };
 348
 349 enum e1000_ms_type {
 350         e1000_ms_hw_default = 0,
 351         e1000_ms_force_master,
 352         e1000_ms_force_slave,
 353         e1000_ms_auto
 354 };
 355
 356 enum e1000_smart_speed {
 357         e1000_smart_speed_default = 0,
 358         e1000_smart_speed_on,
 359         e1000_smart_speed_off
 360 };
 361
 362 enum e1000_serdes_link_state {
 363         e1000_serdes_link_down = 0,
 364         e1000_serdes_link_autoneg_progress,
 365         e1000_serdes_link_autoneg_complete,
 366         e1000_serdes_link_forced_up
 367 };
 368
 369 #define __le16 u16
 370 #define __le32 u32
 371 #define __le64 u64
 372 /* Receive Descriptor */
 373 struct e1000_rx_desc {
 374         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 375         __le16 length;      /* Length of data DMAed into data buffer */
 376         __le16 csum; /* Packet checksum */
 377         u8  status;  /* Descriptor status */
 378         u8  errors;  /* Descriptor Errors */
 379         __le16 special;
 380 };
 381
 382 /* Receive Descriptor - Extended */
 383 union e1000_rx_desc_extended {
 384         struct {
 385                 __le64 buffer_addr;
 386                 __le64 reserved;
 387         } read;
 388         struct {
 389                 struct {
 390                         __le32 mrq; /* Multiple Rx Queues */
 391                         union {
 392                                 __le32 rss; /* RSS Hash */
 393                                 struct {
 394                                         __le16 ip_id;  /* IP id */
 395                                         __le16 csum;   /* Packet Checksum */
 396                                 } csum_ip;
 397                         } hi_dword;
 398                 } lower;
 399                 struct {
 400                         __le32 status_error;  /* ext status/error */
 401                         __le16 length;
 402                         __le16 vlan; /* VLAN tag */
 403                 } upper;
 404         } wb;  /* writeback */
 405 };
 406
 407 #define MAX_PS_BUFFERS 4
 408
 409 /* Number of packet split data buffers (not including the header buffer) */
 410 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 411
 412 /* Receive Descriptor - Packet Split */
 413 union e1000_rx_desc_packet_split {
 414         struct {
 415                 /* one buffer for protocol header(s), three data buffers */
 416                 __le64 buffer_addr[MAX_PS_BUFFERS];
 417         } read;
 418         struct {
 419                 struct {
 420                         __le32 mrq;  /* Multiple Rx Queues */
 421                         union {
 422                                 __le32 rss; /* RSS Hash */
 423                                 struct {
 424                                         __le16 ip_id;    /* IP id */
 425                                         __le16 csum;     /* Packet Checksum */
 426                                 } csum_ip;
 427                         } hi_dword;
 428                 } lower;
 429                 struct {
 430                         __le32 status_error;  /* ext status/error */
 431                         __le16 length0;  /* length of buffer 0 */
 432                         __le16 vlan;  /* VLAN tag */
 433                 } middle;
 434                 struct {
 435                         __le16 header_status;
 436                         /* length of buffers 1-3 */
 437                         __le16 length[PS_PAGE_BUFFERS];
 438                 } upper;
 439                 __le64 reserved;
 440         } wb; /* writeback */
 441 };
 442
 443 /* Transmit Descriptor */
 444 struct e1000_tx_desc {
 445         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 446         union {
 447                 __le32 data;
 448                 struct {
 449                         __le16 length;  /* Data buffer length */
 450                         u8 cso;  /* Checksum offset */
 451                         u8 cmd;  /* Descriptor control */
 452                 } flags;
 453         } lower;
 454         union {
 455                 __le32 data;
 456                 struct {
 457                         u8 status; /* Descriptor status */
 458                         u8 css;  /* Checksum start */
 459                         __le16 special;
 460                 } fields;
 461         } upper;
 462 };
 463
 464 /* Offload Context Descriptor */
 465 struct e1000_context_desc {
 466         union {
 467                 __le32 ip_config;
 468                 struct {
 469                         u8 ipcss;  /* IP checksum start */
 470                         u8 ipcso;  /* IP checksum offset */
 471                         __le16 ipcse;  /* IP checksum end */
 472                 } ip_fields;
 473         } lower_setup;
 474         union {
 475                 __le32 tcp_config;
 476                 struct {
 477                         u8 tucss;  /* TCP checksum start */
 478                         u8 tucso;  /* TCP checksum offset */
 479                         __le16 tucse;  /* TCP checksum end */
 480                 } tcp_fields;
 481         } upper_setup;
 482         __le32 cmd_and_length;
 483         union {
 484                 __le32 data;
 485                 struct {
 486                         u8 status;  /* Descriptor status */
 487                         u8 hdr_len;  /* Header length */
 488                         __le16 mss;  /* Maximum segment size */
 489                 } fields;
 490         } tcp_seg_setup;
 491 };
 492
 493 /* Offload data descriptor */
 494 struct e1000_data_desc {
 495         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 496         union {
 497                 __le32 data;
 498                 struct {
 499                         __le16 length;  /* Data buffer length */
 500                         u8 typ_len_ext;
 501                         u8 cmd;
 502                 } flags;
 503         } lower;
 504         union {
 505                 __le32 data;
 506                 struct {
 507                         u8 status;  /* Descriptor status */
 508                         u8 popts;  /* Packet Options */
 509                         __le16 special;
 510                 } fields;
 511         } upper;
 512 };
 513
 514 /* Statistics counters collected by the MAC */
 515 struct e1000_hw_stats {
 516         u64 crcerrs;
 517         u64 algnerrc;
 518         u64 symerrs;
 519         u64 rxerrc;
 520         u64 mpc;
 521         u64 scc;
 522         u64 ecol;
 523         u64 mcc;
 524         u64 latecol;
 525         u64 colc;
 526         u64 dc;
 527         u64 tncrs;
 528         u64 sec;
 529         u64 cexterr;
 530         u64 rlec;
 531         u64 xonrxc;
 532         u64 xontxc;
 533         u64 xoffrxc;
 534         u64 xofftxc;
 535         u64 fcruc;
 536         u64 prc64;
 537         u64 prc127;
 538         u64 prc255;
 539         u64 prc511;
 540         u64 prc1023;
 541         u64 prc1522;
 542         u64 gprc;
 543         u64 bprc;
 544         u64 mprc;
 545         u64 gptc;
 546         u64 gorc;
 547         u64 gotc;
 548         u64 rnbc;
 549         u64 ruc;
 550         u64 rfc;
 551         u64 roc;
 552         u64 rjc;
 553         u64 mgprc;
 554         u64 mgpdc;
 555         u64 mgptc;
 556         u64 tor;
 557         u64 tot;
 558         u64 tpr;
 559         u64 tpt;
 560         u64 ptc64;
 561         u64 ptc127;
 562         u64 ptc255;
 563         u64 ptc511;
 564         u64 ptc1023;
 565         u64 ptc1522;
 566         u64 mptc;
 567         u64 bptc;
 568         u64 tsctc;
 569         u64 tsctfc;
 570         u64 iac;
 571         u64 icrxptc;
 572         u64 icrxatc;
 573         u64 ictxptc;
 574         u64 ictxatc;
 575         u64 ictxqec;
 576         u64 ictxqmtc;
 577         u64 icrxdmtc;
 578         u64 icrxoc;
 579         u64 cbtmpc;
 580         u64 htdpmc;
 581         u64 cbrdpc;
 582         u64 cbrmpc;
 583         u64 rpthc;
 584         u64 hgptc;
 585         u64 htcbdpc;
 586         u64 hgorc;
 587         u64 hgotc;
 588         u64 lenerrs;
 589         u64 scvpc;
 590         u64 hrmpc;
 591         u64 doosync;
 592         u64 o2bgptc;
 593         u64 o2bspc;
 594         u64 b2ospc;
 595         u64 b2ogprc;
 596 };
 597
 598 struct e1000_vf_stats {
 599         u64 base_gprc;
 600         u64 base_gptc;
 601         u64 base_gorc;
 602         u64 base_gotc;
 603         u64 base_mprc;
 604         u64 base_gotlbc;
 605         u64 base_gptlbc;
 606         u64 base_gorlbc;
 607         u64 base_gprlbc;
 608
 609         u32 last_gprc;
 610         u32 last_gptc;
 611         u32 last_gorc;
 612         u32 last_gotc;
 613         u32 last_mprc;
 614         u32 last_gotlbc;
 615         u32 last_gptlbc;
 616         u32 last_gorlbc;
 617         u32 last_gprlbc;
 618
 619         u64 gprc;
 620         u64 gptc;
 621         u64 gorc;
 622         u64 gotc;
 623         u64 mprc;
 624         u64 gotlbc;
 625         u64 gptlbc;
 626         u64 gorlbc;
 627         u64 gprlbc;
 628 };
 629
 630 struct e1000_phy_stats {
 631         u32 idle_errors;
 632         u32 receive_errors;
 633 };
 634
 635 struct e1000_host_mng_dhcp_cookie {
 636         u32 signature;
 637         u8  status;
 638         u8  reserved0;
 639         u16 vlan_id;
 640         u32 reserved1;
 641         u16 reserved2;
 642         u8  reserved3;
 643         u8  checksum;
 644 };
 645
 646 /* Host Interface "Rev 1" */
 647 struct e1000_host_command_header {
 648         u8 command_id;
 649         u8 command_length;
 650         u8 command_options;
 651         u8 checksum;
 652 };
 653
 654 #define E1000_HI_MAX_DATA_LENGTH        252
 655 struct e1000_host_command_info {
 656         struct e1000_host_command_header command_header;
 657         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 658 };
 659
 660 /* Host Interface "Rev 2" */
 661 struct e1000_host_mng_command_header {
 662         u8  command_id;
 663         u8  checksum;
 664         u16 reserved1;
 665         u16 reserved2;
 666         u16 command_length;
 667 };
 668
 669 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 670 struct e1000_host_mng_command_info {
 671         struct e1000_host_mng_command_header command_header;
 672         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 673 };
 674
 675 #include "e1000_mac.h"
 676 #include "e1000_phy.h"
 677 #include "e1000_nvm.h"
 678 #include "e1000_manage.h"
 679 #include "e1000_mbx.h"
 680
 681 /* Function pointers for the MAC. */
 682 struct e1000_mac_operations {
 683         s32  (*init_params)(struct e1000_hw *);
 684         s32  (*id_led_init)(struct e1000_hw *);
 685         s32  (*blink_led)(struct e1000_hw *);
 686         bool (*check_mng_mode)(struct e1000_hw *);
 687         s32  (*check_for_link)(struct e1000_hw *);
 688         s32  (*cleanup_led)(struct e1000_hw *);
 689         void (*clear_hw_cntrs)(struct e1000_hw *);
 690         void (*clear_vfta)(struct e1000_hw *);
 691         s32  (*get_bus_info)(struct e1000_hw *);
 692         void (*set_lan_id)(struct e1000_hw *);
 693         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 694         s32  (*led_on)(struct e1000_hw *);
 695         s32  (*led_off)(struct e1000_hw *);
 696         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 697         s32  (*reset_hw)(struct e1000_hw *);
 698         s32  (*init_hw)(struct e1000_hw *);
 699         void (*shutdown_serdes)(struct e1000_hw *);
 700         void (*power_up_serdes)(struct e1000_hw *);
 701         s32  (*setup_link)(struct e1000_hw *);
 702         s32  (*setup_physical_interface)(struct e1000_hw *);
 703         s32  (*setup_led)(struct e1000_hw *);
 704         void (*write_vfta)(struct e1000_hw *, u32, u32);
 705         void (*config_collision_dist)(struct e1000_hw *);
 706         void (*rar_set)(struct e1000_hw *, u8*, u32);
 707         s32  (*read_mac_addr)(struct e1000_hw *);
 708         s32  (*validate_mdi_setting)(struct e1000_hw *);
 709         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 710         void (*release_swfw_sync)(struct e1000_hw *, u16);
 711 };
 712
 713 /* When to use various PHY register access functions:
 714  *
 715  *                 Func   Caller
 716  *   Function      Does   Does    When to use
 717  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 718  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 719  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 720  *                                on different pages
 721  *   X_reg_page    A      L,P     for multiple accesses of different regs
 722  *                                on the same page
 723  *
 724  * Where X=[read|write], L=locking, P=sets page, A=register access
 725  *
 726  */
 727 struct e1000_phy_operations {
 728         s32  (*init_params)(struct e1000_hw *);
 729         s32  (*acquire)(struct e1000_hw *);
 730         s32  (*cfg_on_link_up)(struct e1000_hw *);
 731         s32  (*check_polarity)(struct e1000_hw *);
 732         s32  (*check_reset_block)(struct e1000_hw *);
 733         s32  (*commit)(struct e1000_hw *);
 734         s32  (*force_speed_duplex)(struct e1000_hw *);
 735         s32  (*get_cfg_done)(struct e1000_hw *hw);
 736         s32  (*get_cable_length)(struct e1000_hw *);
 737         s32  (*get_info)(struct e1000_hw *);
 738         s32  (*set_page)(struct e1000_hw *, u16);
 739         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 740         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 741         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 742         void (*release)(struct e1000_hw *);
 743         s32  (*reset)(struct e1000_hw *);
 744         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 745         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 746         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 747         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 748         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 749         void (*power_up)(struct e1000_hw *);
 750         void (*power_down)(struct e1000_hw *);
 751         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 752         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 753 };
 754
 755 /* Function pointers for the NVM. */
 756 struct e1000_nvm_operations {
 757         s32  (*init_params)(struct e1000_hw *);
 758         s32  (*acquire)(struct e1000_hw *);
 759         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 760         void (*release)(struct e1000_hw *);
 761         void (*reload)(struct e1000_hw *);
 762         s32  (*update)(struct e1000_hw *);
 763         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 764         s32  (*validate)(struct e1000_hw *);
 765         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 766 };
 767
 768 struct e1000_mac_info {
 769         struct e1000_mac_operations ops;
 770         u8 addr[ETH_ADDR_LEN];
 771         u8 perm_addr[ETH_ADDR_LEN];
 772
 773         enum e1000_mac_type type;
 774
 775         u32 collision_delta;
 776         u32 ledctl_default;
 777         u32 ledctl_mode1;
 778         u32 ledctl_mode2;
 779         u32 mc_filter_type;
 780         u32 tx_packet_delta;
 781         u32 txcw;
 782
 783         u16 current_ifs_val;
 784         u16 ifs_max_val;
 785         u16 ifs_min_val;
 786         u16 ifs_ratio;
 787         u16 ifs_step_size;
 788         u16 mta_reg_count;
 789         u16 uta_reg_count;
 790
 791         /* Maximum size of the MTA register table in all supported adapters */
 792         #define MAX_MTA_REG 128
 793         u32 mta_shadow[MAX_MTA_REG];
 794         u16 rar_entry_count;
 795
 796         u8  forced_speed_duplex;
 797
 798         bool adaptive_ifs;
 799         bool has_fwsm;
 800         bool arc_subsystem_valid;
 801         bool asf_firmware_present;
 802         bool autoneg;
 803         bool autoneg_failed;
 804         bool get_link_status;
 805         bool in_ifs_mode;
 806         bool report_tx_early;
 807         enum e1000_serdes_link_state serdes_link_state;
 808         bool serdes_has_link;
 809         bool tx_pkt_filtering;
 810 };
 811
 812 struct e1000_phy_info {
 813         struct e1000_phy_operations ops;
 814         enum e1000_phy_type type;
 815
 816         enum e1000_1000t_rx_status local_rx;
 817         enum e1000_1000t_rx_status remote_rx;
 818         enum e1000_ms_type ms_type;
 819         enum e1000_ms_type original_ms_type;
 820         enum e1000_rev_polarity cable_polarity;
 821         enum e1000_smart_speed smart_speed;
 822
 823         u32 addr;
 824         u32 id;
 825         u32 reset_delay_us; /* in usec */
 826         u32 revision;
 827
 828         enum e1000_media_type media_type;
 829
 830         u16 autoneg_advertised;
 831         u16 autoneg_mask;
 832         u16 cable_length;
 833         u16 max_cable_length;
 834         u16 min_cable_length;
 835
 836         u8 mdix;
 837
 838         bool disable_polarity_correction;
 839         bool is_mdix;
 840         bool polarity_correction;
 841         bool speed_downgraded;
 842         bool autoneg_wait_to_complete;
 843 };
 844
 845 struct e1000_nvm_info {
 846         struct e1000_nvm_operations ops;
 847         enum e1000_nvm_type type;
 848         enum e1000_nvm_override override;
 849
 850         u32 flash_bank_size;
 851         u32 flash_base_addr;
 852
 853         u16 word_size;
 854         u16 delay_usec;
 855         u16 address_bits;
 856         u16 opcode_bits;
 857         u16 page_size;
 858 };
 859
 860 struct e1000_bus_info {
 861         enum e1000_bus_type type;
 862         enum e1000_bus_speed speed;
 863         enum e1000_bus_width width;
 864
 865         u16 func;
 866         u16 pci_cmd_word;
 867 };
 868
 869 struct e1000_fc_info {
 870         u32 high_water;  /* Flow control high-water mark */
 871         u32 low_water;  /* Flow control low-water mark */
 872         u16 pause_time;  /* Flow control pause timer */
 873         u16 refresh_time;  /* Flow control refresh timer */
 874         bool send_xon;  /* Flow control send XON */
 875         bool strict_ieee;  /* Strict IEEE mode */
 876         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 877         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 878 };
 879
 880 struct e1000_mbx_operations {
 881         s32 (*init_params)(struct e1000_hw *hw);
 882         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 883         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 884         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 885         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 886         s32 (*check_for_msg)(struct e1000_hw *, u16);
 887         s32 (*check_for_ack)(struct e1000_hw *, u16);
 888         s32 (*check_for_rst)(struct e1000_hw *, u16);
 889 };
 890
 891 struct e1000_mbx_stats {
 892         u32 msgs_tx;
 893         u32 msgs_rx;
 894
 895         u32 acks;
 896         u32 reqs;
 897         u32 rsts;
 898 };
 899
 900 struct e1000_mbx_info {
 901         struct e1000_mbx_operations ops;
 902         struct e1000_mbx_stats stats;
 903         u32 timeout;
 904         u32 usec_delay;
 905         u16 size;
 906 };
 907
 908 struct e1000_dev_spec_82541 {
 909         enum e1000_dsp_config dsp_config;
 910         enum e1000_ffe_config ffe_config;
 911         u16 spd_default;
 912         bool phy_init_script;
 913 };
 914
 915 struct e1000_dev_spec_82542 {
 916         bool dma_fairness;
 917 };
 918
 919 struct e1000_dev_spec_82543 {
 920         u32  tbi_compatibility;
 921         bool dma_fairness;
 922         bool init_phy_disabled;
 923 };
 924
 925 struct e1000_dev_spec_82571 {
 926         bool laa_is_present;
 927         u32 smb_counter;
 928         E1000_MUTEX swflag_mutex;
 929 };
 930
 931 struct e1000_dev_spec_80003es2lan {
 932         bool  mdic_wa_enable;
 933 };
 934
 935 struct e1000_shadow_ram {
 936         u16  value;
 937         bool modified;
 938 };
 939
 940 #define E1000_SHADOW_RAM_WORDS          2048
 941
 942 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
 943 /* I218 PHY Ultra Low Power (ULP) states */
 944 enum e1000_ulp_state {
 945         e1000_ulp_state_unknown,
 946         e1000_ulp_state_off,
 947         e1000_ulp_state_on,
 948 };
 949
 950 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
 951 struct e1000_dev_spec_ich8lan {
 952         bool kmrn_lock_loss_workaround_enabled;
 953         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 954         E1000_MUTEX nvm_mutex;
 955         E1000_MUTEX swflag_mutex;
 956         bool nvm_k1_enabled;
 957         bool eee_disable;
 958         u16 eee_lp_ability;
 959 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
 960         enum e1000_ulp_state ulp_state;
 961 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
 962 #ifdef C10_SUPPORT
 963         u16 lat_enc;
 964         u16 max_ltr_enc;
 965 #endif
 966 };
 967
 968 struct e1000_dev_spec_82575 {
 969         bool sgmii_active;
 970         bool global_device_reset;
 971         bool eee_disable;
 972         bool module_plugged;
 973         bool clear_semaphore_once;
 974         u32 mtu;
 975         struct sfp_e1000_flags eth_flags;
 976         u8 media_port;
 977         bool media_changed;
 978 };
 979
 980 struct e1000_dev_spec_vf {
 981         u32 vf_number;
 982         u32 v2p_mailbox;
 983 };
 984
 985 struct e1000_hw {
 986         void *back;
 987
 988         u8 *hw_addr;
 989         u8 *flash_address;
 990         unsigned long io_base;
 991
 992         struct e1000_mac_info  mac;
 993         struct e1000_fc_info   fc;
 994         struct e1000_phy_info  phy;
 995         struct e1000_nvm_info  nvm;
 996         struct e1000_bus_info  bus;
 997         struct e1000_mbx_info mbx;
 998         struct e1000_host_mng_dhcp_cookie mng_cookie;
 999
1000         union {
1001                 struct e1000_dev_spec_82541 _82541;
1002                 struct e1000_dev_spec_82542 _82542;
1003                 struct e1000_dev_spec_82543 _82543;
1004                 struct e1000_dev_spec_82571 _82571;
1005                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1006                 struct e1000_dev_spec_ich8lan ich8lan;
1007                 struct e1000_dev_spec_82575 _82575;
1008                 struct e1000_dev_spec_vf vf;
1009         } dev_spec;
1010
1011         u16 device_id;
1012         u16 subsystem_vendor_id;
1013         u16 subsystem_device_id;
1014         u16 vendor_id;
1015
1016         u8  revision_id;
1017 };
1018
1019 #include "e1000_82541.h"
1020 #include "e1000_82543.h"
1021 #include "e1000_82571.h"
1022 #include "e1000_80003es2lan.h"
1023 #include "e1000_ich8lan.h"
1024 #include "e1000_82575.h"
1025 #include "e1000_i210.h"
1026
1027 /* These functions must be implemented by drivers */
1028 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1029 void e1000_pci_set_mwi(struct e1000_hw *hw);
1030 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1031 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1032 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1033 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1034
1035 #endif