lib/librte_pmd_e1000/e1000/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  * Ethernet Connection I217-LM
  62  * Ethernet Connection I217-V
  63  * Ethernet Connection I218-V
  64  * Ethernet Connection I218-LM
  65  */
  66
  67 #include "e1000_api.h"
  68
  69 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  70 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  71 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  72 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  73 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  74 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  75 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  76 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  77 STATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  78 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  79 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  80 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  81                                               u8 *mc_addr_list,
  82                                               u32 mc_addr_count);
  83 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  84 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  85 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  86 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  87 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  88                                             bool active);
  89 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  90                                             bool active);
  91 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  92                                    u16 words, u16 *data);
  93 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  94                                     u16 words, u16 *data);
  95 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  96 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  98                                             u16 *data);
  99 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 100 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 101 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 102 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 103 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 104 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 105 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 106 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 107                                            u16 *speed, u16 *duplex);
 108 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 109 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 110 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 111 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 112 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 113 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 114 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 115 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 116 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 117 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 119 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 120 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 121                                           u32 offset, u8 *data);
 122 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                           u8 size, u16 *data);
 124 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 125                                           u32 offset, u16 *data);
 126 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 127                                                  u32 offset, u8 byte);
 128 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 129 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 130 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 131 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 132 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 133 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 134
 135 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 136 /* Offset 04h HSFSTS */
 137 union ich8_hws_flash_status {
 138         struct ich8_hsfsts {
 139                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 140                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 141                 u16 dael:1; /* bit 2 Direct Access error Log */
 142                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 143                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 144                 u16 reserved1:2; /* bit 13:6 Reserved */
 145                 u16 reserved2:6; /* bit 13:6 Reserved */
 146                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 147                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 148         } hsf_status;
 149         u16 regval;
 150 };
 151
 152 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 153 /* Offset 06h FLCTL */
 154 union ich8_hws_flash_ctrl {
 155         struct ich8_hsflctl {
 156                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 157                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 158                 u16 reserved:5;   /* 7:3 Reserved  */
 159                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 160                 u16 flockdn:6;   /* 15:10 Reserved */
 161         } hsf_ctrl;
 162         u16 regval;
 163 };
 164
 165 /* ICH Flash Region Access Permissions */
 166 union ich8_hws_flash_regacc {
 167         struct ich8_flracc {
 168                 u32 grra:8; /* 0:7 GbE region Read Access */
 169                 u32 grwa:8; /* 8:15 GbE region Write Access */
 170                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 171                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 172         } hsf_flregacc;
 173         u16 regval;
 174 };
 175
 176 /**
 177  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 178  *  @hw: pointer to the HW structure
 179  *
 180  *  Test access to the PHY registers by reading the PHY ID registers.  If
 181  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 182  *  otherwise assume the read PHY ID is correct if it is valid.
 183  *
 184  *  Assumes the sw/fw/hw semaphore is already acquired.
 185  **/
 186 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 187 {
 188         u16 phy_reg = 0;
 189         u32 phy_id = 0;
 190         s32 ret_val = 0;
 191         u16 retry_count;
 192         u32 mac_reg = 0;
 193
 194         for (retry_count = 0; retry_count < 2; retry_count++) {
 195                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 196                 if (ret_val || (phy_reg == 0xFFFF))
 197                         continue;
 198                 phy_id = (u32)(phy_reg << 16);
 199
 200                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 201                 if (ret_val || (phy_reg == 0xFFFF)) {
 202                         phy_id = 0;
 203                         continue;
 204                 }
 205                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 206                 break;
 207         }
 208
 209         if (hw->phy.id) {
 210                 if  (hw->phy.id == phy_id)
 211                         goto out;
 212         } else if (phy_id) {
 213                 hw->phy.id = phy_id;
 214                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 215                 goto out;
 216         }
 217
 218         /* In case the PHY needs to be in mdio slow mode,
 219          * set slow mode and try to get the PHY id again.
 220          */
 221         if (hw->mac.type < e1000_pch_lpt) {
 222                 hw->phy.ops.release(hw);
 223                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 224                 if (!ret_val)
 225                         ret_val = e1000_get_phy_id(hw);
 226                 hw->phy.ops.acquire(hw);
 227         }
 228
 229         if (ret_val)
 230                 return false;
 231 out:
 232         if (hw->mac.type == e1000_pch_lpt) {
 233                 /* Unforce SMBus mode in PHY */
 234                 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 235                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 236                 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 237
 238                 /* Unforce SMBus mode in MAC */
 239                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 240                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 241                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 242         }
 243
 244         return true;
 245 }
 246
 247 /**
 248  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 249  *  @hw: pointer to the HW structure
 250  *
 251  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 252  *  used to reset the PHY to a quiescent state when necessary.
 253  **/
 254 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 255 {
 256         u32 mac_reg;
 257
 258         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 259
 260         /* Set Phy Config Counter to 50msec */
 261         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 262         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 263         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 264         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 265
 266         /* Toggle LANPHYPC Value bit */
 267         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 268         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 269         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 270         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 271         E1000_WRITE_FLUSH(hw);
 272         usec_delay(10);
 273         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 274         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 275         E1000_WRITE_FLUSH(hw);
 276
 277         if (hw->mac.type < e1000_pch_lpt) {
 278                 msec_delay(50);
 279         } else {
 280                 u16 count = 20;
 281
 282                 do {
 283                         msec_delay(5);
 284                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 285                            E1000_CTRL_EXT_LPCD) && count--);
 286
 287                 msec_delay(30);
 288         }
 289 }
 290
 291 /**
 292  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 293  *  @hw: pointer to the HW structure
 294  *
 295  *  Workarounds/flow necessary for PHY initialization during driver load
 296  *  and resume paths.
 297  **/
 298 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 299 {
 300         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 301         s32 ret_val;
 302
 303         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 304
 305         /* Gate automatic PHY configuration by hardware on managed and
 306          * non-managed 82579 and newer adapters.
 307          */
 308         e1000_gate_hw_phy_config_ich8lan(hw, true);
 309
 310 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
 311         /* It is not possible to be certain of the current state of ULP
 312          * so forcibly disable it.
 313          */
 314         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 315
 316 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
 317         ret_val = hw->phy.ops.acquire(hw);
 318         if (ret_val) {
 319                 DEBUGOUT("Failed to initialize PHY flow\n");
 320                 goto out;
 321         }
 322
 323         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 324          * inaccessible and resetting the PHY is not blocked, toggle the
 325          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 326          */
 327         switch (hw->mac.type) {
 328         case e1000_pch_lpt:
 329                 if (e1000_phy_is_accessible_pchlan(hw))
 330                         break;
 331
 332                 /* Before toggling LANPHYPC, see if PHY is accessible by
 333                  * forcing MAC to SMBus mode first.
 334                  */
 335                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 336                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 337                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 338
 339                 /* Wait 50 milliseconds for MAC to finish any retries
 340                  * that it might be trying to perform from previous
 341                  * attempts to acknowledge any phy read requests.
 342                  */
 343                  msec_delay(50);
 344
 345                 /* fall-through */
 346         case e1000_pch2lan:
 347                 if (e1000_phy_is_accessible_pchlan(hw))
 348                         break;
 349
 350                 /* fall-through */
 351         case e1000_pchlan:
 352                 if ((hw->mac.type == e1000_pchlan) &&
 353                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 354                         break;
 355
 356                 if (hw->phy.ops.check_reset_block(hw)) {
 357                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 358                         ret_val = -E1000_ERR_PHY;
 359                         break;
 360                 }
 361
 362                 /* Toggle LANPHYPC Value bit */
 363                 e1000_toggle_lanphypc_pch_lpt(hw);
 364                 if (hw->mac.type >= e1000_pch_lpt) {
 365                         if (e1000_phy_is_accessible_pchlan(hw))
 366                                 break;
 367
 368                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 369                          * so ensure that the MAC is also out of SMBus mode
 370                          */
 371                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 372                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 373                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 374
 375                         if (e1000_phy_is_accessible_pchlan(hw))
 376                                 break;
 377
 378                         ret_val = -E1000_ERR_PHY;
 379                 }
 380                 break;
 381         default:
 382                 break;
 383         }
 384
 385         hw->phy.ops.release(hw);
 386         if (!ret_val) {
 387
 388                 /* Check to see if able to reset PHY.  Print error if not */
 389                 if (hw->phy.ops.check_reset_block(hw)) {
 390                         ERROR_REPORT("Reset blocked by ME\n");
 391                         goto out;
 392                 }
 393
 394                 /* Reset the PHY before any access to it.  Doing so, ensures
 395                  * that the PHY is in a known good state before we read/write
 396                  * PHY registers.  The generic reset is sufficient here,
 397                  * because we haven't determined the PHY type yet.
 398                  */
 399                 ret_val = e1000_phy_hw_reset_generic(hw);
 400                 if (ret_val)
 401                         goto out;
 402
 403                 /* On a successful reset, possibly need to wait for the PHY
 404                  * to quiesce to an accessible state before returning control
 405                  * to the calling function.  If the PHY does not quiesce, then
 406                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 407                  *  the PHY is in.
 408                  */
 409                 ret_val = hw->phy.ops.check_reset_block(hw);
 410                 if (ret_val)
 411                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 412         }
 413
 414 out:
 415         /* Ungate automatic PHY configuration on non-managed 82579 */
 416         if ((hw->mac.type == e1000_pch2lan) &&
 417             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 418                 msec_delay(10);
 419                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 420         }
 421
 422         return ret_val;
 423 }
 424
 425 /**
 426  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 427  *  @hw: pointer to the HW structure
 428  *
 429  *  Initialize family-specific PHY parameters and function pointers.
 430  **/
 431 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 432 {
 433         struct e1000_phy_info *phy = &hw->phy;
 434         s32 ret_val;
 435
 436         DEBUGFUNC("e1000_init_phy_params_pchlan");
 437
 438         phy->addr               = 1;
 439         phy->reset_delay_us     = 100;
 440
 441         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 442         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 443         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 444         phy->ops.set_page       = e1000_set_page_igp;
 445         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 446         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 447         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 448         phy->ops.release        = e1000_release_swflag_ich8lan;
 449         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 450         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 451         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 452         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 453         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 454         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 455         phy->ops.power_up       = e1000_power_up_phy_copper;
 456         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 457         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458
 459         phy->id = e1000_phy_unknown;
 460
 461         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 462         if (ret_val)
 463                 return ret_val;
 464
 465         if (phy->id == e1000_phy_unknown)
 466                 switch (hw->mac.type) {
 467                 default:
 468                         ret_val = e1000_get_phy_id(hw);
 469                         if (ret_val)
 470                                 return ret_val;
 471                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 472                                 break;
 473                         /* fall-through */
 474                 case e1000_pch2lan:
 475                 case e1000_pch_lpt:
 476                         /* In case the PHY needs to be in mdio slow mode,
 477                          * set slow mode and try to get the PHY id again.
 478                          */
 479                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 480                         if (ret_val)
 481                                 return ret_val;
 482                         ret_val = e1000_get_phy_id(hw);
 483                         if (ret_val)
 484                                 return ret_val;
 485                         break;
 486                 }
 487         phy->type = e1000_get_phy_type_from_id(phy->id);
 488
 489         switch (phy->type) {
 490         case e1000_phy_82577:
 491         case e1000_phy_82579:
 492         case e1000_phy_i217:
 493                 phy->ops.check_polarity = e1000_check_polarity_82577;
 494                 phy->ops.force_speed_duplex =
 495                         e1000_phy_force_speed_duplex_82577;
 496                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 497                 phy->ops.get_info = e1000_get_phy_info_82577;
 498                 phy->ops.commit = e1000_phy_sw_reset_generic;
 499                 break;
 500         case e1000_phy_82578:
 501                 phy->ops.check_polarity = e1000_check_polarity_m88;
 502                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 503                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 504                 phy->ops.get_info = e1000_get_phy_info_m88;
 505                 break;
 506         default:
 507                 ret_val = -E1000_ERR_PHY;
 508                 break;
 509         }
 510
 511         return ret_val;
 512 }
 513
 514 /**
 515  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 516  *  @hw: pointer to the HW structure
 517  *
 518  *  Initialize family-specific PHY parameters and function pointers.
 519  **/
 520 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 521 {
 522         struct e1000_phy_info *phy = &hw->phy;
 523         s32 ret_val;
 524         u16 i = 0;
 525
 526         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 527
 528         phy->addr               = 1;
 529         phy->reset_delay_us     = 100;
 530
 531         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 532         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 533         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 534         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 535         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 536         phy->ops.release        = e1000_release_swflag_ich8lan;
 537         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 538         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 539         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 540         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 541         phy->ops.power_up       = e1000_power_up_phy_copper;
 542         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 543
 544         /* We may need to do this twice - once for IGP and if that fails,
 545          * we'll set BM func pointers and try again
 546          */
 547         ret_val = e1000_determine_phy_address(hw);
 548         if (ret_val) {
 549                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 550                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 551                 ret_val = e1000_determine_phy_address(hw);
 552                 if (ret_val) {
 553                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 554                         return ret_val;
 555                 }
 556         }
 557
 558         phy->id = 0;
 559         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 560                (i++ < 100)) {
 561                 msec_delay(1);
 562                 ret_val = e1000_get_phy_id(hw);
 563                 if (ret_val)
 564                         return ret_val;
 565         }
 566
 567         /* Verify phy id */
 568         switch (phy->id) {
 569         case IGP03E1000_E_PHY_ID:
 570                 phy->type = e1000_phy_igp_3;
 571                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 572                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 573                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 574                 phy->ops.get_info = e1000_get_phy_info_igp;
 575                 phy->ops.check_polarity = e1000_check_polarity_igp;
 576                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 577                 break;
 578         case IFE_E_PHY_ID:
 579         case IFE_PLUS_E_PHY_ID:
 580         case IFE_C_E_PHY_ID:
 581                 phy->type = e1000_phy_ife;
 582                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 583                 phy->ops.get_info = e1000_get_phy_info_ife;
 584                 phy->ops.check_polarity = e1000_check_polarity_ife;
 585                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 586                 break;
 587         case BME1000_E_PHY_ID:
 588                 phy->type = e1000_phy_bm;
 589                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 590                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 591                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 592                 phy->ops.commit = e1000_phy_sw_reset_generic;
 593                 phy->ops.get_info = e1000_get_phy_info_m88;
 594                 phy->ops.check_polarity = e1000_check_polarity_m88;
 595                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 596                 break;
 597         default:
 598                 return -E1000_ERR_PHY;
 599                 break;
 600         }
 601
 602         return E1000_SUCCESS;
 603 }
 604
 605 /**
 606  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 607  *  @hw: pointer to the HW structure
 608  *
 609  *  Initialize family-specific NVM parameters and function
 610  *  pointers.
 611  **/
 612 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 613 {
 614         struct e1000_nvm_info *nvm = &hw->nvm;
 615         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 616         u32 gfpreg, sector_base_addr, sector_end_addr;
 617         u16 i;
 618
 619         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 620
 621         /* Can't read flash registers if the register set isn't mapped. */
 622         nvm->type = e1000_nvm_flash_sw;
 623         if (!hw->flash_address) {
 624                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 625                 return -E1000_ERR_CONFIG;
 626         }
 627
 628         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 629
 630         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 631          * Add 1 to sector_end_addr since this sector is included in
 632          * the overall size.
 633          */
 634         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 635         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 636
 637         /* flash_base_addr is byte-aligned */
 638         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 639
 640         /* find total size of the NVM, then cut in half since the total
 641          * size represents two separate NVM banks.
 642          */
 643         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 644                                 << FLASH_SECTOR_ADDR_SHIFT);
 645         nvm->flash_bank_size /= 2;
 646         /* Adjust to word count */
 647         nvm->flash_bank_size /= sizeof(u16);
 648
 649         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 650
 651         /* Clear shadow ram */
 652         for (i = 0; i < nvm->word_size; i++) {
 653                 dev_spec->shadow_ram[i].modified = false;
 654                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 655         }
 656
 657         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 658         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 659
 660         /* Function Pointers */
 661         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 662         nvm->ops.release        = e1000_release_nvm_ich8lan;
 663         nvm->ops.read           = e1000_read_nvm_ich8lan;
 664         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 665         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 666         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 667         nvm->ops.write          = e1000_write_nvm_ich8lan;
 668
 669         return E1000_SUCCESS;
 670 }
 671
 672 /**
 673  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 674  *  @hw: pointer to the HW structure
 675  *
 676  *  Initialize family-specific MAC parameters and function
 677  *  pointers.
 678  **/
 679 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 680 {
 681         struct e1000_mac_info *mac = &hw->mac;
 682 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 683         u16 pci_cfg;
 684 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 685
 686         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 687
 688         /* Set media type function pointer */
 689         hw->phy.media_type = e1000_media_type_copper;
 690
 691         /* Set mta register count */
 692         mac->mta_reg_count = 32;
 693         /* Set rar entry count */
 694         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 695         if (mac->type == e1000_ich8lan)
 696                 mac->rar_entry_count--;
 697         /* Set if part includes ASF firmware */
 698         mac->asf_firmware_present = true;
 699         /* FWSM register */
 700         mac->has_fwsm = true;
 701         /* ARC subsystem not supported */
 702         mac->arc_subsystem_valid = false;
 703         /* Adaptive IFS supported */
 704         mac->adaptive_ifs = true;
 705
 706         /* Function pointers */
 707
 708         /* bus type/speed/width */
 709         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 710         /* function id */
 711         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 712         /* reset */
 713         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 714         /* hw initialization */
 715         mac->ops.init_hw = e1000_init_hw_ich8lan;
 716         /* link setup */
 717         mac->ops.setup_link = e1000_setup_link_ich8lan;
 718         /* physical interface setup */
 719         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 720         /* check for link */
 721         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 722         /* link info */
 723         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 724         /* multicast address update */
 725         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 726         /* clear hardware counters */
 727         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 728
 729         /* LED and other operations */
 730         switch (mac->type) {
 731         case e1000_ich8lan:
 732         case e1000_ich9lan:
 733         case e1000_ich10lan:
 734                 /* check management mode */
 735                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 736                 /* ID LED init */
 737                 mac->ops.id_led_init = e1000_id_led_init_generic;
 738                 /* blink LED */
 739                 mac->ops.blink_led = e1000_blink_led_generic;
 740                 /* setup LED */
 741                 mac->ops.setup_led = e1000_setup_led_generic;
 742                 /* cleanup LED */
 743                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 744                 /* turn on/off LED */
 745                 mac->ops.led_on = e1000_led_on_ich8lan;
 746                 mac->ops.led_off = e1000_led_off_ich8lan;
 747                 break;
 748         case e1000_pch2lan:
 749                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 750                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 751                 /* fall-through */
 752         case e1000_pch_lpt:
 753 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 754                 /* multicast address update for pch2 */
 755                 mac->ops.update_mc_addr_list =
 756                         e1000_update_mc_addr_list_pch2lan;
 757 #endif
 758         case e1000_pchlan:
 759 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 760                 /* save PCH revision_id */
 761                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 762                 hw->revision_id = (u8)(pci_cfg &= 0x000F);
 763 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 764                 /* check management mode */
 765                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 766                 /* ID LED init */
 767                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 768                 /* setup LED */
 769                 mac->ops.setup_led = e1000_setup_led_pchlan;
 770                 /* cleanup LED */
 771                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 772                 /* turn on/off LED */
 773                 mac->ops.led_on = e1000_led_on_pchlan;
 774                 mac->ops.led_off = e1000_led_off_pchlan;
 775                 break;
 776         default:
 777                 break;
 778         }
 779
 780         if (mac->type == e1000_pch_lpt) {
 781                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 782                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 783                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 784         }
 785
 786         /* Enable PCS Lock-loss workaround for ICH8 */
 787         if (mac->type == e1000_ich8lan)
 788                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 789
 790         return E1000_SUCCESS;
 791 }
 792
 793 /**
 794  *  __e1000_access_emi_reg_locked - Read/write EMI register
 795  *  @hw: pointer to the HW structure
 796  *  @addr: EMI address to program
 797  *  @data: pointer to value to read/write from/to the EMI address
 798  *  @read: boolean flag to indicate read or write
 799  *
 800  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 801  **/
 802 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 803                                          u16 *data, bool read)
 804 {
 805         s32 ret_val;
 806
 807         DEBUGFUNC("__e1000_access_emi_reg_locked");
 808
 809         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 810         if (ret_val)
 811                 return ret_val;
 812
 813         if (read)
 814                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 815                                                       data);
 816         else
 817                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 818                                                        *data);
 819
 820         return ret_val;
 821 }
 822
 823 /**
 824  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 825  *  @hw: pointer to the HW structure
 826  *  @addr: EMI address to program
 827  *  @data: value to be read from the EMI address
 828  *
 829  *  Assumes the SW/FW/HW Semaphore is already acquired.
 830  **/
 831 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 832 {
 833         DEBUGFUNC("e1000_read_emi_reg_locked");
 834
 835         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 836 }
 837
 838 /**
 839  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 840  *  @hw: pointer to the HW structure
 841  *  @addr: EMI address to program
 842  *  @data: value to be written to the EMI address
 843  *
 844  *  Assumes the SW/FW/HW Semaphore is already acquired.
 845  **/
 846 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 847 {
 848         DEBUGFUNC("e1000_read_emi_reg_locked");
 849
 850         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 851 }
 852
 853 /**
 854  *  e1000_set_eee_pchlan - Enable/disable EEE support
 855  *  @hw: pointer to the HW structure
 856  *
 857  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 858  *  the link and the EEE capabilities of the link partner.  The LPI Control
 859  *  register bits will remain set only if/when link is up.
 860  *
 861  *  EEE LPI must not be asserted earlier than one second after link is up.
 862  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 863  *  can be link issues with some switches.  Other devices can have EEE LPI
 864  *  enabled immediately upon link up since they have a timer in hardware which
 865  *  prevents LPI from being asserted too early.
 866  **/
 867 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 868 {
 869         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 870         s32 ret_val;
 871         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 872
 873         DEBUGFUNC("e1000_set_eee_pchlan");
 874
 875         switch (hw->phy.type) {
 876         case e1000_phy_82579:
 877                 lpa = I82579_EEE_LP_ABILITY;
 878                 pcs_status = I82579_EEE_PCS_STATUS;
 879                 adv_addr = I82579_EEE_ADVERTISEMENT;
 880                 break;
 881         case e1000_phy_i217:
 882                 lpa = I217_EEE_LP_ABILITY;
 883                 pcs_status = I217_EEE_PCS_STATUS;
 884                 adv_addr = I217_EEE_ADVERTISEMENT;
 885                 break;
 886         default:
 887                 return E1000_SUCCESS;
 888         }
 889
 890         ret_val = hw->phy.ops.acquire(hw);
 891         if (ret_val)
 892                 return ret_val;
 893
 894         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 895         if (ret_val)
 896                 goto release;
 897
 898         /* Clear bits that enable EEE in various speeds */
 899         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 900
 901         /* Enable EEE if not disabled by user */
 902         if (!dev_spec->eee_disable) {
 903                 /* Save off link partner's EEE ability */
 904                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 905                                                     &dev_spec->eee_lp_ability);
 906                 if (ret_val)
 907                         goto release;
 908
 909                 /* Read EEE advertisement */
 910                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 911                 if (ret_val)
 912                         goto release;
 913
 914                 /* Enable EEE only for speeds in which the link partner is
 915                  * EEE capable and for which we advertise EEE.
 916                  */
 917                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 918                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 919
 920                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 921                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 922                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 923                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 924                         else
 925                                 /* EEE is not supported in 100Half, so ignore
 926                                  * partner's EEE in 100 ability if full-duplex
 927                                  * is not advertised.
 928                                  */
 929                                 dev_spec->eee_lp_ability &=
 930                                     ~I82579_EEE_100_SUPPORTED;
 931                 }
 932         }
 933
 934         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 935         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 936         if (ret_val)
 937                 goto release;
 938
 939         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 940 release:
 941         hw->phy.ops.release(hw);
 942
 943         return ret_val;
 944 }
 945
 946 /**
 947  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 948  *  @hw:   pointer to the HW structure
 949  *  @link: link up bool flag
 950  *
 951  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 952  *  preventing further DMA write requests.  Workaround the issue by disabling
 953  *  the de-assertion of the clock request when in 1Gpbs mode.
 954  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 955  *  speeds in order to avoid Tx hangs.
 956  **/
 957 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 958 {
 959         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 960         u32 status = E1000_READ_REG(hw, E1000_STATUS);
 961         s32 ret_val = E1000_SUCCESS;
 962         u16 reg;
 963
 964         if (link && (status & E1000_STATUS_SPEED_1000)) {
 965                 ret_val = hw->phy.ops.acquire(hw);
 966                 if (ret_val)
 967                         return ret_val;
 968
 969                 ret_val =
 970                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 971                                                &reg);
 972                 if (ret_val)
 973                         goto release;
 974
 975                 ret_val =
 976                     e1000_write_kmrn_reg_locked(hw,
 977                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 978                                                 reg &
 979                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
 980                 if (ret_val)
 981                         goto release;
 982
 983                 usec_delay(10);
 984
 985                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
 986                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 987
 988                 ret_val =
 989                     e1000_write_kmrn_reg_locked(hw,
 990                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 991                                                 reg);
 992 release:
 993                 hw->phy.ops.release(hw);
 994         } else {
 995                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 996                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 997
 998                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
 999                               (status & E1000_STATUS_FD)))
1000                         goto update_fextnvm6;
1001
1002                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1003                 if (ret_val)
1004                         return ret_val;
1005
1006                 /* Clear link status transmit timeout */
1007                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1008
1009                 if (status & E1000_STATUS_SPEED_100) {
1010                         /* Set inband Tx timeout to 5x10us for 100Half */
1011                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1012
1013                         /* Do not extend the K1 entry latency for 100Half */
1014                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1015                 } else {
1016                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1017                         reg |= 50 <<
1018                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1019
1020                         /* Extend the K1 entry latency for 10 Mbps */
1021                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1022                 }
1023
1024                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1025                 if (ret_val)
1026                         return ret_val;
1027
1028 update_fextnvm6:
1029                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1030         }
1031
1032         return ret_val;
1033 }
1034
1035 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
1036 /**
1037  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1038  *  @hw: pointer to the HW structure
1039  *  @to_sx: boolean indicating a system power state transition to Sx
1040  *
1041  *  When link is down, configure ULP mode to significantly reduce the power
1042  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1043  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1044  *  system, configure the ULP mode by software.
1045  */
1046 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1047 {
1048         u32 mac_reg;
1049         s32 ret_val = E1000_SUCCESS;
1050         u16 phy_reg;
1051
1052         if ((hw->mac.type < e1000_pch_lpt) ||
1053             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1054             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1055             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1056                 return 0;
1057
1058         if (!to_sx) {
1059                 int i = 0;
1060
1061                 /* Poll up to 5 seconds for Cable Disconnected indication */
1062                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1063                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1064                         /* Bail if link is re-acquired */
1065                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1066                                 return -E1000_ERR_PHY;
1067
1068                         if (i++ == 100)
1069                                 break;
1070
1071                         msec_delay(50);
1072                 }
1073                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1074                           (E1000_READ_REG(hw, E1000_FEXT) &
1075                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1076                           i * 50);
1077         }
1078
1079         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1080                 /* Request ME configure ULP mode in the PHY */
1081                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1082                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1083                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1084
1085                 goto out;
1086         }
1087
1088         ret_val = hw->phy.ops.acquire(hw);
1089         if (ret_val)
1090                 goto out;
1091
1092         /* During S0 Idle keep the phy in PCI-E mode */
1093         if (hw->dev_spec.ich8lan.smbus_disable)
1094                 goto skip_smbus;
1095
1096         /* Force SMBus mode in PHY */
1097         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1098         if (ret_val)
1099                 goto release;
1100         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1101         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1102
1103         /* Force SMBus mode in MAC */
1104         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1105         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1106         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1107
1108 skip_smbus:
1109         if (!to_sx) {
1110                 /* Change the 'Link Status Change' interrupt to trigger
1111                  * on 'Cable Status Change'
1112                  */
1113                 ret_val = e1000_read_kmrn_reg_locked(hw,
1114                                                      E1000_KMRNCTRLSTA_OP_MODES,
1115                                                      &phy_reg);
1116                 if (ret_val)
1117                         goto release;
1118                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1119                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1120                                             phy_reg);
1121         }
1122
1123         /* Set Inband ULP Exit, Reset to SMBus mode and
1124          * Disable SMBus Release on PERST# in PHY
1125          */
1126         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1127         if (ret_val)
1128                 goto release;
1129         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1130                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1131         if (to_sx) {
1132                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1133                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1134
1135                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1136         } else {
1137                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1138         }
1139         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1140
1141         /* Set Disable SMBus Release on PERST# in MAC */
1142         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1143         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1144         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1145
1146         /* Commit ULP changes in PHY by starting auto ULP configuration */
1147         phy_reg |= I218_ULP_CONFIG1_START;
1148         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1149
1150         if (!to_sx) {
1151                 /* Disable Tx so that the MAC doesn't send any (buffered)
1152                  * packets to the PHY.
1153                  */
1154                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1155                 mac_reg &= ~E1000_TCTL_EN;
1156                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1157         }
1158 release:
1159         hw->phy.ops.release(hw);
1160 out:
1161         if (ret_val)
1162                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1163         else
1164                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1165
1166         return ret_val;
1167 }
1168
1169 /**
1170  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1171  *  @hw: pointer to the HW structure
1172  *  @force: boolean indicating whether or not to force disabling ULP
1173  *
1174  *  Un-configure ULP mode when link is up, the system is transitioned from
1175  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1176  *  system, poll for an indication from ME that ULP has been un-configured.
1177  *  If not on an ME enabled system, un-configure the ULP mode by software.
1178  *
1179  *  During nominal operation, this function is called when link is acquired
1180  *  to disable ULP mode (force=false); otherwise, for example when unloading
1181  *  the driver or during Sx->S0 transitions, this is called with force=true
1182  *  to forcibly disable ULP.
1183
1184  *  When the cable is plugged in while the device is in D0, a Cable Status
1185  *  Change interrupt is generated which causes this function to be called
1186  *  to partially disable ULP mode and restart autonegotiation.  This function
1187  *  is then called again due to the resulting Link Status Change interrupt
1188  *  to finish cleaning up after the ULP flow.
1189  */
1190 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1191 {
1192         s32 ret_val = E1000_SUCCESS;
1193         u32 mac_reg;
1194         u16 phy_reg;
1195         int i = 0;
1196
1197         if ((hw->mac.type < e1000_pch_lpt) ||
1198             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1199             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1200             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1201                 return 0;
1202
1203         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1204                 if (force) {
1205                         /* Request ME un-configure ULP mode in the PHY */
1206                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1207                         mac_reg &= ~E1000_H2ME_ULP;
1208                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1209                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1210                 }
1211
1212                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1213                 while (E1000_READ_REG(hw, E1000_FWSM) &
1214                        E1000_FWSM_ULP_CFG_DONE) {
1215                         if (i++ == 10) {
1216                                 ret_val = -E1000_ERR_PHY;
1217                                 goto out;
1218                         }
1219
1220                         msec_delay(10);
1221                 }
1222                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1223
1224                 if (force) {
1225                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1226                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1227                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1228                 } else {
1229                         /* Clear H2ME.ULP after ME ULP configuration */
1230                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1231                         mac_reg &= ~E1000_H2ME_ULP;
1232                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1233
1234                         /* Restore link speed advertisements and restart
1235                          * Auto-negotiation
1236                          */
1237                         ret_val = e1000_phy_setup_autoneg(hw);
1238                         if (ret_val)
1239                                 goto out;
1240
1241                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1242                 }
1243
1244                 goto out;
1245         }
1246
1247         ret_val = hw->phy.ops.acquire(hw);
1248         if (ret_val)
1249                 goto out;
1250
1251         /* Revert the change to the 'Link Status Change'
1252          * interrupt to trigger on 'Cable Status Change'
1253          */
1254         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1255                                              &phy_reg);
1256         if (ret_val)
1257                 goto release;
1258         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1259         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1260
1261         if (force)
1262                 /* Toggle LANPHYPC Value bit */
1263                 e1000_toggle_lanphypc_pch_lpt(hw);
1264
1265         /* Unforce SMBus mode in PHY */
1266         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1267         if (ret_val) {
1268                 /* The MAC might be in PCIe mode, so temporarily force to
1269                  * SMBus mode in order to access the PHY.
1270                  */
1271                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1272                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1273                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1274
1275                 msec_delay(50);
1276
1277                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1278                                                        &phy_reg);
1279                 if (ret_val)
1280                         goto release;
1281         }
1282         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1283         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1284
1285         /* Unforce SMBus mode in MAC */
1286         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1287         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1288         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1289
1290         /* When ULP mode was previously entered, K1 was disabled by the
1291          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1292          */
1293         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1294         if (ret_val)
1295                 goto release;
1296         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1297         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1298
1299         /* Clear ULP enabled configuration */
1300         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1301         if (ret_val)
1302                 goto release;
1303         /* CSC interrupt received due to ULP Indication */
1304         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1305                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1306                              I218_ULP_CONFIG1_STICKY_ULP |
1307                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1308                              I218_ULP_CONFIG1_WOL_HOST |
1309                              I218_ULP_CONFIG1_INBAND_EXIT |
1310                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1311                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1312
1313                 /* Commit ULP changes by starting auto ULP configuration */
1314                 phy_reg |= I218_ULP_CONFIG1_START;
1315                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1316
1317                 /* Clear Disable SMBus Release on PERST# in MAC */
1318                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1319                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1320                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1321
1322                 if (!force) {
1323                         hw->phy.ops.release(hw);
1324
1325                         if (hw->mac.autoneg)
1326                                 e1000_phy_setup_autoneg(hw);
1327
1328                         e1000_sw_lcd_config_ich8lan(hw);
1329
1330                         e1000_oem_bits_config_ich8lan(hw, true);
1331
1332                         /* Set ULP state to unknown and return non-zero to
1333                          * indicate no link (yet) and re-enter on the next LSC
1334                          * to finish disabling ULP flow.
1335                          */
1336                         hw->dev_spec.ich8lan.ulp_state =
1337                             e1000_ulp_state_unknown;
1338
1339                         return 1;
1340                 }
1341         }
1342
1343         /* Re-enable Tx */
1344         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1345         mac_reg |= E1000_TCTL_EN;
1346         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1347
1348 release:
1349         hw->phy.ops.release(hw);
1350         if (force) {
1351                 hw->phy.ops.reset(hw);
1352                 msec_delay(50);
1353         }
1354 out:
1355         if (ret_val)
1356                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1357         else
1358                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1359
1360         return ret_val;
1361 }
1362
1363 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
1364 /**
1365  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1366  *  @hw: pointer to the HW structure
1367  *
1368  *  Checks to see of the link status of the hardware has changed.  If a
1369  *  change in link status has been detected, then we read the PHY registers
1370  *  to get the current speed/duplex if link exists.
1371  **/
1372 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1373 {
1374         struct e1000_mac_info *mac = &hw->mac;
1375         s32 ret_val;
1376         bool link = false;
1377         u16 phy_reg;
1378
1379         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1380
1381         /* We only want to go out to the PHY registers to see if Auto-Neg
1382          * has completed and/or if our link status has changed.  The
1383          * get_link_status flag is set upon receiving a Link Status
1384          * Change or Rx Sequence Error interrupt.
1385          */
1386         if (!mac->get_link_status)
1387                 return E1000_SUCCESS;
1388
1389         if ((hw->mac.type < e1000_pch_lpt) ||
1390             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1391             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1392                 /* First we want to see if the MII Status Register reports
1393                  * link.  If so, then we want to get the current speed/duplex
1394                  * of the PHY.
1395                  */
1396                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1397                 if (ret_val)
1398                         return ret_val;
1399         } else {
1400                 /* Check the MAC's STATUS register to determine link state
1401                  * since the PHY could be inaccessible while in ULP mode.
1402                  */
1403                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1404                 if (link)
1405                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1406                 else
1407                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1408
1409                 if (ret_val)
1410                         return ret_val;
1411         }
1412
1413         if (hw->mac.type == e1000_pchlan) {
1414                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1415                 if (ret_val)
1416                         return ret_val;
1417         }
1418
1419         /* When connected at 10Mbps half-duplex, some parts are excessively
1420          * aggressive resulting in many collisions. To avoid this, increase
1421          * the IPG and reduce Rx latency in the PHY.
1422          */
1423         if (((hw->mac.type == e1000_pch2lan) ||
1424              (hw->mac.type == e1000_pch_lpt)) && link) {
1425                 u32 reg;
1426                 reg = E1000_READ_REG(hw, E1000_STATUS);
1427                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1428                         u16 emi_addr;
1429
1430                         reg = E1000_READ_REG(hw, E1000_TIPG);
1431                         reg &= ~E1000_TIPG_IPGT_MASK;
1432                         reg |= 0xFF;
1433                         E1000_WRITE_REG(hw, E1000_TIPG, reg);
1434
1435                         /* Reduce Rx latency in analog PHY */
1436                         ret_val = hw->phy.ops.acquire(hw);
1437                         if (ret_val)
1438                                 return ret_val;
1439
1440                         if (hw->mac.type == e1000_pch2lan)
1441                                 emi_addr = I82579_RX_CONFIG;
1442                         else
1443                                 emi_addr = I217_RX_CONFIG;
1444                         ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1445
1446                         hw->phy.ops.release(hw);
1447
1448                         if (ret_val)
1449                                 return ret_val;
1450                 }
1451         }
1452
1453         /* Work-around I218 hang issue */
1454         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1455             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
1456                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1457                 if (ret_val)
1458                         return ret_val;
1459         }
1460
1461         /* Clear link partner's EEE ability */
1462         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1463
1464         if (!link)
1465                 return E1000_SUCCESS; /* No link detected */
1466
1467         mac->get_link_status = false;
1468
1469         switch (hw->mac.type) {
1470         case e1000_pch2lan:
1471                 ret_val = e1000_k1_workaround_lv(hw);
1472                 if (ret_val)
1473                         return ret_val;
1474                 /* fall-thru */
1475         case e1000_pchlan:
1476                 if (hw->phy.type == e1000_phy_82578) {
1477                         ret_val = e1000_link_stall_workaround_hv(hw);
1478                         if (ret_val)
1479                                 return ret_val;
1480                 }
1481
1482                 /* Workaround for PCHx parts in half-duplex:
1483                  * Set the number of preambles removed from the packet
1484                  * when it is passed from the PHY to the MAC to prevent
1485                  * the MAC from misinterpreting the packet type.
1486                  */
1487                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1488                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1489
1490                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1491                     E1000_STATUS_FD)
1492                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1493
1494                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1495                 break;
1496         default:
1497                 break;
1498         }
1499
1500         /* Check if there was DownShift, must be checked
1501          * immediately after link-up
1502          */
1503         e1000_check_downshift_generic(hw);
1504
1505         /* Enable/Disable EEE after link up */
1506         if (hw->phy.type > e1000_phy_82579) {
1507                 ret_val = e1000_set_eee_pchlan(hw);
1508                 if (ret_val)
1509                         return ret_val;
1510         }
1511
1512         /* If we are forcing speed/duplex, then we simply return since
1513          * we have already determined whether we have link or not.
1514          */
1515         if (!mac->autoneg)
1516                 return -E1000_ERR_CONFIG;
1517
1518         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1519          * of MAC speed/duplex configuration.  So we only need to
1520          * configure Collision Distance in the MAC.
1521          */
1522         mac->ops.config_collision_dist(hw);
1523
1524         /* Configure Flow Control now that Auto-Neg has completed.
1525          * First, we need to restore the desired flow control
1526          * settings because we may have had to re-autoneg with a
1527          * different link partner.
1528          */
1529         ret_val = e1000_config_fc_after_link_up_generic(hw);
1530         if (ret_val)
1531                 DEBUGOUT("Error configuring flow control\n");
1532
1533         return ret_val;
1534 }
1535
1536 /**
1537  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1538  *  @hw: pointer to the HW structure
1539  *
1540  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1541  **/
1542 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1543 {
1544         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1545
1546         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1547         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1548         switch (hw->mac.type) {
1549         case e1000_ich8lan:
1550         case e1000_ich9lan:
1551         case e1000_ich10lan:
1552                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1553                 break;
1554         case e1000_pchlan:
1555         case e1000_pch2lan:
1556         case e1000_pch_lpt:
1557                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1558                 break;
1559         default:
1560                 break;
1561         }
1562 }
1563
1564 /**
1565  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1566  *  @hw: pointer to the HW structure
1567  *
1568  *  Acquires the mutex for performing NVM operations.
1569  **/
1570 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1571 {
1572         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1573
1574         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1575
1576         return E1000_SUCCESS;
1577 }
1578
1579 /**
1580  *  e1000_release_nvm_ich8lan - Release NVM mutex
1581  *  @hw: pointer to the HW structure
1582  *
1583  *  Releases the mutex used while performing NVM operations.
1584  **/
1585 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1586 {
1587         DEBUGFUNC("e1000_release_nvm_ich8lan");
1588
1589         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1590
1591         return;
1592 }
1593
1594 /**
1595  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1596  *  @hw: pointer to the HW structure
1597  *
1598  *  Acquires the software control flag for performing PHY and select
1599  *  MAC CSR accesses.
1600  **/
1601 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1602 {
1603         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1604         s32 ret_val = E1000_SUCCESS;
1605
1606         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1607
1608         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1609
1610         while (timeout) {
1611                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1612                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1613                         break;
1614
1615                 msec_delay_irq(1);
1616                 timeout--;
1617         }
1618
1619         if (!timeout) {
1620                 DEBUGOUT("SW has already locked the resource.\n");
1621                 ret_val = -E1000_ERR_CONFIG;
1622                 goto out;
1623         }
1624
1625         timeout = SW_FLAG_TIMEOUT;
1626
1627         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1628         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1629
1630         while (timeout) {
1631                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1632                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1633                         break;
1634
1635                 msec_delay_irq(1);
1636                 timeout--;
1637         }
1638
1639         if (!timeout) {
1640                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1641                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1642                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1643                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1644                 ret_val = -E1000_ERR_CONFIG;
1645                 goto out;
1646         }
1647
1648 out:
1649         if (ret_val)
1650                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1651
1652         return ret_val;
1653 }
1654
1655 /**
1656  *  e1000_release_swflag_ich8lan - Release software control flag
1657  *  @hw: pointer to the HW structure
1658  *
1659  *  Releases the software control flag for performing PHY and select
1660  *  MAC CSR accesses.
1661  **/
1662 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1663 {
1664         u32 extcnf_ctrl;
1665
1666         DEBUGFUNC("e1000_release_swflag_ich8lan");
1667
1668         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1669
1670         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1671                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1672                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1673         } else {
1674                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1675         }
1676
1677         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1678
1679         return;
1680 }
1681
1682 /**
1683  *  e1000_check_mng_mode_ich8lan - Checks management mode
1684  *  @hw: pointer to the HW structure
1685  *
1686  *  This checks if the adapter has any manageability enabled.
1687  *  This is a function pointer entry point only called by read/write
1688  *  routines for the PHY and NVM parts.
1689  **/
1690 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1691 {
1692         u32 fwsm;
1693
1694         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1695
1696         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1697
1698         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1699                ((fwsm & E1000_FWSM_MODE_MASK) ==
1700                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1701 }
1702
1703 /**
1704  *  e1000_check_mng_mode_pchlan - Checks management mode
1705  *  @hw: pointer to the HW structure
1706  *
1707  *  This checks if the adapter has iAMT enabled.
1708  *  This is a function pointer entry point only called by read/write
1709  *  routines for the PHY and NVM parts.
1710  **/
1711 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1712 {
1713         u32 fwsm;
1714
1715         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1716
1717         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1718
1719         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1720                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1721 }
1722
1723 /**
1724  *  e1000_rar_set_pch2lan - Set receive address register
1725  *  @hw: pointer to the HW structure
1726  *  @addr: pointer to the receive address
1727  *  @index: receive address array register
1728  *
1729  *  Sets the receive address array register at index to the address passed
1730  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1731  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1732  *  Use SHRA[0-3] in place of those reserved for ME.
1733  **/
1734 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1735 {
1736         u32 rar_low, rar_high;
1737
1738         DEBUGFUNC("e1000_rar_set_pch2lan");
1739
1740         /* HW expects these in little endian so we reverse the byte order
1741          * from network order (big endian) to little endian
1742          */
1743         rar_low = ((u32) addr[0] |
1744                    ((u32) addr[1] << 8) |
1745                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1746
1747         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1748
1749         /* If MAC address zero, no need to set the AV bit */
1750         if (rar_low || rar_high)
1751                 rar_high |= E1000_RAH_AV;
1752
1753         if (index == 0) {
1754                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1755                 E1000_WRITE_FLUSH(hw);
1756                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1757                 E1000_WRITE_FLUSH(hw);
1758                 return;
1759         }
1760
1761         /* RAR[1-6] are owned by manageability.  Skip those and program the
1762          * next address into the SHRA register array.
1763          */
1764         if (index < (u32) (hw->mac.rar_entry_count)) {
1765                 s32 ret_val;
1766
1767                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1768                 if (ret_val)
1769                         goto out;
1770
1771                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1772                 E1000_WRITE_FLUSH(hw);
1773                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1774                 E1000_WRITE_FLUSH(hw);
1775
1776                 e1000_release_swflag_ich8lan(hw);
1777
1778                 /* verify the register updates */
1779                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1780                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1781                         return;
1782
1783                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1784                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1785         }
1786
1787 out:
1788         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1789 }
1790
1791 /**
1792  *  e1000_rar_set_pch_lpt - Set receive address registers
1793  *  @hw: pointer to the HW structure
1794  *  @addr: pointer to the receive address
1795  *  @index: receive address array register
1796  *
1797  *  Sets the receive address register array at index to the address passed
1798  *  in by addr. For LPT, RAR[0] is the base address register that is to
1799  *  contain the MAC address. SHRA[0-10] are the shared receive address
1800  *  registers that are shared between the Host and manageability engine (ME).
1801  **/
1802 STATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1803 {
1804         u32 rar_low, rar_high;
1805         u32 wlock_mac;
1806
1807         DEBUGFUNC("e1000_rar_set_pch_lpt");
1808
1809         /* HW expects these in little endian so we reverse the byte order
1810          * from network order (big endian) to little endian
1811          */
1812         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1813                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1814
1815         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1816
1817         /* If MAC address zero, no need to set the AV bit */
1818         if (rar_low || rar_high)
1819                 rar_high |= E1000_RAH_AV;
1820
1821         if (index == 0) {
1822                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1823                 E1000_WRITE_FLUSH(hw);
1824                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1825                 E1000_WRITE_FLUSH(hw);
1826                 return;
1827         }
1828
1829         /* The manageability engine (ME) can lock certain SHRAR registers that
1830          * it is using - those registers are unavailable for use.
1831          */
1832         if (index < hw->mac.rar_entry_count) {
1833                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1834                             E1000_FWSM_WLOCK_MAC_MASK;
1835                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1836
1837                 /* Check if all SHRAR registers are locked */
1838                 if (wlock_mac == 1)
1839                         goto out;
1840
1841                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1842                         s32 ret_val;
1843
1844                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1845
1846                         if (ret_val)
1847                                 goto out;
1848
1849                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1850                                         rar_low);
1851                         E1000_WRITE_FLUSH(hw);
1852                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1853                                         rar_high);
1854                         E1000_WRITE_FLUSH(hw);
1855
1856                         e1000_release_swflag_ich8lan(hw);
1857
1858                         /* verify the register updates */
1859                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1860                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1861                                 return;
1862                 }
1863         }
1864
1865 out:
1866         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1867 }
1868
1869 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1870 /**
1871  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1872  *  @hw: pointer to the HW structure
1873  *  @mc_addr_list: array of multicast addresses to program
1874  *  @mc_addr_count: number of multicast addresses to program
1875  *
1876  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1877  *  The caller must have a packed mc_addr_list of multicast addresses.
1878  **/
1879 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1880                                               u8 *mc_addr_list,
1881                                               u32 mc_addr_count)
1882 {
1883         u16 phy_reg = 0;
1884         int i;
1885         s32 ret_val;
1886
1887         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1888
1889         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1890
1891         ret_val = hw->phy.ops.acquire(hw);
1892         if (ret_val)
1893                 return;
1894
1895         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1896         if (ret_val)
1897                 goto release;
1898
1899         for (i = 0; i < hw->mac.mta_reg_count; i++) {
1900                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1901                                            (u16)(hw->mac.mta_shadow[i] &
1902                                                  0xFFFF));
1903                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1904                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
1905                                                  0xFFFF));
1906         }
1907
1908         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1909
1910 release:
1911         hw->phy.ops.release(hw);
1912 }
1913
1914 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1915 /**
1916  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1917  *  @hw: pointer to the HW structure
1918  *
1919  *  Checks if firmware is blocking the reset of the PHY.
1920  *  This is a function pointer entry point only called by
1921  *  reset routines.
1922  **/
1923 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1924 {
1925         u32 fwsm;
1926         bool blocked = false;
1927         int i = 0;
1928
1929         DEBUGFUNC("e1000_check_reset_block_ich8lan");
1930
1931         do {
1932                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1933                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
1934                         blocked = true;
1935                         msec_delay(10);
1936                         continue;
1937                 }
1938                 blocked = false;
1939         } while (blocked && (i++ < 10));
1940         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
1941 }
1942
1943 /**
1944  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1945  *  @hw: pointer to the HW structure
1946  *
1947  *  Assumes semaphore already acquired.
1948  *
1949  **/
1950 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1951 {
1952         u16 phy_data;
1953         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
1954         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1955                 E1000_STRAP_SMT_FREQ_SHIFT;
1956         s32 ret_val;
1957
1958         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1959
1960         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1961         if (ret_val)
1962                 return ret_val;
1963
1964         phy_data &= ~HV_SMB_ADDR_MASK;
1965         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1966         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1967
1968         if (hw->phy.type == e1000_phy_i217) {
1969                 /* Restore SMBus frequency */
1970                 if (freq--) {
1971                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1972                         phy_data |= (freq & (1 << 0)) <<
1973                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1974                         phy_data |= (freq & (1 << 1)) <<
1975                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1976                 } else {
1977                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
1978                 }
1979         }
1980
1981         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1982 }
1983
1984 /**
1985  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1986  *  @hw:   pointer to the HW structure
1987  *
1988  *  SW should configure the LCD from the NVM extended configuration region
1989  *  as a workaround for certain parts.
1990  **/
1991 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1992 {
1993         struct e1000_phy_info *phy = &hw->phy;
1994         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1995         s32 ret_val = E1000_SUCCESS;
1996         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1997
1998         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
1999
2000         /* Initialize the PHY from the NVM on ICH platforms.  This
2001          * is needed due to an issue where the NVM configuration is
2002          * not properly autoloaded after power transitions.
2003          * Therefore, after each PHY reset, we will load the
2004          * configuration data out of the NVM manually.
2005          */
2006         switch (hw->mac.type) {
2007         case e1000_ich8lan:
2008                 if (phy->type != e1000_phy_igp_3)
2009                         return ret_val;
2010
2011                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2012                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2013                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2014                         break;
2015                 }
2016                 /* Fall-thru */
2017         case e1000_pchlan:
2018         case e1000_pch2lan:
2019         case e1000_pch_lpt:
2020                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2021                 break;
2022         default:
2023                 return ret_val;
2024         }
2025
2026         ret_val = hw->phy.ops.acquire(hw);
2027         if (ret_val)
2028                 return ret_val;
2029
2030         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2031         if (!(data & sw_cfg_mask))
2032                 goto release;
2033
2034         /* Make sure HW does not configure LCD from PHY
2035          * extended configuration before SW configuration
2036          */
2037         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2038         if ((hw->mac.type < e1000_pch2lan) &&
2039             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2040                         goto release;
2041
2042         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2043         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2044         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2045         if (!cnf_size)
2046                 goto release;
2047
2048         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2049         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2050
2051         if (((hw->mac.type == e1000_pchlan) &&
2052              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2053             (hw->mac.type > e1000_pchlan)) {
2054                 /* HW configures the SMBus address and LEDs when the
2055                  * OEM and LCD Write Enable bits are set in the NVM.
2056                  * When both NVM bits are cleared, SW will configure
2057                  * them instead.
2058                  */
2059                 ret_val = e1000_write_smbus_addr(hw);
2060                 if (ret_val)
2061                         goto release;
2062
2063                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2064                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2065                                                         (u16)data);
2066                 if (ret_val)
2067                         goto release;
2068         }
2069
2070         /* Configure LCD from extended configuration region. */
2071
2072         /* cnf_base_addr is in DWORD */
2073         word_addr = (u16)(cnf_base_addr << 1);
2074
2075         for (i = 0; i < cnf_size; i++) {
2076                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2077                                            &reg_data);
2078                 if (ret_val)
2079                         goto release;
2080
2081                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2082                                            1, &reg_addr);
2083                 if (ret_val)
2084                         goto release;
2085
2086                 /* Save off the PHY page for future writes. */
2087                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2088                         phy_page = reg_data;
2089                         continue;
2090                 }
2091
2092                 reg_addr &= PHY_REG_MASK;
2093                 reg_addr |= phy_page;
2094
2095                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2096                                                     reg_data);
2097                 if (ret_val)
2098                         goto release;
2099         }
2100
2101 release:
2102         hw->phy.ops.release(hw);
2103         return ret_val;
2104 }
2105
2106 /**
2107  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2108  *  @hw:   pointer to the HW structure
2109  *  @link: link up bool flag
2110  *
2111  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2112  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2113  *  If link is down, the function will restore the default K1 setting located
2114  *  in the NVM.
2115  **/
2116 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2117 {
2118         s32 ret_val = E1000_SUCCESS;
2119         u16 status_reg = 0;
2120         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2121
2122         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2123
2124         if (hw->mac.type != e1000_pchlan)
2125                 return E1000_SUCCESS;
2126
2127         /* Wrap the whole flow with the sw flag */
2128         ret_val = hw->phy.ops.acquire(hw);
2129         if (ret_val)
2130                 return ret_val;
2131
2132         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2133         if (link) {
2134                 if (hw->phy.type == e1000_phy_82578) {
2135                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2136                                                               &status_reg);
2137                         if (ret_val)
2138                                 goto release;
2139
2140                         status_reg &= (BM_CS_STATUS_LINK_UP |
2141                                        BM_CS_STATUS_RESOLVED |
2142                                        BM_CS_STATUS_SPEED_MASK);
2143
2144                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2145                                            BM_CS_STATUS_RESOLVED |
2146                                            BM_CS_STATUS_SPEED_1000))
2147                                 k1_enable = false;
2148                 }
2149
2150                 if (hw->phy.type == e1000_phy_82577) {
2151                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2152                                                               &status_reg);
2153                         if (ret_val)
2154                                 goto release;
2155
2156                         status_reg &= (HV_M_STATUS_LINK_UP |
2157                                        HV_M_STATUS_AUTONEG_COMPLETE |
2158                                        HV_M_STATUS_SPEED_MASK);
2159
2160                         if (status_reg == (HV_M_STATUS_LINK_UP |
2161                                            HV_M_STATUS_AUTONEG_COMPLETE |
2162                                            HV_M_STATUS_SPEED_1000))
2163                                 k1_enable = false;
2164                 }
2165
2166                 /* Link stall fix for link up */
2167                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2168                                                        0x0100);
2169                 if (ret_val)
2170                         goto release;
2171
2172         } else {
2173                 /* Link stall fix for link down */
2174                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2175                                                        0x4100);
2176                 if (ret_val)
2177                         goto release;
2178         }
2179
2180         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2181
2182 release:
2183         hw->phy.ops.release(hw);
2184
2185         return ret_val;
2186 }
2187
2188 /**
2189  *  e1000_configure_k1_ich8lan - Configure K1 power state
2190  *  @hw: pointer to the HW structure
2191  *  @enable: K1 state to configure
2192  *
2193  *  Configure the K1 power state based on the provided parameter.
2194  *  Assumes semaphore already acquired.
2195  *
2196  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2197  **/
2198 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2199 {
2200         s32 ret_val;
2201         u32 ctrl_reg = 0;
2202         u32 ctrl_ext = 0;
2203         u32 reg = 0;
2204         u16 kmrn_reg = 0;
2205
2206         DEBUGFUNC("e1000_configure_k1_ich8lan");
2207
2208         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2209                                              &kmrn_reg);
2210         if (ret_val)
2211                 return ret_val;
2212
2213         if (k1_enable)
2214                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2215         else
2216                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2217
2218         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2219                                               kmrn_reg);
2220         if (ret_val)
2221                 return ret_val;
2222
2223         usec_delay(20);
2224         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2225         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2226
2227         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2228         reg |= E1000_CTRL_FRCSPD;
2229         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2230
2231         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2232         E1000_WRITE_FLUSH(hw);
2233         usec_delay(20);
2234         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2235         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2236         E1000_WRITE_FLUSH(hw);
2237         usec_delay(20);
2238
2239         return E1000_SUCCESS;
2240 }
2241
2242 /**
2243  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2244  *  @hw:       pointer to the HW structure
2245  *  @d0_state: boolean if entering d0 or d3 device state
2246  *
2247  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2248  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2249  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2250  **/
2251 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2252 {
2253         s32 ret_val = 0;
2254         u32 mac_reg;
2255         u16 oem_reg;
2256
2257         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2258
2259         if (hw->mac.type < e1000_pchlan)
2260                 return ret_val;
2261
2262         ret_val = hw->phy.ops.acquire(hw);
2263         if (ret_val)
2264                 return ret_val;
2265
2266         if (hw->mac.type == e1000_pchlan) {
2267                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2268                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2269                         goto release;
2270         }
2271
2272         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2273         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2274                 goto release;
2275
2276         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2277
2278         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2279         if (ret_val)
2280                 goto release;
2281
2282         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2283
2284         if (d0_state) {
2285                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2286                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2287
2288                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2289                         oem_reg |= HV_OEM_BITS_LPLU;
2290         } else {
2291                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2292                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2293                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2294
2295                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2296                     E1000_PHY_CTRL_NOND0A_LPLU))
2297                         oem_reg |= HV_OEM_BITS_LPLU;
2298         }
2299
2300         /* Set Restart auto-neg to activate the bits */
2301         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2302             !hw->phy.ops.check_reset_block(hw))
2303                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2304
2305         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2306
2307 release:
2308         hw->phy.ops.release(hw);
2309
2310         return ret_val;
2311 }
2312
2313
2314 /**
2315  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2316  *  @hw:   pointer to the HW structure
2317  **/
2318 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2319 {
2320         s32 ret_val;
2321         u16 data;
2322
2323         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2324
2325         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2326         if (ret_val)
2327                 return ret_val;
2328
2329         data |= HV_KMRN_MDIO_SLOW;
2330
2331         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2332
2333         return ret_val;
2334 }
2335
2336 /**
2337  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2338  *  done after every PHY reset.
2339  **/
2340 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2341 {
2342         s32 ret_val = E1000_SUCCESS;
2343         u16 phy_data;
2344
2345         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2346
2347         if (hw->mac.type != e1000_pchlan)
2348                 return E1000_SUCCESS;
2349
2350         /* Set MDIO slow mode before any other MDIO access */
2351         if (hw->phy.type == e1000_phy_82577) {
2352                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2353                 if (ret_val)
2354                         return ret_val;
2355         }
2356
2357         if (((hw->phy.type == e1000_phy_82577) &&
2358              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2359             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2360                 /* Disable generation of early preamble */
2361                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2362                 if (ret_val)
2363                         return ret_val;
2364
2365                 /* Preamble tuning for SSC */
2366                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2367                                                 0xA204);
2368                 if (ret_val)
2369                         return ret_val;
2370         }
2371
2372         if (hw->phy.type == e1000_phy_82578) {
2373                 /* Return registers to default by doing a soft reset then
2374                  * writing 0x3140 to the control register.
2375                  */
2376                 if (hw->phy.revision < 2) {
2377                         e1000_phy_sw_reset_generic(hw);
2378                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2379                                                         0x3140);
2380                 }
2381         }
2382
2383         /* Select page 0 */
2384         ret_val = hw->phy.ops.acquire(hw);
2385         if (ret_val)
2386                 return ret_val;
2387
2388         hw->phy.addr = 1;
2389         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2390         hw->phy.ops.release(hw);
2391         if (ret_val)
2392                 return ret_val;
2393
2394         /* Configure the K1 Si workaround during phy reset assuming there is
2395          * link so that it disables K1 if link is in 1Gbps.
2396          */
2397         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2398         if (ret_val)
2399                 return ret_val;
2400
2401         /* Workaround for link disconnects on a busy hub in half duplex */
2402         ret_val = hw->phy.ops.acquire(hw);
2403         if (ret_val)
2404                 return ret_val;
2405         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2406         if (ret_val)
2407                 goto release;
2408         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2409                                                phy_data & 0x00FF);
2410         if (ret_val)
2411                 goto release;
2412
2413         /* set MSE higher to enable link to stay up when noise is high */
2414         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2415 release:
2416         hw->phy.ops.release(hw);
2417
2418         return ret_val;
2419 }
2420
2421 /**
2422  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2423  *  @hw:   pointer to the HW structure
2424  **/
2425 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2426 {
2427         u32 mac_reg;
2428         u16 i, phy_reg = 0;
2429         s32 ret_val;
2430
2431         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2432
2433         ret_val = hw->phy.ops.acquire(hw);
2434         if (ret_val)
2435                 return;
2436         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2437         if (ret_val)
2438                 goto release;
2439
2440         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2441         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2442                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2443                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2444                                            (u16)(mac_reg & 0xFFFF));
2445                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2446                                            (u16)((mac_reg >> 16) & 0xFFFF));
2447
2448                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2449                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2450                                            (u16)(mac_reg & 0xFFFF));
2451                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2452                                            (u16)((mac_reg & E1000_RAH_AV)
2453                                                  >> 16));
2454         }
2455
2456         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2457
2458 release:
2459         hw->phy.ops.release(hw);
2460 }
2461
2462 #ifndef CRC32_OS_SUPPORT
2463 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2464 {
2465         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2466         u32 i, j, mask, crc;
2467
2468         DEBUGFUNC("e1000_calc_rx_da_crc");
2469
2470         crc = 0xffffffff;
2471         for (i = 0; i < 6; i++) {
2472                 crc = crc ^ mac[i];
2473                 for (j = 8; j > 0; j--) {
2474                         mask = (crc & 1) * (-1);
2475                         crc = (crc >> 1) ^ (poly & mask);
2476                 }
2477         }
2478         return ~crc;
2479 }
2480
2481 #endif /* CRC32_OS_SUPPORT */
2482 /**
2483  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2484  *  with 82579 PHY
2485  *  @hw: pointer to the HW structure
2486  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2487  **/
2488 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2489 {
2490         s32 ret_val = E1000_SUCCESS;
2491         u16 phy_reg, data;
2492         u32 mac_reg;
2493         u16 i;
2494
2495         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2496
2497         if (hw->mac.type < e1000_pch2lan)
2498                 return E1000_SUCCESS;
2499
2500         /* disable Rx path while enabling/disabling workaround */
2501         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2502         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2503                                         phy_reg | (1 << 14));
2504         if (ret_val)
2505                 return ret_val;
2506
2507         if (enable) {
2508                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2509                  * SHRAL/H) and initial CRC values to the MAC
2510                  */
2511                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2512                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2513                         u32 addr_high, addr_low;
2514
2515                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2516                         if (!(addr_high & E1000_RAH_AV))
2517                                 continue;
2518                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2519                         mac_addr[0] = (addr_low & 0xFF);
2520                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2521                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2522                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2523                         mac_addr[4] = (addr_high & 0xFF);
2524                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2525
2526 #ifndef CRC32_OS_SUPPORT
2527                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2528                                         e1000_calc_rx_da_crc(mac_addr));
2529 #else /* CRC32_OS_SUPPORT */
2530                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2531                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2532 #endif /* CRC32_OS_SUPPORT */
2533                 }
2534
2535                 /* Write Rx addresses to the PHY */
2536                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2537
2538                 /* Enable jumbo frame workaround in the MAC */
2539                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2540                 mac_reg &= ~(1 << 14);
2541                 mac_reg |= (7 << 15);
2542                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2543
2544                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2545                 mac_reg |= E1000_RCTL_SECRC;
2546                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2547
2548                 ret_val = e1000_read_kmrn_reg_generic(hw,
2549                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2550                                                 &data);
2551                 if (ret_val)
2552                         return ret_val;
2553                 ret_val = e1000_write_kmrn_reg_generic(hw,
2554                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2555                                                 data | (1 << 0));
2556                 if (ret_val)
2557                         return ret_val;
2558                 ret_val = e1000_read_kmrn_reg_generic(hw,
2559                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2560                                                 &data);
2561                 if (ret_val)
2562                         return ret_val;
2563                 data &= ~(0xF << 8);
2564                 data |= (0xB << 8);
2565                 ret_val = e1000_write_kmrn_reg_generic(hw,
2566                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2567                                                 data);
2568                 if (ret_val)
2569                         return ret_val;
2570
2571                 /* Enable jumbo frame workaround in the PHY */
2572                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2573                 data &= ~(0x7F << 5);
2574                 data |= (0x37 << 5);
2575                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2576                 if (ret_val)
2577                         return ret_val;
2578                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2579                 data &= ~(1 << 13);
2580                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2581                 if (ret_val)
2582                         return ret_val;
2583                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2584                 data &= ~(0x3FF << 2);
2585                 data |= (0x1A << 2);
2586                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2587                 if (ret_val)
2588                         return ret_val;
2589                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2590                 if (ret_val)
2591                         return ret_val;
2592                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2593                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2594                                                 (1 << 10));
2595                 if (ret_val)
2596                         return ret_val;
2597         } else {
2598                 /* Write MAC register values back to h/w defaults */
2599                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2600                 mac_reg &= ~(0xF << 14);
2601                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2602
2603                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2604                 mac_reg &= ~E1000_RCTL_SECRC;
2605                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2606
2607                 ret_val = e1000_read_kmrn_reg_generic(hw,
2608                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2609                                                 &data);
2610                 if (ret_val)
2611                         return ret_val;
2612                 ret_val = e1000_write_kmrn_reg_generic(hw,
2613                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2614                                                 data & ~(1 << 0));
2615                 if (ret_val)
2616                         return ret_val;
2617                 ret_val = e1000_read_kmrn_reg_generic(hw,
2618                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2619                                                 &data);
2620                 if (ret_val)
2621                         return ret_val;
2622                 data &= ~(0xF << 8);
2623                 data |= (0xB << 8);
2624                 ret_val = e1000_write_kmrn_reg_generic(hw,
2625                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2626                                                 data);
2627                 if (ret_val)
2628                         return ret_val;
2629
2630                 /* Write PHY register values back to h/w defaults */
2631                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2632                 data &= ~(0x7F << 5);
2633                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2634                 if (ret_val)
2635                         return ret_val;
2636                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2637                 data |= (1 << 13);
2638                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2639                 if (ret_val)
2640                         return ret_val;
2641                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2642                 data &= ~(0x3FF << 2);
2643                 data |= (0x8 << 2);
2644                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2645                 if (ret_val)
2646                         return ret_val;
2647                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2648                 if (ret_val)
2649                         return ret_val;
2650                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2651                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2652                                                 ~(1 << 10));
2653                 if (ret_val)
2654                         return ret_val;
2655         }
2656
2657         /* re-enable Rx path after enabling/disabling workaround */
2658         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2659                                      ~(1 << 14));
2660 }
2661
2662 /**
2663  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2664  *  done after every PHY reset.
2665  **/
2666 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2667 {
2668         s32 ret_val = E1000_SUCCESS;
2669
2670         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2671
2672         if (hw->mac.type != e1000_pch2lan)
2673                 return E1000_SUCCESS;
2674
2675         /* Set MDIO slow mode before any other MDIO access */
2676         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2677         if (ret_val)
2678                 return ret_val;
2679
2680         ret_val = hw->phy.ops.acquire(hw);
2681         if (ret_val)
2682                 return ret_val;
2683         /* set MSE higher to enable link to stay up when noise is high */
2684         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2685         if (ret_val)
2686                 goto release;
2687         /* drop link after 5 times MSE threshold was reached */
2688         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2689 release:
2690         hw->phy.ops.release(hw);
2691
2692         return ret_val;
2693 }
2694
2695 /**
2696  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2697  *  @hw:   pointer to the HW structure
2698  *
2699  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2700  *  Disable K1 for 1000 and 100 speeds
2701  **/
2702 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2703 {
2704         s32 ret_val = E1000_SUCCESS;
2705         u16 status_reg = 0;
2706
2707         DEBUGFUNC("e1000_k1_workaround_lv");
2708
2709         if (hw->mac.type != e1000_pch2lan)
2710                 return E1000_SUCCESS;
2711
2712         /* Set K1 beacon duration based on 10Mbs speed */
2713         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2714         if (ret_val)
2715                 return ret_val;
2716
2717         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2718             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2719                 if (status_reg &
2720                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2721                         u16 pm_phy_reg;
2722
2723                         /* LV 1G/100 Packet drop issue wa  */
2724                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2725                                                        &pm_phy_reg);
2726                         if (ret_val)
2727                                 return ret_val;
2728                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2729                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2730                                                         pm_phy_reg);
2731                         if (ret_val)
2732                                 return ret_val;
2733                 } else {
2734                         u32 mac_reg;
2735                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2736                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2737                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2738                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2739                 }
2740         }
2741
2742         return ret_val;
2743 }
2744
2745 /**
2746  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2747  *  @hw:   pointer to the HW structure
2748  *  @gate: boolean set to true to gate, false to ungate
2749  *
2750  *  Gate/ungate the automatic PHY configuration via hardware; perform
2751  *  the configuration via software instead.
2752  **/
2753 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2754 {
2755         u32 extcnf_ctrl;
2756
2757         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2758
2759         if (hw->mac.type < e1000_pch2lan)
2760                 return;
2761
2762         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2763
2764         if (gate)
2765                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2766         else
2767                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2768
2769         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2770 }
2771
2772 /**
2773  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2774  *  @hw: pointer to the HW structure
2775  *
2776  *  Check the appropriate indication the MAC has finished configuring the
2777  *  PHY after a software reset.
2778  **/
2779 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2780 {
2781         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2782
2783         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2784
2785         /* Wait for basic configuration completes before proceeding */
2786         do {
2787                 data = E1000_READ_REG(hw, E1000_STATUS);
2788                 data &= E1000_STATUS_LAN_INIT_DONE;
2789                 usec_delay(100);
2790         } while ((!data) && --loop);
2791
2792         /* If basic configuration is incomplete before the above loop
2793          * count reaches 0, loading the configuration from NVM will
2794          * leave the PHY in a bad state possibly resulting in no link.
2795          */
2796         if (loop == 0)
2797                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2798
2799         /* Clear the Init Done bit for the next init event */
2800         data = E1000_READ_REG(hw, E1000_STATUS);
2801         data &= ~E1000_STATUS_LAN_INIT_DONE;
2802         E1000_WRITE_REG(hw, E1000_STATUS, data);
2803 }
2804
2805 /**
2806  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2807  *  @hw: pointer to the HW structure
2808  **/
2809 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2810 {
2811         s32 ret_val = E1000_SUCCESS;
2812         u16 reg;
2813
2814         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2815
2816         if (hw->phy.ops.check_reset_block(hw))
2817                 return E1000_SUCCESS;
2818
2819         /* Allow time for h/w to get to quiescent state after reset */
2820         msec_delay(10);
2821
2822         /* Perform any necessary post-reset workarounds */
2823         switch (hw->mac.type) {
2824         case e1000_pchlan:
2825                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2826                 if (ret_val)
2827                         return ret_val;
2828                 break;
2829         case e1000_pch2lan:
2830                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2831                 if (ret_val)
2832                         return ret_val;
2833                 break;
2834         default:
2835                 break;
2836         }
2837
2838         /* Clear the host wakeup bit after lcd reset */
2839         if (hw->mac.type >= e1000_pchlan) {
2840                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2841                 reg &= ~BM_WUC_HOST_WU_BIT;
2842                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2843         }
2844
2845         /* Configure the LCD with the extended configuration region in NVM */
2846         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2847         if (ret_val)
2848                 return ret_val;
2849
2850         /* Configure the LCD with the OEM bits in NVM */
2851         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2852
2853         if (hw->mac.type == e1000_pch2lan) {
2854                 /* Ungate automatic PHY configuration on non-managed 82579 */
2855                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2856                     E1000_ICH_FWSM_FW_VALID)) {
2857                         msec_delay(10);
2858                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2859                 }
2860
2861                 /* Set EEE LPI Update Timer to 200usec */
2862                 ret_val = hw->phy.ops.acquire(hw);
2863                 if (ret_val)
2864                         return ret_val;
2865                 ret_val = e1000_write_emi_reg_locked(hw,
2866                                                      I82579_LPI_UPDATE_TIMER,
2867                                                      0x1387);
2868                 hw->phy.ops.release(hw);
2869         }
2870
2871         return ret_val;
2872 }
2873
2874 /**
2875  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2876  *  @hw: pointer to the HW structure
2877  *
2878  *  Resets the PHY
2879  *  This is a function pointer entry point called by drivers
2880  *  or other shared routines.
2881  **/
2882 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2883 {
2884         s32 ret_val = E1000_SUCCESS;
2885
2886         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2887
2888         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2889         if ((hw->mac.type == e1000_pch2lan) &&
2890             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2891                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2892
2893         ret_val = e1000_phy_hw_reset_generic(hw);
2894         if (ret_val)
2895                 return ret_val;
2896
2897         return e1000_post_phy_reset_ich8lan(hw);
2898 }
2899
2900 /**
2901  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2902  *  @hw: pointer to the HW structure
2903  *  @active: true to enable LPLU, false to disable
2904  *
2905  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2906  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2907  *  the phy speed. This function will manually set the LPLU bit and restart
2908  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2909  *  since it configures the same bit.
2910  **/
2911 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2912 {
2913         s32 ret_val;
2914         u16 oem_reg;
2915
2916         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2917
2918         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2919         if (ret_val)
2920                 return ret_val;
2921
2922         if (active)
2923                 oem_reg |= HV_OEM_BITS_LPLU;
2924         else
2925                 oem_reg &= ~HV_OEM_BITS_LPLU;
2926
2927         if (!hw->phy.ops.check_reset_block(hw))
2928                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2929
2930         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2931 }
2932
2933 /**
2934  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2935  *  @hw: pointer to the HW structure
2936  *  @active: true to enable LPLU, false to disable
2937  *
2938  *  Sets the LPLU D0 state according to the active flag.  When
2939  *  activating LPLU this function also disables smart speed
2940  *  and vice versa.  LPLU will not be activated unless the
2941  *  device autonegotiation advertisement meets standards of
2942  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2943  *  This is a function pointer entry point only called by
2944  *  PHY setup routines.
2945  **/
2946 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2947 {
2948         struct e1000_phy_info *phy = &hw->phy;
2949         u32 phy_ctrl;
2950         s32 ret_val = E1000_SUCCESS;
2951         u16 data;
2952
2953         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
2954
2955         if (phy->type == e1000_phy_ife)
2956                 return E1000_SUCCESS;
2957
2958         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2959
2960         if (active) {
2961                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2962                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2963
2964                 if (phy->type != e1000_phy_igp_3)
2965                         return E1000_SUCCESS;
2966
2967                 /* Call gig speed drop workaround on LPLU before accessing
2968                  * any PHY registers
2969                  */
2970                 if (hw->mac.type == e1000_ich8lan)
2971                         e1000_gig_downshift_workaround_ich8lan(hw);
2972
2973                 /* When LPLU is enabled, we should disable SmartSpeed */
2974                 ret_val = phy->ops.read_reg(hw,
2975                                             IGP01E1000_PHY_PORT_CONFIG,
2976                                             &data);
2977                 if (ret_val)
2978                         return ret_val;
2979                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2980                 ret_val = phy->ops.write_reg(hw,
2981                                              IGP01E1000_PHY_PORT_CONFIG,
2982                                              data);
2983                 if (ret_val)
2984                         return ret_val;
2985         } else {
2986                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2987                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2988
2989                 if (phy->type != e1000_phy_igp_3)
2990                         return E1000_SUCCESS;
2991
2992                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2993                  * during Dx states where the power conservation is most
2994                  * important.  During driver activity we should enable
2995                  * SmartSpeed, so performance is maintained.
2996                  */
2997                 if (phy->smart_speed == e1000_smart_speed_on) {
2998                         ret_val = phy->ops.read_reg(hw,
2999                                                     IGP01E1000_PHY_PORT_CONFIG,
3000                                                     &data);
3001                         if (ret_val)
3002                                 return ret_val;
3003
3004                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3005                         ret_val = phy->ops.write_reg(hw,
3006                                                      IGP01E1000_PHY_PORT_CONFIG,
3007                                                      data);
3008                         if (ret_val)
3009                                 return ret_val;
3010                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3011                         ret_val = phy->ops.read_reg(hw,
3012                                                     IGP01E1000_PHY_PORT_CONFIG,
3013                                                     &data);
3014                         if (ret_val)
3015                                 return ret_val;
3016
3017                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3018                         ret_val = phy->ops.write_reg(hw,
3019                                                      IGP01E1000_PHY_PORT_CONFIG,
3020                                                      data);
3021                         if (ret_val)
3022                                 return ret_val;
3023                 }
3024         }
3025
3026         return E1000_SUCCESS;
3027 }
3028
3029 /**
3030  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3031  *  @hw: pointer to the HW structure
3032  *  @active: true to enable LPLU, false to disable
3033  *
3034  *  Sets the LPLU D3 state according to the active flag.  When
3035  *  activating LPLU this function also disables smart speed
3036  *  and vice versa.  LPLU will not be activated unless the
3037  *  device autonegotiation advertisement meets standards of
3038  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3039  *  This is a function pointer entry point only called by
3040  *  PHY setup routines.
3041  **/
3042 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3043 {
3044         struct e1000_phy_info *phy = &hw->phy;
3045         u32 phy_ctrl;
3046         s32 ret_val = E1000_SUCCESS;
3047         u16 data;
3048
3049         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3050
3051         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3052
3053         if (!active) {
3054                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3055                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3056
3057                 if (phy->type != e1000_phy_igp_3)
3058                         return E1000_SUCCESS;
3059
3060                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3061                  * during Dx states where the power conservation is most
3062                  * important.  During driver activity we should enable
3063                  * SmartSpeed, so performance is maintained.
3064                  */
3065                 if (phy->smart_speed == e1000_smart_speed_on) {
3066                         ret_val = phy->ops.read_reg(hw,
3067                                                     IGP01E1000_PHY_PORT_CONFIG,
3068                                                     &data);
3069                         if (ret_val)
3070                                 return ret_val;
3071
3072                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3073                         ret_val = phy->ops.write_reg(hw,
3074                                                      IGP01E1000_PHY_PORT_CONFIG,
3075                                                      data);
3076                         if (ret_val)
3077                                 return ret_val;
3078                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3079                         ret_val = phy->ops.read_reg(hw,
3080                                                     IGP01E1000_PHY_PORT_CONFIG,
3081                                                     &data);
3082                         if (ret_val)
3083                                 return ret_val;
3084
3085                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3086                         ret_val = phy->ops.write_reg(hw,
3087                                                      IGP01E1000_PHY_PORT_CONFIG,
3088                                                      data);
3089                         if (ret_val)
3090                                 return ret_val;
3091                 }
3092         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3093                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3094                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3095                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3096                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3097
3098                 if (phy->type != e1000_phy_igp_3)
3099                         return E1000_SUCCESS;
3100
3101                 /* Call gig speed drop workaround on LPLU before accessing
3102                  * any PHY registers
3103                  */
3104                 if (hw->mac.type == e1000_ich8lan)
3105                         e1000_gig_downshift_workaround_ich8lan(hw);
3106
3107                 /* When LPLU is enabled, we should disable SmartSpeed */
3108                 ret_val = phy->ops.read_reg(hw,
3109                                             IGP01E1000_PHY_PORT_CONFIG,
3110                                             &data);
3111                 if (ret_val)
3112                         return ret_val;
3113
3114                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3115                 ret_val = phy->ops.write_reg(hw,
3116                                              IGP01E1000_PHY_PORT_CONFIG,
3117                                              data);
3118         }
3119
3120         return ret_val;
3121 }
3122
3123 /**
3124  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3125  *  @hw: pointer to the HW structure
3126  *  @bank:  pointer to the variable that returns the active bank
3127  *
3128  *  Reads signature byte from the NVM using the flash access registers.
3129  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3130  **/
3131 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3132 {
3133         u32 eecd;
3134         struct e1000_nvm_info *nvm = &hw->nvm;
3135         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3136         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3137         u8 sig_byte = 0;
3138         s32 ret_val;
3139
3140         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3141
3142         switch (hw->mac.type) {
3143         case e1000_ich8lan:
3144         case e1000_ich9lan:
3145                 eecd = E1000_READ_REG(hw, E1000_EECD);
3146                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3147                     E1000_EECD_SEC1VAL_VALID_MASK) {
3148                         if (eecd & E1000_EECD_SEC1VAL)
3149                                 *bank = 1;
3150                         else
3151                                 *bank = 0;
3152
3153                         return E1000_SUCCESS;
3154                 }
3155                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3156                 /* fall-thru */
3157         default:
3158                 /* set bank to 0 in case flash read fails */
3159                 *bank = 0;
3160
3161                 /* Check bank 0 */
3162                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3163                                                         &sig_byte);
3164                 if (ret_val)
3165                         return ret_val;
3166                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3167                     E1000_ICH_NVM_SIG_VALUE) {
3168                         *bank = 0;
3169                         return E1000_SUCCESS;
3170                 }
3171
3172                 /* Check bank 1 */
3173                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3174                                                         bank1_offset,
3175                                                         &sig_byte);
3176                 if (ret_val)
3177                         return ret_val;
3178                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3179                     E1000_ICH_NVM_SIG_VALUE) {
3180                         *bank = 1;
3181                         return E1000_SUCCESS;
3182                 }
3183
3184                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3185                 return -E1000_ERR_NVM;
3186         }
3187 }
3188
3189 /**
3190  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3191  *  @hw: pointer to the HW structure
3192  *  @offset: The offset (in bytes) of the word(s) to read.
3193  *  @words: Size of data to read in words
3194  *  @data: Pointer to the word(s) to read at offset.
3195  *
3196  *  Reads a word(s) from the NVM using the flash access registers.
3197  **/
3198 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3199                                   u16 *data)
3200 {
3201         struct e1000_nvm_info *nvm = &hw->nvm;
3202         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3203         u32 act_offset;
3204         s32 ret_val = E1000_SUCCESS;
3205         u32 bank = 0;
3206         u16 i, word;
3207
3208         DEBUGFUNC("e1000_read_nvm_ich8lan");
3209
3210         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3211             (words == 0)) {
3212                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3213                 ret_val = -E1000_ERR_NVM;
3214                 goto out;
3215         }
3216
3217         nvm->ops.acquire(hw);
3218
3219         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3220         if (ret_val != E1000_SUCCESS) {
3221                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3222                 bank = 0;
3223         }
3224
3225         act_offset = (bank) ? nvm->flash_bank_size : 0;
3226         act_offset += offset;
3227
3228         ret_val = E1000_SUCCESS;
3229         for (i = 0; i < words; i++) {
3230                 if (dev_spec->shadow_ram[offset+i].modified) {
3231                         data[i] = dev_spec->shadow_ram[offset+i].value;
3232                 } else {
3233                         ret_val = e1000_read_flash_word_ich8lan(hw,
3234                                                                 act_offset + i,
3235                                                                 &word);
3236                         if (ret_val)
3237                                 break;
3238                         data[i] = word;
3239                 }
3240         }
3241
3242         nvm->ops.release(hw);
3243
3244 out:
3245         if (ret_val)
3246                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3247
3248         return ret_val;
3249 }
3250
3251 /**
3252  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3253  *  @hw: pointer to the HW structure
3254  *
3255  *  This function does initial flash setup so that a new read/write/erase cycle
3256  *  can be started.
3257  **/
3258 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3259 {
3260         union ich8_hws_flash_status hsfsts;
3261         s32 ret_val = -E1000_ERR_NVM;
3262
3263         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3264
3265         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3266
3267         /* Check if the flash descriptor is valid */
3268         if (!hsfsts.hsf_status.fldesvalid) {
3269                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3270                 return -E1000_ERR_NVM;
3271         }
3272
3273         /* Clear FCERR and DAEL in hw status by writing 1 */
3274         hsfsts.hsf_status.flcerr = 1;
3275         hsfsts.hsf_status.dael = 1;
3276         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3277
3278         /* Either we should have a hardware SPI cycle in progress
3279          * bit to check against, in order to start a new cycle or
3280          * FDONE bit should be changed in the hardware so that it
3281          * is 1 after hardware reset, which can then be used as an
3282          * indication whether a cycle is in progress or has been
3283          * completed.
3284          */
3285
3286         if (!hsfsts.hsf_status.flcinprog) {
3287                 /* There is no cycle running at present,
3288                  * so we can start a cycle.
3289                  * Begin by setting Flash Cycle Done.
3290                  */
3291                 hsfsts.hsf_status.flcdone = 1;
3292                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3293                 ret_val = E1000_SUCCESS;
3294         } else {
3295                 s32 i;
3296
3297                 /* Otherwise poll for sometime so the current
3298                  * cycle has a chance to end before giving up.
3299                  */
3300                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3301                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3302                                                               ICH_FLASH_HSFSTS);
3303                         if (!hsfsts.hsf_status.flcinprog) {
3304                                 ret_val = E1000_SUCCESS;
3305                                 break;
3306                         }
3307                         usec_delay(1);
3308                 }
3309                 if (ret_val == E1000_SUCCESS) {
3310                         /* Successful in waiting for previous cycle to timeout,
3311                          * now set the Flash Cycle Done.
3312                          */
3313                         hsfsts.hsf_status.flcdone = 1;
3314                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3315                                                 hsfsts.regval);
3316                 } else {
3317                         DEBUGOUT("Flash controller busy, cannot get access\n");
3318                 }
3319         }
3320
3321         return ret_val;
3322 }
3323
3324 /**
3325  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3326  *  @hw: pointer to the HW structure
3327  *  @timeout: maximum time to wait for completion
3328  *
3329  *  This function starts a flash cycle and waits for its completion.
3330  **/
3331 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3332 {
3333         union ich8_hws_flash_ctrl hsflctl;
3334         union ich8_hws_flash_status hsfsts;
3335         u32 i = 0;
3336
3337         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3338
3339         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3340         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3341         hsflctl.hsf_ctrl.flcgo = 1;
3342
3343         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3344
3345         /* wait till FDONE bit is set to 1 */
3346         do {
3347                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3348                 if (hsfsts.hsf_status.flcdone)
3349                         break;
3350                 usec_delay(1);
3351         } while (i++ < timeout);
3352
3353         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3354                 return E1000_SUCCESS;
3355
3356         return -E1000_ERR_NVM;
3357 }
3358
3359 /**
3360  *  e1000_read_flash_word_ich8lan - Read word from flash
3361  *  @hw: pointer to the HW structure
3362  *  @offset: offset to data location
3363  *  @data: pointer to the location for storing the data
3364  *
3365  *  Reads the flash word at offset into data.  Offset is converted
3366  *  to bytes before read.
3367  **/
3368 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3369                                          u16 *data)
3370 {
3371         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3372
3373         if (!data)
3374                 return -E1000_ERR_NVM;
3375
3376         /* Must convert offset into bytes. */
3377         offset <<= 1;
3378
3379         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3380 }
3381
3382 /**
3383  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3384  *  @hw: pointer to the HW structure
3385  *  @offset: The offset of the byte to read.
3386  *  @data: Pointer to a byte to store the value read.
3387  *
3388  *  Reads a single byte from the NVM using the flash access registers.
3389  **/
3390 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3391                                          u8 *data)
3392 {
3393         s32 ret_val;
3394         u16 word = 0;
3395
3396         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3397
3398         if (ret_val)
3399                 return ret_val;
3400
3401         *data = (u8)word;
3402
3403         return E1000_SUCCESS;
3404 }
3405
3406 /**
3407  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3408  *  @hw: pointer to the HW structure
3409  *  @offset: The offset (in bytes) of the byte or word to read.
3410  *  @size: Size of data to read, 1=byte 2=word
3411  *  @data: Pointer to the word to store the value read.
3412  *
3413  *  Reads a byte or word from the NVM using the flash access registers.
3414  **/
3415 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3416                                          u8 size, u16 *data)
3417 {
3418         union ich8_hws_flash_status hsfsts;
3419         union ich8_hws_flash_ctrl hsflctl;
3420         u32 flash_linear_addr;
3421         u32 flash_data = 0;
3422         s32 ret_val = -E1000_ERR_NVM;
3423         u8 count = 0;
3424
3425         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3426
3427         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3428                 return -E1000_ERR_NVM;
3429         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3430                              hw->nvm.flash_base_addr);
3431
3432         do {
3433                 usec_delay(1);
3434                 /* Steps */
3435                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3436                 if (ret_val != E1000_SUCCESS)
3437                         break;
3438                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3439
3440                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3441                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3442                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3443                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3444
3445                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3446
3447                 ret_val =
3448                     e1000_flash_cycle_ich8lan(hw,
3449                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3450
3451                 /* Check if FCERR is set to 1, if set to 1, clear it
3452                  * and try the whole sequence a few more times, else
3453                  * read in (shift in) the Flash Data0, the order is
3454                  * least significant byte first msb to lsb
3455                  */
3456                 if (ret_val == E1000_SUCCESS) {
3457                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3458                         if (size == 1)
3459                                 *data = (u8)(flash_data & 0x000000FF);
3460                         else if (size == 2)
3461                                 *data = (u16)(flash_data & 0x0000FFFF);
3462                         break;
3463                 } else {
3464                         /* If we've gotten here, then things are probably
3465                          * completely hosed, but if the error condition is
3466                          * detected, it won't hurt to give it another try...
3467                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3468                          */
3469                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3470                                                               ICH_FLASH_HSFSTS);
3471                         if (hsfsts.hsf_status.flcerr) {
3472                                 /* Repeat for some time before giving up. */
3473                                 continue;
3474                         } else if (!hsfsts.hsf_status.flcdone) {
3475                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3476                                 break;
3477                         }
3478                 }
3479         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3480
3481         return ret_val;
3482 }
3483
3484 /**
3485  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3486  *  @hw: pointer to the HW structure
3487  *  @offset: The offset (in bytes) of the word(s) to write.
3488  *  @words: Size of data to write in words
3489  *  @data: Pointer to the word(s) to write at offset.
3490  *
3491  *  Writes a byte or word to the NVM using the flash access registers.
3492  **/
3493 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3494                                    u16 *data)
3495 {
3496         struct e1000_nvm_info *nvm = &hw->nvm;
3497         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3498         u16 i;
3499
3500         DEBUGFUNC("e1000_write_nvm_ich8lan");
3501
3502         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3503             (words == 0)) {
3504                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3505                 return -E1000_ERR_NVM;
3506         }
3507
3508         nvm->ops.acquire(hw);
3509
3510         for (i = 0; i < words; i++) {
3511                 dev_spec->shadow_ram[offset+i].modified = true;
3512                 dev_spec->shadow_ram[offset+i].value = data[i];
3513         }
3514
3515         nvm->ops.release(hw);
3516
3517         return E1000_SUCCESS;
3518 }
3519
3520 /**
3521  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3522  *  @hw: pointer to the HW structure
3523  *
3524  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3525  *  which writes the checksum to the shadow ram.  The changes in the shadow
3526  *  ram are then committed to the EEPROM by processing each bank at a time
3527  *  checking for the modified bit and writing only the pending changes.
3528  *  After a successful commit, the shadow ram is cleared and is ready for
3529  *  future writes.
3530  **/
3531 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3532 {
3533         struct e1000_nvm_info *nvm = &hw->nvm;
3534         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3535         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3536         s32 ret_val;
3537         u16 data;
3538
3539         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3540
3541         ret_val = e1000_update_nvm_checksum_generic(hw);
3542         if (ret_val)
3543                 goto out;
3544
3545         if (nvm->type != e1000_nvm_flash_sw)
3546                 goto out;
3547
3548         nvm->ops.acquire(hw);
3549
3550         /* We're writing to the opposite bank so if we're on bank 1,
3551          * write to bank 0 etc.  We also need to erase the segment that
3552          * is going to be written
3553          */
3554         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3555         if (ret_val != E1000_SUCCESS) {
3556                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3557                 bank = 0;
3558         }
3559
3560         if (bank == 0) {
3561                 new_bank_offset = nvm->flash_bank_size;
3562                 old_bank_offset = 0;
3563                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3564                 if (ret_val)
3565                         goto release;
3566         } else {
3567                 old_bank_offset = nvm->flash_bank_size;
3568                 new_bank_offset = 0;
3569                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3570                 if (ret_val)
3571                         goto release;
3572         }
3573
3574         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3575                 /* Determine whether to write the value stored
3576                  * in the other NVM bank or a modified value stored
3577                  * in the shadow RAM
3578                  */
3579                 if (dev_spec->shadow_ram[i].modified) {
3580                         data = dev_spec->shadow_ram[i].value;
3581                 } else {
3582                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3583                                                                 old_bank_offset,
3584                                                                 &data);
3585                         if (ret_val)
3586                                 break;
3587                 }
3588
3589                 /* If the word is 0x13, then make sure the signature bits
3590                  * (15:14) are 11b until the commit has completed.
3591                  * This will allow us to write 10b which indicates the
3592                  * signature is valid.  We want to do this after the write
3593                  * has completed so that we don't mark the segment valid
3594                  * while the write is still in progress
3595                  */
3596                 if (i == E1000_ICH_NVM_SIG_WORD)
3597                         data |= E1000_ICH_NVM_SIG_MASK;
3598
3599                 /* Convert offset to bytes. */
3600                 act_offset = (i + new_bank_offset) << 1;
3601
3602                 usec_delay(100);
3603                 /* Write the bytes to the new bank. */
3604                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3605                                                                act_offset,
3606                                                                (u8)data);
3607                 if (ret_val)
3608                         break;
3609
3610                 usec_delay(100);
3611                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3612                                                           act_offset + 1,
3613                                                           (u8)(data >> 8));
3614                 if (ret_val)
3615                         break;
3616         }
3617
3618         /* Don't bother writing the segment valid bits if sector
3619          * programming failed.
3620          */
3621         if (ret_val) {
3622                 DEBUGOUT("Flash commit failed.\n");
3623                 goto release;
3624         }
3625
3626         /* Finally validate the new segment by setting bit 15:14
3627          * to 10b in word 0x13 , this can be done without an
3628          * erase as well since these bits are 11 to start with
3629          * and we need to change bit 14 to 0b
3630          */
3631         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3632         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3633         if (ret_val)
3634                 goto release;
3635
3636         data &= 0xBFFF;
3637         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3638                                                        act_offset * 2 + 1,
3639                                                        (u8)(data >> 8));
3640         if (ret_val)
3641                 goto release;
3642
3643         /* And invalidate the previously valid segment by setting
3644          * its signature word (0x13) high_byte to 0b. This can be
3645          * done without an erase because flash erase sets all bits
3646          * to 1's. We can write 1's to 0's without an erase
3647          */
3648         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3649         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3650         if (ret_val)
3651                 goto release;
3652
3653         /* Great!  Everything worked, we can now clear the cached entries. */
3654         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3655                 dev_spec->shadow_ram[i].modified = false;
3656                 dev_spec->shadow_ram[i].value = 0xFFFF;
3657         }
3658
3659 release:
3660         nvm->ops.release(hw);
3661
3662         /* Reload the EEPROM, or else modifications will not appear
3663          * until after the next adapter reset.
3664          */
3665         if (!ret_val) {
3666                 nvm->ops.reload(hw);
3667                 msec_delay(10);
3668         }
3669
3670 out:
3671         if (ret_val)
3672                 DEBUGOUT1("NVM update error: %d\n", ret_val);
3673
3674         return ret_val;
3675 }
3676
3677 /**
3678  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3679  *  @hw: pointer to the HW structure
3680  *
3681  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3682  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3683  *  calculated, in which case we need to calculate the checksum and set bit 6.
3684  **/
3685 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3686 {
3687         s32 ret_val;
3688         u16 data;
3689         u16 word;
3690         u16 valid_csum_mask;
3691
3692         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3693
3694         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3695          * the checksum needs to be fixed.  This bit is an indication that
3696          * the NVM was prepared by OEM software and did not calculate
3697          * the checksum...a likely scenario.
3698          */
3699         switch (hw->mac.type) {
3700         case e1000_pch_lpt:
3701                 word = NVM_COMPAT;
3702                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3703                 break;
3704         default:
3705                 word = NVM_FUTURE_INIT_WORD1;
3706                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3707                 break;
3708         }
3709
3710         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3711         if (ret_val)
3712                 return ret_val;
3713
3714         if (!(data & valid_csum_mask)) {
3715                 data |= valid_csum_mask;
3716                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3717                 if (ret_val)
3718                         return ret_val;
3719                 ret_val = hw->nvm.ops.update(hw);
3720                 if (ret_val)
3721                         return ret_val;
3722         }
3723
3724         return e1000_validate_nvm_checksum_generic(hw);
3725 }
3726
3727 /**
3728  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3729  *  @hw: pointer to the HW structure
3730  *  @offset: The offset (in bytes) of the byte/word to read.
3731  *  @size: Size of data to read, 1=byte 2=word
3732  *  @data: The byte(s) to write to the NVM.
3733  *
3734  *  Writes one/two bytes to the NVM using the flash access registers.
3735  **/
3736 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3737                                           u8 size, u16 data)
3738 {
3739         union ich8_hws_flash_status hsfsts;
3740         union ich8_hws_flash_ctrl hsflctl;
3741         u32 flash_linear_addr;
3742         u32 flash_data = 0;
3743         s32 ret_val;
3744         u8 count = 0;
3745
3746         DEBUGFUNC("e1000_write_ich8_data");
3747
3748         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3749                 return -E1000_ERR_NVM;
3750
3751         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3752                              hw->nvm.flash_base_addr);
3753
3754         do {
3755                 usec_delay(1);
3756                 /* Steps */
3757                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3758                 if (ret_val != E1000_SUCCESS)
3759                         break;
3760                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3761
3762                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3763                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3764                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3765                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3766
3767                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3768
3769                 if (size == 1)
3770                         flash_data = (u32)data & 0x00FF;
3771                 else
3772                         flash_data = (u32)data;
3773
3774                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3775
3776                 /* check if FCERR is set to 1 , if set to 1, clear it
3777                  * and try the whole sequence a few more times else done
3778                  */
3779                 ret_val =
3780                     e1000_flash_cycle_ich8lan(hw,
3781                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3782                 if (ret_val == E1000_SUCCESS)
3783                         break;
3784
3785                 /* If we're here, then things are most likely
3786                  * completely hosed, but if the error condition
3787                  * is detected, it won't hurt to give it another
3788                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3789                  */
3790                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3791                 if (hsfsts.hsf_status.flcerr)
3792                         /* Repeat for some time before giving up. */
3793                         continue;
3794                 if (!hsfsts.hsf_status.flcdone) {
3795                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3796                         break;
3797                 }
3798         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3799
3800         return ret_val;
3801 }
3802
3803 /**
3804  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3805  *  @hw: pointer to the HW structure
3806  *  @offset: The index of the byte to read.
3807  *  @data: The byte to write to the NVM.
3808  *
3809  *  Writes a single byte to the NVM using the flash access registers.
3810  **/
3811 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3812                                           u8 data)
3813 {
3814         u16 word = (u16)data;
3815
3816         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3817
3818         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3819 }
3820
3821 /**
3822  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3823  *  @hw: pointer to the HW structure
3824  *  @offset: The offset of the byte to write.
3825  *  @byte: The byte to write to the NVM.
3826  *
3827  *  Writes a single byte to the NVM using the flash access registers.
3828  *  Goes through a retry algorithm before giving up.
3829  **/
3830 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3831                                                 u32 offset, u8 byte)
3832 {
3833         s32 ret_val;
3834         u16 program_retries;
3835
3836         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3837
3838         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3839         if (!ret_val)
3840                 return ret_val;
3841
3842         for (program_retries = 0; program_retries < 100; program_retries++) {
3843                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3844                 usec_delay(100);
3845                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3846                 if (ret_val == E1000_SUCCESS)
3847                         break;
3848         }
3849         if (program_retries == 100)
3850                 return -E1000_ERR_NVM;
3851
3852         return E1000_SUCCESS;
3853 }
3854
3855 /**
3856  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3857  *  @hw: pointer to the HW structure
3858  *  @bank: 0 for first bank, 1 for second bank, etc.
3859  *
3860  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3861  *  bank N is 4096 * N + flash_reg_addr.
3862  **/
3863 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3864 {
3865         struct e1000_nvm_info *nvm = &hw->nvm;
3866         union ich8_hws_flash_status hsfsts;
3867         union ich8_hws_flash_ctrl hsflctl;
3868         u32 flash_linear_addr;
3869         /* bank size is in 16bit words - adjust to bytes */
3870         u32 flash_bank_size = nvm->flash_bank_size * 2;
3871         s32 ret_val;
3872         s32 count = 0;
3873         s32 j, iteration, sector_size;
3874
3875         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3876
3877         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3878
3879         /* Determine HW Sector size: Read BERASE bits of hw flash status
3880          * register
3881          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3882          *     consecutive sectors.  The start index for the nth Hw sector
3883          *     can be calculated as = bank * 4096 + n * 256
3884          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3885          *     The start index for the nth Hw sector can be calculated
3886          *     as = bank * 4096
3887          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3888          *     (ich9 only, otherwise error condition)
3889          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3890          */
3891         switch (hsfsts.hsf_status.berasesz) {
3892         case 0:
3893                 /* Hw sector size 256 */
3894                 sector_size = ICH_FLASH_SEG_SIZE_256;
3895                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3896                 break;
3897         case 1:
3898                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3899                 iteration = 1;
3900                 break;
3901         case 2:
3902                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3903                 iteration = 1;
3904                 break;
3905         case 3:
3906                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3907                 iteration = 1;
3908                 break;
3909         default:
3910                 return -E1000_ERR_NVM;
3911         }
3912
3913         /* Start with the base address, then add the sector offset. */
3914         flash_linear_addr = hw->nvm.flash_base_addr;
3915         flash_linear_addr += (bank) ? flash_bank_size : 0;
3916
3917         for (j = 0; j < iteration; j++) {
3918                 do {
3919                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3920
3921                         /* Steps */
3922                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3923                         if (ret_val)
3924                                 return ret_val;
3925
3926                         /* Write a value 11 (block Erase) in Flash
3927                          * Cycle field in hw flash control
3928                          */
3929                         hsflctl.regval =
3930                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3931
3932                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3933                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3934                                                 hsflctl.regval);
3935
3936                         /* Write the last 24 bits of an index within the
3937                          * block into Flash Linear address field in Flash
3938                          * Address.
3939                          */
3940                         flash_linear_addr += (j * sector_size);
3941                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3942                                               flash_linear_addr);
3943
3944                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3945                         if (ret_val == E1000_SUCCESS)
3946                                 break;
3947
3948                         /* Check if FCERR is set to 1.  If 1,
3949                          * clear it and try the whole sequence
3950                          * a few more times else Done
3951                          */
3952                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3953                                                       ICH_FLASH_HSFSTS);
3954                         if (hsfsts.hsf_status.flcerr)
3955                                 /* repeat for some time before giving up */
3956                                 continue;
3957                         else if (!hsfsts.hsf_status.flcdone)
3958                                 return ret_val;
3959                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3960         }
3961
3962         return E1000_SUCCESS;
3963 }
3964
3965 /**
3966  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3967  *  @hw: pointer to the HW structure
3968  *  @data: Pointer to the LED settings
3969  *
3970  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3971  *  settings is all 0's or F's, set the LED default to a valid LED default
3972  *  setting.
3973  **/
3974 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3975 {
3976         s32 ret_val;
3977
3978         DEBUGFUNC("e1000_valid_led_default_ich8lan");
3979
3980         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3981         if (ret_val) {
3982                 DEBUGOUT("NVM Read Error\n");
3983                 return ret_val;
3984         }
3985
3986         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3987                 *data = ID_LED_DEFAULT_ICH8LAN;
3988
3989         return E1000_SUCCESS;
3990 }
3991
3992 /**
3993  *  e1000_id_led_init_pchlan - store LED configurations
3994  *  @hw: pointer to the HW structure
3995  *
3996  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3997  *  the PHY LED configuration register.
3998  *
3999  *  PCH also does not have an "always on" or "always off" mode which
4000  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4001  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4002  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4003  *  link based on logic in e1000_led_[on|off]_pchlan().
4004  **/
4005 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4006 {
4007         struct e1000_mac_info *mac = &hw->mac;
4008         s32 ret_val;
4009         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4010         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4011         u16 data, i, temp, shift;
4012
4013         DEBUGFUNC("e1000_id_led_init_pchlan");
4014
4015         /* Get default ID LED modes */
4016         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4017         if (ret_val)
4018                 return ret_val;
4019
4020         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4021         mac->ledctl_mode1 = mac->ledctl_default;
4022         mac->ledctl_mode2 = mac->ledctl_default;
4023
4024         for (i = 0; i < 4; i++) {
4025                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4026                 shift = (i * 5);
4027                 switch (temp) {
4028                 case ID_LED_ON1_DEF2:
4029                 case ID_LED_ON1_ON2:
4030                 case ID_LED_ON1_OFF2:
4031                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4032                         mac->ledctl_mode1 |= (ledctl_on << shift);
4033                         break;
4034                 case ID_LED_OFF1_DEF2:
4035                 case ID_LED_OFF1_ON2:
4036                 case ID_LED_OFF1_OFF2:
4037                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4038                         mac->ledctl_mode1 |= (ledctl_off << shift);
4039                         break;
4040                 default:
4041                         /* Do nothing */
4042                         break;
4043                 }
4044                 switch (temp) {
4045                 case ID_LED_DEF1_ON2:
4046                 case ID_LED_ON1_ON2:
4047                 case ID_LED_OFF1_ON2:
4048                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4049                         mac->ledctl_mode2 |= (ledctl_on << shift);
4050                         break;
4051                 case ID_LED_DEF1_OFF2:
4052                 case ID_LED_ON1_OFF2:
4053                 case ID_LED_OFF1_OFF2:
4054                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4055                         mac->ledctl_mode2 |= (ledctl_off << shift);
4056                         break;
4057                 default:
4058                         /* Do nothing */
4059                         break;
4060                 }
4061         }
4062
4063         return E1000_SUCCESS;
4064 }
4065
4066 /**
4067  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4068  *  @hw: pointer to the HW structure
4069  *
4070  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4071  *  register, so the the bus width is hard coded.
4072  **/
4073 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4074 {
4075         struct e1000_bus_info *bus = &hw->bus;
4076         s32 ret_val;
4077
4078         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4079
4080         ret_val = e1000_get_bus_info_pcie_generic(hw);
4081
4082         /* ICH devices are "PCI Express"-ish.  They have
4083          * a configuration space, but do not contain
4084          * PCI Express Capability registers, so bus width
4085          * must be hardcoded.
4086          */
4087         if (bus->width == e1000_bus_width_unknown)
4088                 bus->width = e1000_bus_width_pcie_x1;
4089
4090         return ret_val;
4091 }
4092
4093 /**
4094  *  e1000_reset_hw_ich8lan - Reset the hardware
4095  *  @hw: pointer to the HW structure
4096  *
4097  *  Does a full reset of the hardware which includes a reset of the PHY and
4098  *  MAC.
4099  **/
4100 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4101 {
4102         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4103         u16 kum_cfg;
4104         u32 ctrl, reg;
4105         s32 ret_val;
4106
4107         DEBUGFUNC("e1000_reset_hw_ich8lan");
4108
4109         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4110          * on the last TLP read/write transaction when MAC is reset.
4111          */
4112         ret_val = e1000_disable_pcie_master_generic(hw);
4113         if (ret_val)
4114                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4115
4116         DEBUGOUT("Masking off all interrupts\n");
4117         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4118
4119         /* Disable the Transmit and Receive units.  Then delay to allow
4120          * any pending transactions to complete before we hit the MAC
4121          * with the global reset.
4122          */
4123         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4124         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4125         E1000_WRITE_FLUSH(hw);
4126
4127         msec_delay(10);
4128
4129         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4130         if (hw->mac.type == e1000_ich8lan) {
4131                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4132                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4133                 /* Set Packet Buffer Size to 16k. */
4134                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4135         }
4136
4137         if (hw->mac.type == e1000_pchlan) {
4138                 /* Save the NVM K1 bit setting*/
4139                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4140                 if (ret_val)
4141                         return ret_val;
4142
4143                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4144                         dev_spec->nvm_k1_enabled = true;
4145                 else
4146                         dev_spec->nvm_k1_enabled = false;
4147         }
4148
4149         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4150
4151         if (!hw->phy.ops.check_reset_block(hw)) {
4152                 /* Full-chip reset requires MAC and PHY reset at the same
4153                  * time to make sure the interface between MAC and the
4154                  * external PHY is reset.
4155                  */
4156                 ctrl |= E1000_CTRL_PHY_RST;
4157
4158                 /* Gate automatic PHY configuration by hardware on
4159                  * non-managed 82579
4160                  */
4161                 if ((hw->mac.type == e1000_pch2lan) &&
4162                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4163                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4164         }
4165         ret_val = e1000_acquire_swflag_ich8lan(hw);
4166         DEBUGOUT("Issuing a global reset to ich8lan\n");
4167         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4168         /* cannot issue a flush here because it hangs the hardware */
4169         msec_delay(20);
4170
4171         /* Set Phy Config Counter to 50msec */
4172         if (hw->mac.type == e1000_pch2lan) {
4173                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4174                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4175                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4176                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4177         }
4178
4179         if (!ret_val)
4180                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4181
4182         if (ctrl & E1000_CTRL_PHY_RST) {
4183                 ret_val = hw->phy.ops.get_cfg_done(hw);
4184                 if (ret_val)
4185                         return ret_val;
4186
4187                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4188                 if (ret_val)
4189                         return ret_val;
4190         }
4191
4192         /* For PCH, this write will make sure that any noise
4193          * will be detected as a CRC error and be dropped rather than show up
4194          * as a bad packet to the DMA engine.
4195          */
4196         if (hw->mac.type == e1000_pchlan)
4197                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4198
4199         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4200         E1000_READ_REG(hw, E1000_ICR);
4201
4202         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4203         reg |= E1000_KABGTXD_BGSQLBIAS;
4204         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4205
4206         return E1000_SUCCESS;
4207 }
4208
4209 /**
4210  *  e1000_init_hw_ich8lan - Initialize the hardware
4211  *  @hw: pointer to the HW structure
4212  *
4213  *  Prepares the hardware for transmit and receive by doing the following:
4214  *   - initialize hardware bits
4215  *   - initialize LED identification
4216  *   - setup receive address registers
4217  *   - setup flow control
4218  *   - setup transmit descriptors
4219  *   - clear statistics
4220  **/
4221 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4222 {
4223         struct e1000_mac_info *mac = &hw->mac;
4224         u32 ctrl_ext, txdctl, snoop;
4225         s32 ret_val;
4226         u16 i;
4227
4228         DEBUGFUNC("e1000_init_hw_ich8lan");
4229
4230         e1000_initialize_hw_bits_ich8lan(hw);
4231
4232         /* Initialize identification LED */
4233         ret_val = mac->ops.id_led_init(hw);
4234         /* An error is not fatal and we should not stop init due to this */
4235         if (ret_val)
4236                 DEBUGOUT("Error initializing identification LED\n");
4237
4238         /* Setup the receive address. */
4239         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4240
4241         /* Zero out the Multicast HASH table */
4242         DEBUGOUT("Zeroing the MTA\n");
4243         for (i = 0; i < mac->mta_reg_count; i++)
4244                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4245
4246         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4247          * the ME.  Disable wakeup by clearing the host wakeup bit.
4248          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4249          */
4250         if (hw->phy.type == e1000_phy_82578) {
4251                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4252                 i &= ~BM_WUC_HOST_WU_BIT;
4253                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4254                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4255                 if (ret_val)
4256                         return ret_val;
4257         }
4258
4259         /* Setup link and flow control */
4260         ret_val = mac->ops.setup_link(hw);
4261
4262         /* Set the transmit descriptor write-back policy for both queues */
4263         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4264         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4265                   E1000_TXDCTL_FULL_TX_DESC_WB);
4266         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4267                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4268         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4269         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4270         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4271                   E1000_TXDCTL_FULL_TX_DESC_WB);
4272         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4273                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4274         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4275
4276         /* ICH8 has opposite polarity of no_snoop bits.
4277          * By default, we should use snoop behavior.
4278          */
4279         if (mac->type == e1000_ich8lan)
4280                 snoop = PCIE_ICH8_SNOOP_ALL;
4281         else
4282                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4283         e1000_set_pcie_no_snoop_generic(hw, snoop);
4284
4285         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4286         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4287         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4288
4289         /* Clear all of the statistics registers (clear on read).  It is
4290          * important that we do this after we have tried to establish link
4291          * because the symbol error count will increment wildly if there
4292          * is no link.
4293          */
4294         e1000_clear_hw_cntrs_ich8lan(hw);
4295
4296         return ret_val;
4297 }
4298
4299 /**
4300  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4301  *  @hw: pointer to the HW structure
4302  *
4303  *  Sets/Clears required hardware bits necessary for correctly setting up the
4304  *  hardware for transmit and receive.
4305  **/
4306 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4307 {
4308         u32 reg;
4309
4310         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4311
4312         /* Extended Device Control */
4313         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4314         reg |= (1 << 22);
4315         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4316         if (hw->mac.type >= e1000_pchlan)
4317                 reg |= E1000_CTRL_EXT_PHYPDEN;
4318         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4319
4320         /* Transmit Descriptor Control 0 */
4321         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4322         reg |= (1 << 22);
4323         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4324
4325         /* Transmit Descriptor Control 1 */
4326         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4327         reg |= (1 << 22);
4328         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4329
4330         /* Transmit Arbitration Control 0 */
4331         reg = E1000_READ_REG(hw, E1000_TARC(0));
4332         if (hw->mac.type == e1000_ich8lan)
4333                 reg |= (1 << 28) | (1 << 29);
4334         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4335         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4336
4337         /* Transmit Arbitration Control 1 */
4338         reg = E1000_READ_REG(hw, E1000_TARC(1));
4339         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4340                 reg &= ~(1 << 28);
4341         else
4342                 reg |= (1 << 28);
4343         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4344         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4345
4346         /* Device Status */
4347         if (hw->mac.type == e1000_ich8lan) {
4348                 reg = E1000_READ_REG(hw, E1000_STATUS);
4349                 reg &= ~(1 << 31);
4350                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4351         }
4352
4353         /* work-around descriptor data corruption issue during nfs v2 udp
4354          * traffic, just disable the nfs filtering capability
4355          */
4356         reg = E1000_READ_REG(hw, E1000_RFCTL);
4357         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4358
4359         /* Disable IPv6 extension header parsing because some malformed
4360          * IPv6 headers can hang the Rx.
4361          */
4362         if (hw->mac.type == e1000_ich8lan)
4363                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4364         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4365
4366         /* Enable ECC on Lynxpoint */
4367         if (hw->mac.type == e1000_pch_lpt) {
4368                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4369                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4370                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4371
4372                 reg = E1000_READ_REG(hw, E1000_CTRL);
4373                 reg |= E1000_CTRL_MEHE;
4374                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4375         }
4376
4377         return;
4378 }
4379
4380 /**
4381  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4382  *  @hw: pointer to the HW structure
4383  *
4384  *  Determines which flow control settings to use, then configures flow
4385  *  control.  Calls the appropriate media-specific link configuration
4386  *  function.  Assuming the adapter has a valid link partner, a valid link
4387  *  should be established.  Assumes the hardware has previously been reset
4388  *  and the transmitter and receiver are not enabled.
4389  **/
4390 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4391 {
4392         s32 ret_val;
4393
4394         DEBUGFUNC("e1000_setup_link_ich8lan");
4395
4396         if (hw->phy.ops.check_reset_block(hw))
4397                 return E1000_SUCCESS;
4398
4399         /* ICH parts do not have a word in the NVM to determine
4400          * the default flow control setting, so we explicitly
4401          * set it to full.
4402          */
4403         if (hw->fc.requested_mode == e1000_fc_default)
4404                 hw->fc.requested_mode = e1000_fc_full;
4405
4406         /* Save off the requested flow control mode for use later.  Depending
4407          * on the link partner's capabilities, we may or may not use this mode.
4408          */
4409         hw->fc.current_mode = hw->fc.requested_mode;
4410
4411         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4412                 hw->fc.current_mode);
4413
4414         /* Continue to configure the copper link. */
4415         ret_val = hw->mac.ops.setup_physical_interface(hw);
4416         if (ret_val)
4417                 return ret_val;
4418
4419         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4420         if ((hw->phy.type == e1000_phy_82578) ||
4421             (hw->phy.type == e1000_phy_82579) ||
4422             (hw->phy.type == e1000_phy_i217) ||
4423             (hw->phy.type == e1000_phy_82577)) {
4424                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4425
4426                 ret_val = hw->phy.ops.write_reg(hw,
4427                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
4428                                              hw->fc.pause_time);
4429                 if (ret_val)
4430                         return ret_val;
4431         }
4432
4433         return e1000_set_fc_watermarks_generic(hw);
4434 }
4435
4436 /**
4437  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4438  *  @hw: pointer to the HW structure
4439  *
4440  *  Configures the kumeran interface to the PHY to wait the appropriate time
4441  *  when polling the PHY, then call the generic setup_copper_link to finish
4442  *  configuring the copper link.
4443  **/
4444 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4445 {
4446         u32 ctrl;
4447         s32 ret_val;
4448         u16 reg_data;
4449
4450         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4451
4452         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4453         ctrl |= E1000_CTRL_SLU;
4454         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4455         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4456
4457         /* Set the mac to wait the maximum time between each iteration
4458          * and increase the max iterations when polling the phy;
4459          * this fixes erroneous timeouts at 10Mbps.
4460          */
4461         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4462                                                0xFFFF);
4463         if (ret_val)
4464                 return ret_val;
4465         ret_val = e1000_read_kmrn_reg_generic(hw,
4466                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
4467                                               &reg_data);
4468         if (ret_val)
4469                 return ret_val;
4470         reg_data |= 0x3F;
4471         ret_val = e1000_write_kmrn_reg_generic(hw,
4472                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
4473                                                reg_data);
4474         if (ret_val)
4475                 return ret_val;
4476
4477         switch (hw->phy.type) {
4478         case e1000_phy_igp_3:
4479                 ret_val = e1000_copper_link_setup_igp(hw);
4480                 if (ret_val)
4481                         return ret_val;
4482                 break;
4483         case e1000_phy_bm:
4484         case e1000_phy_82578:
4485                 ret_val = e1000_copper_link_setup_m88(hw);
4486                 if (ret_val)
4487                         return ret_val;
4488                 break;
4489         case e1000_phy_82577:
4490         case e1000_phy_82579:
4491                 ret_val = e1000_copper_link_setup_82577(hw);
4492                 if (ret_val)
4493                         return ret_val;
4494                 break;
4495         case e1000_phy_ife:
4496                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4497                                                &reg_data);
4498                 if (ret_val)
4499                         return ret_val;
4500
4501                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4502
4503                 switch (hw->phy.mdix) {
4504                 case 1:
4505                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4506                         break;
4507                 case 2:
4508                         reg_data |= IFE_PMC_FORCE_MDIX;
4509                         break;
4510                 case 0:
4511                 default:
4512                         reg_data |= IFE_PMC_AUTO_MDIX;
4513                         break;
4514                 }
4515                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4516                                                 reg_data);
4517                 if (ret_val)
4518                         return ret_val;
4519                 break;
4520         default:
4521                 break;
4522         }
4523
4524         return e1000_setup_copper_link_generic(hw);
4525 }
4526
4527 /**
4528  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4529  *  @hw: pointer to the HW structure
4530  *
4531  *  Calls the PHY specific link setup function and then calls the
4532  *  generic setup_copper_link to finish configuring the link for
4533  *  Lynxpoint PCH devices
4534  **/
4535 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4536 {
4537         u32 ctrl;
4538         s32 ret_val;
4539
4540         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4541
4542         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4543         ctrl |= E1000_CTRL_SLU;
4544         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4545         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4546
4547         ret_val = e1000_copper_link_setup_82577(hw);
4548         if (ret_val)
4549                 return ret_val;
4550
4551         return e1000_setup_copper_link_generic(hw);
4552 }
4553
4554 /**
4555  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4556  *  @hw: pointer to the HW structure
4557  *  @speed: pointer to store current link speed
4558  *  @duplex: pointer to store the current link duplex
4559  *
4560  *  Calls the generic get_speed_and_duplex to retrieve the current link
4561  *  information and then calls the Kumeran lock loss workaround for links at
4562  *  gigabit speeds.
4563  **/
4564 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4565                                           u16 *duplex)
4566 {
4567         s32 ret_val;
4568
4569         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4570
4571         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4572         if (ret_val)
4573                 return ret_val;
4574
4575         if ((hw->mac.type == e1000_ich8lan) &&
4576             (hw->phy.type == e1000_phy_igp_3) &&
4577             (*speed == SPEED_1000)) {
4578                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4579         }
4580
4581         return ret_val;
4582 }
4583
4584 /**
4585  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4586  *  @hw: pointer to the HW structure
4587  *
4588  *  Work-around for 82566 Kumeran PCS lock loss:
4589  *  On link status change (i.e. PCI reset, speed change) and link is up and
4590  *  speed is gigabit-
4591  *    0) if workaround is optionally disabled do nothing
4592  *    1) wait 1ms for Kumeran link to come up
4593  *    2) check Kumeran Diagnostic register PCS lock loss bit
4594  *    3) if not set the link is locked (all is good), otherwise...
4595  *    4) reset the PHY
4596  *    5) repeat up to 10 times
4597  *  Note: this is only called for IGP3 copper when speed is 1gb.
4598  **/
4599 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4600 {
4601         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4602         u32 phy_ctrl;
4603         s32 ret_val;
4604         u16 i, data;
4605         bool link;
4606
4607         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4608
4609         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4610                 return E1000_SUCCESS;
4611
4612         /* Make sure link is up before proceeding.  If not just return.
4613          * Attempting this while link is negotiating fouled up link
4614          * stability
4615          */
4616         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4617         if (!link)
4618                 return E1000_SUCCESS;
4619
4620         for (i = 0; i < 10; i++) {
4621                 /* read once to clear */
4622                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4623                 if (ret_val)
4624                         return ret_val;
4625                 /* and again to get new status */
4626                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4627                 if (ret_val)
4628                         return ret_val;
4629
4630                 /* check for PCS lock */
4631                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4632                         return E1000_SUCCESS;
4633
4634                 /* Issue PHY reset */
4635                 hw->phy.ops.reset(hw);
4636                 msec_delay_irq(5);
4637         }
4638         /* Disable GigE link negotiation */
4639         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4640         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4641                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4642         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4643
4644         /* Call gig speed drop workaround on Gig disable before accessing
4645          * any PHY registers
4646          */
4647         e1000_gig_downshift_workaround_ich8lan(hw);
4648
4649         /* unable to acquire PCS lock */
4650         return -E1000_ERR_PHY;
4651 }
4652
4653 /**
4654  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4655  *  @hw: pointer to the HW structure
4656  *  @state: boolean value used to set the current Kumeran workaround state
4657  *
4658  *  If ICH8, set the current Kumeran workaround state (enabled - true
4659  *  /disabled - false).
4660  **/
4661 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4662                                                  bool state)
4663 {
4664         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4665
4666         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4667
4668         if (hw->mac.type != e1000_ich8lan) {
4669                 DEBUGOUT("Workaround applies to ICH8 only.\n");
4670                 return;
4671         }
4672
4673         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4674
4675         return;
4676 }
4677
4678 /**
4679  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4680  *  @hw: pointer to the HW structure
4681  *
4682  *  Workaround for 82566 power-down on D3 entry:
4683  *    1) disable gigabit link
4684  *    2) write VR power-down enable
4685  *    3) read it back
4686  *  Continue if successful, else issue LCD reset and repeat
4687  **/
4688 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4689 {
4690         u32 reg;
4691         u16 data;
4692         u8  retry = 0;
4693
4694         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4695
4696         if (hw->phy.type != e1000_phy_igp_3)
4697                 return;
4698
4699         /* Try the workaround twice (if needed) */
4700         do {
4701                 /* Disable link */
4702                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4703                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4704                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4705                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4706
4707                 /* Call gig speed drop workaround on Gig disable before
4708                  * accessing any PHY registers
4709                  */
4710                 if (hw->mac.type == e1000_ich8lan)
4711                         e1000_gig_downshift_workaround_ich8lan(hw);
4712
4713                 /* Write VR power-down enable */
4714                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4715                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4716                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4717                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4718
4719                 /* Read it back and test */
4720                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4721                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4722                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4723                         break;
4724
4725                 /* Issue PHY reset and repeat at most one more time */
4726                 reg = E1000_READ_REG(hw, E1000_CTRL);
4727                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4728                 retry++;
4729         } while (retry);
4730 }
4731
4732 /**
4733  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4734  *  @hw: pointer to the HW structure
4735  *
4736  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4737  *  LPLU, Gig disable, MDIC PHY reset):
4738  *    1) Set Kumeran Near-end loopback
4739  *    2) Clear Kumeran Near-end loopback
4740  *  Should only be called for ICH8[m] devices with any 1G Phy.
4741  **/
4742 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4743 {
4744         s32 ret_val;
4745         u16 reg_data;
4746
4747         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4748
4749         if ((hw->mac.type != e1000_ich8lan) ||
4750             (hw->phy.type == e1000_phy_ife))
4751                 return;
4752
4753         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4754                                               &reg_data);
4755         if (ret_val)
4756                 return;
4757         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4758         ret_val = e1000_write_kmrn_reg_generic(hw,
4759                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
4760                                                reg_data);
4761         if (ret_val)
4762                 return;
4763         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4764         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4765                                      reg_data);
4766 }
4767
4768 /**
4769  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4770  *  @hw: pointer to the HW structure
4771  *
4772  *  During S0 to Sx transition, it is possible the link remains at gig
4773  *  instead of negotiating to a lower speed.  Before going to Sx, set
4774  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4775  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4776  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4777  *  needs to be written.
4778  *  Parts that support (and are linked to a partner which support) EEE in
4779  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4780  *  than 10Mbps w/o EEE.
4781  **/
4782 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4783 {
4784         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4785         u32 phy_ctrl;
4786         s32 ret_val;
4787
4788         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4789
4790         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4791         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4792
4793         if (hw->phy.type == e1000_phy_i217) {
4794                 u16 phy_reg, device_id = hw->device_id;
4795
4796                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4797                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
4798                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4799
4800                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4801                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4802                 }
4803
4804                 ret_val = hw->phy.ops.acquire(hw);
4805                 if (ret_val)
4806                         goto out;
4807
4808                 if (!dev_spec->eee_disable) {
4809                         u16 eee_advert;
4810
4811                         ret_val =
4812                             e1000_read_emi_reg_locked(hw,
4813                                                       I217_EEE_ADVERTISEMENT,
4814                                                       &eee_advert);
4815                         if (ret_val)
4816                                 goto release;
4817
4818                         /* Disable LPLU if both link partners support 100BaseT
4819                          * EEE and 100Full is advertised on both ends of the
4820                          * link, and enable Auto Enable LPI since there will
4821                          * be no driver to enable LPI while in Sx.
4822                          */
4823                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4824                             (dev_spec->eee_lp_ability &
4825                              I82579_EEE_100_SUPPORTED) &&
4826                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4827                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4828                                               E1000_PHY_CTRL_NOND0A_LPLU);
4829
4830                                 /* Set Auto Enable LPI after link up */
4831                                 hw->phy.ops.read_reg_locked(hw,
4832                                                             I217_LPI_GPIO_CTRL,
4833                                                             &phy_reg);
4834                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4835                                 hw->phy.ops.write_reg_locked(hw,
4836                                                              I217_LPI_GPIO_CTRL,
4837                                                              phy_reg);
4838                         }
4839                 }
4840
4841                 /* For i217 Intel Rapid Start Technology support,
4842                  * when the system is going into Sx and no manageability engine
4843                  * is present, the driver must configure proxy to reset only on
4844                  * power good.  LPI (Low Power Idle) state must also reset only
4845                  * on power good, as well as the MTA (Multicast table array).
4846                  * The SMBus release must also be disabled on LCD reset.
4847                  */
4848                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4849                       E1000_ICH_FWSM_FW_VALID)) {
4850                         /* Enable proxy to reset only on power good. */
4851                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4852                                                     &phy_reg);
4853                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4854                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4855                                                      phy_reg);
4856
4857                         /* Set bit enable LPI (EEE) to reset only on
4858                          * power good.
4859                         */
4860                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4861                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4862                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4863
4864                         /* Disable the SMB release on LCD reset. */
4865                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4866                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4867                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4868                 }
4869
4870                 /* Enable MTA to reset for Intel Rapid Start Technology
4871                  * Support
4872                  */
4873                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4874                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4875                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4876
4877 release:
4878                 hw->phy.ops.release(hw);
4879         }
4880 out:
4881         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4882
4883         if (hw->mac.type == e1000_ich8lan)
4884                 e1000_gig_downshift_workaround_ich8lan(hw);
4885
4886         if (hw->mac.type >= e1000_pchlan) {
4887                 e1000_oem_bits_config_ich8lan(hw, false);
4888
4889                 /* Reset PHY to activate OEM bits on 82577/8 */
4890                 if (hw->mac.type == e1000_pchlan)
4891                         e1000_phy_hw_reset_generic(hw);
4892
4893                 ret_val = hw->phy.ops.acquire(hw);
4894                 if (ret_val)
4895                         return;
4896                 e1000_write_smbus_addr(hw);
4897                 hw->phy.ops.release(hw);
4898         }
4899
4900         return;
4901 }
4902
4903 /**
4904  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4905  *  @hw: pointer to the HW structure
4906  *
4907  *  During Sx to S0 transitions on non-managed devices or managed devices
4908  *  on which PHY resets are not blocked, if the PHY registers cannot be
4909  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4910  *  the PHY.
4911  *  On i217, setup Intel Rapid Start Technology.
4912  **/
4913 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4914 {
4915         s32 ret_val;
4916
4917         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4918
4919         if (hw->mac.type < e1000_pch2lan)
4920                 return;
4921
4922         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4923         if (ret_val) {
4924                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4925                 return;
4926         }
4927
4928         /* For i217 Intel Rapid Start Technology support when the system
4929          * is transitioning from Sx and no manageability engine is present
4930          * configure SMBus to restore on reset, disable proxy, and enable
4931          * the reset on MTA (Multicast table array).
4932          */
4933         if (hw->phy.type == e1000_phy_i217) {
4934                 u16 phy_reg;
4935
4936                 ret_val = hw->phy.ops.acquire(hw);
4937                 if (ret_val) {
4938                         DEBUGOUT("Failed to setup iRST\n");
4939                         return;
4940                 }
4941
4942                 /* Clear Auto Enable LPI after link up */
4943                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
4944                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4945                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
4946
4947                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4948                     E1000_ICH_FWSM_FW_VALID)) {
4949                         /* Restore clear on SMB if no manageability engine
4950                          * is present
4951                          */
4952                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
4953                                                               &phy_reg);
4954                         if (ret_val)
4955                                 goto release;
4956                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4957                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4958
4959                         /* Disable Proxy */
4960                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
4961                 }
4962                 /* Enable reset on MTA */
4963                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
4964                                                       &phy_reg);
4965                 if (ret_val)
4966                         goto release;
4967                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4968                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4969 release:
4970                 if (ret_val)
4971                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
4972                 hw->phy.ops.release(hw);
4973         }
4974 }
4975
4976 /**
4977  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4978  *  @hw: pointer to the HW structure
4979  *
4980  *  Return the LED back to the default configuration.
4981  **/
4982 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4983 {
4984         DEBUGFUNC("e1000_cleanup_led_ich8lan");
4985
4986         if (hw->phy.type == e1000_phy_ife)
4987                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4988                                              0);
4989
4990         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
4991         return E1000_SUCCESS;
4992 }
4993
4994 /**
4995  *  e1000_led_on_ich8lan - Turn LEDs on
4996  *  @hw: pointer to the HW structure
4997  *
4998  *  Turn on the LEDs.
4999  **/
5000 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5001 {
5002         DEBUGFUNC("e1000_led_on_ich8lan");
5003
5004         if (hw->phy.type == e1000_phy_ife)
5005                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5006                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5007
5008         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5009         return E1000_SUCCESS;
5010 }
5011
5012 /**
5013  *  e1000_led_off_ich8lan - Turn LEDs off
5014  *  @hw: pointer to the HW structure
5015  *
5016  *  Turn off the LEDs.
5017  **/
5018 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5019 {
5020         DEBUGFUNC("e1000_led_off_ich8lan");
5021
5022         if (hw->phy.type == e1000_phy_ife)
5023                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5024                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5025
5026         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5027         return E1000_SUCCESS;
5028 }
5029
5030 /**
5031  *  e1000_setup_led_pchlan - Configures SW controllable LED
5032  *  @hw: pointer to the HW structure
5033  *
5034  *  This prepares the SW controllable LED for use.
5035  **/
5036 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5037 {
5038         DEBUGFUNC("e1000_setup_led_pchlan");
5039
5040         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5041                                      (u16)hw->mac.ledctl_mode1);
5042 }
5043
5044 /**
5045  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5046  *  @hw: pointer to the HW structure
5047  *
5048  *  Return the LED back to the default configuration.
5049  **/
5050 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5051 {
5052         DEBUGFUNC("e1000_cleanup_led_pchlan");
5053
5054         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5055                                      (u16)hw->mac.ledctl_default);
5056 }
5057
5058 /**
5059  *  e1000_led_on_pchlan - Turn LEDs on
5060  *  @hw: pointer to the HW structure
5061  *
5062  *  Turn on the LEDs.
5063  **/
5064 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5065 {
5066         u16 data = (u16)hw->mac.ledctl_mode2;
5067         u32 i, led;
5068
5069         DEBUGFUNC("e1000_led_on_pchlan");
5070
5071         /* If no link, then turn LED on by setting the invert bit
5072          * for each LED that's mode is "link_up" in ledctl_mode2.
5073          */
5074         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5075                 for (i = 0; i < 3; i++) {
5076                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5077                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5078                             E1000_LEDCTL_MODE_LINK_UP)
5079                                 continue;
5080                         if (led & E1000_PHY_LED0_IVRT)
5081                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5082                         else
5083                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5084                 }
5085         }
5086
5087         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5088 }
5089
5090 /**
5091  *  e1000_led_off_pchlan - Turn LEDs off
5092  *  @hw: pointer to the HW structure
5093  *
5094  *  Turn off the LEDs.
5095  **/
5096 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5097 {
5098         u16 data = (u16)hw->mac.ledctl_mode1;
5099         u32 i, led;
5100
5101         DEBUGFUNC("e1000_led_off_pchlan");
5102
5103         /* If no link, then turn LED off by clearing the invert bit
5104          * for each LED that's mode is "link_up" in ledctl_mode1.
5105          */
5106         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5107                 for (i = 0; i < 3; i++) {
5108                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5109                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5110                             E1000_LEDCTL_MODE_LINK_UP)
5111                                 continue;
5112                         if (led & E1000_PHY_LED0_IVRT)
5113                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5114                         else
5115                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5116                 }
5117         }
5118
5119         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5120 }
5121
5122 /**
5123  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5124  *  @hw: pointer to the HW structure
5125  *
5126  *  Read appropriate register for the config done bit for completion status
5127  *  and configure the PHY through s/w for EEPROM-less parts.
5128  *
5129  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5130  *  config done bit, so only an error is logged and continues.  If we were
5131  *  to return with error, EEPROM-less silicon would not be able to be reset
5132  *  or change link.
5133  **/
5134 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5135 {
5136         s32 ret_val = E1000_SUCCESS;
5137         u32 bank = 0;
5138         u32 status;
5139
5140         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5141
5142         e1000_get_cfg_done_generic(hw);
5143
5144         /* Wait for indication from h/w that it has completed basic config */
5145         if (hw->mac.type >= e1000_ich10lan) {
5146                 e1000_lan_init_done_ich8lan(hw);
5147         } else {
5148                 ret_val = e1000_get_auto_rd_done_generic(hw);
5149                 if (ret_val) {
5150                         /* When auto config read does not complete, do not
5151                          * return with an error. This can happen in situations
5152                          * where there is no eeprom and prevents getting link.
5153                          */
5154                         DEBUGOUT("Auto Read Done did not complete\n");
5155                         ret_val = E1000_SUCCESS;
5156                 }
5157         }
5158
5159         /* Clear PHY Reset Asserted bit */
5160         status = E1000_READ_REG(hw, E1000_STATUS);
5161         if (status & E1000_STATUS_PHYRA)
5162                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5163         else
5164                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5165
5166         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5167         if (hw->mac.type <= e1000_ich9lan) {
5168                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5169                     (hw->phy.type == e1000_phy_igp_3)) {
5170                         e1000_phy_init_script_igp3(hw);
5171                 }
5172         } else {
5173                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5174                         /* Maybe we should do a basic PHY config */
5175                         DEBUGOUT("EEPROM not present\n");
5176                         ret_val = -E1000_ERR_CONFIG;
5177                 }
5178         }
5179
5180         return ret_val;
5181 }
5182
5183 /**
5184  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5185  * @hw: pointer to the HW structure
5186  *
5187  * In the case of a PHY power down to save power, or to turn off link during a
5188  * driver unload, or wake on lan is not enabled, remove the link.
5189  **/
5190 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5191 {
5192         /* If the management interface is not enabled, then power down */
5193         if (!(hw->mac.ops.check_mng_mode(hw) ||
5194               hw->phy.ops.check_reset_block(hw)))
5195                 e1000_power_down_phy_copper(hw);
5196
5197         return;
5198 }
5199
5200 /**
5201  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5202  *  @hw: pointer to the HW structure
5203  *
5204  *  Clears hardware counters specific to the silicon family and calls
5205  *  clear_hw_cntrs_generic to clear all general purpose counters.
5206  **/
5207 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5208 {
5209         u16 phy_data;
5210         s32 ret_val;
5211
5212         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5213
5214         e1000_clear_hw_cntrs_base_generic(hw);
5215
5216         E1000_READ_REG(hw, E1000_ALGNERRC);
5217         E1000_READ_REG(hw, E1000_RXERRC);
5218         E1000_READ_REG(hw, E1000_TNCRS);
5219         E1000_READ_REG(hw, E1000_CEXTERR);
5220         E1000_READ_REG(hw, E1000_TSCTC);
5221         E1000_READ_REG(hw, E1000_TSCTFC);
5222
5223         E1000_READ_REG(hw, E1000_MGTPRC);
5224         E1000_READ_REG(hw, E1000_MGTPDC);
5225         E1000_READ_REG(hw, E1000_MGTPTC);
5226
5227         E1000_READ_REG(hw, E1000_IAC);
5228         E1000_READ_REG(hw, E1000_ICRXOC);
5229
5230         /* Clear PHY statistics registers */
5231         if ((hw->phy.type == e1000_phy_82578) ||
5232             (hw->phy.type == e1000_phy_82579) ||
5233             (hw->phy.type == e1000_phy_i217) ||
5234             (hw->phy.type == e1000_phy_82577)) {
5235                 ret_val = hw->phy.ops.acquire(hw);
5236                 if (ret_val)
5237                         return;
5238                 ret_val = hw->phy.ops.set_page(hw,
5239                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5240                 if (ret_val)
5241                         goto release;
5242                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5243                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5244                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5245                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5246                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5247                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5248                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5249                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5250                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5251                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5252                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5253                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5254                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5255                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5256 release:
5257                 hw->phy.ops.release(hw);
5258         }
5259 }
5260