lib/librte_pmd_e1000/e1000/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  */
  62
  63 #include "e1000_api.h"
  64
  65 STATIC s32  e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
  66 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
  67 STATIC s32  e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
  68 STATIC s32  e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
  69 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  70 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  71 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  72 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  73 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  74 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  75 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  76 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  77 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  78 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  79 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  80                                             bool active);
  81 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  82                                             bool active);
  83 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  84                                    u16 words, u16 *data);
  85 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  86                                     u16 words, u16 *data);
  87 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  88 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  90                                             u16 *data);
  91 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
  92 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  93 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  94 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  95 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  96 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  98                                            u16 *speed, u16 *duplex);
  99 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 100 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 101 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 102 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 103 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 104 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 105 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 106 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 107 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 108 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 109 static s32  e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
 110 static s32  e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
 111 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 112 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 113 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 114                                           u32 offset, u8 *data);
 115 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 116                                           u8 size, u16 *data);
 117 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 118                                           u32 offset, u16 *data);
 119 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 120                                                  u32 offset, u8 byte);
 121 STATIC s32  e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
 122                                            u32 offset, u8 data);
 123 static s32  e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 124                                            u8 size, u16 data);
 125 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 126 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 127 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 128 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 129 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
 130 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 131 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 132 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 133
 134 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 135 /* Offset 04h HSFSTS */
 136 union ich8_hws_flash_status {
 137         struct ich8_hsfsts {
 138                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 139                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 140                 u16 dael:1; /* bit 2 Direct Access error Log */
 141                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 142                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 143                 u16 reserved1:2; /* bit 13:6 Reserved */
 144                 u16 reserved2:6; /* bit 13:6 Reserved */
 145                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 146                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 147         } hsf_status;
 148         u16 regval;
 149 };
 150
 151 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 152 /* Offset 06h FLCTL */
 153 union ich8_hws_flash_ctrl {
 154         struct ich8_hsflctl {
 155                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 156                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 157                 u16 reserved:5;   /* 7:3 Reserved  */
 158                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 159                 u16 flockdn:6;   /* 15:10 Reserved */
 160         } hsf_ctrl;
 161         u16 regval;
 162 };
 163
 164 /* ICH Flash Region Access Permissions */
 165 union ich8_hws_flash_regacc {
 166         struct ich8_flracc {
 167                 u32 grra:8; /* 0:7 GbE region Read Access */
 168                 u32 grwa:8; /* 8:15 GbE region Write Access */
 169                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 170                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 171         } hsf_flregacc;
 172         u16 regval;
 173 };
 174
 175 /**
 176  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 177  *  @hw: pointer to the HW structure
 178  *
 179  *  Test access to the PHY registers by reading the PHY ID registers.  If
 180  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 181  *  otherwise assume the read PHY ID is correct if it is valid.
 182  *
 183  *  Assumes the sw/fw/hw semaphore is already acquired.
 184  **/
 185 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 186 {
 187         u16 phy_reg = 0;
 188         u32 phy_id = 0;
 189         s32 ret_val;
 190         u16 retry_count;
 191
 192         for (retry_count = 0; retry_count < 2; retry_count++) {
 193                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 194                 if (ret_val || (phy_reg == 0xFFFF))
 195                         continue;
 196                 phy_id = (u32)(phy_reg << 16);
 197
 198                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 199                 if (ret_val || (phy_reg == 0xFFFF)) {
 200                         phy_id = 0;
 201                         continue;
 202                 }
 203                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 204                 break;
 205         }
 206
 207         if (hw->phy.id) {
 208                 if  (hw->phy.id == phy_id)
 209                         return true;
 210         } else if (phy_id) {
 211                 hw->phy.id = phy_id;
 212                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 213                 return true;
 214         }
 215
 216         /*
 217          * In case the PHY needs to be in mdio slow mode,
 218          * set slow mode and try to get the PHY id again.
 219          */
 220         hw->phy.ops.release(hw);
 221         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 222         if (!ret_val)
 223                 ret_val = e1000_get_phy_id(hw);
 224         hw->phy.ops.acquire(hw);
 225
 226         return !ret_val;
 227 }
 228
 229 /**
 230  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 231  *  @hw: pointer to the HW structure
 232  *
 233  *  Workarounds/flow necessary for PHY initialization during driver load
 234  *  and resume paths.
 235  **/
 236 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 237 {
 238         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 239         s32 ret_val;
 240
 241         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 242
 243         ret_val = hw->phy.ops.acquire(hw);
 244         if (ret_val) {
 245                 DEBUGOUT("Failed to initialize PHY flow\n");
 246                 return ret_val;
 247         }
 248
 249         /*
 250          * The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 251          * inaccessible and resetting the PHY is not blocked, toggle the
 252          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 253          */
 254         switch (hw->mac.type) {
 255         case e1000_pch2lan:
 256                 /*
 257                  * Gate automatic PHY configuration by hardware on
 258                  * non-managed 82579
 259                  */
 260                 if ((hw->mac.type == e1000_pch2lan) &&
 261                     !(fwsm & E1000_ICH_FWSM_FW_VALID))
 262                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 263
 264                 if (e1000_phy_is_accessible_pchlan(hw)) {
 265                         break;
 266                 }
 267
 268                 /* fall-through */
 269         case e1000_pchlan:
 270                 if ((hw->mac.type == e1000_pchlan) &&
 271                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 272                         break;
 273
 274                 if (hw->phy.ops.check_reset_block(hw)) {
 275                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 276                         break;
 277                 }
 278
 279                 DEBUGOUT("Toggling LANPHYPC\n");
 280
 281                 /* Set Phy Config Counter to 50msec */
 282                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 283                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 284                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 285                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 286
 287                 /* Toggle LANPHYPC Value bit */
 288                 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 289                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 290                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 291                 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 292                 E1000_WRITE_FLUSH(hw);
 293                 usec_delay(10);
 294                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 295                 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 296                 E1000_WRITE_FLUSH(hw);
 297                 msec_delay(50);
 298                 break;
 299         default:
 300                 break;
 301         }
 302
 303         hw->phy.ops.release(hw);
 304
 305         /*
 306          * Reset the PHY before any access to it.  Doing so, ensures
 307          * that the PHY is in a known good state before we read/write
 308          * PHY registers.  The generic reset is sufficient here,
 309          * because we haven't determined the PHY type yet.
 310          */
 311         ret_val = e1000_phy_hw_reset_generic(hw);
 312
 313         /* Ungate automatic PHY configuration on non-managed 82579 */
 314         if ((hw->mac.type == e1000_pch2lan) &&
 315             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 316                 msec_delay(10);
 317                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 318         }
 319
 320         return ret_val;
 321 }
 322
 323 /**
 324  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 325  *  @hw: pointer to the HW structure
 326  *
 327  *  Initialize family-specific PHY parameters and function pointers.
 328  **/
 329 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 330 {
 331         struct e1000_phy_info *phy = &hw->phy;
 332         s32 ret_val = E1000_SUCCESS;
 333
 334         DEBUGFUNC("e1000_init_phy_params_pchlan");
 335
 336         phy->addr               = 1;
 337         phy->reset_delay_us     = 100;
 338
 339         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 340         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 341         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 342         phy->ops.set_page       = e1000_set_page_igp;
 343         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 344         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 345         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 346         phy->ops.release        = e1000_release_swflag_ich8lan;
 347         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 348         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 349         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 350         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 351         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 352         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 353         phy->ops.power_up       = e1000_power_up_phy_copper;
 354         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 355         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 356
 357         phy->id = e1000_phy_unknown;
 358
 359         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 360         if (ret_val)
 361                 return ret_val;
 362
 363         if (phy->id == e1000_phy_unknown)
 364                 switch (hw->mac.type) {
 365                 default:
 366                         ret_val = e1000_get_phy_id(hw);
 367                         if (ret_val)
 368                                 return ret_val;
 369                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 370                                 break;
 371                         /* fall-through */
 372                 case e1000_pch2lan:
 373                         /*
 374                          * In case the PHY needs to be in mdio slow mode,
 375                          * set slow mode and try to get the PHY id again.
 376                          */
 377                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 378                         if (ret_val)
 379                                 return ret_val;
 380                         ret_val = e1000_get_phy_id(hw);
 381                         if (ret_val)
 382                                 return ret_val;
 383                         break;
 384                 }
 385         phy->type = e1000_get_phy_type_from_id(phy->id);
 386
 387         switch (phy->type) {
 388         case e1000_phy_82577:
 389         case e1000_phy_82579:
 390         case e1000_phy_i217:
 391                 phy->ops.check_polarity = e1000_check_polarity_82577;
 392                 phy->ops.force_speed_duplex =
 393                         e1000_phy_force_speed_duplex_82577;
 394                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 395                 phy->ops.get_info = e1000_get_phy_info_82577;
 396                 phy->ops.commit = e1000_phy_sw_reset_generic;
 397                 break;
 398         case e1000_phy_82578:
 399                 phy->ops.check_polarity = e1000_check_polarity_m88;
 400                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 401                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 402                 phy->ops.get_info = e1000_get_phy_info_m88;
 403                 break;
 404         default:
 405                 ret_val = -E1000_ERR_PHY;
 406                 break;
 407         }
 408
 409         return ret_val;
 410 }
 411
 412 /**
 413  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 414  *  @hw: pointer to the HW structure
 415  *
 416  *  Initialize family-specific PHY parameters and function pointers.
 417  **/
 418 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 419 {
 420         struct e1000_phy_info *phy = &hw->phy;
 421         s32 ret_val;
 422         u16 i = 0;
 423
 424         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 425
 426         phy->addr               = 1;
 427         phy->reset_delay_us     = 100;
 428
 429         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 430         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 431         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 432         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 433         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 434         phy->ops.release        = e1000_release_swflag_ich8lan;
 435         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 436         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 437         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 438         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 439         phy->ops.power_up       = e1000_power_up_phy_copper;
 440         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 441
 442         /* We may need to do this twice - once for IGP and if that fails,
 443          * we'll set BM func pointers and try again
 444          */
 445         ret_val = e1000_determine_phy_address(hw);
 446         if (ret_val) {
 447                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 448                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 449                 ret_val = e1000_determine_phy_address(hw);
 450                 if (ret_val) {
 451                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 452                         return ret_val;
 453                 }
 454         }
 455
 456         phy->id = 0;
 457         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 458                (i++ < 100)) {
 459                 msec_delay(1);
 460                 ret_val = e1000_get_phy_id(hw);
 461                 if (ret_val)
 462                         return ret_val;
 463         }
 464
 465         /* Verify phy id */
 466         switch (phy->id) {
 467         case IGP03E1000_E_PHY_ID:
 468                 phy->type = e1000_phy_igp_3;
 469                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 470                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 471                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 472                 phy->ops.get_info = e1000_get_phy_info_igp;
 473                 phy->ops.check_polarity = e1000_check_polarity_igp;
 474                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 475                 break;
 476         case IFE_E_PHY_ID:
 477         case IFE_PLUS_E_PHY_ID:
 478         case IFE_C_E_PHY_ID:
 479                 phy->type = e1000_phy_ife;
 480                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 481                 phy->ops.get_info = e1000_get_phy_info_ife;
 482                 phy->ops.check_polarity = e1000_check_polarity_ife;
 483                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 484                 break;
 485         case BME1000_E_PHY_ID:
 486                 phy->type = e1000_phy_bm;
 487                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 488                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 489                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 490                 phy->ops.commit = e1000_phy_sw_reset_generic;
 491                 phy->ops.get_info = e1000_get_phy_info_m88;
 492                 phy->ops.check_polarity = e1000_check_polarity_m88;
 493                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 494                 break;
 495         default:
 496                 return -E1000_ERR_PHY;
 497                 break;
 498         }
 499
 500         return E1000_SUCCESS;
 501 }
 502
 503 /**
 504  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 505  *  @hw: pointer to the HW structure
 506  *
 507  *  Initialize family-specific NVM parameters and function
 508  *  pointers.
 509  **/
 510 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 511 {
 512         struct e1000_nvm_info *nvm = &hw->nvm;
 513         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 514         u32 gfpreg, sector_base_addr, sector_end_addr;
 515         u16 i;
 516
 517         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 518
 519         /* Can't read flash registers if the register set isn't mapped. */
 520         if (!hw->flash_address) {
 521                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 522                 return -E1000_ERR_CONFIG;
 523         }
 524
 525         nvm->type = e1000_nvm_flash_sw;
 526
 527         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 528
 529         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 530          * Add 1 to sector_end_addr since this sector is included in
 531          * the overall size.
 532          */
 533         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 534         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 535
 536         /* flash_base_addr is byte-aligned */
 537         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 538
 539         /* find total size of the NVM, then cut in half since the total
 540          * size represents two separate NVM banks.
 541          */
 542         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 543                                 << FLASH_SECTOR_ADDR_SHIFT;
 544         nvm->flash_bank_size /= 2;
 545         /* Adjust to word count */
 546         nvm->flash_bank_size /= sizeof(u16);
 547
 548         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 549
 550         /* Clear shadow ram */
 551         for (i = 0; i < nvm->word_size; i++) {
 552                 dev_spec->shadow_ram[i].modified = false;
 553                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 554         }
 555
 556         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 557         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 558
 559         /* Function Pointers */
 560         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 561         nvm->ops.release        = e1000_release_nvm_ich8lan;
 562         nvm->ops.read           = e1000_read_nvm_ich8lan;
 563         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 564         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 565         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 566         nvm->ops.write          = e1000_write_nvm_ich8lan;
 567
 568         return E1000_SUCCESS;
 569 }
 570
 571 /**
 572  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 573  *  @hw: pointer to the HW structure
 574  *
 575  *  Initialize family-specific MAC parameters and function
 576  *  pointers.
 577  **/
 578 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 579 {
 580         struct e1000_mac_info *mac = &hw->mac;
 581
 582         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 583
 584         /* Set media type function pointer */
 585         hw->phy.media_type = e1000_media_type_copper;
 586
 587         /* Set mta register count */
 588         mac->mta_reg_count = 32;
 589         /* Set rar entry count */
 590         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 591         if (mac->type == e1000_ich8lan)
 592                 mac->rar_entry_count--;
 593         /* Set if part includes ASF firmware */
 594         mac->asf_firmware_present = true;
 595         /* FWSM register */
 596         mac->has_fwsm = true;
 597         /* ARC subsystem not supported */
 598         mac->arc_subsystem_valid = false;
 599         /* Adaptive IFS supported */
 600         mac->adaptive_ifs = true;
 601
 602         /* Function pointers */
 603
 604         /* bus type/speed/width */
 605         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 606         /* function id */
 607         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 608         /* reset */
 609         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 610         /* hw initialization */
 611         mac->ops.init_hw = e1000_init_hw_ich8lan;
 612         /* link setup */
 613         mac->ops.setup_link = e1000_setup_link_ich8lan;
 614         /* physical interface setup */
 615         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 616         /* check for link */
 617         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 618         /* link info */
 619         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 620         /* multicast address update */
 621         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 622         /* clear hardware counters */
 623         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 624
 625         /* LED and other operations */
 626         switch (mac->type) {
 627         case e1000_ich8lan:
 628         case e1000_ich9lan:
 629         case e1000_ich10lan:
 630                 /* check management mode */
 631                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 632                 /* ID LED init */
 633                 mac->ops.id_led_init = e1000_id_led_init_generic;
 634                 /* blink LED */
 635                 mac->ops.blink_led = e1000_blink_led_generic;
 636                 /* setup LED */
 637                 mac->ops.setup_led = e1000_setup_led_generic;
 638                 /* cleanup LED */
 639                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 640                 /* turn on/off LED */
 641                 mac->ops.led_on = e1000_led_on_ich8lan;
 642                 mac->ops.led_off = e1000_led_off_ich8lan;
 643                 break;
 644         case e1000_pch2lan:
 645                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 646                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 647                 /* fall-through */
 648         case e1000_pchlan:
 649                 /* check management mode */
 650                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 651                 /* ID LED init */
 652                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 653                 /* setup LED */
 654                 mac->ops.setup_led = e1000_setup_led_pchlan;
 655                 /* cleanup LED */
 656                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 657                 /* turn on/off LED */
 658                 mac->ops.led_on = e1000_led_on_pchlan;
 659                 mac->ops.led_off = e1000_led_off_pchlan;
 660                 break;
 661         default:
 662                 break;
 663         }
 664
 665         /* Enable PCS Lock-loss workaround for ICH8 */
 666         if (mac->type == e1000_ich8lan)
 667                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 668
 669         /* Gate automatic PHY configuration by hardware on managed 82579 */
 670         if ((mac->type == e1000_pch2lan) &&
 671             (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
 672                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 673
 674         return E1000_SUCCESS;
 675 }
 676
 677 /**
 678  *  __e1000_access_emi_reg_locked - Read/write EMI register
 679  *  @hw: pointer to the HW structure
 680  *  @addr: EMI address to program
 681  *  @data: pointer to value to read/write from/to the EMI address
 682  *  @read: boolean flag to indicate read or write
 683  *
 684  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 685  **/
 686 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 687                                          u16 *data, bool read)
 688 {
 689         s32 ret_val = E1000_SUCCESS;
 690
 691         DEBUGFUNC("__e1000_access_emi_reg_locked");
 692
 693         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 694         if (ret_val)
 695                 return ret_val;
 696
 697         if (read)
 698                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 699                                                       data);
 700         else
 701                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 702                                                        *data);
 703
 704         return ret_val;
 705 }
 706
 707 /**
 708  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 709  *  @hw: pointer to the HW structure
 710  *  @addr: EMI address to program
 711  *  @data: value to be read from the EMI address
 712  *
 713  *  Assumes the SW/FW/HW Semaphore is already acquired.
 714  **/
 715 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 716 {
 717         DEBUGFUNC("e1000_read_emi_reg_locked");
 718
 719         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 720 }
 721
 722 /**
 723  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 724  *  @hw: pointer to the HW structure
 725  *  @addr: EMI address to program
 726  *  @data: value to be written to the EMI address
 727  *
 728  *  Assumes the SW/FW/HW Semaphore is already acquired.
 729  **/
 730 STATIC s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 731 {
 732         DEBUGFUNC("e1000_read_emi_reg_locked");
 733
 734         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 735 }
 736
 737 /**
 738  *  e1000_set_eee_pchlan - Enable/disable EEE support
 739  *  @hw: pointer to the HW structure
 740  *
 741  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 742  *  the link and the EEE capabilities of the link partner.  The LPI Control
 743  *  register bits will remain set only if/when link is up.
 744  **/
 745 STATIC s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 746 {
 747         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 748         s32 ret_val;
 749         u16 lpi_ctrl;
 750
 751         DEBUGFUNC("e1000_set_eee_pchlan");
 752
 753         if ((hw->phy.type != e1000_phy_82579) &&
 754             (hw->phy.type != e1000_phy_i217))
 755                 return E1000_SUCCESS;
 756
 757         ret_val = hw->phy.ops.acquire(hw);
 758         if (ret_val)
 759                 return ret_val;
 760
 761         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 762         if (ret_val)
 763                 goto release;
 764
 765         /* Clear bits that enable EEE in various speeds */
 766         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 767
 768         /* Enable EEE if not disabled by user */
 769         if (!dev_spec->eee_disable) {
 770                 u16 lpa, pcs_status, data;
 771
 772                 /* Save off link partner's EEE ability */
 773                 switch (hw->phy.type) {
 774                 case e1000_phy_82579:
 775                         lpa = I82579_EEE_LP_ABILITY;
 776                         pcs_status = I82579_EEE_PCS_STATUS;
 777                         break;
 778                 case e1000_phy_i217:
 779                         lpa = I217_EEE_LP_ABILITY;
 780                         pcs_status = I217_EEE_PCS_STATUS;
 781                         break;
 782                 default:
 783                         ret_val = -E1000_ERR_PHY;
 784                         goto release;
 785                 }
 786                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 787                                                     &dev_spec->eee_lp_ability);
 788                 if (ret_val)
 789                         goto release;
 790
 791                 /*
 792                  * Enable EEE only for speeds in which the link partner is
 793                  * EEE capable.
 794                  */
 795                 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 796                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 797
 798                 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 799                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 800                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 801                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 802                         else
 803                                 /*
 804                                  * EEE is not supported in 100Half, so ignore
 805                                  * partner's EEE in 100 ability if full-duplex
 806                                  * is not advertised.
 807                                  */
 808                                 dev_spec->eee_lp_ability &=
 809                                     ~I82579_EEE_100_SUPPORTED;
 810                 }
 811
 812                 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 813                 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 814                 if (ret_val)
 815                         goto release;
 816         }
 817
 818         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 819 release:
 820         hw->phy.ops.release(hw);
 821
 822         return ret_val;
 823 }
 824
 825 /**
 826  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 827  *  @hw: pointer to the HW structure
 828  *
 829  *  Checks to see of the link status of the hardware has changed.  If a
 830  *  change in link status has been detected, then we read the PHY registers
 831  *  to get the current speed/duplex if link exists.
 832  **/
 833 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 834 {
 835         struct e1000_mac_info *mac = &hw->mac;
 836         s32 ret_val;
 837         bool link;
 838         u16 phy_reg;
 839
 840         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
 841
 842         /* We only want to go out to the PHY registers to see if Auto-Neg
 843          * has completed and/or if our link status has changed.  The
 844          * get_link_status flag is set upon receiving a Link Status
 845          * Change or Rx Sequence Error interrupt.
 846          */
 847         if (!mac->get_link_status)
 848                 return E1000_SUCCESS;
 849
 850         /*
 851          * First we want to see if the MII Status Register reports
 852          * link.  If so, then we want to get the current speed/duplex
 853          * of the PHY.
 854          */
 855         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 856         if (ret_val)
 857                 return ret_val;
 858
 859         if (hw->mac.type == e1000_pchlan) {
 860                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 861                 if (ret_val)
 862                         return ret_val;
 863         }
 864
 865         /* Clear link partner's EEE ability */
 866         hw->dev_spec.ich8lan.eee_lp_ability = 0;
 867
 868         if (!link)
 869                 return E1000_SUCCESS; /* No link detected */
 870
 871         mac->get_link_status = false;
 872
 873         switch (hw->mac.type) {
 874         case e1000_pch2lan:
 875                 ret_val = e1000_k1_workaround_lv(hw);
 876                 if (ret_val)
 877                         return ret_val;
 878                 /* fall-thru */
 879         case e1000_pchlan:
 880                 if (hw->phy.type == e1000_phy_82578) {
 881                         ret_val = e1000_link_stall_workaround_hv(hw);
 882                         if (ret_val)
 883                                 return ret_val;
 884                 }
 885
 886                 /* Workaround for PCHx parts in half-duplex:
 887                  * Set the number of preambles removed from the packet
 888                  * when it is passed from the PHY to the MAC to prevent
 889                  * the MAC from misinterpreting the packet type.
 890                  */
 891                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 892                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 893
 894                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
 895                     E1000_STATUS_FD)
 896                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 897
 898                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 899                 break;
 900         default:
 901                 break;
 902         }
 903
 904         /* Check if there was DownShift, must be checked
 905          * immediately after link-up
 906          */
 907         e1000_check_downshift_generic(hw);
 908
 909         /* Enable/Disable EEE after link up */
 910         ret_val = e1000_set_eee_pchlan(hw);
 911         if (ret_val)
 912                 return ret_val;
 913
 914         /* If we are forcing speed/duplex, then we simply return since
 915          * we have already determined whether we have link or not.
 916          */
 917         if (!mac->autoneg)
 918                 return -E1000_ERR_CONFIG;
 919
 920         /* Auto-Neg is enabled.  Auto Speed Detection takes care
 921          * of MAC speed/duplex configuration.  So we only need to
 922          * configure Collision Distance in the MAC.
 923          */
 924         mac->ops.config_collision_dist(hw);
 925
 926         /* Configure Flow Control now that Auto-Neg has completed.
 927          * First, we need to restore the desired flow control
 928          * settings because we may have had to re-autoneg with a
 929          * different link partner.
 930          */
 931         ret_val = e1000_config_fc_after_link_up_generic(hw);
 932         if (ret_val)
 933                 DEBUGOUT("Error configuring flow control\n");
 934
 935         return ret_val;
 936 }
 937
 938 /**
 939  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
 940  *  @hw: pointer to the HW structure
 941  *
 942  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
 943  **/
 944 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
 945 {
 946         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
 947
 948         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
 949         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
 950         switch (hw->mac.type) {
 951         case e1000_ich8lan:
 952         case e1000_ich9lan:
 953         case e1000_ich10lan:
 954                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
 955                 break;
 956         case e1000_pchlan:
 957         case e1000_pch2lan:
 958                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
 959                 break;
 960         default:
 961                 break;
 962         }
 963 }
 964
 965 /**
 966  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 967  *  @hw: pointer to the HW structure
 968  *
 969  *  Acquires the mutex for performing NVM operations.
 970  **/
 971 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 972 {
 973         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
 974
 975         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
 976
 977         return E1000_SUCCESS;
 978 }
 979
 980 /**
 981  *  e1000_release_nvm_ich8lan - Release NVM mutex
 982  *  @hw: pointer to the HW structure
 983  *
 984  *  Releases the mutex used while performing NVM operations.
 985  **/
 986 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 987 {
 988         DEBUGFUNC("e1000_release_nvm_ich8lan");
 989
 990         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
 991
 992         return;
 993 }
 994
 995 /**
 996  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 997  *  @hw: pointer to the HW structure
 998  *
 999  *  Acquires the software control flag for performing PHY and select
1000  *  MAC CSR accesses.
1001  **/
1002 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1003 {
1004         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1005         s32 ret_val = E1000_SUCCESS;
1006
1007         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1008
1009         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1010
1011         while (timeout) {
1012                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1013                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1014                         break;
1015
1016                 msec_delay_irq(1);
1017                 timeout--;
1018         }
1019
1020         if (!timeout) {
1021                 DEBUGOUT("SW has already locked the resource.\n");
1022                 ret_val = -E1000_ERR_CONFIG;
1023                 goto out;
1024         }
1025
1026         timeout = SW_FLAG_TIMEOUT;
1027
1028         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1029         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1030
1031         while (timeout) {
1032                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1033                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1034                         break;
1035
1036                 msec_delay_irq(1);
1037                 timeout--;
1038         }
1039
1040         if (!timeout) {
1041                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1042                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1043                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1044                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1045                 ret_val = -E1000_ERR_CONFIG;
1046                 goto out;
1047         }
1048
1049 out:
1050         if (ret_val)
1051                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1052
1053         return ret_val;
1054 }
1055
1056 /**
1057  *  e1000_release_swflag_ich8lan - Release software control flag
1058  *  @hw: pointer to the HW structure
1059  *
1060  *  Releases the software control flag for performing PHY and select
1061  *  MAC CSR accesses.
1062  **/
1063 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1064 {
1065         u32 extcnf_ctrl;
1066
1067         DEBUGFUNC("e1000_release_swflag_ich8lan");
1068
1069         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1070
1071         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1072                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1073                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1074         } else {
1075                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1076         }
1077
1078         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1079
1080         return;
1081 }
1082
1083 /**
1084  *  e1000_check_mng_mode_ich8lan - Checks management mode
1085  *  @hw: pointer to the HW structure
1086  *
1087  *  This checks if the adapter has any manageability enabled.
1088  *  This is a function pointer entry point only called by read/write
1089  *  routines for the PHY and NVM parts.
1090  **/
1091 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1092 {
1093         u32 fwsm;
1094
1095         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1096
1097         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1098
1099         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1100                ((fwsm & E1000_FWSM_MODE_MASK) ==
1101                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1102 }
1103
1104 /**
1105  *  e1000_check_mng_mode_pchlan - Checks management mode
1106  *  @hw: pointer to the HW structure
1107  *
1108  *  This checks if the adapter has iAMT enabled.
1109  *  This is a function pointer entry point only called by read/write
1110  *  routines for the PHY and NVM parts.
1111  **/
1112 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1113 {
1114         u32 fwsm;
1115
1116         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1117
1118         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1119
1120         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1121                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1122 }
1123
1124 /**
1125  *  e1000_rar_set_pch2lan - Set receive address register
1126  *  @hw: pointer to the HW structure
1127  *  @addr: pointer to the receive address
1128  *  @index: receive address array register
1129  *
1130  *  Sets the receive address array register at index to the address passed
1131  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1132  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1133  *  Use SHRA[0-3] in place of those reserved for ME.
1134  **/
1135 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1136 {
1137         u32 rar_low, rar_high;
1138
1139         DEBUGFUNC("e1000_rar_set_pch2lan");
1140
1141         /* HW expects these in little endian so we reverse the byte order
1142          * from network order (big endian) to little endian
1143          */
1144         rar_low = ((u32) addr[0] |
1145                    ((u32) addr[1] << 8) |
1146                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1147
1148         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1149
1150         /* If MAC address zero, no need to set the AV bit */
1151         if (rar_low || rar_high)
1152                 rar_high |= E1000_RAH_AV;
1153
1154         if (index == 0) {
1155                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1156                 E1000_WRITE_FLUSH(hw);
1157                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1158                 E1000_WRITE_FLUSH(hw);
1159                 return;
1160         }
1161
1162         if (index < hw->mac.rar_entry_count) {
1163                 s32 ret_val;
1164
1165                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1166                 if (ret_val)
1167                         goto out;
1168
1169                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1170                 E1000_WRITE_FLUSH(hw);
1171                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1172                 E1000_WRITE_FLUSH(hw);
1173
1174                 e1000_release_swflag_ich8lan(hw);
1175
1176                 /* verify the register updates */
1177                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1178                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1179                         return;
1180
1181                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1182                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1183         }
1184
1185 out:
1186         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1187 }
1188
1189 /**
1190  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1191  *  @hw: pointer to the HW structure
1192  *
1193  *  Checks if firmware is blocking the reset of the PHY.
1194  *  This is a function pointer entry point only called by
1195  *  reset routines.
1196  **/
1197 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1198 {
1199         u32 fwsm;
1200
1201         DEBUGFUNC("e1000_check_reset_block_ich8lan");
1202
1203         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1204
1205         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
1206                                                 : E1000_BLK_PHY_RESET;
1207 }
1208
1209 /**
1210  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1211  *  @hw: pointer to the HW structure
1212  *
1213  *  Assumes semaphore already acquired.
1214  *
1215  **/
1216 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1217 {
1218         u16 phy_data;
1219         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
1220         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1221                 E1000_STRAP_SMT_FREQ_SHIFT;
1222         s32 ret_val = E1000_SUCCESS;
1223
1224         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1225
1226         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1227         if (ret_val)
1228                 return ret_val;
1229
1230         phy_data &= ~HV_SMB_ADDR_MASK;
1231         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1232         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1233
1234         if (hw->phy.type == e1000_phy_i217) {
1235                 /* Restore SMBus frequency */
1236                 if (freq--) {
1237                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1238                         phy_data |= (freq & (1 << 0)) <<
1239                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1240                         phy_data |= (freq & (1 << 1)) <<
1241                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1242                 } else {
1243                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
1244                 }
1245         }
1246
1247         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1248 }
1249
1250 /**
1251  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1252  *  @hw:   pointer to the HW structure
1253  *
1254  *  SW should configure the LCD from the NVM extended configuration region
1255  *  as a workaround for certain parts.
1256  **/
1257 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1258 {
1259         struct e1000_phy_info *phy = &hw->phy;
1260         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1261         s32 ret_val = E1000_SUCCESS;
1262         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1263
1264         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
1265
1266         /* Initialize the PHY from the NVM on ICH platforms.  This
1267          * is needed due to an issue where the NVM configuration is
1268          * not properly autoloaded after power transitions.
1269          * Therefore, after each PHY reset, we will load the
1270          * configuration data out of the NVM manually.
1271          */
1272         switch (hw->mac.type) {
1273         case e1000_ich8lan:
1274                 if (phy->type != e1000_phy_igp_3)
1275                         return ret_val;
1276
1277                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
1278                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
1279                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1280                         break;
1281                 }
1282                 /* Fall-thru */
1283         case e1000_pchlan:
1284         case e1000_pch2lan:
1285                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1286                 break;
1287         default:
1288                 return ret_val;
1289         }
1290
1291         ret_val = hw->phy.ops.acquire(hw);
1292         if (ret_val)
1293                 return ret_val;
1294
1295         data = E1000_READ_REG(hw, E1000_FEXTNVM);
1296         if (!(data & sw_cfg_mask))
1297                 goto release;
1298
1299         /* Make sure HW does not configure LCD from PHY
1300          * extended configuration before SW configuration
1301          */
1302         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1303         if ((hw->mac.type < e1000_pch2lan) &&
1304             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1305                         goto release;
1306
1307         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
1308         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1309         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1310         if (!cnf_size)
1311                 goto release;
1312
1313         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1314         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1315
1316         if (((hw->mac.type == e1000_pchlan) &&
1317              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1318             (hw->mac.type > e1000_pchlan)) {
1319                 /* HW configures the SMBus address and LEDs when the
1320                  * OEM and LCD Write Enable bits are set in the NVM.
1321                  * When both NVM bits are cleared, SW will configure
1322                  * them instead.
1323                  */
1324                 ret_val = e1000_write_smbus_addr(hw);
1325                 if (ret_val)
1326                         goto release;
1327
1328                 data = E1000_READ_REG(hw, E1000_LEDCTL);
1329                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1330                                                         (u16)data);
1331                 if (ret_val)
1332                         goto release;
1333         }
1334
1335         /* Configure LCD from extended configuration region. */
1336
1337         /* cnf_base_addr is in DWORD */
1338         word_addr = (u16)(cnf_base_addr << 1);
1339
1340         for (i = 0; i < cnf_size; i++) {
1341                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
1342                                            &reg_data);
1343                 if (ret_val)
1344                         goto release;
1345
1346                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
1347                                            1, &reg_addr);
1348                 if (ret_val)
1349                         goto release;
1350
1351                 /* Save off the PHY page for future writes. */
1352                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1353                         phy_page = reg_data;
1354                         continue;
1355                 }
1356
1357                 reg_addr &= PHY_REG_MASK;
1358                 reg_addr |= phy_page;
1359
1360                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1361                                                     reg_data);
1362                 if (ret_val)
1363                         goto release;
1364         }
1365
1366 release:
1367         hw->phy.ops.release(hw);
1368         return ret_val;
1369 }
1370
1371 /**
1372  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1373  *  @hw:   pointer to the HW structure
1374  *  @link: link up bool flag
1375  *
1376  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1377  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1378  *  If link is down, the function will restore the default K1 setting located
1379  *  in the NVM.
1380  **/
1381 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1382 {
1383         s32 ret_val = E1000_SUCCESS;
1384         u16 status_reg = 0;
1385         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1386
1387         DEBUGFUNC("e1000_k1_gig_workaround_hv");
1388
1389         if (hw->mac.type != e1000_pchlan)
1390                 return E1000_SUCCESS;
1391
1392         /* Wrap the whole flow with the sw flag */
1393         ret_val = hw->phy.ops.acquire(hw);
1394         if (ret_val)
1395                 return ret_val;
1396
1397         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1398         if (link) {
1399                 if (hw->phy.type == e1000_phy_82578) {
1400                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1401                                                               &status_reg);
1402                         if (ret_val)
1403                                 goto release;
1404
1405                         status_reg &= BM_CS_STATUS_LINK_UP |
1406                                       BM_CS_STATUS_RESOLVED |
1407                                       BM_CS_STATUS_SPEED_MASK;
1408
1409                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1410                                            BM_CS_STATUS_RESOLVED |
1411                                            BM_CS_STATUS_SPEED_1000))
1412                                 k1_enable = false;
1413                 }
1414
1415                 if (hw->phy.type == e1000_phy_82577) {
1416                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1417                                                               &status_reg);
1418                         if (ret_val)
1419                                 goto release;
1420
1421                         status_reg &= HV_M_STATUS_LINK_UP |
1422                                       HV_M_STATUS_AUTONEG_COMPLETE |
1423                                       HV_M_STATUS_SPEED_MASK;
1424
1425                         if (status_reg == (HV_M_STATUS_LINK_UP |
1426                                            HV_M_STATUS_AUTONEG_COMPLETE |
1427                                            HV_M_STATUS_SPEED_1000))
1428                                 k1_enable = false;
1429                 }
1430
1431                 /* Link stall fix for link up */
1432                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1433                                                        0x0100);
1434                 if (ret_val)
1435                         goto release;
1436
1437         } else {
1438                 /* Link stall fix for link down */
1439                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1440                                                        0x4100);
1441                 if (ret_val)
1442                         goto release;
1443         }
1444
1445         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1446
1447 release:
1448         hw->phy.ops.release(hw);
1449
1450         return ret_val;
1451 }
1452
1453 /**
1454  *  e1000_configure_k1_ich8lan - Configure K1 power state
1455  *  @hw: pointer to the HW structure
1456  *  @enable: K1 state to configure
1457  *
1458  *  Configure the K1 power state based on the provided parameter.
1459  *  Assumes semaphore already acquired.
1460  *
1461  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1462  **/
1463 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1464 {
1465         s32 ret_val = E1000_SUCCESS;
1466         u32 ctrl_reg = 0;
1467         u32 ctrl_ext = 0;
1468         u32 reg = 0;
1469         u16 kmrn_reg = 0;
1470
1471         DEBUGFUNC("e1000_configure_k1_ich8lan");
1472
1473         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1474                                              &kmrn_reg);
1475         if (ret_val)
1476                 return ret_val;
1477
1478         if (k1_enable)
1479                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1480         else
1481                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1482
1483         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1484                                               kmrn_reg);
1485         if (ret_val)
1486                 return ret_val;
1487
1488         usec_delay(20);
1489         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1490         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1491
1492         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1493         reg |= E1000_CTRL_FRCSPD;
1494         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1495
1496         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1497         E1000_WRITE_FLUSH(hw);
1498         usec_delay(20);
1499         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1500         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1501         E1000_WRITE_FLUSH(hw);
1502         usec_delay(20);
1503
1504         return E1000_SUCCESS;
1505 }
1506
1507 /**
1508  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1509  *  @hw:       pointer to the HW structure
1510  *  @d0_state: boolean if entering d0 or d3 device state
1511  *
1512  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1513  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1514  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1515  **/
1516 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1517 {
1518         s32 ret_val = 0;
1519         u32 mac_reg;
1520         u16 oem_reg;
1521
1522         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
1523
1524         if (hw->mac.type < e1000_pchlan)
1525                 return ret_val;
1526
1527         ret_val = hw->phy.ops.acquire(hw);
1528         if (ret_val)
1529                 return ret_val;
1530
1531         if (hw->mac.type == e1000_pchlan) {
1532                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1533                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1534                         goto release;
1535         }
1536
1537         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
1538         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1539                 goto release;
1540
1541         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
1542
1543         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1544         if (ret_val)
1545                 goto release;
1546
1547         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1548
1549         if (d0_state) {
1550                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1551                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1552
1553                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1554                         oem_reg |= HV_OEM_BITS_LPLU;
1555         } else {
1556                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1557                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1558                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1559
1560                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1561                     E1000_PHY_CTRL_NOND0A_LPLU))
1562                         oem_reg |= HV_OEM_BITS_LPLU;
1563         }
1564
1565         /* Set Restart auto-neg to activate the bits */
1566         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1567             !hw->phy.ops.check_reset_block(hw))
1568                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1569
1570         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1571
1572 release:
1573         hw->phy.ops.release(hw);
1574
1575         return ret_val;
1576 }
1577
1578
1579 /**
1580  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1581  *  @hw:   pointer to the HW structure
1582  **/
1583 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1584 {
1585         s32 ret_val;
1586         u16 data;
1587
1588         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
1589
1590         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
1591         if (ret_val)
1592                 return ret_val;
1593
1594         data |= HV_KMRN_MDIO_SLOW;
1595
1596         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
1597
1598         return ret_val;
1599 }
1600
1601 /**
1602  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1603  *  done after every PHY reset.
1604  **/
1605 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1606 {
1607         s32 ret_val = E1000_SUCCESS;
1608         u16 phy_data;
1609
1610         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
1611
1612         if (hw->mac.type != e1000_pchlan)
1613                 return E1000_SUCCESS;
1614
1615         /* Set MDIO slow mode before any other MDIO access */
1616         if (hw->phy.type == e1000_phy_82577) {
1617                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1618                 if (ret_val)
1619                         return ret_val;
1620         }
1621
1622         if (((hw->phy.type == e1000_phy_82577) &&
1623              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1624             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1625                 /* Disable generation of early preamble */
1626                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1627                 if (ret_val)
1628                         return ret_val;
1629
1630                 /* Preamble tuning for SSC */
1631                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
1632                                                 0xA204);
1633                 if (ret_val)
1634                         return ret_val;
1635         }
1636
1637         if (hw->phy.type == e1000_phy_82578) {
1638                 /* Return registers to default by doing a soft reset then
1639                  * writing 0x3140 to the control register.
1640                  */
1641                 if (hw->phy.revision < 2) {
1642                         e1000_phy_sw_reset_generic(hw);
1643                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
1644                                                         0x3140);
1645                 }
1646         }
1647
1648         /* Select page 0 */
1649         ret_val = hw->phy.ops.acquire(hw);
1650         if (ret_val)
1651                 return ret_val;
1652
1653         hw->phy.addr = 1;
1654         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1655         hw->phy.ops.release(hw);
1656         if (ret_val)
1657                 return ret_val;
1658
1659         /* Configure the K1 Si workaround during phy reset assuming there is
1660          * link so that it disables K1 if link is in 1Gbps.
1661          */
1662         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1663         if (ret_val)
1664                 return ret_val;
1665
1666         /* Workaround for link disconnects on a busy hub in half duplex */
1667         ret_val = hw->phy.ops.acquire(hw);
1668         if (ret_val)
1669                 return ret_val;
1670         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1671         if (ret_val)
1672                 goto release;
1673         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1674                                                phy_data & 0x00FF);
1675         if (ret_val)
1676                 goto release;
1677
1678         /* set MSE higher to enable link to stay up when noise is high */
1679         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1680 release:
1681         hw->phy.ops.release(hw);
1682
1683         return ret_val;
1684 }
1685
1686 /**
1687  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1688  *  @hw:   pointer to the HW structure
1689  **/
1690 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1691 {
1692         u32 mac_reg;
1693         u16 i, phy_reg = 0;
1694         s32 ret_val;
1695
1696         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
1697
1698         ret_val = hw->phy.ops.acquire(hw);
1699         if (ret_val)
1700                 return;
1701         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1702         if (ret_val)
1703                 goto release;
1704
1705         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1706         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1707                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
1708                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1709                                            (u16)(mac_reg & 0xFFFF));
1710                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1711                                            (u16)((mac_reg >> 16) & 0xFFFF));
1712
1713                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
1714                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1715                                            (u16)(mac_reg & 0xFFFF));
1716                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1717                                            (u16)((mac_reg & E1000_RAH_AV)
1718                                                  >> 16));
1719         }
1720
1721         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1722
1723 release:
1724         hw->phy.ops.release(hw);
1725 }
1726
1727 static u32 e1000_calc_rx_da_crc(u8 mac[])
1728 {
1729         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
1730         u32 i, j, mask, crc;
1731
1732         DEBUGFUNC("e1000_calc_rx_da_crc");
1733
1734         crc = 0xffffffff;
1735         for (i = 0; i < 6; i++) {
1736                 crc = crc ^ mac[i];
1737                 for (j = 8; j > 0; j--) {
1738                         mask = (crc & 1) * (-1);
1739                         crc = (crc >> 1) ^ (poly & mask);
1740                 }
1741         }
1742         return ~crc;
1743 }
1744
1745 /**
1746  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1747  *  with 82579 PHY
1748  *  @hw: pointer to the HW structure
1749  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1750  **/
1751 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1752 {
1753         s32 ret_val = E1000_SUCCESS;
1754         u16 phy_reg, data;
1755         u32 mac_reg;
1756         u16 i;
1757
1758         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
1759
1760         if (hw->mac.type != e1000_pch2lan)
1761                 return E1000_SUCCESS;
1762
1763         /* disable Rx path while enabling/disabling workaround */
1764         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
1765         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
1766                                         phy_reg | (1 << 14));
1767         if (ret_val)
1768                 return ret_val;
1769
1770         if (enable) {
1771                 /* Write Rx addresses (rar_entry_count for RAL/H, and
1772                  * SHRAL/H) and initial CRC values to the MAC
1773                  */
1774                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1775                         u8 mac_addr[ETH_ADDR_LEN] = {0};
1776                         u32 addr_high, addr_low;
1777
1778                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
1779                         if (!(addr_high & E1000_RAH_AV))
1780                                 continue;
1781                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
1782                         mac_addr[0] = (addr_low & 0xFF);
1783                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1784                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1785                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1786                         mac_addr[4] = (addr_high & 0xFF);
1787                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1788
1789                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
1790                                         e1000_calc_rx_da_crc(mac_addr));
1791                 }
1792
1793                 /* Write Rx addresses to the PHY */
1794                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1795
1796                 /* Enable jumbo frame workaround in the MAC */
1797                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
1798                 mac_reg &= ~(1 << 14);
1799                 mac_reg |= (7 << 15);
1800                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
1801
1802                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
1803                 mac_reg |= E1000_RCTL_SECRC;
1804                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
1805
1806                 ret_val = e1000_read_kmrn_reg_generic(hw,
1807                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1808                                                 &data);
1809                 if (ret_val)
1810                         return ret_val;
1811                 ret_val = e1000_write_kmrn_reg_generic(hw,
1812                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1813                                                 data | (1 << 0));
1814                 if (ret_val)
1815                         return ret_val;
1816                 ret_val = e1000_read_kmrn_reg_generic(hw,
1817                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1818                                                 &data);
1819                 if (ret_val)
1820                         return ret_val;
1821                 data &= ~(0xF << 8);
1822                 data |= (0xB << 8);
1823                 ret_val = e1000_write_kmrn_reg_generic(hw,
1824                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1825                                                 data);
1826                 if (ret_val)
1827                         return ret_val;
1828
1829                 /* Enable jumbo frame workaround in the PHY */
1830                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
1831                 data &= ~(0x7F << 5);
1832                 data |= (0x37 << 5);
1833                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
1834                 if (ret_val)
1835                         return ret_val;
1836                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
1837                 data &= ~(1 << 13);
1838                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
1839                 if (ret_val)
1840                         return ret_val;
1841                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
1842                 data &= ~(0x3FF << 2);
1843                 data |= (0x1A << 2);
1844                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1845                 if (ret_val)
1846                         return ret_val;
1847                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
1848                 if (ret_val)
1849                         return ret_val;
1850                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1851                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
1852                                                 (1 << 10));
1853                 if (ret_val)
1854                         return ret_val;
1855         } else {
1856                 /* Write MAC register values back to h/w defaults */
1857                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
1858                 mac_reg &= ~(0xF << 14);
1859                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
1860
1861                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
1862                 mac_reg &= ~E1000_RCTL_SECRC;
1863                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
1864
1865                 ret_val = e1000_read_kmrn_reg_generic(hw,
1866                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1867                                                 &data);
1868                 if (ret_val)
1869                         return ret_val;
1870                 ret_val = e1000_write_kmrn_reg_generic(hw,
1871                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1872                                                 data & ~(1 << 0));
1873                 if (ret_val)
1874                         return ret_val;
1875                 ret_val = e1000_read_kmrn_reg_generic(hw,
1876                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1877                                                 &data);
1878                 if (ret_val)
1879                         return ret_val;
1880                 data &= ~(0xF << 8);
1881                 data |= (0xB << 8);
1882                 ret_val = e1000_write_kmrn_reg_generic(hw,
1883                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1884                                                 data);
1885                 if (ret_val)
1886                         return ret_val;
1887
1888                 /* Write PHY register values back to h/w defaults */
1889                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
1890                 data &= ~(0x7F << 5);
1891                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
1892                 if (ret_val)
1893                         return ret_val;
1894                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
1895                 data |= (1 << 13);
1896                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
1897                 if (ret_val)
1898                         return ret_val;
1899                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
1900                 data &= ~(0x3FF << 2);
1901                 data |= (0x8 << 2);
1902                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1903                 if (ret_val)
1904                         return ret_val;
1905                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
1906                 if (ret_val)
1907                         return ret_val;
1908                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1909                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
1910                                                 ~(1 << 10));
1911                 if (ret_val)
1912                         return ret_val;
1913         }
1914
1915         /* re-enable Rx path after enabling/disabling workaround */
1916         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
1917                                      ~(1 << 14));
1918 }
1919
1920 /**
1921  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1922  *  done after every PHY reset.
1923  **/
1924 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1925 {
1926         s32 ret_val = E1000_SUCCESS;
1927
1928         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
1929
1930         if (hw->mac.type != e1000_pch2lan)
1931                 return E1000_SUCCESS;
1932
1933         /* Set MDIO slow mode before any other MDIO access */
1934         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1935         if (ret_val)
1936                 return ret_val;
1937
1938         ret_val = hw->phy.ops.acquire(hw);
1939         if (ret_val)
1940                 return ret_val;
1941         /* set MSE higher to enable link to stay up when noise is high */
1942         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
1943         if (ret_val)
1944                 goto release;
1945         /* drop link after 5 times MSE threshold was reached */
1946         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
1947 release:
1948         hw->phy.ops.release(hw);
1949
1950         return ret_val;
1951 }
1952
1953 /**
1954  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1955  *  @hw:   pointer to the HW structure
1956  *
1957  *  Workaround to set the K1 beacon duration for 82579 parts
1958  **/
1959 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1960 {
1961         s32 ret_val = E1000_SUCCESS;
1962         u16 status_reg = 0;
1963         u32 mac_reg;
1964         u16 phy_reg;
1965
1966         DEBUGFUNC("e1000_k1_workaround_lv");
1967
1968         if (hw->mac.type != e1000_pch2lan)
1969                 return E1000_SUCCESS;
1970
1971         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1972         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
1973         if (ret_val)
1974                 return ret_val;
1975
1976         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1977             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1978                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1979                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1980
1981                 ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
1982                 if (ret_val)
1983                         return ret_val;
1984
1985                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1986                         u16 pm_phy_reg;
1987
1988                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1989                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1990                         /* LV 1G Packet drop issue wa  */
1991                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
1992                                                        &pm_phy_reg);
1993                         if (ret_val)
1994                                 return ret_val;
1995                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
1996                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
1997                                                         pm_phy_reg);
1998                         if (ret_val)
1999                                 return ret_val;
2000                 } else {
2001                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2002                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2003                 }
2004                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2005                 ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
2006         }
2007
2008         return ret_val;
2009 }
2010
2011 /**
2012  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2013  *  @hw:   pointer to the HW structure
2014  *  @gate: boolean set to true to gate, false to ungate
2015  *
2016  *  Gate/ungate the automatic PHY configuration via hardware; perform
2017  *  the configuration via software instead.
2018  **/
2019 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2020 {
2021         u32 extcnf_ctrl;
2022
2023         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2024
2025         if (hw->mac.type != e1000_pch2lan)
2026                 return;
2027
2028         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2029
2030         if (gate)
2031                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2032         else
2033                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2034
2035         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2036 }
2037
2038 /**
2039  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2040  *  @hw: pointer to the HW structure
2041  *
2042  *  Check the appropriate indication the MAC has finished configuring the
2043  *  PHY after a software reset.
2044  **/
2045 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2046 {
2047         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2048
2049         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2050
2051         /* Wait for basic configuration completes before proceeding */
2052         do {
2053                 data = E1000_READ_REG(hw, E1000_STATUS);
2054                 data &= E1000_STATUS_LAN_INIT_DONE;
2055                 usec_delay(100);
2056         } while ((!data) && --loop);
2057
2058         /* If basic configuration is incomplete before the above loop
2059          * count reaches 0, loading the configuration from NVM will
2060          * leave the PHY in a bad state possibly resulting in no link.
2061          */
2062         if (loop == 0)
2063                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2064
2065         /* Clear the Init Done bit for the next init event */
2066         data = E1000_READ_REG(hw, E1000_STATUS);
2067         data &= ~E1000_STATUS_LAN_INIT_DONE;
2068         E1000_WRITE_REG(hw, E1000_STATUS, data);
2069 }
2070
2071 /**
2072  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2073  *  @hw: pointer to the HW structure
2074  **/
2075 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2076 {
2077         s32 ret_val = E1000_SUCCESS;
2078         u16 reg;
2079
2080         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2081
2082         if (hw->phy.ops.check_reset_block(hw))
2083                 return E1000_SUCCESS;
2084
2085         /* Allow time for h/w to get to quiescent state after reset */
2086         msec_delay(10);
2087
2088         /* Perform any necessary post-reset workarounds */
2089         switch (hw->mac.type) {
2090         case e1000_pchlan:
2091                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2092                 if (ret_val)
2093                         return ret_val;
2094                 break;
2095         case e1000_pch2lan:
2096                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2097                 if (ret_val)
2098                         return ret_val;
2099                 break;
2100         default:
2101                 break;
2102         }
2103
2104         /* Clear the host wakeup bit after lcd reset */
2105         if (hw->mac.type >= e1000_pchlan) {
2106                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2107                 reg &= ~BM_WUC_HOST_WU_BIT;
2108                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2109         }
2110
2111         /* Configure the LCD with the extended configuration region in NVM */
2112         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2113         if (ret_val)
2114                 return ret_val;
2115
2116         /* Configure the LCD with the OEM bits in NVM */
2117         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2118
2119         if (hw->mac.type == e1000_pch2lan) {
2120                 /* Ungate automatic PHY configuration on non-managed 82579 */
2121                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2122                     E1000_ICH_FWSM_FW_VALID)) {
2123                         msec_delay(10);
2124                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2125                 }
2126
2127                 /* Set EEE LPI Update Timer to 200usec */
2128                 ret_val = hw->phy.ops.acquire(hw);
2129                 if (ret_val)
2130                         return ret_val;
2131                 ret_val = e1000_write_emi_reg_locked(hw,
2132                                                      I82579_LPI_UPDATE_TIMER,
2133                                                      0x1387);
2134                 hw->phy.ops.release(hw);
2135         }
2136
2137         return ret_val;
2138 }
2139
2140 /**
2141  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2142  *  @hw: pointer to the HW structure
2143  *
2144  *  Resets the PHY
2145  *  This is a function pointer entry point called by drivers
2146  *  or other shared routines.
2147  **/
2148 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2149 {
2150         s32 ret_val = E1000_SUCCESS;
2151
2152         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2153
2154         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2155         if ((hw->mac.type == e1000_pch2lan) &&
2156             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2157                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2158
2159         ret_val = e1000_phy_hw_reset_generic(hw);
2160         if (ret_val)
2161                 return ret_val;
2162
2163         return e1000_post_phy_reset_ich8lan(hw);
2164 }
2165
2166 /**
2167  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2168  *  @hw: pointer to the HW structure
2169  *  @active: true to enable LPLU, false to disable
2170  *
2171  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2172  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2173  *  the phy speed. This function will manually set the LPLU bit and restart
2174  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2175  *  since it configures the same bit.
2176  **/
2177 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2178 {
2179         s32 ret_val = E1000_SUCCESS;
2180         u16 oem_reg;
2181
2182         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2183
2184         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2185         if (ret_val)
2186                 return ret_val;
2187
2188         if (active)
2189                 oem_reg |= HV_OEM_BITS_LPLU;
2190         else
2191                 oem_reg &= ~HV_OEM_BITS_LPLU;
2192
2193         if (!hw->phy.ops.check_reset_block(hw))
2194                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2195
2196         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2197 }
2198
2199 /**
2200  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2201  *  @hw: pointer to the HW structure
2202  *  @active: true to enable LPLU, false to disable
2203  *
2204  *  Sets the LPLU D0 state according to the active flag.  When
2205  *  activating LPLU this function also disables smart speed
2206  *  and vice versa.  LPLU will not be activated unless the
2207  *  device autonegotiation advertisement meets standards of
2208  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2209  *  This is a function pointer entry point only called by
2210  *  PHY setup routines.
2211  **/
2212 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2213 {
2214         struct e1000_phy_info *phy = &hw->phy;
2215         u32 phy_ctrl;
2216         s32 ret_val = E1000_SUCCESS;
2217         u16 data;
2218
2219         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
2220
2221         if (phy->type == e1000_phy_ife)
2222                 return E1000_SUCCESS;
2223
2224         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2225
2226         if (active) {
2227                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2228                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2229
2230                 if (phy->type != e1000_phy_igp_3)
2231                         return E1000_SUCCESS;
2232
2233                 /* Call gig speed drop workaround on LPLU before accessing
2234                  * any PHY registers
2235                  */
2236                 if (hw->mac.type == e1000_ich8lan)
2237                         e1000_gig_downshift_workaround_ich8lan(hw);
2238
2239                 /* When LPLU is enabled, we should disable SmartSpeed */
2240                 ret_val = phy->ops.read_reg(hw,
2241                                             IGP01E1000_PHY_PORT_CONFIG,
2242                                             &data);
2243                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2244                 ret_val = phy->ops.write_reg(hw,
2245                                              IGP01E1000_PHY_PORT_CONFIG,
2246                                              data);
2247                 if (ret_val)
2248                         return ret_val;
2249         } else {
2250                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2251                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2252
2253                 if (phy->type != e1000_phy_igp_3)
2254                         return E1000_SUCCESS;
2255
2256                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2257                  * during Dx states where the power conservation is most
2258                  * important.  During driver activity we should enable
2259                  * SmartSpeed, so performance is maintained.
2260                  */
2261                 if (phy->smart_speed == e1000_smart_speed_on) {
2262                         ret_val = phy->ops.read_reg(hw,
2263                                                     IGP01E1000_PHY_PORT_CONFIG,
2264                                                     &data);
2265                         if (ret_val)
2266                                 return ret_val;
2267
2268                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2269                         ret_val = phy->ops.write_reg(hw,
2270                                                      IGP01E1000_PHY_PORT_CONFIG,
2271                                                      data);
2272                         if (ret_val)
2273                                 return ret_val;
2274                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2275                         ret_val = phy->ops.read_reg(hw,
2276                                                     IGP01E1000_PHY_PORT_CONFIG,
2277                                                     &data);
2278                         if (ret_val)
2279                                 return ret_val;
2280
2281                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2282                         ret_val = phy->ops.write_reg(hw,
2283                                                      IGP01E1000_PHY_PORT_CONFIG,
2284                                                      data);
2285                         if (ret_val)
2286                                 return ret_val;
2287                 }
2288         }
2289
2290         return E1000_SUCCESS;
2291 }
2292
2293 /**
2294  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2295  *  @hw: pointer to the HW structure
2296  *  @active: true to enable LPLU, false to disable
2297  *
2298  *  Sets the LPLU D3 state according to the active flag.  When
2299  *  activating LPLU this function also disables smart speed
2300  *  and vice versa.  LPLU will not be activated unless the
2301  *  device autonegotiation advertisement meets standards of
2302  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2303  *  This is a function pointer entry point only called by
2304  *  PHY setup routines.
2305  **/
2306 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2307 {
2308         struct e1000_phy_info *phy = &hw->phy;
2309         u32 phy_ctrl;
2310         s32 ret_val = E1000_SUCCESS;
2311         u16 data;
2312
2313         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
2314
2315         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2316
2317         if (!active) {
2318                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2319                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2320
2321                 if (phy->type != e1000_phy_igp_3)
2322                         return E1000_SUCCESS;
2323
2324                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2325                  * during Dx states where the power conservation is most
2326                  * important.  During driver activity we should enable
2327                  * SmartSpeed, so performance is maintained.
2328                  */
2329                 if (phy->smart_speed == e1000_smart_speed_on) {
2330                         ret_val = phy->ops.read_reg(hw,
2331                                                     IGP01E1000_PHY_PORT_CONFIG,
2332                                                     &data);
2333                         if (ret_val)
2334                                 return ret_val;
2335
2336                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2337                         ret_val = phy->ops.write_reg(hw,
2338                                                      IGP01E1000_PHY_PORT_CONFIG,
2339                                                      data);
2340                         if (ret_val)
2341                                 return ret_val;
2342                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2343                         ret_val = phy->ops.read_reg(hw,
2344                                                     IGP01E1000_PHY_PORT_CONFIG,
2345                                                     &data);
2346                         if (ret_val)
2347                                 return ret_val;
2348
2349                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2350                         ret_val = phy->ops.write_reg(hw,
2351                                                      IGP01E1000_PHY_PORT_CONFIG,
2352                                                      data);
2353                         if (ret_val)
2354                                 return ret_val;
2355                 }
2356         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2357                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2358                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2359                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2360                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2361
2362                 if (phy->type != e1000_phy_igp_3)
2363                         return E1000_SUCCESS;
2364
2365                 /* Call gig speed drop workaround on LPLU before accessing
2366                  * any PHY registers
2367                  */
2368                 if (hw->mac.type == e1000_ich8lan)
2369                         e1000_gig_downshift_workaround_ich8lan(hw);
2370
2371                 /* When LPLU is enabled, we should disable SmartSpeed */
2372                 ret_val = phy->ops.read_reg(hw,
2373                                             IGP01E1000_PHY_PORT_CONFIG,
2374                                             &data);
2375                 if (ret_val)
2376                         return ret_val;
2377
2378                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2379                 ret_val = phy->ops.write_reg(hw,
2380                                              IGP01E1000_PHY_PORT_CONFIG,
2381                                              data);
2382         }
2383
2384         return ret_val;
2385 }
2386
2387 /**
2388  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2389  *  @hw: pointer to the HW structure
2390  *  @bank:  pointer to the variable that returns the active bank
2391  *
2392  *  Reads signature byte from the NVM using the flash access registers.
2393  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2394  **/
2395 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2396 {
2397         u32 eecd;
2398         struct e1000_nvm_info *nvm = &hw->nvm;
2399         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2400         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2401         u8 sig_byte = 0;
2402         s32 ret_val;
2403
2404         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
2405
2406         switch (hw->mac.type) {
2407         case e1000_ich8lan:
2408         case e1000_ich9lan:
2409                 eecd = E1000_READ_REG(hw, E1000_EECD);
2410                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2411                     E1000_EECD_SEC1VAL_VALID_MASK) {
2412                         if (eecd & E1000_EECD_SEC1VAL)
2413                                 *bank = 1;
2414                         else
2415                                 *bank = 0;
2416
2417                         return E1000_SUCCESS;
2418                 }
2419                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2420                 /* fall-thru */
2421         default:
2422                 /* set bank to 0 in case flash read fails */
2423                 *bank = 0;
2424
2425                 /* Check bank 0 */
2426                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2427                                                         &sig_byte);
2428                 if (ret_val)
2429                         return ret_val;
2430                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2431                     E1000_ICH_NVM_SIG_VALUE) {
2432                         *bank = 0;
2433                         return E1000_SUCCESS;
2434                 }
2435
2436                 /* Check bank 1 */
2437                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2438                                                         bank1_offset,
2439                                                         &sig_byte);
2440                 if (ret_val)
2441                         return ret_val;
2442                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2443                     E1000_ICH_NVM_SIG_VALUE) {
2444                         *bank = 1;
2445                         return E1000_SUCCESS;
2446                 }
2447
2448                 DEBUGOUT("ERROR: No valid NVM bank present\n");
2449                 return -E1000_ERR_NVM;
2450         }
2451 }
2452
2453 /**
2454  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2455  *  @hw: pointer to the HW structure
2456  *  @offset: The offset (in bytes) of the word(s) to read.
2457  *  @words: Size of data to read in words
2458  *  @data: Pointer to the word(s) to read at offset.
2459  *
2460  *  Reads a word(s) from the NVM using the flash access registers.
2461  **/
2462 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2463                                   u16 *data)
2464 {
2465         struct e1000_nvm_info *nvm = &hw->nvm;
2466         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2467         u32 act_offset;
2468         s32 ret_val = E1000_SUCCESS;
2469         u32 bank = 0;
2470         u16 i, word;
2471
2472         DEBUGFUNC("e1000_read_nvm_ich8lan");
2473
2474         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2475             (words == 0)) {
2476                 DEBUGOUT("nvm parameter(s) out of bounds\n");
2477                 ret_val = -E1000_ERR_NVM;
2478                 goto out;
2479         }
2480
2481         nvm->ops.acquire(hw);
2482
2483         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2484         if (ret_val != E1000_SUCCESS) {
2485                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
2486                 bank = 0;
2487         }
2488
2489         act_offset = (bank) ? nvm->flash_bank_size : 0;
2490         act_offset += offset;
2491
2492         ret_val = E1000_SUCCESS;
2493         for (i = 0; i < words; i++) {
2494                 if (dev_spec->shadow_ram[offset+i].modified) {
2495                         data[i] = dev_spec->shadow_ram[offset+i].value;
2496                 } else {
2497                         ret_val = e1000_read_flash_word_ich8lan(hw,
2498                                                                 act_offset + i,
2499                                                                 &word);
2500                         if (ret_val)
2501                                 break;
2502                         data[i] = word;
2503                 }
2504         }
2505
2506         nvm->ops.release(hw);
2507
2508 out:
2509         if (ret_val)
2510                 DEBUGOUT1("NVM read error: %d\n", ret_val);
2511
2512         return ret_val;
2513 }
2514
2515 /**
2516  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2517  *  @hw: pointer to the HW structure
2518  *
2519  *  This function does initial flash setup so that a new read/write/erase cycle
2520  *  can be started.
2521  **/
2522 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2523 {
2524         union ich8_hws_flash_status hsfsts;
2525         s32 ret_val = -E1000_ERR_NVM;
2526
2527         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
2528
2529         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2530
2531         /* Check if the flash descriptor is valid */
2532         if (!hsfsts.hsf_status.fldesvalid) {
2533                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
2534                 return -E1000_ERR_NVM;
2535         }
2536
2537         /* Clear FCERR and DAEL in hw status by writing 1 */
2538         hsfsts.hsf_status.flcerr = 1;
2539         hsfsts.hsf_status.dael = 1;
2540
2541         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
2542
2543         /* Either we should have a hardware SPI cycle in progress
2544          * bit to check against, in order to start a new cycle or
2545          * FDONE bit should be changed in the hardware so that it
2546          * is 1 after hardware reset, which can then be used as an
2547          * indication whether a cycle is in progress or has been
2548          * completed.
2549          */
2550
2551         if (!hsfsts.hsf_status.flcinprog) {
2552                 /* There is no cycle running at present,
2553                  * so we can start a cycle.
2554                  * Begin by setting Flash Cycle Done.
2555                  */
2556                 hsfsts.hsf_status.flcdone = 1;
2557                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
2558                 ret_val = E1000_SUCCESS;
2559         } else {
2560                 s32 i;
2561
2562                 /* Otherwise poll for sometime so the current
2563                  * cycle has a chance to end before giving up.
2564                  */
2565                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2566                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2567                                                               ICH_FLASH_HSFSTS);
2568                         if (!hsfsts.hsf_status.flcinprog) {
2569                                 ret_val = E1000_SUCCESS;
2570                                 break;
2571                         }
2572                         usec_delay(1);
2573                 }
2574                 if (ret_val == E1000_SUCCESS) {
2575                         /* Successful in waiting for previous cycle to timeout,
2576                          * now set the Flash Cycle Done.
2577                          */
2578                         hsfsts.hsf_status.flcdone = 1;
2579                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
2580                                                 hsfsts.regval);
2581                 } else {
2582                         DEBUGOUT("Flash controller busy, cannot get access\n");
2583                 }
2584         }
2585
2586         return ret_val;
2587 }
2588
2589 /**
2590  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2591  *  @hw: pointer to the HW structure
2592  *  @timeout: maximum time to wait for completion
2593  *
2594  *  This function starts a flash cycle and waits for its completion.
2595  **/
2596 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2597 {
2598         union ich8_hws_flash_ctrl hsflctl;
2599         union ich8_hws_flash_status hsfsts;
2600         u32 i = 0;
2601
2602         DEBUGFUNC("e1000_flash_cycle_ich8lan");
2603
2604         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2605         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
2606         hsflctl.hsf_ctrl.flcgo = 1;
2607         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
2608
2609         /* wait till FDONE bit is set to 1 */
2610         do {
2611                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2612                 if (hsfsts.hsf_status.flcdone)
2613                         break;
2614                 usec_delay(1);
2615         } while (i++ < timeout);
2616
2617         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2618                 return E1000_SUCCESS;
2619
2620         return -E1000_ERR_NVM;
2621 }
2622
2623 /**
2624  *  e1000_read_flash_word_ich8lan - Read word from flash
2625  *  @hw: pointer to the HW structure
2626  *  @offset: offset to data location
2627  *  @data: pointer to the location for storing the data
2628  *
2629  *  Reads the flash word at offset into data.  Offset is converted
2630  *  to bytes before read.
2631  **/
2632 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2633                                          u16 *data)
2634 {
2635         DEBUGFUNC("e1000_read_flash_word_ich8lan");
2636
2637         if (!data)
2638                 return -E1000_ERR_NVM;
2639
2640         /* Must convert offset into bytes. */
2641         offset <<= 1;
2642
2643         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2644 }
2645
2646 /**
2647  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2648  *  @hw: pointer to the HW structure
2649  *  @offset: The offset of the byte to read.
2650  *  @data: Pointer to a byte to store the value read.
2651  *
2652  *  Reads a single byte from the NVM using the flash access registers.
2653  **/
2654 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2655                                          u8 *data)
2656 {
2657         s32 ret_val;
2658         u16 word = 0;
2659
2660         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2661         if (ret_val)
2662                 return ret_val;
2663
2664         *data = (u8)word;
2665
2666         return E1000_SUCCESS;
2667 }
2668
2669 /**
2670  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2671  *  @hw: pointer to the HW structure
2672  *  @offset: The offset (in bytes) of the byte or word to read.
2673  *  @size: Size of data to read, 1=byte 2=word
2674  *  @data: Pointer to the word to store the value read.
2675  *
2676  *  Reads a byte or word from the NVM using the flash access registers.
2677  **/
2678 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2679                                          u8 size, u16 *data)
2680 {
2681         union ich8_hws_flash_status hsfsts;
2682         union ich8_hws_flash_ctrl hsflctl;
2683         u32 flash_linear_addr;
2684         u32 flash_data = 0;
2685         s32 ret_val = -E1000_ERR_NVM;
2686         u8 count = 0;
2687
2688         DEBUGFUNC("e1000_read_flash_data_ich8lan");
2689
2690         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2691                 return -E1000_ERR_NVM;
2692
2693         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2694                             hw->nvm.flash_base_addr;
2695
2696         do {
2697                 usec_delay(1);
2698                 /* Steps */
2699                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2700                 if (ret_val != E1000_SUCCESS)
2701                         break;
2702
2703                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
2704                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2705                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2706                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2707                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
2708
2709                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
2710
2711                 ret_val = e1000_flash_cycle_ich8lan(hw,
2712                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2713
2714                 /* Check if FCERR is set to 1, if set to 1, clear it
2715                  * and try the whole sequence a few more times, else
2716                  * read in (shift in) the Flash Data0, the order is
2717                  * least significant byte first msb to lsb
2718                  */
2719                 if (ret_val == E1000_SUCCESS) {
2720                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
2721                         if (size == 1)
2722                                 *data = (u8)(flash_data & 0x000000FF);
2723                         else if (size == 2)
2724                                 *data = (u16)(flash_data & 0x0000FFFF);
2725                         break;
2726                 } else {
2727                         /* If we've gotten here, then things are probably
2728                          * completely hosed, but if the error condition is
2729                          * detected, it won't hurt to give it another try...
2730                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2731                          */
2732                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2733                                                               ICH_FLASH_HSFSTS);
2734                         if (hsfsts.hsf_status.flcerr) {
2735                                 /* Repeat for some time before giving up. */
2736                                 continue;
2737                         } else if (!hsfsts.hsf_status.flcdone) {
2738                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
2739                                 break;
2740                         }
2741                 }
2742         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2743
2744         return ret_val;
2745 }
2746
2747 /**
2748  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2749  *  @hw: pointer to the HW structure
2750  *  @offset: The offset (in bytes) of the word(s) to write.
2751  *  @words: Size of data to write in words
2752  *  @data: Pointer to the word(s) to write at offset.
2753  *
2754  *  Writes a byte or word to the NVM using the flash access registers.
2755  **/
2756 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2757                                    u16 *data)
2758 {
2759         struct e1000_nvm_info *nvm = &hw->nvm;
2760         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2761         u16 i;
2762
2763         DEBUGFUNC("e1000_write_nvm_ich8lan");
2764
2765         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2766             (words == 0)) {
2767                 DEBUGOUT("nvm parameter(s) out of bounds\n");
2768                 return -E1000_ERR_NVM;
2769         }
2770
2771         nvm->ops.acquire(hw);
2772
2773         for (i = 0; i < words; i++) {
2774                 dev_spec->shadow_ram[offset+i].modified = true;
2775                 dev_spec->shadow_ram[offset+i].value = data[i];
2776         }
2777
2778         nvm->ops.release(hw);
2779
2780         return E1000_SUCCESS;
2781 }
2782
2783 /**
2784  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2785  *  @hw: pointer to the HW structure
2786  *
2787  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2788  *  which writes the checksum to the shadow ram.  The changes in the shadow
2789  *  ram are then committed to the EEPROM by processing each bank at a time
2790  *  checking for the modified bit and writing only the pending changes.
2791  *  After a successful commit, the shadow ram is cleared and is ready for
2792  *  future writes.
2793  **/
2794 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2795 {
2796         struct e1000_nvm_info *nvm = &hw->nvm;
2797         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2798         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2799         s32 ret_val;
2800         u16 data;
2801
2802         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
2803
2804         ret_val = e1000_update_nvm_checksum_generic(hw);
2805         if (ret_val)
2806                 goto out;
2807
2808         if (nvm->type != e1000_nvm_flash_sw)
2809                 goto out;
2810
2811         nvm->ops.acquire(hw);
2812
2813         /* We're writing to the opposite bank so if we're on bank 1,
2814          * write to bank 0 etc.  We also need to erase the segment that
2815          * is going to be written
2816          */
2817         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2818         if (ret_val != E1000_SUCCESS) {
2819                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
2820                 bank = 0;
2821         }
2822
2823         if (bank == 0) {
2824                 new_bank_offset = nvm->flash_bank_size;
2825                 old_bank_offset = 0;
2826                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2827                 if (ret_val)
2828                         goto release;
2829         } else {
2830                 old_bank_offset = nvm->flash_bank_size;
2831                 new_bank_offset = 0;
2832                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2833                 if (ret_val)
2834                         goto release;
2835         }
2836
2837         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
2838                 /* Determine whether to write the value stored
2839                  * in the other NVM bank or a modified value stored
2840                  * in the shadow RAM
2841                  */
2842                 if (dev_spec->shadow_ram[i].modified) {
2843                         data = dev_spec->shadow_ram[i].value;
2844                 } else {
2845                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2846                                                                 old_bank_offset,
2847                                                                 &data);
2848                         if (ret_val)
2849                                 break;
2850                 }
2851
2852                 /* If the word is 0x13, then make sure the signature bits
2853                  * (15:14) are 11b until the commit has completed.
2854                  * This will allow us to write 10b which indicates the
2855                  * signature is valid.  We want to do this after the write
2856                  * has completed so that we don't mark the segment valid
2857                  * while the write is still in progress
2858                  */
2859                 if (i == E1000_ICH_NVM_SIG_WORD)
2860                         data |= E1000_ICH_NVM_SIG_MASK;
2861
2862                 /* Convert offset to bytes. */
2863                 act_offset = (i + new_bank_offset) << 1;
2864
2865                 usec_delay(100);
2866                 /* Write the bytes to the new bank. */
2867                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2868                                                                act_offset,
2869                                                                (u8)data);
2870                 if (ret_val)
2871                         break;
2872
2873                 usec_delay(100);
2874                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2875                                                           act_offset + 1,
2876                                                           (u8)(data >> 8));
2877                 if (ret_val)
2878                         break;
2879         }
2880
2881         /* Don't bother writing the segment valid bits if sector
2882          * programming failed.
2883          */
2884         if (ret_val) {
2885                 DEBUGOUT("Flash commit failed.\n");
2886                 goto release;
2887         }
2888
2889         /* Finally validate the new segment by setting bit 15:14
2890          * to 10b in word 0x13 , this can be done without an
2891          * erase as well since these bits are 11 to start with
2892          * and we need to change bit 14 to 0b
2893          */
2894         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2895         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2896         if (ret_val)
2897                 goto release;
2898
2899         data &= 0xBFFF;
2900         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2901                                                        act_offset * 2 + 1,
2902                                                        (u8)(data >> 8));
2903         if (ret_val)
2904                 goto release;
2905
2906         /* And invalidate the previously valid segment by setting
2907          * its signature word (0x13) high_byte to 0b. This can be
2908          * done without an erase because flash erase sets all bits
2909          * to 1's. We can write 1's to 0's without an erase
2910          */
2911         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2912         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2913         if (ret_val)
2914                 goto release;
2915
2916         /* Great!  Everything worked, we can now clear the cached entries. */
2917         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
2918                 dev_spec->shadow_ram[i].modified = false;
2919                 dev_spec->shadow_ram[i].value = 0xFFFF;
2920         }
2921
2922 release:
2923         nvm->ops.release(hw);
2924
2925         /* Reload the EEPROM, or else modifications will not appear
2926          * until after the next adapter reset.
2927          */
2928         if (!ret_val) {
2929                 nvm->ops.reload(hw);
2930                 msec_delay(10);
2931         }
2932
2933 out:
2934         if (ret_val)
2935                 DEBUGOUT1("NVM update error: %d\n", ret_val);
2936
2937         return ret_val;
2938 }
2939
2940 /**
2941  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2942  *  @hw: pointer to the HW structure
2943  *
2944  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2945  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2946  *  calculated, in which case we need to calculate the checksum and set bit 6.
2947  **/
2948 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2949 {
2950         s32 ret_val;
2951         u16 data;
2952         u16 word;
2953         u16 valid_csum_mask;
2954
2955         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
2956
2957         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
2958          * the checksum needs to be fixed.  This bit is an indication that
2959          * the NVM was prepared by OEM software and did not calculate
2960          * the checksum...a likely scenario.
2961          */
2962         switch (hw->mac.type) {
2963         default:
2964                 word = NVM_FUTURE_INIT_WORD1;
2965                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
2966                 break;
2967         }
2968
2969         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
2970         if (ret_val)
2971                 return ret_val;
2972
2973         if (!(data & valid_csum_mask)) {
2974                 data |= valid_csum_mask;
2975                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
2976                 if (ret_val)
2977                         return ret_val;
2978                 ret_val = hw->nvm.ops.update(hw);
2979                 if (ret_val)
2980                         return ret_val;
2981         }
2982
2983         return e1000_validate_nvm_checksum_generic(hw);
2984 }
2985
2986 /**
2987  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2988  *  @hw: pointer to the HW structure
2989  *  @offset: The offset (in bytes) of the byte/word to read.
2990  *  @size: Size of data to read, 1=byte 2=word
2991  *  @data: The byte(s) to write to the NVM.
2992  *
2993  *  Writes one/two bytes to the NVM using the flash access registers.
2994  **/
2995 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2996                                           u8 size, u16 data)
2997 {
2998         union ich8_hws_flash_status hsfsts;
2999         union ich8_hws_flash_ctrl hsflctl;
3000         u32 flash_linear_addr;
3001         u32 flash_data = 0;
3002         s32 ret_val;
3003         u8 count = 0;
3004
3005         DEBUGFUNC("e1000_write_ich8_data");
3006
3007         if (size < 1 || size > 2 || data > size * 0xff ||
3008             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3009                 return -E1000_ERR_NVM;
3010
3011         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3012                             hw->nvm.flash_base_addr;
3013
3014         do {
3015                 usec_delay(1);
3016                 /* Steps */
3017                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3018                 if (ret_val != E1000_SUCCESS)
3019                         break;
3020
3021                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3022                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3023                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3024                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3025                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3026
3027                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3028
3029                 if (size == 1)
3030                         flash_data = (u32)data & 0x00FF;
3031                 else
3032                         flash_data = (u32)data;
3033
3034                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3035
3036                 /* check if FCERR is set to 1 , if set to 1, clear it
3037                  * and try the whole sequence a few more times else done
3038                  */
3039                 ret_val = e1000_flash_cycle_ich8lan(hw,
3040                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3041                 if (ret_val == E1000_SUCCESS)
3042                         break;
3043
3044                 /* If we're here, then things are most likely
3045                  * completely hosed, but if the error condition
3046                  * is detected, it won't hurt to give it another
3047                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3048                  */
3049                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3050                 if (hsfsts.hsf_status.flcerr)
3051                         /* Repeat for some time before giving up. */
3052                         continue;
3053                 if (!hsfsts.hsf_status.flcdone) {
3054                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3055                         break;
3056                 }
3057         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3058
3059         return ret_val;
3060 }
3061
3062 /**
3063  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3064  *  @hw: pointer to the HW structure
3065  *  @offset: The index of the byte to read.
3066  *  @data: The byte to write to the NVM.
3067  *
3068  *  Writes a single byte to the NVM using the flash access registers.
3069  **/
3070 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3071                                           u8 data)
3072 {
3073         u16 word = (u16)data;
3074
3075         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3076
3077         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3078 }
3079
3080 /**
3081  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3082  *  @hw: pointer to the HW structure
3083  *  @offset: The offset of the byte to write.
3084  *  @byte: The byte to write to the NVM.
3085  *
3086  *  Writes a single byte to the NVM using the flash access registers.
3087  *  Goes through a retry algorithm before giving up.
3088  **/
3089 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3090                                                 u32 offset, u8 byte)
3091 {
3092         s32 ret_val;
3093         u16 program_retries;
3094
3095         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3096
3097         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3098         if (!ret_val)
3099                 return ret_val;
3100
3101         for (program_retries = 0; program_retries < 100; program_retries++) {
3102                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3103                 usec_delay(100);
3104                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3105                 if (ret_val == E1000_SUCCESS)
3106                         break;
3107         }
3108         if (program_retries == 100)
3109                 return -E1000_ERR_NVM;
3110
3111         return E1000_SUCCESS;
3112 }
3113
3114 /**
3115  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3116  *  @hw: pointer to the HW structure
3117  *  @bank: 0 for first bank, 1 for second bank, etc.
3118  *
3119  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3120  *  bank N is 4096 * N + flash_reg_addr.
3121  **/
3122 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3123 {
3124         struct e1000_nvm_info *nvm = &hw->nvm;
3125         union ich8_hws_flash_status hsfsts;
3126         union ich8_hws_flash_ctrl hsflctl;
3127         u32 flash_linear_addr;
3128         /* bank size is in 16bit words - adjust to bytes */
3129         u32 flash_bank_size = nvm->flash_bank_size * 2;
3130         s32 ret_val;
3131         s32 count = 0;
3132         s32 j, iteration, sector_size;
3133
3134         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3135
3136         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3137
3138         /* Determine HW Sector size: Read BERASE bits of hw flash status
3139          * register
3140          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3141          *     consecutive sectors.  The start index for the nth Hw sector
3142          *     can be calculated as = bank * 4096 + n * 256
3143          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3144          *     The start index for the nth Hw sector can be calculated
3145          *     as = bank * 4096
3146          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3147          *     (ich9 only, otherwise error condition)
3148          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3149          */
3150         switch (hsfsts.hsf_status.berasesz) {
3151         case 0:
3152                 /* Hw sector size 256 */
3153                 sector_size = ICH_FLASH_SEG_SIZE_256;
3154                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3155                 break;
3156         case 1:
3157                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3158                 iteration = 1;
3159                 break;
3160         case 2:
3161                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3162                 iteration = 1;
3163                 break;
3164         case 3:
3165                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3166                 iteration = 1;
3167                 break;
3168         default:
3169                 return -E1000_ERR_NVM;
3170         }
3171
3172         /* Start with the base address, then add the sector offset. */
3173         flash_linear_addr = hw->nvm.flash_base_addr;
3174         flash_linear_addr += (bank) ? flash_bank_size : 0;
3175
3176         for (j = 0; j < iteration ; j++) {
3177                 do {
3178                         /* Steps */
3179                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3180                         if (ret_val)
3181                                 return ret_val;
3182
3183                         /* Write a value 11 (block Erase) in Flash
3184                          * Cycle field in hw flash control
3185                          */
3186                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
3187                                                               ICH_FLASH_HSFCTL);
3188                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3189                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3190                                                 hsflctl.regval);
3191
3192                         /* Write the last 24 bits of an index within the
3193                          * block into Flash Linear address field in Flash
3194                          * Address.
3195                          */
3196                         flash_linear_addr += (j * sector_size);
3197                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3198                                               flash_linear_addr);
3199
3200                         ret_val = e1000_flash_cycle_ich8lan(hw,
3201                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3202                         if (ret_val == E1000_SUCCESS)
3203                                 break;
3204
3205                         /* Check if FCERR is set to 1.  If 1,
3206                          * clear it and try the whole sequence
3207                          * a few more times else Done
3208                          */
3209                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3210                                                       ICH_FLASH_HSFSTS);
3211                         if (hsfsts.hsf_status.flcerr)
3212                                 /* repeat for some time before giving up */
3213                                 continue;
3214                         else if (!hsfsts.hsf_status.flcdone)
3215                                 return ret_val;
3216                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3217         }
3218
3219         return E1000_SUCCESS;
3220 }
3221
3222 /**
3223  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3224  *  @hw: pointer to the HW structure
3225  *  @data: Pointer to the LED settings
3226  *
3227  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3228  *  settings is all 0's or F's, set the LED default to a valid LED default
3229  *  setting.
3230  **/
3231 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3232 {
3233         s32 ret_val;
3234
3235         DEBUGFUNC("e1000_valid_led_default_ich8lan");
3236
3237         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3238         if (ret_val) {
3239                 DEBUGOUT("NVM Read Error\n");
3240                 return ret_val;
3241         }
3242
3243         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3244                 *data = ID_LED_DEFAULT_ICH8LAN;
3245
3246         return E1000_SUCCESS;
3247 }
3248
3249 /**
3250  *  e1000_id_led_init_pchlan - store LED configurations
3251  *  @hw: pointer to the HW structure
3252  *
3253  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3254  *  the PHY LED configuration register.
3255  *
3256  *  PCH also does not have an "always on" or "always off" mode which
3257  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3258  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
3259  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3260  *  link based on logic in e1000_led_[on|off]_pchlan().
3261  **/
3262 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3263 {
3264         struct e1000_mac_info *mac = &hw->mac;
3265         s32 ret_val;
3266         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3267         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3268         u16 data, i, temp, shift;
3269
3270         DEBUGFUNC("e1000_id_led_init_pchlan");
3271
3272         /* Get default ID LED modes */
3273         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3274         if (ret_val)
3275                 return ret_val;
3276
3277         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
3278         mac->ledctl_mode1 = mac->ledctl_default;
3279         mac->ledctl_mode2 = mac->ledctl_default;
3280
3281         for (i = 0; i < 4; i++) {
3282                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3283                 shift = (i * 5);
3284                 switch (temp) {
3285                 case ID_LED_ON1_DEF2:
3286                 case ID_LED_ON1_ON2:
3287                 case ID_LED_ON1_OFF2:
3288                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3289                         mac->ledctl_mode1 |= (ledctl_on << shift);
3290                         break;
3291                 case ID_LED_OFF1_DEF2:
3292                 case ID_LED_OFF1_ON2:
3293                 case ID_LED_OFF1_OFF2:
3294                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3295                         mac->ledctl_mode1 |= (ledctl_off << shift);
3296                         break;
3297                 default:
3298                         /* Do nothing */
3299                         break;
3300                 }
3301                 switch (temp) {
3302                 case ID_LED_DEF1_ON2:
3303                 case ID_LED_ON1_ON2:
3304                 case ID_LED_OFF1_ON2:
3305                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3306                         mac->ledctl_mode2 |= (ledctl_on << shift);
3307                         break;
3308                 case ID_LED_DEF1_OFF2:
3309                 case ID_LED_ON1_OFF2:
3310                 case ID_LED_OFF1_OFF2:
3311                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3312                         mac->ledctl_mode2 |= (ledctl_off << shift);
3313                         break;
3314                 default:
3315                         /* Do nothing */
3316                         break;
3317                 }
3318         }
3319
3320         return E1000_SUCCESS;
3321 }
3322
3323 /**
3324  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3325  *  @hw: pointer to the HW structure
3326  *
3327  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3328  *  register, so the the bus width is hard coded.
3329  **/
3330 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3331 {
3332         struct e1000_bus_info *bus = &hw->bus;
3333         s32 ret_val;
3334
3335         DEBUGFUNC("e1000_get_bus_info_ich8lan");
3336
3337         ret_val = e1000_get_bus_info_pcie_generic(hw);
3338
3339         /* ICH devices are "PCI Express"-ish.  They have
3340          * a configuration space, but do not contain
3341          * PCI Express Capability registers, so bus width
3342          * must be hardcoded.
3343          */
3344         if (bus->width == e1000_bus_width_unknown)
3345                 bus->width = e1000_bus_width_pcie_x1;
3346
3347         return ret_val;
3348 }
3349
3350 /**
3351  *  e1000_reset_hw_ich8lan - Reset the hardware
3352  *  @hw: pointer to the HW structure
3353  *
3354  *  Does a full reset of the hardware which includes a reset of the PHY and
3355  *  MAC.
3356  **/
3357 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3358 {
3359         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3360         u16 kum_cfg;
3361         u32 ctrl, reg;
3362         s32 ret_val;
3363
3364         DEBUGFUNC("e1000_reset_hw_ich8lan");
3365
3366         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3367          * on the last TLP read/write transaction when MAC is reset.
3368          */
3369         ret_val = e1000_disable_pcie_master_generic(hw);
3370         if (ret_val)
3371                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
3372
3373         DEBUGOUT("Masking off all interrupts\n");
3374         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3375
3376         /* Disable the Transmit and Receive units.  Then delay to allow
3377          * any pending transactions to complete before we hit the MAC
3378          * with the global reset.
3379          */
3380         E1000_WRITE_REG(hw, E1000_RCTL, 0);
3381         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
3382         E1000_WRITE_FLUSH(hw);
3383
3384         msec_delay(10);
3385
3386         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3387         if (hw->mac.type == e1000_ich8lan) {
3388                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3389                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
3390                 /* Set Packet Buffer Size to 16k. */
3391                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
3392         }
3393
3394         if (hw->mac.type == e1000_pchlan) {
3395                 /* Save the NVM K1 bit setting*/
3396                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3397                 if (ret_val)
3398                         return ret_val;
3399
3400                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3401                         dev_spec->nvm_k1_enabled = true;
3402                 else
3403                         dev_spec->nvm_k1_enabled = false;
3404         }
3405
3406         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3407
3408         if (!hw->phy.ops.check_reset_block(hw)) {
3409                 /* Full-chip reset requires MAC and PHY reset at the same
3410                  * time to make sure the interface between MAC and the
3411                  * external PHY is reset.
3412                  */
3413                 ctrl |= E1000_CTRL_PHY_RST;
3414
3415                 /* Gate automatic PHY configuration by hardware on
3416                  * non-managed 82579
3417                  */
3418                 if ((hw->mac.type == e1000_pch2lan) &&
3419                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3420                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3421         }
3422         ret_val = e1000_acquire_swflag_ich8lan(hw);
3423         DEBUGOUT("Issuing a global reset to ich8lan\n");
3424         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
3425         /* cannot issue a flush here because it hangs the hardware */
3426         msec_delay(20);
3427
3428         /* Set Phy Config Counter to 50msec */
3429         if (hw->mac.type == e1000_pch2lan) {
3430                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
3431                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3432                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3433                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
3434         }
3435
3436         if (!ret_val)
3437                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
3438
3439         if (ctrl & E1000_CTRL_PHY_RST) {
3440                 ret_val = hw->phy.ops.get_cfg_done(hw);
3441                 if (ret_val)
3442                         return ret_val;
3443
3444                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3445                 if (ret_val)
3446                         return ret_val;
3447         }
3448
3449         /* For PCH, this write will make sure that any noise
3450          * will be detected as a CRC error and be dropped rather than show up
3451          * as a bad packet to the DMA engine.
3452          */
3453         if (hw->mac.type == e1000_pchlan)
3454                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
3455
3456         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3457         E1000_READ_REG(hw, E1000_ICR);
3458
3459         reg = E1000_READ_REG(hw, E1000_KABGTXD);
3460         reg |= E1000_KABGTXD_BGSQLBIAS;
3461         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
3462
3463         return E1000_SUCCESS;
3464 }
3465
3466 /**
3467  *  e1000_init_hw_ich8lan - Initialize the hardware
3468  *  @hw: pointer to the HW structure
3469  *
3470  *  Prepares the hardware for transmit and receive by doing the following:
3471  *   - initialize hardware bits
3472  *   - initialize LED identification
3473  *   - setup receive address registers
3474  *   - setup flow control
3475  *   - setup transmit descriptors
3476  *   - clear statistics
3477  **/
3478 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3479 {
3480         struct e1000_mac_info *mac = &hw->mac;
3481         u32 ctrl_ext, txdctl, snoop;
3482         s32 ret_val;
3483         u16 i;
3484
3485         DEBUGFUNC("e1000_init_hw_ich8lan");
3486
3487         e1000_initialize_hw_bits_ich8lan(hw);
3488
3489         /* Initialize identification LED */
3490         ret_val = mac->ops.id_led_init(hw);
3491         if (ret_val)
3492                 DEBUGOUT("Error initializing identification LED\n");
3493                 /* This is not fatal and we should not stop init due to this */
3494
3495         /* Setup the receive address. */
3496         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
3497
3498         /* Zero out the Multicast HASH table */
3499         DEBUGOUT("Zeroing the MTA\n");
3500         for (i = 0; i < mac->mta_reg_count; i++)
3501                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3502
3503         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3504          * the ME.  Disable wakeup by clearing the host wakeup bit.
3505          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3506          */
3507         if (hw->phy.type == e1000_phy_82578) {
3508                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
3509                 i &= ~BM_WUC_HOST_WU_BIT;
3510                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
3511                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3512                 if (ret_val)
3513                         return ret_val;
3514         }
3515
3516         /* Setup link and flow control */
3517         ret_val = mac->ops.setup_link(hw);
3518
3519         /* Set the transmit descriptor write-back policy for both queues */
3520         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
3521         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3522                  E1000_TXDCTL_FULL_TX_DESC_WB;
3523         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3524                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3525         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
3526         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
3527         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3528                  E1000_TXDCTL_FULL_TX_DESC_WB;
3529         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3530                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3531         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
3532
3533         /* ICH8 has opposite polarity of no_snoop bits.
3534          * By default, we should use snoop behavior.
3535          */
3536         if (mac->type == e1000_ich8lan)
3537                 snoop = PCIE_ICH8_SNOOP_ALL;
3538         else
3539                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3540         e1000_set_pcie_no_snoop_generic(hw, snoop);
3541
3542         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3543         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3544         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3545
3546         /* Clear all of the statistics registers (clear on read).  It is
3547          * important that we do this after we have tried to establish link
3548          * because the symbol error count will increment wildly if there
3549          * is no link.
3550          */
3551         e1000_clear_hw_cntrs_ich8lan(hw);
3552
3553         return ret_val;
3554 }
3555
3556 /**
3557  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3558  *  @hw: pointer to the HW structure
3559  *
3560  *  Sets/Clears required hardware bits necessary for correctly setting up the
3561  *  hardware for transmit and receive.
3562  **/
3563 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3564 {
3565         u32 reg;
3566
3567         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
3568
3569         /* Extended Device Control */
3570         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3571         reg |= (1 << 22);
3572         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3573         if (hw->mac.type >= e1000_pchlan)
3574                 reg |= E1000_CTRL_EXT_PHYPDEN;
3575         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
3576
3577         /* Transmit Descriptor Control 0 */
3578         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
3579         reg |= (1 << 22);
3580         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
3581
3582         /* Transmit Descriptor Control 1 */
3583         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
3584         reg |= (1 << 22);
3585         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
3586
3587         /* Transmit Arbitration Control 0 */
3588         reg = E1000_READ_REG(hw, E1000_TARC(0));
3589         if (hw->mac.type == e1000_ich8lan)
3590                 reg |= (1 << 28) | (1 << 29);
3591         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3592         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3593
3594         /* Transmit Arbitration Control 1 */
3595         reg = E1000_READ_REG(hw, E1000_TARC(1));
3596         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
3597                 reg &= ~(1 << 28);
3598         else
3599                 reg |= (1 << 28);
3600         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3601         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
3602
3603         /* Device Status */
3604         if (hw->mac.type == e1000_ich8lan) {
3605                 reg = E1000_READ_REG(hw, E1000_STATUS);
3606                 reg &= ~(1 << 31);
3607                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
3608         }
3609
3610         /* work-around descriptor data corruption issue during nfs v2 udp
3611          * traffic, just disable the nfs filtering capability
3612          */
3613         reg = E1000_READ_REG(hw, E1000_RFCTL);
3614         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3615
3616         /* Disable IPv6 extension header parsing because some malformed
3617          * IPv6 headers can hang the Rx.
3618          */
3619         if (hw->mac.type == e1000_ich8lan)
3620                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3621         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
3622
3623         return;
3624 }
3625
3626 /**
3627  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3628  *  @hw: pointer to the HW structure
3629  *
3630  *  Determines which flow control settings to use, then configures flow
3631  *  control.  Calls the appropriate media-specific link configuration
3632  *  function.  Assuming the adapter has a valid link partner, a valid link
3633  *  should be established.  Assumes the hardware has previously been reset
3634  *  and the transmitter and receiver are not enabled.
3635  **/
3636 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3637 {
3638         s32 ret_val;
3639
3640         DEBUGFUNC("e1000_setup_link_ich8lan");
3641
3642         if (hw->phy.ops.check_reset_block(hw))
3643                 return E1000_SUCCESS;
3644
3645         /* ICH parts do not have a word in the NVM to determine
3646          * the default flow control setting, so we explicitly
3647          * set it to full.
3648          */
3649         if (hw->fc.requested_mode == e1000_fc_default)
3650                 hw->fc.requested_mode = e1000_fc_full;
3651
3652         /* Save off the requested flow control mode for use later.  Depending
3653          * on the link partner's capabilities, we may or may not use this mode.
3654          */
3655         hw->fc.current_mode = hw->fc.requested_mode;
3656
3657         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
3658                 hw->fc.current_mode);
3659
3660         /* Continue to configure the copper link. */
3661         ret_val = hw->mac.ops.setup_physical_interface(hw);
3662         if (ret_val)
3663                 return ret_val;
3664
3665         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
3666         if ((hw->phy.type == e1000_phy_82578) ||
3667             (hw->phy.type == e1000_phy_82579) ||
3668             (hw->phy.type == e1000_phy_i217) ||
3669             (hw->phy.type == e1000_phy_82577)) {
3670                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
3671
3672                 ret_val = hw->phy.ops.write_reg(hw,
3673                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
3674                                              hw->fc.pause_time);
3675                 if (ret_val)
3676                         return ret_val;
3677         }
3678
3679         return e1000_set_fc_watermarks_generic(hw);
3680 }
3681
3682 /**
3683  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3684  *  @hw: pointer to the HW structure
3685  *
3686  *  Configures the kumeran interface to the PHY to wait the appropriate time
3687  *  when polling the PHY, then call the generic setup_copper_link to finish
3688  *  configuring the copper link.
3689  **/
3690 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3691 {
3692         u32 ctrl;
3693         s32 ret_val;
3694         u16 reg_data;
3695
3696         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
3697
3698         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3699         ctrl |= E1000_CTRL_SLU;
3700         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3701         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3702
3703         /* Set the mac to wait the maximum time between each iteration
3704          * and increase the max iterations when polling the phy;
3705          * this fixes erroneous timeouts at 10Mbps.
3706          */
3707         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
3708                                                0xFFFF);
3709         if (ret_val)
3710                 return ret_val;
3711         ret_val = e1000_read_kmrn_reg_generic(hw,
3712                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
3713                                               &reg_data);
3714         if (ret_val)
3715                 return ret_val;
3716         reg_data |= 0x3F;
3717         ret_val = e1000_write_kmrn_reg_generic(hw,
3718                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
3719                                                reg_data);
3720         if (ret_val)
3721                 return ret_val;
3722
3723         switch (hw->phy.type) {
3724         case e1000_phy_igp_3:
3725                 ret_val = e1000_copper_link_setup_igp(hw);
3726                 if (ret_val)
3727                         return ret_val;
3728                 break;
3729         case e1000_phy_bm:
3730         case e1000_phy_82578:
3731                 ret_val = e1000_copper_link_setup_m88(hw);
3732                 if (ret_val)
3733                         return ret_val;
3734                 break;
3735         case e1000_phy_82577:
3736         case e1000_phy_82579:
3737         case e1000_phy_i217:
3738                 ret_val = e1000_copper_link_setup_82577(hw);
3739                 if (ret_val)
3740                         return ret_val;
3741                 break;
3742         case e1000_phy_ife:
3743                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3744                                                &reg_data);
3745                 if (ret_val)
3746                         return ret_val;
3747
3748                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3749
3750                 switch (hw->phy.mdix) {
3751                 case 1:
3752                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3753                         break;
3754                 case 2:
3755                         reg_data |= IFE_PMC_FORCE_MDIX;
3756                         break;
3757                 case 0:
3758                 default:
3759                         reg_data |= IFE_PMC_AUTO_MDIX;
3760                         break;
3761                 }
3762                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3763                                                 reg_data);
3764                 if (ret_val)
3765                         return ret_val;
3766                 break;
3767         default:
3768                 break;
3769         }
3770
3771         return e1000_setup_copper_link_generic(hw);
3772 }
3773
3774 /**
3775  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3776  *  @hw: pointer to the HW structure
3777  *  @speed: pointer to store current link speed
3778  *  @duplex: pointer to store the current link duplex
3779  *
3780  *  Calls the generic get_speed_and_duplex to retrieve the current link
3781  *  information and then calls the Kumeran lock loss workaround for links at
3782  *  gigabit speeds.
3783  **/
3784 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3785                                           u16 *duplex)
3786 {
3787         s32 ret_val;
3788
3789         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
3790
3791         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
3792         if (ret_val)
3793                 return ret_val;
3794
3795         if ((hw->mac.type == e1000_ich8lan) &&
3796             (hw->phy.type == e1000_phy_igp_3) &&
3797             (*speed == SPEED_1000)) {
3798                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3799         }
3800
3801         return ret_val;
3802 }
3803
3804 /**
3805  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3806  *  @hw: pointer to the HW structure
3807  *
3808  *  Work-around for 82566 Kumeran PCS lock loss:
3809  *  On link status change (i.e. PCI reset, speed change) and link is up and
3810  *  speed is gigabit-
3811  *    0) if workaround is optionally disabled do nothing
3812  *    1) wait 1ms for Kumeran link to come up
3813  *    2) check Kumeran Diagnostic register PCS lock loss bit
3814  *    3) if not set the link is locked (all is good), otherwise...
3815  *    4) reset the PHY
3816  *    5) repeat up to 10 times
3817  *  Note: this is only called for IGP3 copper when speed is 1gb.
3818  **/
3819 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3820 {
3821         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3822         u32 phy_ctrl;
3823         s32 ret_val;
3824         u16 i, data;
3825         bool link;
3826
3827         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
3828
3829         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3830                 return E1000_SUCCESS;
3831
3832         /* Make sure link is up before proceeding.  If not just return.
3833          * Attempting this while link is negotiating fouled up link
3834          * stability
3835          */
3836         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3837         if (!link)
3838                 return E1000_SUCCESS;
3839
3840         for (i = 0; i < 10; i++) {
3841                 /* read once to clear */
3842                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
3843                 if (ret_val)
3844                         return ret_val;
3845                 /* and again to get new status */
3846                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
3847                 if (ret_val)
3848                         return ret_val;
3849
3850                 /* check for PCS lock */
3851                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3852                         return E1000_SUCCESS;
3853
3854                 /* Issue PHY reset */
3855                 hw->phy.ops.reset(hw);
3856                 msec_delay_irq(5);
3857         }
3858         /* Disable GigE link negotiation */
3859         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3860         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3861                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3862         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3863
3864         /* Call gig speed drop workaround on Gig disable before accessing
3865          * any PHY registers
3866          */
3867         e1000_gig_downshift_workaround_ich8lan(hw);
3868
3869         /* unable to acquire PCS lock */
3870         return -E1000_ERR_PHY;
3871 }
3872
3873 /**
3874  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3875  *  @hw: pointer to the HW structure
3876  *  @state: boolean value used to set the current Kumeran workaround state
3877  *
3878  *  If ICH8, set the current Kumeran workaround state (enabled - true
3879  *  /disabled - false).
3880  **/
3881 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3882                                                  bool state)
3883 {
3884         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3885
3886         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
3887
3888         if (hw->mac.type != e1000_ich8lan) {
3889                 DEBUGOUT("Workaround applies to ICH8 only.\n");
3890                 return;
3891         }
3892
3893         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3894
3895         return;
3896 }
3897
3898 /**
3899  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3900  *  @hw: pointer to the HW structure
3901  *
3902  *  Workaround for 82566 power-down on D3 entry:
3903  *    1) disable gigabit link
3904  *    2) write VR power-down enable
3905  *    3) read it back
3906  *  Continue if successful, else issue LCD reset and repeat
3907  **/
3908 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3909 {
3910         u32 reg;
3911         u16 data;
3912         u8  retry = 0;
3913
3914         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
3915
3916         if (hw->phy.type != e1000_phy_igp_3)
3917                 return;
3918
3919         /* Try the workaround twice (if needed) */
3920         do {
3921                 /* Disable link */
3922                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
3923                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3924                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3925                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
3926
3927                 /* Call gig speed drop workaround on Gig disable before
3928                  * accessing any PHY registers
3929                  */
3930                 if (hw->mac.type == e1000_ich8lan)
3931                         e1000_gig_downshift_workaround_ich8lan(hw);
3932
3933                 /* Write VR power-down enable */
3934                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3935                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3936                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
3937                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3938
3939                 /* Read it back and test */
3940                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3941                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3942                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3943                         break;
3944
3945                 /* Issue PHY reset and repeat at most one more time */
3946                 reg = E1000_READ_REG(hw, E1000_CTRL);
3947                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
3948                 retry++;
3949         } while (retry);
3950 }
3951
3952 /**
3953  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3954  *  @hw: pointer to the HW structure
3955  *
3956  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3957  *  LPLU, Gig disable, MDIC PHY reset):
3958  *    1) Set Kumeran Near-end loopback
3959  *    2) Clear Kumeran Near-end loopback
3960  *  Should only be called for ICH8[m] devices with any 1G Phy.
3961  **/
3962 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3963 {
3964         s32 ret_val;
3965         u16 reg_data;
3966
3967         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
3968
3969         if ((hw->mac.type != e1000_ich8lan) ||
3970             (hw->phy.type == e1000_phy_ife))
3971                 return;
3972
3973         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3974                                               &reg_data);
3975         if (ret_val)
3976                 return;
3977         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3978         ret_val = e1000_write_kmrn_reg_generic(hw,
3979                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
3980                                                reg_data);
3981         if (ret_val)
3982                 return;
3983         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3984         ret_val = e1000_write_kmrn_reg_generic(hw,
3985                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
3986                                                reg_data);
3987 }
3988
3989 /**
3990  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3991  *  @hw: pointer to the HW structure
3992  *
3993  *  During S0 to Sx transition, it is possible the link remains at gig
3994  *  instead of negotiating to a lower speed.  Before going to Sx, set
3995  *  'Gig Disable' to force link speed negotiation to a lower speed based on
3996  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
3997  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3998  *  needs to be written.
3999  *  Parts that support (and are linked to a partner which support) EEE in
4000  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4001  *  than 10Mbps w/o EEE.
4002  **/
4003 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4004 {
4005         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4006         u32 phy_ctrl;
4007         s32 ret_val;
4008
4009         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4010
4011         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4012         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4013         if (hw->phy.type == e1000_phy_i217) {
4014                 u16 phy_reg;
4015
4016                 ret_val = hw->phy.ops.acquire(hw);
4017                 if (ret_val)
4018                         goto out;
4019
4020                 if (!dev_spec->eee_disable) {
4021                         u16 eee_advert;
4022
4023                         ret_val =
4024                             e1000_read_emi_reg_locked(hw,
4025                                                       I217_EEE_ADVERTISEMENT,
4026                                                       &eee_advert);
4027                         if (ret_val)
4028                                 goto release;
4029
4030                         /* Disable LPLU if both link partners support 100BaseT
4031                          * EEE and 100Full is advertised on both ends of the
4032                          * link.
4033                          */
4034                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4035                             (dev_spec->eee_lp_ability &
4036                              I82579_EEE_100_SUPPORTED) &&
4037                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4038                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4039                                               E1000_PHY_CTRL_NOND0A_LPLU);
4040                 }
4041
4042                 /* For i217 Intel Rapid Start Technology support,
4043                  * when the system is going into Sx and no manageability engine
4044                  * is present, the driver must configure proxy to reset only on
4045                  * power good.  LPI (Low Power Idle) state must also reset only
4046                  * on power good, as well as the MTA (Multicast table array).
4047                  * The SMBus release must also be disabled on LCD reset.
4048                  */
4049                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4050                         E1000_ICH_FWSM_FW_VALID)) {
4051
4052                         /* Enable proxy to reset only on power good. */
4053                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4054                                                     &phy_reg);
4055                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4056                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4057                                                      phy_reg);
4058
4059                         /* Set bit enable LPI (EEE) to reset only on
4060                          * power good.
4061                         */
4062                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4063                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4064                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4065
4066                         /* Disable the SMB release on LCD reset. */
4067                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4068                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4069                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4070                 }
4071
4072                 /* Enable MTA to reset for Intel Rapid Start Technology
4073                  * Support
4074                  */
4075                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4076                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4077                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4078
4079 release:
4080                 hw->phy.ops.release(hw);
4081         }
4082 out:
4083         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4084
4085         if (hw->mac.type == e1000_ich8lan)
4086                 e1000_gig_downshift_workaround_ich8lan(hw);
4087
4088         if (hw->mac.type >= e1000_pchlan) {
4089                 e1000_oem_bits_config_ich8lan(hw, false);
4090
4091                 /* Reset PHY to activate OEM bits on 82577/8 */
4092                 if (hw->mac.type == e1000_pchlan)
4093                         e1000_phy_hw_reset_generic(hw);
4094
4095                 ret_val = hw->phy.ops.acquire(hw);
4096                 if (ret_val)
4097                         return;
4098                 e1000_write_smbus_addr(hw);
4099                 hw->phy.ops.release(hw);
4100         }
4101
4102         return;
4103 }
4104
4105 /**
4106  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4107  *  @hw: pointer to the HW structure
4108  *
4109  *  During Sx to S0 transitions on non-managed devices or managed devices
4110  *  on which PHY resets are not blocked, if the PHY registers cannot be
4111  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4112  *  the PHY.
4113  *  On i217, setup Intel Rapid Start Technology.
4114  **/
4115 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4116 {
4117         s32 ret_val;
4118
4119         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4120
4121         if (hw->mac.type < e1000_pch2lan)
4122                 return;
4123
4124         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4125         if (ret_val) {
4126                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4127                 return;
4128         }
4129
4130         /* For i217 Intel Rapid Start Technology support when the system
4131          * is transitioning from Sx and no manageability engine is present
4132          * configure SMBus to restore on reset, disable proxy, and enable
4133          * the reset on MTA (Multicast table array).
4134          */
4135         if (hw->phy.type == e1000_phy_i217) {
4136                 u16 phy_reg;
4137
4138                 ret_val = hw->phy.ops.acquire(hw);
4139                 if (ret_val) {
4140                         DEBUGOUT("Failed to setup iRST\n");
4141                         return;
4142                 }
4143
4144                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4145                     E1000_ICH_FWSM_FW_VALID)) {
4146                         /* Restore clear on SMB if no manageability engine
4147                          * is present
4148                          */
4149                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
4150                                                               &phy_reg);
4151                         if (ret_val)
4152                                 goto release;
4153                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4154                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4155
4156                         /* Disable Proxy */
4157                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
4158                 }
4159                 /* Enable reset on MTA */
4160                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
4161                                                       &phy_reg);
4162                 if (ret_val)
4163                         goto release;
4164                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4165                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4166 release:
4167                 if (ret_val)
4168                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
4169                 hw->phy.ops.release(hw);
4170         }
4171 }
4172
4173 /**
4174  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4175  *  @hw: pointer to the HW structure
4176  *
4177  *  Return the LED back to the default configuration.
4178  **/
4179 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4180 {
4181         DEBUGFUNC("e1000_cleanup_led_ich8lan");
4182
4183         if (hw->phy.type == e1000_phy_ife)
4184                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4185                                              0);
4186
4187         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
4188         return E1000_SUCCESS;
4189 }
4190
4191 /**
4192  *  e1000_led_on_ich8lan - Turn LEDs on
4193  *  @hw: pointer to the HW structure
4194  *
4195  *  Turn on the LEDs.
4196  **/
4197 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4198 {
4199         DEBUGFUNC("e1000_led_on_ich8lan");
4200
4201         if (hw->phy.type == e1000_phy_ife)
4202                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4203                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4204
4205         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
4206         return E1000_SUCCESS;
4207 }
4208
4209 /**
4210  *  e1000_led_off_ich8lan - Turn LEDs off
4211  *  @hw: pointer to the HW structure
4212  *
4213  *  Turn off the LEDs.
4214  **/
4215 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4216 {
4217         DEBUGFUNC("e1000_led_off_ich8lan");
4218
4219         if (hw->phy.type == e1000_phy_ife)
4220                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4221                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
4222
4223         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
4224         return E1000_SUCCESS;
4225 }
4226
4227 /**
4228  *  e1000_setup_led_pchlan - Configures SW controllable LED
4229  *  @hw: pointer to the HW structure
4230  *
4231  *  This prepares the SW controllable LED for use.
4232  **/
4233 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4234 {
4235         DEBUGFUNC("e1000_setup_led_pchlan");
4236
4237         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4238                                      (u16)hw->mac.ledctl_mode1);
4239 }
4240
4241 /**
4242  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4243  *  @hw: pointer to the HW structure
4244  *
4245  *  Return the LED back to the default configuration.
4246  **/
4247 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4248 {
4249         DEBUGFUNC("e1000_cleanup_led_pchlan");
4250
4251         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4252                                      (u16)hw->mac.ledctl_default);
4253 }
4254
4255 /**
4256  *  e1000_led_on_pchlan - Turn LEDs on
4257  *  @hw: pointer to the HW structure
4258  *
4259  *  Turn on the LEDs.
4260  **/
4261 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4262 {
4263         u16 data = (u16)hw->mac.ledctl_mode2;
4264         u32 i, led;
4265
4266         DEBUGFUNC("e1000_led_on_pchlan");
4267
4268         /* If no link, then turn LED on by setting the invert bit
4269          * for each LED that's mode is "link_up" in ledctl_mode2.
4270          */
4271         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
4272                 for (i = 0; i < 3; i++) {
4273                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4274                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4275                             E1000_LEDCTL_MODE_LINK_UP)
4276                                 continue;
4277                         if (led & E1000_PHY_LED0_IVRT)
4278                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4279                         else
4280                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4281                 }
4282         }
4283
4284         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
4285 }
4286
4287 /**
4288  *  e1000_led_off_pchlan - Turn LEDs off
4289  *  @hw: pointer to the HW structure
4290  *
4291  *  Turn off the LEDs.
4292  **/
4293 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4294 {
4295         u16 data = (u16)hw->mac.ledctl_mode1;
4296         u32 i, led;
4297
4298         DEBUGFUNC("e1000_led_off_pchlan");
4299
4300         /* If no link, then turn LED off by clearing the invert bit
4301          * for each LED that's mode is "link_up" in ledctl_mode1.
4302          */
4303         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
4304                 for (i = 0; i < 3; i++) {
4305                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4306                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4307                             E1000_LEDCTL_MODE_LINK_UP)
4308                                 continue;
4309                         if (led & E1000_PHY_LED0_IVRT)
4310                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4311                         else
4312                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4313                 }
4314         }
4315
4316         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
4317 }
4318
4319 /**
4320  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4321  *  @hw: pointer to the HW structure
4322  *
4323  *  Read appropriate register for the config done bit for completion status
4324  *  and configure the PHY through s/w for EEPROM-less parts.
4325  *
4326  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4327  *  config done bit, so only an error is logged and continues.  If we were
4328  *  to return with error, EEPROM-less silicon would not be able to be reset
4329  *  or change link.
4330  **/
4331 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4332 {
4333         s32 ret_val = E1000_SUCCESS;
4334         u32 bank = 0;
4335         u32 status;
4336
4337         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
4338
4339         e1000_get_cfg_done_generic(hw);
4340
4341         /* Wait for indication from h/w that it has completed basic config */
4342         if (hw->mac.type >= e1000_ich10lan) {
4343                 e1000_lan_init_done_ich8lan(hw);
4344         } else {
4345                 ret_val = e1000_get_auto_rd_done_generic(hw);
4346                 if (ret_val) {
4347                         /* When auto config read does not complete, do not
4348                          * return with an error. This can happen in situations
4349                          * where there is no eeprom and prevents getting link.
4350                          */
4351                         DEBUGOUT("Auto Read Done did not complete\n");
4352                         ret_val = E1000_SUCCESS;
4353                 }
4354         }
4355
4356         /* Clear PHY Reset Asserted bit */
4357         status = E1000_READ_REG(hw, E1000_STATUS);
4358         if (status & E1000_STATUS_PHYRA)
4359                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
4360         else
4361                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
4362
4363         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4364         if (hw->mac.type <= e1000_ich9lan) {
4365                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
4366                     (hw->phy.type == e1000_phy_igp_3)) {
4367                         e1000_phy_init_script_igp3(hw);
4368                 }
4369         } else {
4370                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4371                         /* Maybe we should do a basic PHY config */
4372                         DEBUGOUT("EEPROM not present\n");
4373                         ret_val = -E1000_ERR_CONFIG;
4374                 }
4375         }
4376
4377         return ret_val;
4378 }
4379
4380 /**
4381  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4382  * @hw: pointer to the HW structure
4383  *
4384  * In the case of a PHY power down to save power, or to turn off link during a
4385  * driver unload, or wake on lan is not enabled, remove the link.
4386  **/
4387 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4388 {
4389         /* If the management interface is not enabled, then power down */
4390         if (!(hw->mac.ops.check_mng_mode(hw) ||
4391               hw->phy.ops.check_reset_block(hw)))
4392                 e1000_power_down_phy_copper(hw);
4393
4394         return;
4395 }
4396
4397 /**
4398  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4399  *  @hw: pointer to the HW structure
4400  *
4401  *  Clears hardware counters specific to the silicon family and calls
4402  *  clear_hw_cntrs_generic to clear all general purpose counters.
4403  **/
4404 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4405 {
4406         u16 phy_data;
4407         s32 ret_val;
4408
4409         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
4410
4411         e1000_clear_hw_cntrs_base_generic(hw);
4412
4413         E1000_READ_REG(hw, E1000_ALGNERRC);
4414         E1000_READ_REG(hw, E1000_RXERRC);
4415         E1000_READ_REG(hw, E1000_TNCRS);
4416         E1000_READ_REG(hw, E1000_CEXTERR);
4417         E1000_READ_REG(hw, E1000_TSCTC);
4418         E1000_READ_REG(hw, E1000_TSCTFC);
4419
4420         E1000_READ_REG(hw, E1000_MGTPRC);
4421         E1000_READ_REG(hw, E1000_MGTPDC);
4422         E1000_READ_REG(hw, E1000_MGTPTC);
4423
4424         E1000_READ_REG(hw, E1000_IAC);
4425         E1000_READ_REG(hw, E1000_ICRXOC);
4426
4427         /* Clear PHY statistics registers */
4428         if ((hw->phy.type == e1000_phy_82578) ||
4429             (hw->phy.type == e1000_phy_82579) ||
4430             (hw->phy.type == e1000_phy_i217) ||
4431             (hw->phy.type == e1000_phy_82577)) {
4432                 ret_val = hw->phy.ops.acquire(hw);
4433                 if (ret_val)
4434                         return;
4435                 ret_val = hw->phy.ops.set_page(hw,
4436                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4437                 if (ret_val)
4438                         goto release;
4439                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4440                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4441                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4442                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4443                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4444                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4445                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4446                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4447                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4448                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4449                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4450                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4451                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4452                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4453 release:
4454                 hw->phy.ops.release(hw);
4455         }
4456 }
4457