lib/librte_pmd_e1000/e1000/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  * Ethernet Connection I217-LM
  62  * Ethernet Connection I217-V
  63  * Ethernet Connection I218-V
  64  * Ethernet Connection I218-LM
  65  */
  66
  67 #include "e1000_api.h"
  68
  69 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  70 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  71 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  72 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  73 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  74 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  75 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  76 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  77 STATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  78 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  79 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  80 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  81                                               u8 *mc_addr_list,
  82                                               u32 mc_addr_count);
  83 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  84 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  85 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  86 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  87 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  88                                             bool active);
  89 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  90                                             bool active);
  91 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  92                                    u16 words, u16 *data);
  93 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  94                                     u16 words, u16 *data);
  95 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  96 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  98                                             u16 *data);
  99 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 100 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 101 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 102 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 103 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 104 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 105 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 106 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 107                                            u16 *speed, u16 *duplex);
 108 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 109 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 110 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 111 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 112 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 113 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 114 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 115 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 116 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 117 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 119 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 120 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 121                                           u32 offset, u8 *data);
 122 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                           u8 size, u16 *data);
 124 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 125                                           u32 offset, u16 *data);
 126 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 127                                                  u32 offset, u8 byte);
 128 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 129 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 130 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 131 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 132 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 133 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 134
 135 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 136 /* Offset 04h HSFSTS */
 137 union ich8_hws_flash_status {
 138         struct ich8_hsfsts {
 139                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 140                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 141                 u16 dael:1; /* bit 2 Direct Access error Log */
 142                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 143                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 144                 u16 reserved1:2; /* bit 13:6 Reserved */
 145                 u16 reserved2:6; /* bit 13:6 Reserved */
 146                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 147                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 148         } hsf_status;
 149         u16 regval;
 150 };
 151
 152 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 153 /* Offset 06h FLCTL */
 154 union ich8_hws_flash_ctrl {
 155         struct ich8_hsflctl {
 156                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 157                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 158                 u16 reserved:5;   /* 7:3 Reserved  */
 159                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 160                 u16 flockdn:6;   /* 15:10 Reserved */
 161         } hsf_ctrl;
 162         u16 regval;
 163 };
 164
 165 /* ICH Flash Region Access Permissions */
 166 union ich8_hws_flash_regacc {
 167         struct ich8_flracc {
 168                 u32 grra:8; /* 0:7 GbE region Read Access */
 169                 u32 grwa:8; /* 8:15 GbE region Write Access */
 170                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 171                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 172         } hsf_flregacc;
 173         u16 regval;
 174 };
 175
 176 /**
 177  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 178  *  @hw: pointer to the HW structure
 179  *
 180  *  Test access to the PHY registers by reading the PHY ID registers.  If
 181  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 182  *  otherwise assume the read PHY ID is correct if it is valid.
 183  *
 184  *  Assumes the sw/fw/hw semaphore is already acquired.
 185  **/
 186 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 187 {
 188         u16 phy_reg = 0;
 189         u32 phy_id = 0;
 190         s32 ret_val = 0;
 191         u16 retry_count;
 192         u32 mac_reg = 0;
 193
 194         for (retry_count = 0; retry_count < 2; retry_count++) {
 195                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 196                 if (ret_val || (phy_reg == 0xFFFF))
 197                         continue;
 198                 phy_id = (u32)(phy_reg << 16);
 199
 200                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 201                 if (ret_val || (phy_reg == 0xFFFF)) {
 202                         phy_id = 0;
 203                         continue;
 204                 }
 205                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 206                 break;
 207         }
 208
 209         if (hw->phy.id) {
 210                 if  (hw->phy.id == phy_id)
 211                         goto out;
 212         } else if (phy_id) {
 213                 hw->phy.id = phy_id;
 214                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 215                 goto out;
 216         }
 217
 218         /* In case the PHY needs to be in mdio slow mode,
 219          * set slow mode and try to get the PHY id again.
 220          */
 221         if (hw->mac.type < e1000_pch_lpt) {
 222                 hw->phy.ops.release(hw);
 223                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 224                 if (!ret_val)
 225                         ret_val = e1000_get_phy_id(hw);
 226                 hw->phy.ops.acquire(hw);
 227         }
 228
 229         if (ret_val)
 230                 return false;
 231 out:
 232         if (hw->mac.type == e1000_pch_lpt) {
 233                 /* Unforce SMBus mode in PHY */
 234                 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 235                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 236                 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 237
 238                 /* Unforce SMBus mode in MAC */
 239                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 240                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 241                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 242         }
 243
 244         return true;
 245 }
 246
 247 /**
 248  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 249  *  @hw: pointer to the HW structure
 250  *
 251  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 252  *  used to reset the PHY to a quiescent state when necessary.
 253  **/
 254 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 255 {
 256         u32 mac_reg;
 257
 258         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 259
 260         /* Set Phy Config Counter to 50msec */
 261         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 262         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 263         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 264         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 265
 266         /* Toggle LANPHYPC Value bit */
 267         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 268         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 269         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 270         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 271         E1000_WRITE_FLUSH(hw);
 272         usec_delay(10);
 273         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 274         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 275         E1000_WRITE_FLUSH(hw);
 276
 277         if (hw->mac.type < e1000_pch_lpt) {
 278                 msec_delay(50);
 279         } else {
 280                 u16 count = 20;
 281
 282                 do {
 283                         msec_delay(5);
 284                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 285                            E1000_CTRL_EXT_LPCD) && count--);
 286
 287                 msec_delay(30);
 288         }
 289 }
 290
 291 /**
 292  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 293  *  @hw: pointer to the HW structure
 294  *
 295  *  Workarounds/flow necessary for PHY initialization during driver load
 296  *  and resume paths.
 297  **/
 298 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 299 {
 300         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 301         s32 ret_val;
 302
 303         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 304
 305         /* Gate automatic PHY configuration by hardware on managed and
 306          * non-managed 82579 and newer adapters.
 307          */
 308         e1000_gate_hw_phy_config_ich8lan(hw, true);
 309
 310 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
 311         /* It is not possible to be certain of the current state of ULP
 312          * so forcibly disable it.
 313          */
 314         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 315
 316 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
 317         ret_val = hw->phy.ops.acquire(hw);
 318         if (ret_val) {
 319                 DEBUGOUT("Failed to initialize PHY flow\n");
 320                 goto out;
 321         }
 322
 323         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 324          * inaccessible and resetting the PHY is not blocked, toggle the
 325          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 326          */
 327         switch (hw->mac.type) {
 328         case e1000_pch_lpt:
 329                 if (e1000_phy_is_accessible_pchlan(hw))
 330                         break;
 331
 332                 /* Before toggling LANPHYPC, see if PHY is accessible by
 333                  * forcing MAC to SMBus mode first.
 334                  */
 335                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 336                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 337                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 338
 339                 /* Wait 50 milliseconds for MAC to finish any retries
 340                  * that it might be trying to perform from previous
 341                  * attempts to acknowledge any phy read requests.
 342                  */
 343                  msec_delay(50);
 344
 345                 /* fall-through */
 346         case e1000_pch2lan:
 347                 if (e1000_phy_is_accessible_pchlan(hw))
 348                         break;
 349
 350                 /* fall-through */
 351         case e1000_pchlan:
 352                 if ((hw->mac.type == e1000_pchlan) &&
 353                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 354                         break;
 355
 356                 if (hw->phy.ops.check_reset_block(hw)) {
 357                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 358                         ret_val = -E1000_ERR_PHY;
 359                         break;
 360                 }
 361
 362                 /* Toggle LANPHYPC Value bit */
 363                 e1000_toggle_lanphypc_pch_lpt(hw);
 364                 if (hw->mac.type >= e1000_pch_lpt) {
 365                         if (e1000_phy_is_accessible_pchlan(hw))
 366                                 break;
 367
 368                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 369                          * so ensure that the MAC is also out of SMBus mode
 370                          */
 371                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 372                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 373                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 374
 375                         if (e1000_phy_is_accessible_pchlan(hw))
 376                                 break;
 377
 378                         ret_val = -E1000_ERR_PHY;
 379                 }
 380                 break;
 381         default:
 382                 break;
 383         }
 384
 385         hw->phy.ops.release(hw);
 386         if (!ret_val) {
 387
 388                 /* Check to see if able to reset PHY.  Print error if not */
 389                 if (hw->phy.ops.check_reset_block(hw)) {
 390                         ERROR_REPORT("Reset blocked by ME\n");
 391                         goto out;
 392                 }
 393
 394                 /* Reset the PHY before any access to it.  Doing so, ensures
 395                  * that the PHY is in a known good state before we read/write
 396                  * PHY registers.  The generic reset is sufficient here,
 397                  * because we haven't determined the PHY type yet.
 398                  */
 399                 ret_val = e1000_phy_hw_reset_generic(hw);
 400                 if (ret_val)
 401                         goto out;
 402
 403                 /* On a successful reset, possibly need to wait for the PHY
 404                  * to quiesce to an accessible state before returning control
 405                  * to the calling function.  If the PHY does not quiesce, then
 406                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 407                  *  the PHY is in.
 408                  */
 409                 ret_val = hw->phy.ops.check_reset_block(hw);
 410                 if (ret_val)
 411                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 412         }
 413
 414 out:
 415         /* Ungate automatic PHY configuration on non-managed 82579 */
 416         if ((hw->mac.type == e1000_pch2lan) &&
 417             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 418                 msec_delay(10);
 419                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 420         }
 421
 422         return ret_val;
 423 }
 424
 425 /**
 426  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 427  *  @hw: pointer to the HW structure
 428  *
 429  *  Initialize family-specific PHY parameters and function pointers.
 430  **/
 431 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 432 {
 433         struct e1000_phy_info *phy = &hw->phy;
 434         s32 ret_val;
 435
 436         DEBUGFUNC("e1000_init_phy_params_pchlan");
 437
 438         phy->addr               = 1;
 439         phy->reset_delay_us     = 100;
 440
 441         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 442         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 443         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 444         phy->ops.set_page       = e1000_set_page_igp;
 445         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 446         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 447         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 448         phy->ops.release        = e1000_release_swflag_ich8lan;
 449         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 450         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 451         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 452         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 453         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 454         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 455         phy->ops.power_up       = e1000_power_up_phy_copper;
 456         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 457         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458
 459         phy->id = e1000_phy_unknown;
 460
 461         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 462         if (ret_val)
 463                 return ret_val;
 464
 465         if (phy->id == e1000_phy_unknown)
 466                 switch (hw->mac.type) {
 467                 default:
 468                         ret_val = e1000_get_phy_id(hw);
 469                         if (ret_val)
 470                                 return ret_val;
 471                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 472                                 break;
 473                         /* fall-through */
 474                 case e1000_pch2lan:
 475                 case e1000_pch_lpt:
 476                         /* In case the PHY needs to be in mdio slow mode,
 477                          * set slow mode and try to get the PHY id again.
 478                          */
 479                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 480                         if (ret_val)
 481                                 return ret_val;
 482                         ret_val = e1000_get_phy_id(hw);
 483                         if (ret_val)
 484                                 return ret_val;
 485                         break;
 486                 }
 487         phy->type = e1000_get_phy_type_from_id(phy->id);
 488
 489         switch (phy->type) {
 490         case e1000_phy_82577:
 491         case e1000_phy_82579:
 492         case e1000_phy_i217:
 493                 phy->ops.check_polarity = e1000_check_polarity_82577;
 494                 phy->ops.force_speed_duplex =
 495                         e1000_phy_force_speed_duplex_82577;
 496                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 497                 phy->ops.get_info = e1000_get_phy_info_82577;
 498                 phy->ops.commit = e1000_phy_sw_reset_generic;
 499                 break;
 500         case e1000_phy_82578:
 501                 phy->ops.check_polarity = e1000_check_polarity_m88;
 502                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 503                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 504                 phy->ops.get_info = e1000_get_phy_info_m88;
 505                 break;
 506         default:
 507                 ret_val = -E1000_ERR_PHY;
 508                 break;
 509         }
 510
 511         return ret_val;
 512 }
 513
 514 /**
 515  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 516  *  @hw: pointer to the HW structure
 517  *
 518  *  Initialize family-specific PHY parameters and function pointers.
 519  **/
 520 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 521 {
 522         struct e1000_phy_info *phy = &hw->phy;
 523         s32 ret_val;
 524         u16 i = 0;
 525
 526         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 527
 528         phy->addr               = 1;
 529         phy->reset_delay_us     = 100;
 530
 531         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 532         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 533         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 534         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 535         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 536         phy->ops.release        = e1000_release_swflag_ich8lan;
 537         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 538         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 539         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 540         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 541         phy->ops.power_up       = e1000_power_up_phy_copper;
 542         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 543
 544         /* We may need to do this twice - once for IGP and if that fails,
 545          * we'll set BM func pointers and try again
 546          */
 547         ret_val = e1000_determine_phy_address(hw);
 548         if (ret_val) {
 549                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 550                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 551                 ret_val = e1000_determine_phy_address(hw);
 552                 if (ret_val) {
 553                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 554                         return ret_val;
 555                 }
 556         }
 557
 558         phy->id = 0;
 559         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 560                (i++ < 100)) {
 561                 msec_delay(1);
 562                 ret_val = e1000_get_phy_id(hw);
 563                 if (ret_val)
 564                         return ret_val;
 565         }
 566
 567         /* Verify phy id */
 568         switch (phy->id) {
 569         case IGP03E1000_E_PHY_ID:
 570                 phy->type = e1000_phy_igp_3;
 571                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 572                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 573                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 574                 phy->ops.get_info = e1000_get_phy_info_igp;
 575                 phy->ops.check_polarity = e1000_check_polarity_igp;
 576                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 577                 break;
 578         case IFE_E_PHY_ID:
 579         case IFE_PLUS_E_PHY_ID:
 580         case IFE_C_E_PHY_ID:
 581                 phy->type = e1000_phy_ife;
 582                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 583                 phy->ops.get_info = e1000_get_phy_info_ife;
 584                 phy->ops.check_polarity = e1000_check_polarity_ife;
 585                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 586                 break;
 587         case BME1000_E_PHY_ID:
 588                 phy->type = e1000_phy_bm;
 589                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 590                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 591                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 592                 phy->ops.commit = e1000_phy_sw_reset_generic;
 593                 phy->ops.get_info = e1000_get_phy_info_m88;
 594                 phy->ops.check_polarity = e1000_check_polarity_m88;
 595                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 596                 break;
 597         default:
 598                 return -E1000_ERR_PHY;
 599                 break;
 600         }
 601
 602         return E1000_SUCCESS;
 603 }
 604
 605 /**
 606  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 607  *  @hw: pointer to the HW structure
 608  *
 609  *  Initialize family-specific NVM parameters and function
 610  *  pointers.
 611  **/
 612 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 613 {
 614         struct e1000_nvm_info *nvm = &hw->nvm;
 615         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 616         u32 gfpreg, sector_base_addr, sector_end_addr;
 617         u16 i;
 618
 619         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 620
 621         /* Can't read flash registers if the register set isn't mapped. */
 622         nvm->type = e1000_nvm_flash_sw;
 623         if (!hw->flash_address) {
 624                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 625                 return -E1000_ERR_CONFIG;
 626         }
 627
 628         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 629
 630         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 631          * Add 1 to sector_end_addr since this sector is included in
 632          * the overall size.
 633          */
 634         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 635         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 636
 637         /* flash_base_addr is byte-aligned */
 638         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 639
 640         /* find total size of the NVM, then cut in half since the total
 641          * size represents two separate NVM banks.
 642          */
 643         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 644                                 << FLASH_SECTOR_ADDR_SHIFT);
 645         nvm->flash_bank_size /= 2;
 646         /* Adjust to word count */
 647         nvm->flash_bank_size /= sizeof(u16);
 648
 649         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 650
 651         /* Clear shadow ram */
 652         for (i = 0; i < nvm->word_size; i++) {
 653                 dev_spec->shadow_ram[i].modified = false;
 654                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 655         }
 656
 657         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 658         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 659
 660         /* Function Pointers */
 661         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 662         nvm->ops.release        = e1000_release_nvm_ich8lan;
 663         nvm->ops.read           = e1000_read_nvm_ich8lan;
 664         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 665         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 666         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 667         nvm->ops.write          = e1000_write_nvm_ich8lan;
 668
 669         return E1000_SUCCESS;
 670 }
 671
 672 /**
 673  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 674  *  @hw: pointer to the HW structure
 675  *
 676  *  Initialize family-specific MAC parameters and function
 677  *  pointers.
 678  **/
 679 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 680 {
 681         struct e1000_mac_info *mac = &hw->mac;
 682 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 683         u16 pci_cfg;
 684 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 685
 686         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 687
 688         /* Set media type function pointer */
 689         hw->phy.media_type = e1000_media_type_copper;
 690
 691         /* Set mta register count */
 692         mac->mta_reg_count = 32;
 693         /* Set rar entry count */
 694         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 695         if (mac->type == e1000_ich8lan)
 696                 mac->rar_entry_count--;
 697         /* Set if part includes ASF firmware */
 698         mac->asf_firmware_present = true;
 699         /* FWSM register */
 700         mac->has_fwsm = true;
 701         /* ARC subsystem not supported */
 702         mac->arc_subsystem_valid = false;
 703         /* Adaptive IFS supported */
 704         mac->adaptive_ifs = true;
 705
 706         /* Function pointers */
 707
 708         /* bus type/speed/width */
 709         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 710         /* function id */
 711         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 712         /* reset */
 713         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 714         /* hw initialization */
 715         mac->ops.init_hw = e1000_init_hw_ich8lan;
 716         /* link setup */
 717         mac->ops.setup_link = e1000_setup_link_ich8lan;
 718         /* physical interface setup */
 719         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 720         /* check for link */
 721         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 722         /* link info */
 723         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 724         /* multicast address update */
 725         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 726         /* clear hardware counters */
 727         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 728
 729         /* LED and other operations */
 730         switch (mac->type) {
 731         case e1000_ich8lan:
 732         case e1000_ich9lan:
 733         case e1000_ich10lan:
 734                 /* check management mode */
 735                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 736                 /* ID LED init */
 737                 mac->ops.id_led_init = e1000_id_led_init_generic;
 738                 /* blink LED */
 739                 mac->ops.blink_led = e1000_blink_led_generic;
 740                 /* setup LED */
 741                 mac->ops.setup_led = e1000_setup_led_generic;
 742                 /* cleanup LED */
 743                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 744                 /* turn on/off LED */
 745                 mac->ops.led_on = e1000_led_on_ich8lan;
 746                 mac->ops.led_off = e1000_led_off_ich8lan;
 747                 break;
 748         case e1000_pch2lan:
 749                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 750                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 751                 /* fall-through */
 752         case e1000_pch_lpt:
 753 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 754                 /* multicast address update for pch2 */
 755                 mac->ops.update_mc_addr_list =
 756                         e1000_update_mc_addr_list_pch2lan;
 757 #endif
 758         case e1000_pchlan:
 759 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 760                 /* save PCH revision_id */
 761                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 762                 hw->revision_id = (u8)(pci_cfg &= 0x000F);
 763 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 764                 /* check management mode */
 765                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 766                 /* ID LED init */
 767                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 768                 /* setup LED */
 769                 mac->ops.setup_led = e1000_setup_led_pchlan;
 770                 /* cleanup LED */
 771                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 772                 /* turn on/off LED */
 773                 mac->ops.led_on = e1000_led_on_pchlan;
 774                 mac->ops.led_off = e1000_led_off_pchlan;
 775                 break;
 776         default:
 777                 break;
 778         }
 779
 780         if (mac->type == e1000_pch_lpt) {
 781                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 782                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 783                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 784         }
 785
 786         /* Enable PCS Lock-loss workaround for ICH8 */
 787         if (mac->type == e1000_ich8lan)
 788                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 789
 790         return E1000_SUCCESS;
 791 }
 792
 793 /**
 794  *  __e1000_access_emi_reg_locked - Read/write EMI register
 795  *  @hw: pointer to the HW structure
 796  *  @addr: EMI address to program
 797  *  @data: pointer to value to read/write from/to the EMI address
 798  *  @read: boolean flag to indicate read or write
 799  *
 800  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 801  **/
 802 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 803                                          u16 *data, bool read)
 804 {
 805         s32 ret_val;
 806
 807         DEBUGFUNC("__e1000_access_emi_reg_locked");
 808
 809         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 810         if (ret_val)
 811                 return ret_val;
 812
 813         if (read)
 814                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 815                                                       data);
 816         else
 817                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 818                                                        *data);
 819
 820         return ret_val;
 821 }
 822
 823 /**
 824  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 825  *  @hw: pointer to the HW structure
 826  *  @addr: EMI address to program
 827  *  @data: value to be read from the EMI address
 828  *
 829  *  Assumes the SW/FW/HW Semaphore is already acquired.
 830  **/
 831 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 832 {
 833         DEBUGFUNC("e1000_read_emi_reg_locked");
 834
 835         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 836 }
 837
 838 /**
 839  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 840  *  @hw: pointer to the HW structure
 841  *  @addr: EMI address to program
 842  *  @data: value to be written to the EMI address
 843  *
 844  *  Assumes the SW/FW/HW Semaphore is already acquired.
 845  **/
 846 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 847 {
 848         DEBUGFUNC("e1000_read_emi_reg_locked");
 849
 850         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 851 }
 852
 853 /**
 854  *  e1000_set_eee_pchlan - Enable/disable EEE support
 855  *  @hw: pointer to the HW structure
 856  *
 857  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 858  *  the link and the EEE capabilities of the link partner.  The LPI Control
 859  *  register bits will remain set only if/when link is up.
 860  *
 861  *  EEE LPI must not be asserted earlier than one second after link is up.
 862  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 863  *  can be link issues with some switches.  Other devices can have EEE LPI
 864  *  enabled immediately upon link up since they have a timer in hardware which
 865  *  prevents LPI from being asserted too early.
 866  **/
 867 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 868 {
 869         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 870         s32 ret_val;
 871         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 872
 873         DEBUGFUNC("e1000_set_eee_pchlan");
 874
 875         switch (hw->phy.type) {
 876         case e1000_phy_82579:
 877                 lpa = I82579_EEE_LP_ABILITY;
 878                 pcs_status = I82579_EEE_PCS_STATUS;
 879                 adv_addr = I82579_EEE_ADVERTISEMENT;
 880                 break;
 881         case e1000_phy_i217:
 882                 lpa = I217_EEE_LP_ABILITY;
 883                 pcs_status = I217_EEE_PCS_STATUS;
 884                 adv_addr = I217_EEE_ADVERTISEMENT;
 885                 break;
 886         default:
 887                 return E1000_SUCCESS;
 888         }
 889
 890         ret_val = hw->phy.ops.acquire(hw);
 891         if (ret_val)
 892                 return ret_val;
 893
 894         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 895         if (ret_val)
 896                 goto release;
 897
 898         /* Clear bits that enable EEE in various speeds */
 899         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 900
 901         /* Enable EEE if not disabled by user */
 902         if (!dev_spec->eee_disable) {
 903                 /* Save off link partner's EEE ability */
 904                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 905                                                     &dev_spec->eee_lp_ability);
 906                 if (ret_val)
 907                         goto release;
 908
 909                 /* Read EEE advertisement */
 910                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 911                 if (ret_val)
 912                         goto release;
 913
 914                 /* Enable EEE only for speeds in which the link partner is
 915                  * EEE capable and for which we advertise EEE.
 916                  */
 917                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 918                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 919
 920                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 921                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 922                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 923                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 924                         else
 925                                 /* EEE is not supported in 100Half, so ignore
 926                                  * partner's EEE in 100 ability if full-duplex
 927                                  * is not advertised.
 928                                  */
 929                                 dev_spec->eee_lp_ability &=
 930                                     ~I82579_EEE_100_SUPPORTED;
 931                 }
 932         }
 933
 934         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 935         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 936         if (ret_val)
 937                 goto release;
 938
 939         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 940 release:
 941         hw->phy.ops.release(hw);
 942
 943         return ret_val;
 944 }
 945
 946 /**
 947  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 948  *  @hw:   pointer to the HW structure
 949  *  @link: link up bool flag
 950  *
 951  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 952  *  preventing further DMA write requests.  Workaround the issue by disabling
 953  *  the de-assertion of the clock request when in 1Gpbs mode.
 954  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 955  *  speeds in order to avoid Tx hangs.
 956  **/
 957 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 958 {
 959         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 960         u32 status = E1000_READ_REG(hw, E1000_STATUS);
 961         s32 ret_val = E1000_SUCCESS;
 962         u16 reg;
 963
 964         if (link && (status & E1000_STATUS_SPEED_1000)) {
 965                 ret_val = hw->phy.ops.acquire(hw);
 966                 if (ret_val)
 967                         return ret_val;
 968
 969                 ret_val =
 970                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 971                                                &reg);
 972                 if (ret_val)
 973                         goto release;
 974
 975                 ret_val =
 976                     e1000_write_kmrn_reg_locked(hw,
 977                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 978                                                 reg &
 979                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
 980                 if (ret_val)
 981                         goto release;
 982
 983                 usec_delay(10);
 984
 985                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
 986                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 987
 988                 ret_val =
 989                     e1000_write_kmrn_reg_locked(hw,
 990                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 991                                                 reg);
 992 release:
 993                 hw->phy.ops.release(hw);
 994         } else {
 995                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 996                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 997
 998                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
 999                               (status & E1000_STATUS_FD)))
1000                         goto update_fextnvm6;
1001
1002                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1003                 if (ret_val)
1004                         return ret_val;
1005
1006                 /* Clear link status transmit timeout */
1007                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1008
1009                 if (status & E1000_STATUS_SPEED_100) {
1010                         /* Set inband Tx timeout to 5x10us for 100Half */
1011                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1012
1013                         /* Do not extend the K1 entry latency for 100Half */
1014                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1015                 } else {
1016                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1017                         reg |= 50 <<
1018                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1019
1020                         /* Extend the K1 entry latency for 10 Mbps */
1021                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1022                 }
1023
1024                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1025                 if (ret_val)
1026                         return ret_val;
1027
1028 update_fextnvm6:
1029                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1030         }
1031
1032         return ret_val;
1033 }
1034
1035 #if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
1036 /**
1037  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1038  *  @hw: pointer to the HW structure
1039  *  @to_sx: boolean indicating a system power state transition to Sx
1040  *
1041  *  When link is down, configure ULP mode to significantly reduce the power
1042  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1043  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1044  *  system, configure the ULP mode by software.
1045  */
1046 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1047 {
1048         u32 mac_reg;
1049         s32 ret_val = E1000_SUCCESS;
1050         u16 phy_reg;
1051
1052         if ((hw->mac.type < e1000_pch_lpt) ||
1053             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1054             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1055             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1056                 return 0;
1057
1058         if (!to_sx) {
1059                 int i = 0;
1060
1061                 /* Poll up to 5 seconds for Cable Disconnected indication */
1062                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1063                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1064                         /* Bail if link is re-acquired */
1065                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1066                                 return -E1000_ERR_PHY;
1067
1068                         if (i++ == 100)
1069                                 break;
1070
1071                         msec_delay(50);
1072                 }
1073                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1074                           (E1000_READ_REG(hw, E1000_FEXT) &
1075                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1076                           i * 50);
1077         }
1078
1079         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1080                 /* Request ME configure ULP mode in the PHY */
1081                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1082                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1083                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1084
1085                 goto out;
1086         }
1087
1088         ret_val = hw->phy.ops.acquire(hw);
1089         if (ret_val)
1090                 goto out;
1091
1092         /* During S0 Idle keep the phy in PCI-E mode */
1093         if (hw->dev_spec.ich8lan.smbus_disable)
1094                 goto skip_smbus;
1095
1096         /* Force SMBus mode in PHY */
1097         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1098         if (ret_val)
1099                 goto release;
1100         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1101         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1102
1103         /* Force SMBus mode in MAC */
1104         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1105         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1106         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1107
1108 skip_smbus:
1109         if (!to_sx) {
1110                 /* Change the 'Link Status Change' interrupt to trigger
1111                  * on 'Cable Status Change'
1112                  */
1113                 ret_val = e1000_read_kmrn_reg_locked(hw,
1114                                                      E1000_KMRNCTRLSTA_OP_MODES,
1115                                                      &phy_reg);
1116                 if (ret_val)
1117                         goto release;
1118                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1119                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1120                                             phy_reg);
1121         }
1122
1123         /* Set Inband ULP Exit, Reset to SMBus mode and
1124          * Disable SMBus Release on PERST# in PHY
1125          */
1126         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1127         if (ret_val)
1128                 goto release;
1129         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1130                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1131         if (to_sx) {
1132                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1133                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1134
1135                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1136         } else {
1137                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1138         }
1139         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1140
1141         /* Set Disable SMBus Release on PERST# in MAC */
1142         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1143         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1144         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1145
1146         /* Commit ULP changes in PHY by starting auto ULP configuration */
1147         phy_reg |= I218_ULP_CONFIG1_START;
1148         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1149
1150         if (!to_sx) {
1151                 /* Disable Tx so that the MAC doesn't send any (buffered)
1152                  * packets to the PHY.
1153                  */
1154                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1155                 mac_reg &= ~E1000_TCTL_EN;
1156                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1157         }
1158 release:
1159         hw->phy.ops.release(hw);
1160 out:
1161         if (ret_val)
1162                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1163         else
1164                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1165
1166         return ret_val;
1167 }
1168
1169 /**
1170  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1171  *  @hw: pointer to the HW structure
1172  *  @force: boolean indicating whether or not to force disabling ULP
1173  *
1174  *  Un-configure ULP mode when link is up, the system is transitioned from
1175  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1176  *  system, poll for an indication from ME that ULP has been un-configured.
1177  *  If not on an ME enabled system, un-configure the ULP mode by software.
1178  *
1179  *  During nominal operation, this function is called when link is acquired
1180  *  to disable ULP mode (force=false); otherwise, for example when unloading
1181  *  the driver or during Sx->S0 transitions, this is called with force=true
1182  *  to forcibly disable ULP.
1183
1184  *  When the cable is plugged in while the device is in D0, a Cable Status
1185  *  Change interrupt is generated which causes this function to be called
1186  *  to partially disable ULP mode and restart autonegotiation.  This function
1187  *  is then called again due to the resulting Link Status Change interrupt
1188  *  to finish cleaning up after the ULP flow.
1189  */
1190 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1191 {
1192         s32 ret_val = E1000_SUCCESS;
1193         u32 mac_reg;
1194         u16 phy_reg;
1195         int i = 0;
1196
1197         if ((hw->mac.type < e1000_pch_lpt) ||
1198             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1199             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1200             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1201                 return 0;
1202
1203         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1204                 if (force) {
1205                         /* Request ME un-configure ULP mode in the PHY */
1206                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1207                         mac_reg &= ~E1000_H2ME_ULP;
1208                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1209                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1210                 }
1211
1212                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1213                 while (E1000_READ_REG(hw, E1000_FWSM) &
1214                        E1000_FWSM_ULP_CFG_DONE) {
1215                         if (i++ == 10) {
1216                                 ret_val = -E1000_ERR_PHY;
1217                                 goto out;
1218                         }
1219
1220                         msec_delay(10);
1221                 }
1222                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1223
1224                 if (force) {
1225                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1226                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1227                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1228                 } else {
1229                         /* Clear H2ME.ULP after ME ULP configuration */
1230                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1231                         mac_reg &= ~E1000_H2ME_ULP;
1232                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1233
1234                         /* Restore link speed advertisements and restart
1235                          * Auto-negotiation
1236                          */
1237                         ret_val = e1000_phy_setup_autoneg(hw);
1238                         if (ret_val)
1239                                 goto out;
1240
1241                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1242                 }
1243
1244                 goto out;
1245         }
1246
1247         ret_val = hw->phy.ops.acquire(hw);
1248         if (ret_val)
1249                 goto out;
1250
1251         /* Revert the change to the 'Link Status Change'
1252          * interrupt to trigger on 'Cable Status Change'
1253          */
1254         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1255                                              &phy_reg);
1256         if (ret_val)
1257                 goto release;
1258         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1259         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1260
1261         if (force)
1262                 /* Toggle LANPHYPC Value bit */
1263                 e1000_toggle_lanphypc_pch_lpt(hw);
1264
1265         /* Unforce SMBus mode in PHY */
1266         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1267         if (ret_val) {
1268                 /* The MAC might be in PCIe mode, so temporarily force to
1269                  * SMBus mode in order to access the PHY.
1270                  */
1271                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1272                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1273                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1274
1275                 msec_delay(50);
1276
1277                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1278                                                        &phy_reg);
1279                 if (ret_val)
1280                         goto release;
1281         }
1282         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1283         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1284
1285         /* Unforce SMBus mode in MAC */
1286         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1287         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1288         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1289
1290         /* When ULP mode was previously entered, K1 was disabled by the
1291          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1292          */
1293         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1294         if (ret_val)
1295                 goto release;
1296         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1297         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1298
1299         /* Clear ULP enabled configuration */
1300         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1301         if (ret_val)
1302                 goto release;
1303         /* CSC interrupt received due to ULP Indication */
1304         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1305                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1306                              I218_ULP_CONFIG1_STICKY_ULP |
1307                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1308                              I218_ULP_CONFIG1_WOL_HOST |
1309                              I218_ULP_CONFIG1_INBAND_EXIT |
1310                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1311                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1312
1313                 /* Commit ULP changes by starting auto ULP configuration */
1314                 phy_reg |= I218_ULP_CONFIG1_START;
1315                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1316
1317                 /* Clear Disable SMBus Release on PERST# in MAC */
1318                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1319                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1320                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1321
1322                 if (!force) {
1323                         hw->phy.ops.release(hw);
1324
1325                         if (hw->mac.autoneg)
1326                                 e1000_phy_setup_autoneg(hw);
1327
1328                         e1000_sw_lcd_config_ich8lan(hw);
1329
1330                         e1000_oem_bits_config_ich8lan(hw, true);
1331
1332                         /* Set ULP state to unknown and return non-zero to
1333                          * indicate no link (yet) and re-enter on the next LSC
1334                          * to finish disabling ULP flow.
1335                          */
1336                         hw->dev_spec.ich8lan.ulp_state =
1337                             e1000_ulp_state_unknown;
1338
1339                         return 1;
1340                 }
1341         }
1342
1343         /* Re-enable Tx */
1344         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1345         mac_reg |= E1000_TCTL_EN;
1346         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1347
1348 release:
1349         hw->phy.ops.release(hw);
1350         if (force) {
1351                 hw->phy.ops.reset(hw);
1352                 msec_delay(50);
1353         }
1354 out:
1355         if (ret_val)
1356                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1357         else
1358                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1359
1360         return ret_val;
1361 }
1362
1363 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
1364 /**
1365  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1366  *  @hw: pointer to the HW structure
1367  *
1368  *  Checks to see of the link status of the hardware has changed.  If a
1369  *  change in link status has been detected, then we read the PHY registers
1370  *  to get the current speed/duplex if link exists.
1371  **/
1372 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1373 {
1374         struct e1000_mac_info *mac = &hw->mac;
1375         s32 ret_val;
1376         bool link = false;
1377         u16 phy_reg;
1378
1379         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1380
1381         /* We only want to go out to the PHY registers to see if Auto-Neg
1382          * has completed and/or if our link status has changed.  The
1383          * get_link_status flag is set upon receiving a Link Status
1384          * Change or Rx Sequence Error interrupt.
1385          */
1386         if (!mac->get_link_status)
1387                 return E1000_SUCCESS;
1388
1389         if ((hw->mac.type < e1000_pch_lpt) ||
1390             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1391             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1392                 /* First we want to see if the MII Status Register reports
1393                  * link.  If so, then we want to get the current speed/duplex
1394                  * of the PHY.
1395                  */
1396                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1397                 if (ret_val)
1398                         return ret_val;
1399         } else {
1400                 /* Check the MAC's STATUS register to determine link state
1401                  * since the PHY could be inaccessible while in ULP mode.
1402                  */
1403                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1404                 if (link)
1405                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1406                 else
1407                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1408
1409                 if (ret_val)
1410                         return ret_val;
1411         }
1412
1413         if (hw->mac.type == e1000_pchlan) {
1414                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1415                 if (ret_val)
1416                         return ret_val;
1417         }
1418
1419         /* When connected at 10Mbps half-duplex, some parts are excessively
1420          * aggressive resulting in many collisions. To avoid this, increase
1421          * the IPG and reduce Rx latency in the PHY.
1422          */
1423         if (((hw->mac.type == e1000_pch2lan) ||
1424              (hw->mac.type == e1000_pch_lpt)) && link) {
1425                 u32 reg;
1426                 reg = E1000_READ_REG(hw, E1000_STATUS);
1427                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1428                         u16 emi_addr;
1429
1430                         reg = E1000_READ_REG(hw, E1000_TIPG);
1431                         reg &= ~E1000_TIPG_IPGT_MASK;
1432                         reg |= 0xFF;
1433                         E1000_WRITE_REG(hw, E1000_TIPG, reg);
1434
1435                         /* Reduce Rx latency in analog PHY */
1436                         ret_val = hw->phy.ops.acquire(hw);
1437                         if (ret_val)
1438                                 return ret_val;
1439
1440                         if (hw->mac.type == e1000_pch2lan)
1441                                 emi_addr = I82579_RX_CONFIG;
1442                         else
1443                                 emi_addr = I217_RX_CONFIG;
1444                         ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1445
1446                         hw->phy.ops.release(hw);
1447
1448                         if (ret_val)
1449                                 return ret_val;
1450                 }
1451         }
1452
1453         /* Work-around I218 hang issue */
1454         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1455             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
1456                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1457                 if (ret_val)
1458                         return ret_val;
1459         }
1460
1461         /* Clear link partner's EEE ability */
1462         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1463
1464         if (!link)
1465                 return E1000_SUCCESS; /* No link detected */
1466
1467         mac->get_link_status = false;
1468
1469         switch (hw->mac.type) {
1470         case e1000_pch2lan:
1471                 ret_val = e1000_k1_workaround_lv(hw);
1472                 if (ret_val)
1473                         return ret_val;
1474                 /* fall-thru */
1475         case e1000_pchlan:
1476                 if (hw->phy.type == e1000_phy_82578) {
1477                         ret_val = e1000_link_stall_workaround_hv(hw);
1478                         if (ret_val)
1479                                 return ret_val;
1480                 }
1481
1482                 /* Workaround for PCHx parts in half-duplex:
1483                  * Set the number of preambles removed from the packet
1484                  * when it is passed from the PHY to the MAC to prevent
1485                  * the MAC from misinterpreting the packet type.
1486                  */
1487                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1488                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1489
1490                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1491                     E1000_STATUS_FD)
1492                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1493
1494                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1495                 break;
1496         default:
1497                 break;
1498         }
1499
1500         /* Check if there was DownShift, must be checked
1501          * immediately after link-up
1502          */
1503         e1000_check_downshift_generic(hw);
1504
1505         /* Enable/Disable EEE after link up */
1506         if (hw->phy.type > e1000_phy_82579) {
1507                 ret_val = e1000_set_eee_pchlan(hw);
1508                 if (ret_val)
1509                         return ret_val;
1510         }
1511
1512         /* If we are forcing speed/duplex, then we simply return since
1513          * we have already determined whether we have link or not.
1514          */
1515         if (!mac->autoneg)
1516                 return -E1000_ERR_CONFIG;
1517
1518         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1519          * of MAC speed/duplex configuration.  So we only need to
1520          * configure Collision Distance in the MAC.
1521          */
1522         mac->ops.config_collision_dist(hw);
1523
1524         /* Configure Flow Control now that Auto-Neg has completed.
1525          * First, we need to restore the desired flow control
1526          * settings because we may have had to re-autoneg with a
1527          * different link partner.
1528          */
1529         ret_val = e1000_config_fc_after_link_up_generic(hw);
1530         if (ret_val)
1531                 DEBUGOUT("Error configuring flow control\n");
1532
1533         return ret_val;
1534 }
1535
1536 /**
1537  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1538  *  @hw: pointer to the HW structure
1539  *
1540  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1541  **/
1542 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1543 {
1544         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1545
1546         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1547         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1548         switch (hw->mac.type) {
1549         case e1000_ich8lan:
1550         case e1000_ich9lan:
1551         case e1000_ich10lan:
1552                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1553                 break;
1554         case e1000_pchlan:
1555         case e1000_pch2lan:
1556         case e1000_pch_lpt:
1557                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1558                 break;
1559         default:
1560                 break;
1561         }
1562 }
1563
1564 /**
1565  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1566  *  @hw: pointer to the HW structure
1567  *
1568  *  Acquires the mutex for performing NVM operations.
1569  **/
1570 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1571 {
1572         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1573
1574         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1575
1576         return E1000_SUCCESS;
1577 }
1578
1579 /**
1580  *  e1000_release_nvm_ich8lan - Release NVM mutex
1581  *  @hw: pointer to the HW structure
1582  *
1583  *  Releases the mutex used while performing NVM operations.
1584  **/
1585 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1586 {
1587         DEBUGFUNC("e1000_release_nvm_ich8lan");
1588
1589         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1590
1591         return;
1592 }
1593
1594 /**
1595  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1596  *  @hw: pointer to the HW structure
1597  *
1598  *  Acquires the software control flag for performing PHY and select
1599  *  MAC CSR accesses.
1600  **/
1601 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1602 {
1603         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1604         s32 ret_val = E1000_SUCCESS;
1605
1606         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1607
1608         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1609
1610         while (timeout) {
1611                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1612                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1613                         break;
1614
1615                 msec_delay_irq(1);
1616                 timeout--;
1617         }
1618
1619         if (!timeout) {
1620                 DEBUGOUT("SW has already locked the resource.\n");
1621                 ret_val = -E1000_ERR_CONFIG;
1622                 goto out;
1623         }
1624
1625         timeout = SW_FLAG_TIMEOUT;
1626
1627         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1628         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1629
1630         while (timeout) {
1631                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1632                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1633                         break;
1634
1635                 msec_delay_irq(1);
1636                 timeout--;
1637         }
1638
1639         if (!timeout) {
1640                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1641                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1642                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1643                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1644                 ret_val = -E1000_ERR_CONFIG;
1645                 goto out;
1646         }
1647
1648 out:
1649         if (ret_val)
1650                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1651
1652         return ret_val;
1653 }
1654
1655 /**
1656  *  e1000_release_swflag_ich8lan - Release software control flag
1657  *  @hw: pointer to the HW structure
1658  *
1659  *  Releases the software control flag for performing PHY and select
1660  *  MAC CSR accesses.
1661  **/
1662 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1663 {
1664         u32 extcnf_ctrl;
1665
1666         DEBUGFUNC("e1000_release_swflag_ich8lan");
1667
1668         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1669
1670         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1671                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1672                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1673         } else {
1674                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1675         }
1676
1677         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1678
1679         return;
1680 }
1681
1682 /**
1683  *  e1000_check_mng_mode_ich8lan - Checks management mode
1684  *  @hw: pointer to the HW structure
1685  *
1686  *  This checks if the adapter has any manageability enabled.
1687  *  This is a function pointer entry point only called by read/write
1688  *  routines for the PHY and NVM parts.
1689  **/
1690 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1691 {
1692         u32 fwsm;
1693
1694         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1695
1696         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1697
1698         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1699                ((fwsm & E1000_FWSM_MODE_MASK) ==
1700                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1701 }
1702
1703 /**
1704  *  e1000_check_mng_mode_pchlan - Checks management mode
1705  *  @hw: pointer to the HW structure
1706  *
1707  *  This checks if the adapter has iAMT enabled.
1708  *  This is a function pointer entry point only called by read/write
1709  *  routines for the PHY and NVM parts.
1710  **/
1711 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1712 {
1713         u32 fwsm;
1714
1715         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1716
1717         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1718
1719         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1720                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1721 }
1722
1723 /**
1724  *  e1000_rar_set_pch2lan - Set receive address register
1725  *  @hw: pointer to the HW structure
1726  *  @addr: pointer to the receive address
1727  *  @index: receive address array register
1728  *
1729  *  Sets the receive address array register at index to the address passed
1730  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1731  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1732  *  Use SHRA[0-3] in place of those reserved for ME.
1733  **/
1734 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1735 {
1736         u32 rar_low, rar_high;
1737
1738         DEBUGFUNC("e1000_rar_set_pch2lan");
1739
1740         /* HW expects these in little endian so we reverse the byte order
1741          * from network order (big endian) to little endian
1742          */
1743         rar_low = ((u32) addr[0] |
1744                    ((u32) addr[1] << 8) |
1745                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1746
1747         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1748
1749         /* If MAC address zero, no need to set the AV bit */
1750         if (rar_low || rar_high)
1751                 rar_high |= E1000_RAH_AV;
1752
1753         if (index == 0) {
1754                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1755                 E1000_WRITE_FLUSH(hw);
1756                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1757                 E1000_WRITE_FLUSH(hw);
1758                 return;
1759         }
1760
1761         /* RAR[1-6] are owned by manageability.  Skip those and program the
1762          * next address into the SHRA register array.
1763          */
1764         if (index < (u32) (hw->mac.rar_entry_count - 6)) {
1765                 s32 ret_val;
1766
1767                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1768                 if (ret_val)
1769                         goto out;
1770
1771                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1772                 E1000_WRITE_FLUSH(hw);
1773                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1774                 E1000_WRITE_FLUSH(hw);
1775
1776                 e1000_release_swflag_ich8lan(hw);
1777
1778                 /* verify the register updates */
1779                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1780                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1781                         return;
1782
1783                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1784                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1785         }
1786
1787 out:
1788         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1789 }
1790
1791 /**
1792  *  e1000_rar_set_pch_lpt - Set receive address registers
1793  *  @hw: pointer to the HW structure
1794  *  @addr: pointer to the receive address
1795  *  @index: receive address array register
1796  *
1797  *  Sets the receive address register array at index to the address passed
1798  *  in by addr. For LPT, RAR[0] is the base address register that is to
1799  *  contain the MAC address. SHRA[0-10] are the shared receive address
1800  *  registers that are shared between the Host and manageability engine (ME).
1801  **/
1802 STATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1803 {
1804         u32 rar_low, rar_high;
1805         u32 wlock_mac;
1806
1807         DEBUGFUNC("e1000_rar_set_pch_lpt");
1808
1809         /* HW expects these in little endian so we reverse the byte order
1810          * from network order (big endian) to little endian
1811          */
1812         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1813                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1814
1815         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1816
1817         /* If MAC address zero, no need to set the AV bit */
1818         if (rar_low || rar_high)
1819                 rar_high |= E1000_RAH_AV;
1820
1821         if (index == 0) {
1822                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1823                 E1000_WRITE_FLUSH(hw);
1824                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1825                 E1000_WRITE_FLUSH(hw);
1826                 return;
1827         }
1828
1829         /* The manageability engine (ME) can lock certain SHRAR registers that
1830          * it is using - those registers are unavailable for use.
1831          */
1832         if (index < hw->mac.rar_entry_count) {
1833                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1834                             E1000_FWSM_WLOCK_MAC_MASK;
1835                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1836
1837                 /* Check if all SHRAR registers are locked */
1838                 if (wlock_mac == 1)
1839                         goto out;
1840
1841                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1842                         s32 ret_val;
1843
1844                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1845
1846                         if (ret_val)
1847                                 goto out;
1848
1849                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1850                                         rar_low);
1851                         E1000_WRITE_FLUSH(hw);
1852                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1853                                         rar_high);
1854                         E1000_WRITE_FLUSH(hw);
1855
1856                         e1000_release_swflag_ich8lan(hw);
1857
1858                         /* verify the register updates */
1859                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1860                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1861                                 return;
1862                 }
1863         }
1864
1865 out:
1866         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1867 }
1868
1869 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1870 /**
1871  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1872  *  @hw: pointer to the HW structure
1873  *  @mc_addr_list: array of multicast addresses to program
1874  *  @mc_addr_count: number of multicast addresses to program
1875  *
1876  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1877  *  The caller must have a packed mc_addr_list of multicast addresses.
1878  **/
1879 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1880                                               u8 *mc_addr_list,
1881                                               u32 mc_addr_count)
1882 {
1883         u16 phy_reg = 0;
1884         int i;
1885         s32 ret_val;
1886
1887         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1888
1889         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1890
1891         ret_val = hw->phy.ops.acquire(hw);
1892         if (ret_val)
1893                 return;
1894
1895         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1896         if (ret_val)
1897                 goto release;
1898
1899         for (i = 0; i < hw->mac.mta_reg_count; i++) {
1900                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1901                                            (u16)(hw->mac.mta_shadow[i] &
1902                                                  0xFFFF));
1903                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1904                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
1905                                                  0xFFFF));
1906         }
1907
1908         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1909
1910 release:
1911         hw->phy.ops.release(hw);
1912 }
1913
1914 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1915 /**
1916  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1917  *  @hw: pointer to the HW structure
1918  *
1919  *  Checks if firmware is blocking the reset of the PHY.
1920  *  This is a function pointer entry point only called by
1921  *  reset routines.
1922  **/
1923 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1924 {
1925         u32 fwsm;
1926         bool blocked = false;
1927         int i = 0;
1928
1929         DEBUGFUNC("e1000_check_reset_block_ich8lan");
1930
1931         do {
1932                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1933                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
1934                         blocked = true;
1935                         msec_delay(10);
1936                         continue;
1937                 }
1938                 blocked = false;
1939         } while (blocked && (i++ < 10));
1940         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
1941 }
1942
1943 /**
1944  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1945  *  @hw: pointer to the HW structure
1946  *
1947  *  Assumes semaphore already acquired.
1948  *
1949  **/
1950 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1951 {
1952         u16 phy_data;
1953         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
1954         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1955                 E1000_STRAP_SMT_FREQ_SHIFT;
1956         s32 ret_val;
1957
1958         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1959
1960         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1961         if (ret_val)
1962                 return ret_val;
1963
1964         phy_data &= ~HV_SMB_ADDR_MASK;
1965         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1966         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1967
1968         if (hw->phy.type == e1000_phy_i217) {
1969                 /* Restore SMBus frequency */
1970                 if (freq--) {
1971                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1972                         phy_data |= (freq & (1 << 0)) <<
1973                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1974                         phy_data |= (freq & (1 << 1)) <<
1975                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1976                 } else {
1977                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
1978                 }
1979         }
1980
1981         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1982 }
1983
1984 /**
1985  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1986  *  @hw:   pointer to the HW structure
1987  *
1988  *  SW should configure the LCD from the NVM extended configuration region
1989  *  as a workaround for certain parts.
1990  **/
1991 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1992 {
1993         struct e1000_phy_info *phy = &hw->phy;
1994         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1995         s32 ret_val = E1000_SUCCESS;
1996         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1997
1998         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
1999
2000         /* Initialize the PHY from the NVM on ICH platforms.  This
2001          * is needed due to an issue where the NVM configuration is
2002          * not properly autoloaded after power transitions.
2003          * Therefore, after each PHY reset, we will load the
2004          * configuration data out of the NVM manually.
2005          */
2006         switch (hw->mac.type) {
2007         case e1000_ich8lan:
2008                 if (phy->type != e1000_phy_igp_3)
2009                         return ret_val;
2010
2011                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2012                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2013                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2014                         break;
2015                 }
2016                 /* Fall-thru */
2017         case e1000_pchlan:
2018         case e1000_pch2lan:
2019         case e1000_pch_lpt:
2020                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2021                 break;
2022         default:
2023                 return ret_val;
2024         }
2025
2026         ret_val = hw->phy.ops.acquire(hw);
2027         if (ret_val)
2028                 return ret_val;
2029
2030         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2031         if (!(data & sw_cfg_mask))
2032                 goto release;
2033
2034         /* Make sure HW does not configure LCD from PHY
2035          * extended configuration before SW configuration
2036          */
2037         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2038         if ((hw->mac.type < e1000_pch2lan) &&
2039             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2040                         goto release;
2041
2042         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2043         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2044         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2045         if (!cnf_size)
2046                 goto release;
2047
2048         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2049         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2050
2051         if (((hw->mac.type == e1000_pchlan) &&
2052              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2053             (hw->mac.type > e1000_pchlan)) {
2054                 /* HW configures the SMBus address and LEDs when the
2055                  * OEM and LCD Write Enable bits are set in the NVM.
2056                  * When both NVM bits are cleared, SW will configure
2057                  * them instead.
2058                  */
2059                 ret_val = e1000_write_smbus_addr(hw);
2060                 if (ret_val)
2061                         goto release;
2062
2063                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2064                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2065                                                         (u16)data);
2066                 if (ret_val)
2067                         goto release;
2068         }
2069
2070         /* Configure LCD from extended configuration region. */
2071
2072         /* cnf_base_addr is in DWORD */
2073         word_addr = (u16)(cnf_base_addr << 1);
2074
2075         for (i = 0; i < cnf_size; i++) {
2076                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2077                                            &reg_data);
2078                 if (ret_val)
2079                         goto release;
2080
2081                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2082                                            1, &reg_addr);
2083                 if (ret_val)
2084                         goto release;
2085
2086                 /* Save off the PHY page for future writes. */
2087                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2088                         phy_page = reg_data;
2089                         continue;
2090                 }
2091
2092                 reg_addr &= PHY_REG_MASK;
2093                 reg_addr |= phy_page;
2094
2095                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2096                                                     reg_data);
2097                 if (ret_val)
2098                         goto release;
2099         }
2100
2101 release:
2102         hw->phy.ops.release(hw);
2103         return ret_val;
2104 }
2105
2106 /**
2107  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2108  *  @hw:   pointer to the HW structure
2109  *  @link: link up bool flag
2110  *
2111  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2112  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2113  *  If link is down, the function will restore the default K1 setting located
2114  *  in the NVM.
2115  **/
2116 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2117 {
2118         s32 ret_val = E1000_SUCCESS;
2119         u16 status_reg = 0;
2120         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2121
2122         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2123
2124         if (hw->mac.type != e1000_pchlan)
2125                 return E1000_SUCCESS;
2126
2127         /* Wrap the whole flow with the sw flag */
2128         ret_val = hw->phy.ops.acquire(hw);
2129         if (ret_val)
2130                 return ret_val;
2131
2132         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2133         if (link) {
2134                 if (hw->phy.type == e1000_phy_82578) {
2135                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2136                                                               &status_reg);
2137                         if (ret_val)
2138                                 goto release;
2139
2140                         status_reg &= (BM_CS_STATUS_LINK_UP |
2141                                        BM_CS_STATUS_RESOLVED |
2142                                        BM_CS_STATUS_SPEED_MASK);
2143
2144                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2145                                            BM_CS_STATUS_RESOLVED |
2146                                            BM_CS_STATUS_SPEED_1000))
2147                                 k1_enable = false;
2148                 }
2149
2150                 if (hw->phy.type == e1000_phy_82577) {
2151                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2152                                                               &status_reg);
2153                         if (ret_val)
2154                                 goto release;
2155
2156                         status_reg &= (HV_M_STATUS_LINK_UP |
2157                                        HV_M_STATUS_AUTONEG_COMPLETE |
2158                                        HV_M_STATUS_SPEED_MASK);
2159
2160                         if (status_reg == (HV_M_STATUS_LINK_UP |
2161                                            HV_M_STATUS_AUTONEG_COMPLETE |
2162                                            HV_M_STATUS_SPEED_1000))
2163                                 k1_enable = false;
2164                 }
2165
2166                 /* Link stall fix for link up */
2167                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2168                                                        0x0100);
2169                 if (ret_val)
2170                         goto release;
2171
2172         } else {
2173                 /* Link stall fix for link down */
2174                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2175                                                        0x4100);
2176                 if (ret_val)
2177                         goto release;
2178         }
2179
2180         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2181
2182 release:
2183         hw->phy.ops.release(hw);
2184
2185         return ret_val;
2186 }
2187
2188 /**
2189  *  e1000_configure_k1_ich8lan - Configure K1 power state
2190  *  @hw: pointer to the HW structure
2191  *  @enable: K1 state to configure
2192  *
2193  *  Configure the K1 power state based on the provided parameter.
2194  *  Assumes semaphore already acquired.
2195  *
2196  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2197  **/
2198 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2199 {
2200         s32 ret_val;
2201         u32 ctrl_reg = 0;
2202         u32 ctrl_ext = 0;
2203         u32 reg = 0;
2204         u16 kmrn_reg = 0;
2205
2206         DEBUGFUNC("e1000_configure_k1_ich8lan");
2207
2208         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2209                                              &kmrn_reg);
2210         if (ret_val)
2211                 return ret_val;
2212
2213         if (k1_enable)
2214                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2215         else
2216                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2217
2218         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2219                                               kmrn_reg);
2220         if (ret_val)
2221                 return ret_val;
2222
2223         usec_delay(20);
2224         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2225         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2226
2227         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2228         reg |= E1000_CTRL_FRCSPD;
2229         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2230
2231         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2232         E1000_WRITE_FLUSH(hw);
2233         usec_delay(20);
2234         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2235         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2236         E1000_WRITE_FLUSH(hw);
2237         usec_delay(20);
2238
2239         return E1000_SUCCESS;
2240 }
2241
2242 /**
2243  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2244  *  @hw:       pointer to the HW structure
2245  *  @d0_state: boolean if entering d0 or d3 device state
2246  *
2247  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2248  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2249  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2250  **/
2251 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2252 {
2253         s32 ret_val = 0;
2254         u32 mac_reg;
2255         u16 oem_reg;
2256
2257         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2258
2259         if (hw->mac.type < e1000_pchlan)
2260                 return ret_val;
2261
2262         ret_val = hw->phy.ops.acquire(hw);
2263         if (ret_val)
2264                 return ret_val;
2265
2266         if (hw->mac.type == e1000_pchlan) {
2267                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2268                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2269                         goto release;
2270         }
2271
2272         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2273         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2274                 goto release;
2275
2276         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2277
2278         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2279         if (ret_val)
2280                 goto release;
2281
2282         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2283
2284         if (d0_state) {
2285                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2286                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2287
2288                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2289                         oem_reg |= HV_OEM_BITS_LPLU;
2290         } else {
2291                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2292                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2293                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2294
2295                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2296                     E1000_PHY_CTRL_NOND0A_LPLU))
2297                         oem_reg |= HV_OEM_BITS_LPLU;
2298         }
2299
2300         /* Set Restart auto-neg to activate the bits */
2301         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2302             !hw->phy.ops.check_reset_block(hw))
2303                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2304
2305         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2306
2307 release:
2308         hw->phy.ops.release(hw);
2309
2310         return ret_val;
2311 }
2312
2313
2314 /**
2315  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2316  *  @hw:   pointer to the HW structure
2317  **/
2318 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2319 {
2320         s32 ret_val;
2321         u16 data;
2322
2323         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2324
2325         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2326         if (ret_val)
2327                 return ret_val;
2328
2329         data |= HV_KMRN_MDIO_SLOW;
2330
2331         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2332
2333         return ret_val;
2334 }
2335
2336 /**
2337  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2338  *  done after every PHY reset.
2339  **/
2340 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2341 {
2342         s32 ret_val = E1000_SUCCESS;
2343         u16 phy_data;
2344
2345         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2346
2347         if (hw->mac.type != e1000_pchlan)
2348                 return E1000_SUCCESS;
2349
2350         /* Set MDIO slow mode before any other MDIO access */
2351         if (hw->phy.type == e1000_phy_82577) {
2352                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2353                 if (ret_val)
2354                         return ret_val;
2355         }
2356
2357         if (((hw->phy.type == e1000_phy_82577) &&
2358              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2359             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2360                 /* Disable generation of early preamble */
2361                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2362                 if (ret_val)
2363                         return ret_val;
2364
2365                 /* Preamble tuning for SSC */
2366                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2367                                                 0xA204);
2368                 if (ret_val)
2369                         return ret_val;
2370         }
2371
2372         if (hw->phy.type == e1000_phy_82578) {
2373                 /* Return registers to default by doing a soft reset then
2374                  * writing 0x3140 to the control register.
2375                  */
2376                 if (hw->phy.revision < 2) {
2377                         e1000_phy_sw_reset_generic(hw);
2378                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2379                                                         0x3140);
2380                 }
2381         }
2382
2383         /* Select page 0 */
2384         ret_val = hw->phy.ops.acquire(hw);
2385         if (ret_val)
2386                 return ret_val;
2387
2388         hw->phy.addr = 1;
2389         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2390         hw->phy.ops.release(hw);
2391         if (ret_val)
2392                 return ret_val;
2393
2394         /* Configure the K1 Si workaround during phy reset assuming there is
2395          * link so that it disables K1 if link is in 1Gbps.
2396          */
2397         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2398         if (ret_val)
2399                 return ret_val;
2400
2401         /* Workaround for link disconnects on a busy hub in half duplex */
2402         ret_val = hw->phy.ops.acquire(hw);
2403         if (ret_val)
2404                 return ret_val;
2405         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2406         if (ret_val)
2407                 goto release;
2408         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2409                                                phy_data & 0x00FF);
2410         if (ret_val)
2411                 goto release;
2412
2413         /* set MSE higher to enable link to stay up when noise is high */
2414         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2415 release:
2416         hw->phy.ops.release(hw);
2417
2418         return ret_val;
2419 }
2420
2421 /**
2422  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2423  *  @hw:   pointer to the HW structure
2424  **/
2425 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2426 {
2427         u32 mac_reg;
2428         u16 i, phy_reg = 0;
2429         s32 ret_val;
2430
2431         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2432
2433         ret_val = hw->phy.ops.acquire(hw);
2434         if (ret_val)
2435                 return;
2436         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2437         if (ret_val)
2438                 goto release;
2439
2440         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2441         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2442                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2443                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2444                                            (u16)(mac_reg & 0xFFFF));
2445                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2446                                            (u16)((mac_reg >> 16) & 0xFFFF));
2447
2448                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2449                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2450                                            (u16)(mac_reg & 0xFFFF));
2451                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2452                                            (u16)((mac_reg & E1000_RAH_AV)
2453                                                  >> 16));
2454         }
2455
2456         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2457
2458 release:
2459         hw->phy.ops.release(hw);
2460 }
2461
2462 #ifndef CRC32_OS_SUPPORT
2463 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2464 {
2465         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2466         u32 i, j, mask, crc;
2467
2468         DEBUGFUNC("e1000_calc_rx_da_crc");
2469
2470         crc = 0xffffffff;
2471         for (i = 0; i < 6; i++) {
2472                 crc = crc ^ mac[i];
2473                 for (j = 8; j > 0; j--) {
2474                         mask = (crc & 1) * (-1);
2475                         crc = (crc >> 1) ^ (poly & mask);
2476                 }
2477         }
2478         return ~crc;
2479 }
2480
2481 #endif /* CRC32_OS_SUPPORT */
2482 /**
2483  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2484  *  with 82579 PHY
2485  *  @hw: pointer to the HW structure
2486  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2487  **/
2488 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2489 {
2490         s32 ret_val = E1000_SUCCESS;
2491         u16 phy_reg, data;
2492         u32 mac_reg;
2493         u16 i;
2494
2495         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2496
2497         if (hw->mac.type < e1000_pch2lan)
2498                 return E1000_SUCCESS;
2499
2500         /* disable Rx path while enabling/disabling workaround */
2501         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2502         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2503                                         phy_reg | (1 << 14));
2504         if (ret_val)
2505                 return ret_val;
2506
2507         if (enable) {
2508                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2509                  * SHRAL/H) and initial CRC values to the MAC
2510                  */
2511                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2512                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2513                         u32 addr_high, addr_low;
2514
2515                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2516                         if (!(addr_high & E1000_RAH_AV))
2517                                 continue;
2518                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2519                         mac_addr[0] = (addr_low & 0xFF);
2520                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2521                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2522                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2523                         mac_addr[4] = (addr_high & 0xFF);
2524                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2525
2526 #ifndef CRC32_OS_SUPPORT
2527                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2528                                         e1000_calc_rx_da_crc(mac_addr));
2529 #else /* CRC32_OS_SUPPORT */
2530                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2531                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2532 #endif /* CRC32_OS_SUPPORT */
2533                 }
2534
2535                 /* Write Rx addresses to the PHY */
2536                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2537
2538                 /* Enable jumbo frame workaround in the MAC */
2539                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2540                 mac_reg &= ~(1 << 14);
2541                 mac_reg |= (7 << 15);
2542                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2543
2544                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2545                 mac_reg |= E1000_RCTL_SECRC;
2546                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2547
2548                 ret_val = e1000_read_kmrn_reg_generic(hw,
2549                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2550                                                 &data);
2551                 if (ret_val)
2552                         return ret_val;
2553                 ret_val = e1000_write_kmrn_reg_generic(hw,
2554                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2555                                                 data | (1 << 0));
2556                 if (ret_val)
2557                         return ret_val;
2558                 ret_val = e1000_read_kmrn_reg_generic(hw,
2559                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2560                                                 &data);
2561                 if (ret_val)
2562                         return ret_val;
2563                 data &= ~(0xF << 8);
2564                 data |= (0xB << 8);
2565                 ret_val = e1000_write_kmrn_reg_generic(hw,
2566                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2567                                                 data);
2568                 if (ret_val)
2569                         return ret_val;
2570
2571                 /* Enable jumbo frame workaround in the PHY */
2572                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2573                 data &= ~(0x7F << 5);
2574                 data |= (0x37 << 5);
2575                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2576                 if (ret_val)
2577                         return ret_val;
2578                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2579                 data &= ~(1 << 13);
2580                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2581                 if (ret_val)
2582                         return ret_val;
2583                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2584                 data &= ~(0x3FF << 2);
2585                 data |= (0x1A << 2);
2586                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2587                 if (ret_val)
2588                         return ret_val;
2589                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2590                 if (ret_val)
2591                         return ret_val;
2592                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2593                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2594                                                 (1 << 10));
2595                 if (ret_val)
2596                         return ret_val;
2597         } else {
2598                 /* Write MAC register values back to h/w defaults */
2599                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2600                 mac_reg &= ~(0xF << 14);
2601                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2602
2603                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2604                 mac_reg &= ~E1000_RCTL_SECRC;
2605                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2606
2607                 ret_val = e1000_read_kmrn_reg_generic(hw,
2608                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2609                                                 &data);
2610                 if (ret_val)
2611                         return ret_val;
2612                 ret_val = e1000_write_kmrn_reg_generic(hw,
2613                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2614                                                 data & ~(1 << 0));
2615                 if (ret_val)
2616                         return ret_val;
2617                 ret_val = e1000_read_kmrn_reg_generic(hw,
2618                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2619                                                 &data);
2620                 if (ret_val)
2621                         return ret_val;
2622                 data &= ~(0xF << 8);
2623                 data |= (0xB << 8);
2624                 ret_val = e1000_write_kmrn_reg_generic(hw,
2625                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2626                                                 data);
2627                 if (ret_val)
2628                         return ret_val;
2629
2630                 /* Write PHY register values back to h/w defaults */
2631                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2632                 data &= ~(0x7F << 5);
2633                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2634                 if (ret_val)
2635                         return ret_val;
2636                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2637                 data |= (1 << 13);
2638                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2639                 if (ret_val)
2640                         return ret_val;
2641                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2642                 data &= ~(0x3FF << 2);
2643                 data |= (0x8 << 2);
2644                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2645                 if (ret_val)
2646                         return ret_val;
2647                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2648                 if (ret_val)
2649                         return ret_val;
2650                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2651                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2652                                                 ~(1 << 10));
2653                 if (ret_val)
2654                         return ret_val;
2655         }
2656
2657         /* re-enable Rx path after enabling/disabling workaround */
2658         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2659                                      ~(1 << 14));
2660 }
2661
2662 /**
2663  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2664  *  done after every PHY reset.
2665  **/
2666 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2667 {
2668         s32 ret_val = E1000_SUCCESS;
2669
2670         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2671
2672         if (hw->mac.type != e1000_pch2lan)
2673                 return E1000_SUCCESS;
2674
2675         /* Set MDIO slow mode before any other MDIO access */
2676         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2677         if (ret_val)
2678                 return ret_val;
2679
2680         ret_val = hw->phy.ops.acquire(hw);
2681         if (ret_val)
2682                 return ret_val;
2683         /* set MSE higher to enable link to stay up when noise is high */
2684         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2685         if (ret_val)
2686                 goto release;
2687         /* drop link after 5 times MSE threshold was reached */
2688         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2689 release:
2690         hw->phy.ops.release(hw);
2691
2692         return ret_val;
2693 }
2694
2695 /**
2696  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2697  *  @hw:   pointer to the HW structure
2698  *
2699  *  Workaround to set the K1 beacon duration for 82579 parts
2700  **/
2701 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2702 {
2703         s32 ret_val = E1000_SUCCESS;
2704         u16 status_reg = 0;
2705         u32 mac_reg;
2706         u16 phy_reg;
2707
2708         DEBUGFUNC("e1000_k1_workaround_lv");
2709
2710         if (hw->mac.type != e1000_pch2lan)
2711                 return E1000_SUCCESS;
2712
2713         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2714         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2715         if (ret_val)
2716                 return ret_val;
2717
2718         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2719             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2720                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2721                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2722
2723                 ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
2724                 if (ret_val)
2725                         return ret_val;
2726
2727                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2728                         u16 pm_phy_reg;
2729
2730                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2731                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2732                         /* LV 1G Packet drop issue wa  */
2733                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2734                                                        &pm_phy_reg);
2735                         if (ret_val)
2736                                 return ret_val;
2737                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2738                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2739                                                         pm_phy_reg);
2740                         if (ret_val)
2741                                 return ret_val;
2742                 } else {
2743                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2744                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2745                 }
2746                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2747                 ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
2748         }
2749
2750         return ret_val;
2751 }
2752
2753 /**
2754  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2755  *  @hw:   pointer to the HW structure
2756  *  @gate: boolean set to true to gate, false to ungate
2757  *
2758  *  Gate/ungate the automatic PHY configuration via hardware; perform
2759  *  the configuration via software instead.
2760  **/
2761 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2762 {
2763         u32 extcnf_ctrl;
2764
2765         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2766
2767         if (hw->mac.type < e1000_pch2lan)
2768                 return;
2769
2770         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2771
2772         if (gate)
2773                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2774         else
2775                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2776
2777         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2778 }
2779
2780 /**
2781  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2782  *  @hw: pointer to the HW structure
2783  *
2784  *  Check the appropriate indication the MAC has finished configuring the
2785  *  PHY after a software reset.
2786  **/
2787 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2788 {
2789         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2790
2791         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2792
2793         /* Wait for basic configuration completes before proceeding */
2794         do {
2795                 data = E1000_READ_REG(hw, E1000_STATUS);
2796                 data &= E1000_STATUS_LAN_INIT_DONE;
2797                 usec_delay(100);
2798         } while ((!data) && --loop);
2799
2800         /* If basic configuration is incomplete before the above loop
2801          * count reaches 0, loading the configuration from NVM will
2802          * leave the PHY in a bad state possibly resulting in no link.
2803          */
2804         if (loop == 0)
2805                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2806
2807         /* Clear the Init Done bit for the next init event */
2808         data = E1000_READ_REG(hw, E1000_STATUS);
2809         data &= ~E1000_STATUS_LAN_INIT_DONE;
2810         E1000_WRITE_REG(hw, E1000_STATUS, data);
2811 }
2812
2813 /**
2814  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2815  *  @hw: pointer to the HW structure
2816  **/
2817 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2818 {
2819         s32 ret_val = E1000_SUCCESS;
2820         u16 reg;
2821
2822         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2823
2824         if (hw->phy.ops.check_reset_block(hw))
2825                 return E1000_SUCCESS;
2826
2827         /* Allow time for h/w to get to quiescent state after reset */
2828         msec_delay(10);
2829
2830         /* Perform any necessary post-reset workarounds */
2831         switch (hw->mac.type) {
2832         case e1000_pchlan:
2833                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2834                 if (ret_val)
2835                         return ret_val;
2836                 break;
2837         case e1000_pch2lan:
2838                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2839                 if (ret_val)
2840                         return ret_val;
2841                 break;
2842         default:
2843                 break;
2844         }
2845
2846         /* Clear the host wakeup bit after lcd reset */
2847         if (hw->mac.type >= e1000_pchlan) {
2848                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2849                 reg &= ~BM_WUC_HOST_WU_BIT;
2850                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2851         }
2852
2853         /* Configure the LCD with the extended configuration region in NVM */
2854         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2855         if (ret_val)
2856                 return ret_val;
2857
2858         /* Configure the LCD with the OEM bits in NVM */
2859         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2860
2861         if (hw->mac.type == e1000_pch2lan) {
2862                 /* Ungate automatic PHY configuration on non-managed 82579 */
2863                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2864                     E1000_ICH_FWSM_FW_VALID)) {
2865                         msec_delay(10);
2866                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2867                 }
2868
2869                 /* Set EEE LPI Update Timer to 200usec */
2870                 ret_val = hw->phy.ops.acquire(hw);
2871                 if (ret_val)
2872                         return ret_val;
2873                 ret_val = e1000_write_emi_reg_locked(hw,
2874                                                      I82579_LPI_UPDATE_TIMER,
2875                                                      0x1387);
2876                 hw->phy.ops.release(hw);
2877         }
2878
2879         return ret_val;
2880 }
2881
2882 /**
2883  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2884  *  @hw: pointer to the HW structure
2885  *
2886  *  Resets the PHY
2887  *  This is a function pointer entry point called by drivers
2888  *  or other shared routines.
2889  **/
2890 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2891 {
2892         s32 ret_val = E1000_SUCCESS;
2893
2894         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2895
2896         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2897         if ((hw->mac.type == e1000_pch2lan) &&
2898             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2899                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2900
2901         ret_val = e1000_phy_hw_reset_generic(hw);
2902         if (ret_val)
2903                 return ret_val;
2904
2905         return e1000_post_phy_reset_ich8lan(hw);
2906 }
2907
2908 /**
2909  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2910  *  @hw: pointer to the HW structure
2911  *  @active: true to enable LPLU, false to disable
2912  *
2913  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2914  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2915  *  the phy speed. This function will manually set the LPLU bit and restart
2916  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2917  *  since it configures the same bit.
2918  **/
2919 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2920 {
2921         s32 ret_val;
2922         u16 oem_reg;
2923
2924         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2925
2926         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2927         if (ret_val)
2928                 return ret_val;
2929
2930         if (active)
2931                 oem_reg |= HV_OEM_BITS_LPLU;
2932         else
2933                 oem_reg &= ~HV_OEM_BITS_LPLU;
2934
2935         if (!hw->phy.ops.check_reset_block(hw))
2936                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2937
2938         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2939 }
2940
2941 /**
2942  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2943  *  @hw: pointer to the HW structure
2944  *  @active: true to enable LPLU, false to disable
2945  *
2946  *  Sets the LPLU D0 state according to the active flag.  When
2947  *  activating LPLU this function also disables smart speed
2948  *  and vice versa.  LPLU will not be activated unless the
2949  *  device autonegotiation advertisement meets standards of
2950  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2951  *  This is a function pointer entry point only called by
2952  *  PHY setup routines.
2953  **/
2954 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2955 {
2956         struct e1000_phy_info *phy = &hw->phy;
2957         u32 phy_ctrl;
2958         s32 ret_val = E1000_SUCCESS;
2959         u16 data;
2960
2961         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
2962
2963         if (phy->type == e1000_phy_ife)
2964                 return E1000_SUCCESS;
2965
2966         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2967
2968         if (active) {
2969                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2970                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2971
2972                 if (phy->type != e1000_phy_igp_3)
2973                         return E1000_SUCCESS;
2974
2975                 /* Call gig speed drop workaround on LPLU before accessing
2976                  * any PHY registers
2977                  */
2978                 if (hw->mac.type == e1000_ich8lan)
2979                         e1000_gig_downshift_workaround_ich8lan(hw);
2980
2981                 /* When LPLU is enabled, we should disable SmartSpeed */
2982                 ret_val = phy->ops.read_reg(hw,
2983                                             IGP01E1000_PHY_PORT_CONFIG,
2984                                             &data);
2985                 if (ret_val)
2986                         return ret_val;
2987                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2988                 ret_val = phy->ops.write_reg(hw,
2989                                              IGP01E1000_PHY_PORT_CONFIG,
2990                                              data);
2991                 if (ret_val)
2992                         return ret_val;
2993         } else {
2994                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2995                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2996
2997                 if (phy->type != e1000_phy_igp_3)
2998                         return E1000_SUCCESS;
2999
3000                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3001                  * during Dx states where the power conservation is most
3002                  * important.  During driver activity we should enable
3003                  * SmartSpeed, so performance is maintained.
3004                  */
3005                 if (phy->smart_speed == e1000_smart_speed_on) {
3006                         ret_val = phy->ops.read_reg(hw,
3007                                                     IGP01E1000_PHY_PORT_CONFIG,
3008                                                     &data);
3009                         if (ret_val)
3010                                 return ret_val;
3011
3012                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3013                         ret_val = phy->ops.write_reg(hw,
3014                                                      IGP01E1000_PHY_PORT_CONFIG,
3015                                                      data);
3016                         if (ret_val)
3017                                 return ret_val;
3018                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3019                         ret_val = phy->ops.read_reg(hw,
3020                                                     IGP01E1000_PHY_PORT_CONFIG,
3021                                                     &data);
3022                         if (ret_val)
3023                                 return ret_val;
3024
3025                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3026                         ret_val = phy->ops.write_reg(hw,
3027                                                      IGP01E1000_PHY_PORT_CONFIG,
3028                                                      data);
3029                         if (ret_val)
3030                                 return ret_val;
3031                 }
3032         }
3033
3034         return E1000_SUCCESS;
3035 }
3036
3037 /**
3038  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3039  *  @hw: pointer to the HW structure
3040  *  @active: true to enable LPLU, false to disable
3041  *
3042  *  Sets the LPLU D3 state according to the active flag.  When
3043  *  activating LPLU this function also disables smart speed
3044  *  and vice versa.  LPLU will not be activated unless the
3045  *  device autonegotiation advertisement meets standards of
3046  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3047  *  This is a function pointer entry point only called by
3048  *  PHY setup routines.
3049  **/
3050 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3051 {
3052         struct e1000_phy_info *phy = &hw->phy;
3053         u32 phy_ctrl;
3054         s32 ret_val = E1000_SUCCESS;
3055         u16 data;
3056
3057         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3058
3059         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3060
3061         if (!active) {
3062                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3063                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3064
3065                 if (phy->type != e1000_phy_igp_3)
3066                         return E1000_SUCCESS;
3067
3068                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3069                  * during Dx states where the power conservation is most
3070                  * important.  During driver activity we should enable
3071                  * SmartSpeed, so performance is maintained.
3072                  */
3073                 if (phy->smart_speed == e1000_smart_speed_on) {
3074                         ret_val = phy->ops.read_reg(hw,
3075                                                     IGP01E1000_PHY_PORT_CONFIG,
3076                                                     &data);
3077                         if (ret_val)
3078                                 return ret_val;
3079
3080                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3081                         ret_val = phy->ops.write_reg(hw,
3082                                                      IGP01E1000_PHY_PORT_CONFIG,
3083                                                      data);
3084                         if (ret_val)
3085                                 return ret_val;
3086                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3087                         ret_val = phy->ops.read_reg(hw,
3088                                                     IGP01E1000_PHY_PORT_CONFIG,
3089                                                     &data);
3090                         if (ret_val)
3091                                 return ret_val;
3092
3093                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3094                         ret_val = phy->ops.write_reg(hw,
3095                                                      IGP01E1000_PHY_PORT_CONFIG,
3096                                                      data);
3097                         if (ret_val)
3098                                 return ret_val;
3099                 }
3100         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3101                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3102                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3103                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3104                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3105
3106                 if (phy->type != e1000_phy_igp_3)
3107                         return E1000_SUCCESS;
3108
3109                 /* Call gig speed drop workaround on LPLU before accessing
3110                  * any PHY registers
3111                  */
3112                 if (hw->mac.type == e1000_ich8lan)
3113                         e1000_gig_downshift_workaround_ich8lan(hw);
3114
3115                 /* When LPLU is enabled, we should disable SmartSpeed */
3116                 ret_val = phy->ops.read_reg(hw,
3117                                             IGP01E1000_PHY_PORT_CONFIG,
3118                                             &data);
3119                 if (ret_val)
3120                         return ret_val;
3121
3122                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3123                 ret_val = phy->ops.write_reg(hw,
3124                                              IGP01E1000_PHY_PORT_CONFIG,
3125                                              data);
3126         }
3127
3128         return ret_val;
3129 }
3130
3131 /**
3132  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3133  *  @hw: pointer to the HW structure
3134  *  @bank:  pointer to the variable that returns the active bank
3135  *
3136  *  Reads signature byte from the NVM using the flash access registers.
3137  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3138  **/
3139 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3140 {
3141         u32 eecd;
3142         struct e1000_nvm_info *nvm = &hw->nvm;
3143         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3144         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3145         u8 sig_byte = 0;
3146         s32 ret_val;
3147
3148         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3149
3150         switch (hw->mac.type) {
3151         case e1000_ich8lan:
3152         case e1000_ich9lan:
3153                 eecd = E1000_READ_REG(hw, E1000_EECD);
3154                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3155                     E1000_EECD_SEC1VAL_VALID_MASK) {
3156                         if (eecd & E1000_EECD_SEC1VAL)
3157                                 *bank = 1;
3158                         else
3159                                 *bank = 0;
3160
3161                         return E1000_SUCCESS;
3162                 }
3163                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3164                 /* fall-thru */
3165         default:
3166                 /* set bank to 0 in case flash read fails */
3167                 *bank = 0;
3168
3169                 /* Check bank 0 */
3170                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3171                                                         &sig_byte);
3172                 if (ret_val)
3173                         return ret_val;
3174                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3175                     E1000_ICH_NVM_SIG_VALUE) {
3176                         *bank = 0;
3177                         return E1000_SUCCESS;
3178                 }
3179
3180                 /* Check bank 1 */
3181                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3182                                                         bank1_offset,
3183                                                         &sig_byte);
3184                 if (ret_val)
3185                         return ret_val;
3186                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3187                     E1000_ICH_NVM_SIG_VALUE) {
3188                         *bank = 1;
3189                         return E1000_SUCCESS;
3190                 }
3191
3192                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3193                 return -E1000_ERR_NVM;
3194         }
3195 }
3196
3197 /**
3198  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3199  *  @hw: pointer to the HW structure
3200  *  @offset: The offset (in bytes) of the word(s) to read.
3201  *  @words: Size of data to read in words
3202  *  @data: Pointer to the word(s) to read at offset.
3203  *
3204  *  Reads a word(s) from the NVM using the flash access registers.
3205  **/
3206 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3207                                   u16 *data)
3208 {
3209         struct e1000_nvm_info *nvm = &hw->nvm;
3210         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3211         u32 act_offset;
3212         s32 ret_val = E1000_SUCCESS;
3213         u32 bank = 0;
3214         u16 i, word;
3215
3216         DEBUGFUNC("e1000_read_nvm_ich8lan");
3217
3218         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3219             (words == 0)) {
3220                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3221                 ret_val = -E1000_ERR_NVM;
3222                 goto out;
3223         }
3224
3225         nvm->ops.acquire(hw);
3226
3227         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3228         if (ret_val != E1000_SUCCESS) {
3229                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3230                 bank = 0;
3231         }
3232
3233         act_offset = (bank) ? nvm->flash_bank_size : 0;
3234         act_offset += offset;
3235
3236         ret_val = E1000_SUCCESS;
3237         for (i = 0; i < words; i++) {
3238                 if (dev_spec->shadow_ram[offset+i].modified) {
3239                         data[i] = dev_spec->shadow_ram[offset+i].value;
3240                 } else {
3241                         ret_val = e1000_read_flash_word_ich8lan(hw,
3242                                                                 act_offset + i,
3243                                                                 &word);
3244                         if (ret_val)
3245                                 break;
3246                         data[i] = word;
3247                 }
3248         }
3249
3250         nvm->ops.release(hw);
3251
3252 out:
3253         if (ret_val)
3254                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3255
3256         return ret_val;
3257 }
3258
3259 /**
3260  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3261  *  @hw: pointer to the HW structure
3262  *
3263  *  This function does initial flash setup so that a new read/write/erase cycle
3264  *  can be started.
3265  **/
3266 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3267 {
3268         union ich8_hws_flash_status hsfsts;
3269         s32 ret_val = -E1000_ERR_NVM;
3270
3271         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3272
3273         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3274
3275         /* Check if the flash descriptor is valid */
3276         if (!hsfsts.hsf_status.fldesvalid) {
3277                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3278                 return -E1000_ERR_NVM;
3279         }
3280
3281         /* Clear FCERR and DAEL in hw status by writing 1 */
3282         hsfsts.hsf_status.flcerr = 1;
3283         hsfsts.hsf_status.dael = 1;
3284         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3285
3286         /* Either we should have a hardware SPI cycle in progress
3287          * bit to check against, in order to start a new cycle or
3288          * FDONE bit should be changed in the hardware so that it
3289          * is 1 after hardware reset, which can then be used as an
3290          * indication whether a cycle is in progress or has been
3291          * completed.
3292          */
3293
3294         if (!hsfsts.hsf_status.flcinprog) {
3295                 /* There is no cycle running at present,
3296                  * so we can start a cycle.
3297                  * Begin by setting Flash Cycle Done.
3298                  */
3299                 hsfsts.hsf_status.flcdone = 1;
3300                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3301                 ret_val = E1000_SUCCESS;
3302         } else {
3303                 s32 i;
3304
3305                 /* Otherwise poll for sometime so the current
3306                  * cycle has a chance to end before giving up.
3307                  */
3308                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3309                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3310                                                               ICH_FLASH_HSFSTS);
3311                         if (!hsfsts.hsf_status.flcinprog) {
3312                                 ret_val = E1000_SUCCESS;
3313                                 break;
3314                         }
3315                         usec_delay(1);
3316                 }
3317                 if (ret_val == E1000_SUCCESS) {
3318                         /* Successful in waiting for previous cycle to timeout,
3319                          * now set the Flash Cycle Done.
3320                          */
3321                         hsfsts.hsf_status.flcdone = 1;
3322                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3323                                                 hsfsts.regval);
3324                 } else {
3325                         DEBUGOUT("Flash controller busy, cannot get access\n");
3326                 }
3327         }
3328
3329         return ret_val;
3330 }
3331
3332 /**
3333  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3334  *  @hw: pointer to the HW structure
3335  *  @timeout: maximum time to wait for completion
3336  *
3337  *  This function starts a flash cycle and waits for its completion.
3338  **/
3339 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3340 {
3341         union ich8_hws_flash_ctrl hsflctl;
3342         union ich8_hws_flash_status hsfsts;
3343         u32 i = 0;
3344
3345         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3346
3347         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3348         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3349         hsflctl.hsf_ctrl.flcgo = 1;
3350
3351         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3352
3353         /* wait till FDONE bit is set to 1 */
3354         do {
3355                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3356                 if (hsfsts.hsf_status.flcdone)
3357                         break;
3358                 usec_delay(1);
3359         } while (i++ < timeout);
3360
3361         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3362                 return E1000_SUCCESS;
3363
3364         return -E1000_ERR_NVM;
3365 }
3366
3367 /**
3368  *  e1000_read_flash_word_ich8lan - Read word from flash
3369  *  @hw: pointer to the HW structure
3370  *  @offset: offset to data location
3371  *  @data: pointer to the location for storing the data
3372  *
3373  *  Reads the flash word at offset into data.  Offset is converted
3374  *  to bytes before read.
3375  **/
3376 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3377                                          u16 *data)
3378 {
3379         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3380
3381         if (!data)
3382                 return -E1000_ERR_NVM;
3383
3384         /* Must convert offset into bytes. */
3385         offset <<= 1;
3386
3387         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3388 }
3389
3390 /**
3391  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3392  *  @hw: pointer to the HW structure
3393  *  @offset: The offset of the byte to read.
3394  *  @data: Pointer to a byte to store the value read.
3395  *
3396  *  Reads a single byte from the NVM using the flash access registers.
3397  **/
3398 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3399                                          u8 *data)
3400 {
3401         s32 ret_val;
3402         u16 word = 0;
3403
3404         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3405
3406         if (ret_val)
3407                 return ret_val;
3408
3409         *data = (u8)word;
3410
3411         return E1000_SUCCESS;
3412 }
3413
3414 /**
3415  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3416  *  @hw: pointer to the HW structure
3417  *  @offset: The offset (in bytes) of the byte or word to read.
3418  *  @size: Size of data to read, 1=byte 2=word
3419  *  @data: Pointer to the word to store the value read.
3420  *
3421  *  Reads a byte or word from the NVM using the flash access registers.
3422  **/
3423 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3424                                          u8 size, u16 *data)
3425 {
3426         union ich8_hws_flash_status hsfsts;
3427         union ich8_hws_flash_ctrl hsflctl;
3428         u32 flash_linear_addr;
3429         u32 flash_data = 0;
3430         s32 ret_val = -E1000_ERR_NVM;
3431         u8 count = 0;
3432
3433         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3434
3435         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3436                 return -E1000_ERR_NVM;
3437         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3438                              hw->nvm.flash_base_addr);
3439
3440         do {
3441                 usec_delay(1);
3442                 /* Steps */
3443                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3444                 if (ret_val != E1000_SUCCESS)
3445                         break;
3446                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3447
3448                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3449                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3450                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3451                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3452
3453                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3454
3455                 ret_val =
3456                     e1000_flash_cycle_ich8lan(hw,
3457                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3458
3459                 /* Check if FCERR is set to 1, if set to 1, clear it
3460                  * and try the whole sequence a few more times, else
3461                  * read in (shift in) the Flash Data0, the order is
3462                  * least significant byte first msb to lsb
3463                  */
3464                 if (ret_val == E1000_SUCCESS) {
3465                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3466                         if (size == 1)
3467                                 *data = (u8)(flash_data & 0x000000FF);
3468                         else if (size == 2)
3469                                 *data = (u16)(flash_data & 0x0000FFFF);
3470                         break;
3471                 } else {
3472                         /* If we've gotten here, then things are probably
3473                          * completely hosed, but if the error condition is
3474                          * detected, it won't hurt to give it another try...
3475                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3476                          */
3477                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3478                                                               ICH_FLASH_HSFSTS);
3479                         if (hsfsts.hsf_status.flcerr) {
3480                                 /* Repeat for some time before giving up. */
3481                                 continue;
3482                         } else if (!hsfsts.hsf_status.flcdone) {
3483                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3484                                 break;
3485                         }
3486                 }
3487         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3488
3489         return ret_val;
3490 }
3491
3492 /**
3493  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3494  *  @hw: pointer to the HW structure
3495  *  @offset: The offset (in bytes) of the word(s) to write.
3496  *  @words: Size of data to write in words
3497  *  @data: Pointer to the word(s) to write at offset.
3498  *
3499  *  Writes a byte or word to the NVM using the flash access registers.
3500  **/
3501 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3502                                    u16 *data)
3503 {
3504         struct e1000_nvm_info *nvm = &hw->nvm;
3505         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3506         u16 i;
3507
3508         DEBUGFUNC("e1000_write_nvm_ich8lan");
3509
3510         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3511             (words == 0)) {
3512                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3513                 return -E1000_ERR_NVM;
3514         }
3515
3516         nvm->ops.acquire(hw);
3517
3518         for (i = 0; i < words; i++) {
3519                 dev_spec->shadow_ram[offset+i].modified = true;
3520                 dev_spec->shadow_ram[offset+i].value = data[i];
3521         }
3522
3523         nvm->ops.release(hw);
3524
3525         return E1000_SUCCESS;
3526 }
3527
3528 /**
3529  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3530  *  @hw: pointer to the HW structure
3531  *
3532  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3533  *  which writes the checksum to the shadow ram.  The changes in the shadow
3534  *  ram are then committed to the EEPROM by processing each bank at a time
3535  *  checking for the modified bit and writing only the pending changes.
3536  *  After a successful commit, the shadow ram is cleared and is ready for
3537  *  future writes.
3538  **/
3539 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3540 {
3541         struct e1000_nvm_info *nvm = &hw->nvm;
3542         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3543         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3544         s32 ret_val;
3545         u16 data;
3546
3547         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3548
3549         ret_val = e1000_update_nvm_checksum_generic(hw);
3550         if (ret_val)
3551                 goto out;
3552
3553         if (nvm->type != e1000_nvm_flash_sw)
3554                 goto out;
3555
3556         nvm->ops.acquire(hw);
3557
3558         /* We're writing to the opposite bank so if we're on bank 1,
3559          * write to bank 0 etc.  We also need to erase the segment that
3560          * is going to be written
3561          */
3562         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3563         if (ret_val != E1000_SUCCESS) {
3564                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3565                 bank = 0;
3566         }
3567
3568         if (bank == 0) {
3569                 new_bank_offset = nvm->flash_bank_size;
3570                 old_bank_offset = 0;
3571                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3572                 if (ret_val)
3573                         goto release;
3574         } else {
3575                 old_bank_offset = nvm->flash_bank_size;
3576                 new_bank_offset = 0;
3577                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3578                 if (ret_val)
3579                         goto release;
3580         }
3581
3582         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3583                 /* Determine whether to write the value stored
3584                  * in the other NVM bank or a modified value stored
3585                  * in the shadow RAM
3586                  */
3587                 if (dev_spec->shadow_ram[i].modified) {
3588                         data = dev_spec->shadow_ram[i].value;
3589                 } else {
3590                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3591                                                                 old_bank_offset,
3592                                                                 &data);
3593                         if (ret_val)
3594                                 break;
3595                 }
3596
3597                 /* If the word is 0x13, then make sure the signature bits
3598                  * (15:14) are 11b until the commit has completed.
3599                  * This will allow us to write 10b which indicates the
3600                  * signature is valid.  We want to do this after the write
3601                  * has completed so that we don't mark the segment valid
3602                  * while the write is still in progress
3603                  */
3604                 if (i == E1000_ICH_NVM_SIG_WORD)
3605                         data |= E1000_ICH_NVM_SIG_MASK;
3606
3607                 /* Convert offset to bytes. */
3608                 act_offset = (i + new_bank_offset) << 1;
3609
3610                 usec_delay(100);
3611                 /* Write the bytes to the new bank. */
3612                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3613                                                                act_offset,
3614                                                                (u8)data);
3615                 if (ret_val)
3616                         break;
3617
3618                 usec_delay(100);
3619                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3620                                                           act_offset + 1,
3621                                                           (u8)(data >> 8));
3622                 if (ret_val)
3623                         break;
3624         }
3625
3626         /* Don't bother writing the segment valid bits if sector
3627          * programming failed.
3628          */
3629         if (ret_val) {
3630                 DEBUGOUT("Flash commit failed.\n");
3631                 goto release;
3632         }
3633
3634         /* Finally validate the new segment by setting bit 15:14
3635          * to 10b in word 0x13 , this can be done without an
3636          * erase as well since these bits are 11 to start with
3637          * and we need to change bit 14 to 0b
3638          */
3639         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3640         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3641         if (ret_val)
3642                 goto release;
3643
3644         data &= 0xBFFF;
3645         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3646                                                        act_offset * 2 + 1,
3647                                                        (u8)(data >> 8));
3648         if (ret_val)
3649                 goto release;
3650
3651         /* And invalidate the previously valid segment by setting
3652          * its signature word (0x13) high_byte to 0b. This can be
3653          * done without an erase because flash erase sets all bits
3654          * to 1's. We can write 1's to 0's without an erase
3655          */
3656         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3657         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3658         if (ret_val)
3659                 goto release;
3660
3661         /* Great!  Everything worked, we can now clear the cached entries. */
3662         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3663                 dev_spec->shadow_ram[i].modified = false;
3664                 dev_spec->shadow_ram[i].value = 0xFFFF;
3665         }
3666
3667 release:
3668         nvm->ops.release(hw);
3669
3670         /* Reload the EEPROM, or else modifications will not appear
3671          * until after the next adapter reset.
3672          */
3673         if (!ret_val) {
3674                 nvm->ops.reload(hw);
3675                 msec_delay(10);
3676         }
3677
3678 out:
3679         if (ret_val)
3680                 DEBUGOUT1("NVM update error: %d\n", ret_val);
3681
3682         return ret_val;
3683 }
3684
3685 /**
3686  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3687  *  @hw: pointer to the HW structure
3688  *
3689  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3690  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3691  *  calculated, in which case we need to calculate the checksum and set bit 6.
3692  **/
3693 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3694 {
3695         s32 ret_val;
3696         u16 data;
3697         u16 word;
3698         u16 valid_csum_mask;
3699
3700         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3701
3702         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3703          * the checksum needs to be fixed.  This bit is an indication that
3704          * the NVM was prepared by OEM software and did not calculate
3705          * the checksum...a likely scenario.
3706          */
3707         switch (hw->mac.type) {
3708         case e1000_pch_lpt:
3709                 word = NVM_COMPAT;
3710                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3711                 break;
3712         default:
3713                 word = NVM_FUTURE_INIT_WORD1;
3714                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3715                 break;
3716         }
3717
3718         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3719         if (ret_val)
3720                 return ret_val;
3721
3722         if (!(data & valid_csum_mask)) {
3723                 data |= valid_csum_mask;
3724                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3725                 if (ret_val)
3726                         return ret_val;
3727                 ret_val = hw->nvm.ops.update(hw);
3728                 if (ret_val)
3729                         return ret_val;
3730         }
3731
3732         return e1000_validate_nvm_checksum_generic(hw);
3733 }
3734
3735 /**
3736  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3737  *  @hw: pointer to the HW structure
3738  *  @offset: The offset (in bytes) of the byte/word to read.
3739  *  @size: Size of data to read, 1=byte 2=word
3740  *  @data: The byte(s) to write to the NVM.
3741  *
3742  *  Writes one/two bytes to the NVM using the flash access registers.
3743  **/
3744 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3745                                           u8 size, u16 data)
3746 {
3747         union ich8_hws_flash_status hsfsts;
3748         union ich8_hws_flash_ctrl hsflctl;
3749         u32 flash_linear_addr;
3750         u32 flash_data = 0;
3751         s32 ret_val;
3752         u8 count = 0;
3753
3754         DEBUGFUNC("e1000_write_ich8_data");
3755
3756         if (size < 1 || size > 2 || data > size * 0xff ||
3757             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3758                 return -E1000_ERR_NVM;
3759
3760         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3761                              hw->nvm.flash_base_addr);
3762
3763         do {
3764                 usec_delay(1);
3765                 /* Steps */
3766                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3767                 if (ret_val != E1000_SUCCESS)
3768                         break;
3769                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3770
3771                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3772                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3773                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3774                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3775
3776                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3777
3778                 if (size == 1)
3779                         flash_data = (u32)data & 0x00FF;
3780                 else
3781                         flash_data = (u32)data;
3782
3783                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3784
3785                 /* check if FCERR is set to 1 , if set to 1, clear it
3786                  * and try the whole sequence a few more times else done
3787                  */
3788                 ret_val =
3789                     e1000_flash_cycle_ich8lan(hw,
3790                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3791                 if (ret_val == E1000_SUCCESS)
3792                         break;
3793
3794                 /* If we're here, then things are most likely
3795                  * completely hosed, but if the error condition
3796                  * is detected, it won't hurt to give it another
3797                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3798                  */
3799                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3800                 if (hsfsts.hsf_status.flcerr)
3801                         /* Repeat for some time before giving up. */
3802                         continue;
3803                 if (!hsfsts.hsf_status.flcdone) {
3804                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3805                         break;
3806                 }
3807         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3808
3809         return ret_val;
3810 }
3811
3812 /**
3813  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3814  *  @hw: pointer to the HW structure
3815  *  @offset: The index of the byte to read.
3816  *  @data: The byte to write to the NVM.
3817  *
3818  *  Writes a single byte to the NVM using the flash access registers.
3819  **/
3820 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3821                                           u8 data)
3822 {
3823         u16 word = (u16)data;
3824
3825         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3826
3827         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3828 }
3829
3830 /**
3831  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3832  *  @hw: pointer to the HW structure
3833  *  @offset: The offset of the byte to write.
3834  *  @byte: The byte to write to the NVM.
3835  *
3836  *  Writes a single byte to the NVM using the flash access registers.
3837  *  Goes through a retry algorithm before giving up.
3838  **/
3839 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3840                                                 u32 offset, u8 byte)
3841 {
3842         s32 ret_val;
3843         u16 program_retries;
3844
3845         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3846
3847         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3848         if (!ret_val)
3849                 return ret_val;
3850
3851         for (program_retries = 0; program_retries < 100; program_retries++) {
3852                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3853                 usec_delay(100);
3854                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3855                 if (ret_val == E1000_SUCCESS)
3856                         break;
3857         }
3858         if (program_retries == 100)
3859                 return -E1000_ERR_NVM;
3860
3861         return E1000_SUCCESS;
3862 }
3863
3864 /**
3865  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3866  *  @hw: pointer to the HW structure
3867  *  @bank: 0 for first bank, 1 for second bank, etc.
3868  *
3869  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3870  *  bank N is 4096 * N + flash_reg_addr.
3871  **/
3872 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3873 {
3874         struct e1000_nvm_info *nvm = &hw->nvm;
3875         union ich8_hws_flash_status hsfsts;
3876         union ich8_hws_flash_ctrl hsflctl;
3877         u32 flash_linear_addr;
3878         /* bank size is in 16bit words - adjust to bytes */
3879         u32 flash_bank_size = nvm->flash_bank_size * 2;
3880         s32 ret_val;
3881         s32 count = 0;
3882         s32 j, iteration, sector_size;
3883
3884         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3885
3886         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3887
3888         /* Determine HW Sector size: Read BERASE bits of hw flash status
3889          * register
3890          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3891          *     consecutive sectors.  The start index for the nth Hw sector
3892          *     can be calculated as = bank * 4096 + n * 256
3893          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3894          *     The start index for the nth Hw sector can be calculated
3895          *     as = bank * 4096
3896          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3897          *     (ich9 only, otherwise error condition)
3898          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3899          */
3900         switch (hsfsts.hsf_status.berasesz) {
3901         case 0:
3902                 /* Hw sector size 256 */
3903                 sector_size = ICH_FLASH_SEG_SIZE_256;
3904                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3905                 break;
3906         case 1:
3907                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3908                 iteration = 1;
3909                 break;
3910         case 2:
3911                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3912                 iteration = 1;
3913                 break;
3914         case 3:
3915                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3916                 iteration = 1;
3917                 break;
3918         default:
3919                 return -E1000_ERR_NVM;
3920         }
3921
3922         /* Start with the base address, then add the sector offset. */
3923         flash_linear_addr = hw->nvm.flash_base_addr;
3924         flash_linear_addr += (bank) ? flash_bank_size : 0;
3925
3926         for (j = 0; j < iteration; j++) {
3927                 do {
3928                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3929
3930                         /* Steps */
3931                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3932                         if (ret_val)
3933                                 return ret_val;
3934
3935                         /* Write a value 11 (block Erase) in Flash
3936                          * Cycle field in hw flash control
3937                          */
3938                         hsflctl.regval =
3939                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3940
3941                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3942                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3943                                                 hsflctl.regval);
3944
3945                         /* Write the last 24 bits of an index within the
3946                          * block into Flash Linear address field in Flash
3947                          * Address.
3948                          */
3949                         flash_linear_addr += (j * sector_size);
3950                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3951                                               flash_linear_addr);
3952
3953                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3954                         if (ret_val == E1000_SUCCESS)
3955                                 break;
3956
3957                         /* Check if FCERR is set to 1.  If 1,
3958                          * clear it and try the whole sequence
3959                          * a few more times else Done
3960                          */
3961                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3962                                                       ICH_FLASH_HSFSTS);
3963                         if (hsfsts.hsf_status.flcerr)
3964                                 /* repeat for some time before giving up */
3965                                 continue;
3966                         else if (!hsfsts.hsf_status.flcdone)
3967                                 return ret_val;
3968                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3969         }
3970
3971         return E1000_SUCCESS;
3972 }
3973
3974 /**
3975  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3976  *  @hw: pointer to the HW structure
3977  *  @data: Pointer to the LED settings
3978  *
3979  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3980  *  settings is all 0's or F's, set the LED default to a valid LED default
3981  *  setting.
3982  **/
3983 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3984 {
3985         s32 ret_val;
3986
3987         DEBUGFUNC("e1000_valid_led_default_ich8lan");
3988
3989         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3990         if (ret_val) {
3991                 DEBUGOUT("NVM Read Error\n");
3992                 return ret_val;
3993         }
3994
3995         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3996                 *data = ID_LED_DEFAULT_ICH8LAN;
3997
3998         return E1000_SUCCESS;
3999 }
4000
4001 /**
4002  *  e1000_id_led_init_pchlan - store LED configurations
4003  *  @hw: pointer to the HW structure
4004  *
4005  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4006  *  the PHY LED configuration register.
4007  *
4008  *  PCH also does not have an "always on" or "always off" mode which
4009  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4010  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4011  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4012  *  link based on logic in e1000_led_[on|off]_pchlan().
4013  **/
4014 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4015 {
4016         struct e1000_mac_info *mac = &hw->mac;
4017         s32 ret_val;
4018         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4019         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4020         u16 data, i, temp, shift;
4021
4022         DEBUGFUNC("e1000_id_led_init_pchlan");
4023
4024         /* Get default ID LED modes */
4025         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4026         if (ret_val)
4027                 return ret_val;
4028
4029         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4030         mac->ledctl_mode1 = mac->ledctl_default;
4031         mac->ledctl_mode2 = mac->ledctl_default;
4032
4033         for (i = 0; i < 4; i++) {
4034                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4035                 shift = (i * 5);
4036                 switch (temp) {
4037                 case ID_LED_ON1_DEF2:
4038                 case ID_LED_ON1_ON2:
4039                 case ID_LED_ON1_OFF2:
4040                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4041                         mac->ledctl_mode1 |= (ledctl_on << shift);
4042                         break;
4043                 case ID_LED_OFF1_DEF2:
4044                 case ID_LED_OFF1_ON2:
4045                 case ID_LED_OFF1_OFF2:
4046                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4047                         mac->ledctl_mode1 |= (ledctl_off << shift);
4048                         break;
4049                 default:
4050                         /* Do nothing */
4051                         break;
4052                 }
4053                 switch (temp) {
4054                 case ID_LED_DEF1_ON2:
4055                 case ID_LED_ON1_ON2:
4056                 case ID_LED_OFF1_ON2:
4057                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4058                         mac->ledctl_mode2 |= (ledctl_on << shift);
4059                         break;
4060                 case ID_LED_DEF1_OFF2:
4061                 case ID_LED_ON1_OFF2:
4062                 case ID_LED_OFF1_OFF2:
4063                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4064                         mac->ledctl_mode2 |= (ledctl_off << shift);
4065                         break;
4066                 default:
4067                         /* Do nothing */
4068                         break;
4069                 }
4070         }
4071
4072         return E1000_SUCCESS;
4073 }
4074
4075 /**
4076  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4077  *  @hw: pointer to the HW structure
4078  *
4079  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4080  *  register, so the the bus width is hard coded.
4081  **/
4082 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4083 {
4084         struct e1000_bus_info *bus = &hw->bus;
4085         s32 ret_val;
4086
4087         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4088
4089         ret_val = e1000_get_bus_info_pcie_generic(hw);
4090
4091         /* ICH devices are "PCI Express"-ish.  They have
4092          * a configuration space, but do not contain
4093          * PCI Express Capability registers, so bus width
4094          * must be hardcoded.
4095          */
4096         if (bus->width == e1000_bus_width_unknown)
4097                 bus->width = e1000_bus_width_pcie_x1;
4098
4099         return ret_val;
4100 }
4101
4102 /**
4103  *  e1000_reset_hw_ich8lan - Reset the hardware
4104  *  @hw: pointer to the HW structure
4105  *
4106  *  Does a full reset of the hardware which includes a reset of the PHY and
4107  *  MAC.
4108  **/
4109 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4110 {
4111         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4112         u16 kum_cfg;
4113         u32 ctrl, reg;
4114         s32 ret_val;
4115
4116         DEBUGFUNC("e1000_reset_hw_ich8lan");
4117
4118         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4119          * on the last TLP read/write transaction when MAC is reset.
4120          */
4121         ret_val = e1000_disable_pcie_master_generic(hw);
4122         if (ret_val)
4123                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4124
4125         DEBUGOUT("Masking off all interrupts\n");
4126         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4127
4128         /* Disable the Transmit and Receive units.  Then delay to allow
4129          * any pending transactions to complete before we hit the MAC
4130          * with the global reset.
4131          */
4132         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4133         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4134         E1000_WRITE_FLUSH(hw);
4135
4136         msec_delay(10);
4137
4138         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4139         if (hw->mac.type == e1000_ich8lan) {
4140                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4141                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4142                 /* Set Packet Buffer Size to 16k. */
4143                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4144         }
4145
4146         if (hw->mac.type == e1000_pchlan) {
4147                 /* Save the NVM K1 bit setting*/
4148                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4149                 if (ret_val)
4150                         return ret_val;
4151
4152                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4153                         dev_spec->nvm_k1_enabled = true;
4154                 else
4155                         dev_spec->nvm_k1_enabled = false;
4156         }
4157
4158         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4159
4160         if (!hw->phy.ops.check_reset_block(hw)) {
4161                 /* Full-chip reset requires MAC and PHY reset at the same
4162                  * time to make sure the interface between MAC and the
4163                  * external PHY is reset.
4164                  */
4165                 ctrl |= E1000_CTRL_PHY_RST;
4166
4167                 /* Gate automatic PHY configuration by hardware on
4168                  * non-managed 82579
4169                  */
4170                 if ((hw->mac.type == e1000_pch2lan) &&
4171                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4172                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4173         }
4174         ret_val = e1000_acquire_swflag_ich8lan(hw);
4175         DEBUGOUT("Issuing a global reset to ich8lan\n");
4176         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4177         /* cannot issue a flush here because it hangs the hardware */
4178         msec_delay(20);
4179
4180         /* Set Phy Config Counter to 50msec */
4181         if (hw->mac.type == e1000_pch2lan) {
4182                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4183                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4184                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4185                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4186         }
4187
4188         if (!ret_val)
4189                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4190
4191         if (ctrl & E1000_CTRL_PHY_RST) {
4192                 ret_val = hw->phy.ops.get_cfg_done(hw);
4193                 if (ret_val)
4194                         return ret_val;
4195
4196                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4197                 if (ret_val)
4198                         return ret_val;
4199         }
4200
4201         /* For PCH, this write will make sure that any noise
4202          * will be detected as a CRC error and be dropped rather than show up
4203          * as a bad packet to the DMA engine.
4204          */
4205         if (hw->mac.type == e1000_pchlan)
4206                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4207
4208         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4209         E1000_READ_REG(hw, E1000_ICR);
4210
4211         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4212         reg |= E1000_KABGTXD_BGSQLBIAS;
4213         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4214
4215         return E1000_SUCCESS;
4216 }
4217
4218 /**
4219  *  e1000_init_hw_ich8lan - Initialize the hardware
4220  *  @hw: pointer to the HW structure
4221  *
4222  *  Prepares the hardware for transmit and receive by doing the following:
4223  *   - initialize hardware bits
4224  *   - initialize LED identification
4225  *   - setup receive address registers
4226  *   - setup flow control
4227  *   - setup transmit descriptors
4228  *   - clear statistics
4229  **/
4230 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4231 {
4232         struct e1000_mac_info *mac = &hw->mac;
4233         u32 ctrl_ext, txdctl, snoop;
4234         s32 ret_val;
4235         u16 i;
4236
4237         DEBUGFUNC("e1000_init_hw_ich8lan");
4238
4239         e1000_initialize_hw_bits_ich8lan(hw);
4240
4241         /* Initialize identification LED */
4242         ret_val = mac->ops.id_led_init(hw);
4243         /* An error is not fatal and we should not stop init due to this */
4244         if (ret_val)
4245                 DEBUGOUT("Error initializing identification LED\n");
4246
4247         /* Setup the receive address. */
4248         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4249
4250         /* Zero out the Multicast HASH table */
4251         DEBUGOUT("Zeroing the MTA\n");
4252         for (i = 0; i < mac->mta_reg_count; i++)
4253                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4254
4255         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4256          * the ME.  Disable wakeup by clearing the host wakeup bit.
4257          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4258          */
4259         if (hw->phy.type == e1000_phy_82578) {
4260                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4261                 i &= ~BM_WUC_HOST_WU_BIT;
4262                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4263                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4264                 if (ret_val)
4265                         return ret_val;
4266         }
4267
4268         /* Setup link and flow control */
4269         ret_val = mac->ops.setup_link(hw);
4270
4271         /* Set the transmit descriptor write-back policy for both queues */
4272         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4273         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4274                   E1000_TXDCTL_FULL_TX_DESC_WB);
4275         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4276                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4277         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4278         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4279         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4280                   E1000_TXDCTL_FULL_TX_DESC_WB);
4281         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4282                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4283         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4284
4285         /* ICH8 has opposite polarity of no_snoop bits.
4286          * By default, we should use snoop behavior.
4287          */
4288         if (mac->type == e1000_ich8lan)
4289                 snoop = PCIE_ICH8_SNOOP_ALL;
4290         else
4291                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4292         e1000_set_pcie_no_snoop_generic(hw, snoop);
4293
4294         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4295         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4296         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4297
4298         /* Clear all of the statistics registers (clear on read).  It is
4299          * important that we do this after we have tried to establish link
4300          * because the symbol error count will increment wildly if there
4301          * is no link.
4302          */
4303         e1000_clear_hw_cntrs_ich8lan(hw);
4304
4305         return ret_val;
4306 }
4307
4308 /**
4309  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4310  *  @hw: pointer to the HW structure
4311  *
4312  *  Sets/Clears required hardware bits necessary for correctly setting up the
4313  *  hardware for transmit and receive.
4314  **/
4315 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4316 {
4317         u32 reg;
4318
4319         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4320
4321         /* Extended Device Control */
4322         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4323         reg |= (1 << 22);
4324         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4325         if (hw->mac.type >= e1000_pchlan)
4326                 reg |= E1000_CTRL_EXT_PHYPDEN;
4327         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4328
4329         /* Transmit Descriptor Control 0 */
4330         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4331         reg |= (1 << 22);
4332         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4333
4334         /* Transmit Descriptor Control 1 */
4335         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4336         reg |= (1 << 22);
4337         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4338
4339         /* Transmit Arbitration Control 0 */
4340         reg = E1000_READ_REG(hw, E1000_TARC(0));
4341         if (hw->mac.type == e1000_ich8lan)
4342                 reg |= (1 << 28) | (1 << 29);
4343         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4344         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4345
4346         /* Transmit Arbitration Control 1 */
4347         reg = E1000_READ_REG(hw, E1000_TARC(1));
4348         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4349                 reg &= ~(1 << 28);
4350         else
4351                 reg |= (1 << 28);
4352         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4353         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4354
4355         /* Device Status */
4356         if (hw->mac.type == e1000_ich8lan) {
4357                 reg = E1000_READ_REG(hw, E1000_STATUS);
4358                 reg &= ~(1 << 31);
4359                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4360         }
4361
4362         /* work-around descriptor data corruption issue during nfs v2 udp
4363          * traffic, just disable the nfs filtering capability
4364          */
4365         reg = E1000_READ_REG(hw, E1000_RFCTL);
4366         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4367
4368         /* Disable IPv6 extension header parsing because some malformed
4369          * IPv6 headers can hang the Rx.
4370          */
4371         if (hw->mac.type == e1000_ich8lan)
4372                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4373         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4374
4375         /* Enable ECC on Lynxpoint */
4376         if (hw->mac.type == e1000_pch_lpt) {
4377                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4378                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4379                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4380
4381                 reg = E1000_READ_REG(hw, E1000_CTRL);
4382                 reg |= E1000_CTRL_MEHE;
4383                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4384         }
4385
4386         return;
4387 }
4388
4389 /**
4390  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4391  *  @hw: pointer to the HW structure
4392  *
4393  *  Determines which flow control settings to use, then configures flow
4394  *  control.  Calls the appropriate media-specific link configuration
4395  *  function.  Assuming the adapter has a valid link partner, a valid link
4396  *  should be established.  Assumes the hardware has previously been reset
4397  *  and the transmitter and receiver are not enabled.
4398  **/
4399 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4400 {
4401         s32 ret_val;
4402
4403         DEBUGFUNC("e1000_setup_link_ich8lan");
4404
4405         if (hw->phy.ops.check_reset_block(hw))
4406                 return E1000_SUCCESS;
4407
4408         /* ICH parts do not have a word in the NVM to determine
4409          * the default flow control setting, so we explicitly
4410          * set it to full.
4411          */
4412         if (hw->fc.requested_mode == e1000_fc_default)
4413                 hw->fc.requested_mode = e1000_fc_full;
4414
4415         /* Save off the requested flow control mode for use later.  Depending
4416          * on the link partner's capabilities, we may or may not use this mode.
4417          */
4418         hw->fc.current_mode = hw->fc.requested_mode;
4419
4420         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4421                 hw->fc.current_mode);
4422
4423         /* Continue to configure the copper link. */
4424         ret_val = hw->mac.ops.setup_physical_interface(hw);
4425         if (ret_val)
4426                 return ret_val;
4427
4428         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4429         if ((hw->phy.type == e1000_phy_82578) ||
4430             (hw->phy.type == e1000_phy_82579) ||
4431             (hw->phy.type == e1000_phy_i217) ||
4432             (hw->phy.type == e1000_phy_82577)) {
4433                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4434
4435                 ret_val = hw->phy.ops.write_reg(hw,
4436                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
4437                                              hw->fc.pause_time);
4438                 if (ret_val)
4439                         return ret_val;
4440         }
4441
4442         return e1000_set_fc_watermarks_generic(hw);
4443 }
4444
4445 /**
4446  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4447  *  @hw: pointer to the HW structure
4448  *
4449  *  Configures the kumeran interface to the PHY to wait the appropriate time
4450  *  when polling the PHY, then call the generic setup_copper_link to finish
4451  *  configuring the copper link.
4452  **/
4453 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4454 {
4455         u32 ctrl;
4456         s32 ret_val;
4457         u16 reg_data;
4458
4459         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4460
4461         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4462         ctrl |= E1000_CTRL_SLU;
4463         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4464         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4465
4466         /* Set the mac to wait the maximum time between each iteration
4467          * and increase the max iterations when polling the phy;
4468          * this fixes erroneous timeouts at 10Mbps.
4469          */
4470         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4471                                                0xFFFF);
4472         if (ret_val)
4473                 return ret_val;
4474         ret_val = e1000_read_kmrn_reg_generic(hw,
4475                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
4476                                               &reg_data);
4477         if (ret_val)
4478                 return ret_val;
4479         reg_data |= 0x3F;
4480         ret_val = e1000_write_kmrn_reg_generic(hw,
4481                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
4482                                                reg_data);
4483         if (ret_val)
4484                 return ret_val;
4485
4486         switch (hw->phy.type) {
4487         case e1000_phy_igp_3:
4488                 ret_val = e1000_copper_link_setup_igp(hw);
4489                 if (ret_val)
4490                         return ret_val;
4491                 break;
4492         case e1000_phy_bm:
4493         case e1000_phy_82578:
4494                 ret_val = e1000_copper_link_setup_m88(hw);
4495                 if (ret_val)
4496                         return ret_val;
4497                 break;
4498         case e1000_phy_82577:
4499         case e1000_phy_82579:
4500                 ret_val = e1000_copper_link_setup_82577(hw);
4501                 if (ret_val)
4502                         return ret_val;
4503                 break;
4504         case e1000_phy_ife:
4505                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4506                                                &reg_data);
4507                 if (ret_val)
4508                         return ret_val;
4509
4510                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4511
4512                 switch (hw->phy.mdix) {
4513                 case 1:
4514                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4515                         break;
4516                 case 2:
4517                         reg_data |= IFE_PMC_FORCE_MDIX;
4518                         break;
4519                 case 0:
4520                 default:
4521                         reg_data |= IFE_PMC_AUTO_MDIX;
4522                         break;
4523                 }
4524                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4525                                                 reg_data);
4526                 if (ret_val)
4527                         return ret_val;
4528                 break;
4529         default:
4530                 break;
4531         }
4532
4533         return e1000_setup_copper_link_generic(hw);
4534 }
4535
4536 /**
4537  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4538  *  @hw: pointer to the HW structure
4539  *
4540  *  Calls the PHY specific link setup function and then calls the
4541  *  generic setup_copper_link to finish configuring the link for
4542  *  Lynxpoint PCH devices
4543  **/
4544 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4545 {
4546         u32 ctrl;
4547         s32 ret_val;
4548
4549         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4550
4551         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4552         ctrl |= E1000_CTRL_SLU;
4553         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4554         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4555
4556         ret_val = e1000_copper_link_setup_82577(hw);
4557         if (ret_val)
4558                 return ret_val;
4559
4560         return e1000_setup_copper_link_generic(hw);
4561 }
4562
4563 /**
4564  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4565  *  @hw: pointer to the HW structure
4566  *  @speed: pointer to store current link speed
4567  *  @duplex: pointer to store the current link duplex
4568  *
4569  *  Calls the generic get_speed_and_duplex to retrieve the current link
4570  *  information and then calls the Kumeran lock loss workaround for links at
4571  *  gigabit speeds.
4572  **/
4573 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4574                                           u16 *duplex)
4575 {
4576         s32 ret_val;
4577
4578         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4579
4580         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4581         if (ret_val)
4582                 return ret_val;
4583
4584         if ((hw->mac.type == e1000_ich8lan) &&
4585             (hw->phy.type == e1000_phy_igp_3) &&
4586             (*speed == SPEED_1000)) {
4587                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4588         }
4589
4590         return ret_val;
4591 }
4592
4593 /**
4594  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4595  *  @hw: pointer to the HW structure
4596  *
4597  *  Work-around for 82566 Kumeran PCS lock loss:
4598  *  On link status change (i.e. PCI reset, speed change) and link is up and
4599  *  speed is gigabit-
4600  *    0) if workaround is optionally disabled do nothing
4601  *    1) wait 1ms for Kumeran link to come up
4602  *    2) check Kumeran Diagnostic register PCS lock loss bit
4603  *    3) if not set the link is locked (all is good), otherwise...
4604  *    4) reset the PHY
4605  *    5) repeat up to 10 times
4606  *  Note: this is only called for IGP3 copper when speed is 1gb.
4607  **/
4608 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4609 {
4610         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4611         u32 phy_ctrl;
4612         s32 ret_val;
4613         u16 i, data;
4614         bool link;
4615
4616         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4617
4618         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4619                 return E1000_SUCCESS;
4620
4621         /* Make sure link is up before proceeding.  If not just return.
4622          * Attempting this while link is negotiating fouled up link
4623          * stability
4624          */
4625         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4626         if (!link)
4627                 return E1000_SUCCESS;
4628
4629         for (i = 0; i < 10; i++) {
4630                 /* read once to clear */
4631                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4632                 if (ret_val)
4633                         return ret_val;
4634                 /* and again to get new status */
4635                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4636                 if (ret_val)
4637                         return ret_val;
4638
4639                 /* check for PCS lock */
4640                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4641                         return E1000_SUCCESS;
4642
4643                 /* Issue PHY reset */
4644                 hw->phy.ops.reset(hw);
4645                 msec_delay_irq(5);
4646         }
4647         /* Disable GigE link negotiation */
4648         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4649         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4650                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4651         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4652
4653         /* Call gig speed drop workaround on Gig disable before accessing
4654          * any PHY registers
4655          */
4656         e1000_gig_downshift_workaround_ich8lan(hw);
4657
4658         /* unable to acquire PCS lock */
4659         return -E1000_ERR_PHY;
4660 }
4661
4662 /**
4663  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4664  *  @hw: pointer to the HW structure
4665  *  @state: boolean value used to set the current Kumeran workaround state
4666  *
4667  *  If ICH8, set the current Kumeran workaround state (enabled - true
4668  *  /disabled - false).
4669  **/
4670 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4671                                                  bool state)
4672 {
4673         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4674
4675         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4676
4677         if (hw->mac.type != e1000_ich8lan) {
4678                 DEBUGOUT("Workaround applies to ICH8 only.\n");
4679                 return;
4680         }
4681
4682         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4683
4684         return;
4685 }
4686
4687 /**
4688  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4689  *  @hw: pointer to the HW structure
4690  *
4691  *  Workaround for 82566 power-down on D3 entry:
4692  *    1) disable gigabit link
4693  *    2) write VR power-down enable
4694  *    3) read it back
4695  *  Continue if successful, else issue LCD reset and repeat
4696  **/
4697 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4698 {
4699         u32 reg;
4700         u16 data;
4701         u8  retry = 0;
4702
4703         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4704
4705         if (hw->phy.type != e1000_phy_igp_3)
4706                 return;
4707
4708         /* Try the workaround twice (if needed) */
4709         do {
4710                 /* Disable link */
4711                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4712                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4713                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4714                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4715
4716                 /* Call gig speed drop workaround on Gig disable before
4717                  * accessing any PHY registers
4718                  */
4719                 if (hw->mac.type == e1000_ich8lan)
4720                         e1000_gig_downshift_workaround_ich8lan(hw);
4721
4722                 /* Write VR power-down enable */
4723                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4724                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4725                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4726                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4727
4728                 /* Read it back and test */
4729                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4730                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4731                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4732                         break;
4733
4734                 /* Issue PHY reset and repeat at most one more time */
4735                 reg = E1000_READ_REG(hw, E1000_CTRL);
4736                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4737                 retry++;
4738         } while (retry);
4739 }
4740
4741 /**
4742  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4743  *  @hw: pointer to the HW structure
4744  *
4745  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4746  *  LPLU, Gig disable, MDIC PHY reset):
4747  *    1) Set Kumeran Near-end loopback
4748  *    2) Clear Kumeran Near-end loopback
4749  *  Should only be called for ICH8[m] devices with any 1G Phy.
4750  **/
4751 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4752 {
4753         s32 ret_val;
4754         u16 reg_data;
4755
4756         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4757
4758         if ((hw->mac.type != e1000_ich8lan) ||
4759             (hw->phy.type == e1000_phy_ife))
4760                 return;
4761
4762         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4763                                               &reg_data);
4764         if (ret_val)
4765                 return;
4766         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4767         ret_val = e1000_write_kmrn_reg_generic(hw,
4768                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
4769                                                reg_data);
4770         if (ret_val)
4771                 return;
4772         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4773         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4774                                      reg_data);
4775 }
4776
4777 /**
4778  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4779  *  @hw: pointer to the HW structure
4780  *
4781  *  During S0 to Sx transition, it is possible the link remains at gig
4782  *  instead of negotiating to a lower speed.  Before going to Sx, set
4783  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4784  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4785  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4786  *  needs to be written.
4787  *  Parts that support (and are linked to a partner which support) EEE in
4788  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4789  *  than 10Mbps w/o EEE.
4790  **/
4791 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4792 {
4793         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4794         u32 phy_ctrl;
4795         s32 ret_val;
4796
4797         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4798
4799         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4800         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4801
4802         if (hw->phy.type == e1000_phy_i217) {
4803                 u16 phy_reg, device_id = hw->device_id;
4804
4805                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4806                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
4807                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4808
4809                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4810                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4811                 }
4812
4813                 ret_val = hw->phy.ops.acquire(hw);
4814                 if (ret_val)
4815                         goto out;
4816
4817                 if (!dev_spec->eee_disable) {
4818                         u16 eee_advert;
4819
4820                         ret_val =
4821                             e1000_read_emi_reg_locked(hw,
4822                                                       I217_EEE_ADVERTISEMENT,
4823                                                       &eee_advert);
4824                         if (ret_val)
4825                                 goto release;
4826
4827                         /* Disable LPLU if both link partners support 100BaseT
4828                          * EEE and 100Full is advertised on both ends of the
4829                          * link, and enable Auto Enable LPI since there will
4830                          * be no driver to enable LPI while in Sx.
4831                          */
4832                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4833                             (dev_spec->eee_lp_ability &
4834                              I82579_EEE_100_SUPPORTED) &&
4835                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4836                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4837                                               E1000_PHY_CTRL_NOND0A_LPLU);
4838
4839                                 /* Set Auto Enable LPI after link up */
4840                                 hw->phy.ops.read_reg_locked(hw,
4841                                                             I217_LPI_GPIO_CTRL,
4842                                                             &phy_reg);
4843                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4844                                 hw->phy.ops.write_reg_locked(hw,
4845                                                              I217_LPI_GPIO_CTRL,
4846                                                              phy_reg);
4847                         }
4848                 }
4849
4850                 /* For i217 Intel Rapid Start Technology support,
4851                  * when the system is going into Sx and no manageability engine
4852                  * is present, the driver must configure proxy to reset only on
4853                  * power good.  LPI (Low Power Idle) state must also reset only
4854                  * on power good, as well as the MTA (Multicast table array).
4855                  * The SMBus release must also be disabled on LCD reset.
4856                  */
4857                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4858                       E1000_ICH_FWSM_FW_VALID)) {
4859                         /* Enable proxy to reset only on power good. */
4860                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4861                                                     &phy_reg);
4862                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4863                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4864                                                      phy_reg);
4865
4866                         /* Set bit enable LPI (EEE) to reset only on
4867                          * power good.
4868                         */
4869                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4870                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4871                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4872
4873                         /* Disable the SMB release on LCD reset. */
4874                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4875                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4876                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4877                 }
4878
4879                 /* Enable MTA to reset for Intel Rapid Start Technology
4880                  * Support
4881                  */
4882                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4883                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4884                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4885
4886 release:
4887                 hw->phy.ops.release(hw);
4888         }
4889 out:
4890         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4891
4892         if (hw->mac.type == e1000_ich8lan)
4893                 e1000_gig_downshift_workaround_ich8lan(hw);
4894
4895         if (hw->mac.type >= e1000_pchlan) {
4896                 e1000_oem_bits_config_ich8lan(hw, false);
4897
4898                 /* Reset PHY to activate OEM bits on 82577/8 */
4899                 if (hw->mac.type == e1000_pchlan)
4900                         e1000_phy_hw_reset_generic(hw);
4901
4902                 ret_val = hw->phy.ops.acquire(hw);
4903                 if (ret_val)
4904                         return;
4905                 e1000_write_smbus_addr(hw);
4906                 hw->phy.ops.release(hw);
4907         }
4908
4909         return;
4910 }
4911
4912 /**
4913  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4914  *  @hw: pointer to the HW structure
4915  *
4916  *  During Sx to S0 transitions on non-managed devices or managed devices
4917  *  on which PHY resets are not blocked, if the PHY registers cannot be
4918  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4919  *  the PHY.
4920  *  On i217, setup Intel Rapid Start Technology.
4921  **/
4922 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4923 {
4924         s32 ret_val;
4925
4926         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4927
4928         if (hw->mac.type < e1000_pch2lan)
4929                 return;
4930
4931         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4932         if (ret_val) {
4933                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4934                 return;
4935         }
4936
4937         /* For i217 Intel Rapid Start Technology support when the system
4938          * is transitioning from Sx and no manageability engine is present
4939          * configure SMBus to restore on reset, disable proxy, and enable
4940          * the reset on MTA (Multicast table array).
4941          */
4942         if (hw->phy.type == e1000_phy_i217) {
4943                 u16 phy_reg;
4944
4945                 ret_val = hw->phy.ops.acquire(hw);
4946                 if (ret_val) {
4947                         DEBUGOUT("Failed to setup iRST\n");
4948                         return;
4949                 }
4950
4951                 /* Clear Auto Enable LPI after link up */
4952                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
4953                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4954                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
4955
4956                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4957                     E1000_ICH_FWSM_FW_VALID)) {
4958                         /* Restore clear on SMB if no manageability engine
4959                          * is present
4960                          */
4961                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
4962                                                               &phy_reg);
4963                         if (ret_val)
4964                                 goto release;
4965                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4966                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4967
4968                         /* Disable Proxy */
4969                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
4970                 }
4971                 /* Enable reset on MTA */
4972                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
4973                                                       &phy_reg);
4974                 if (ret_val)
4975                         goto release;
4976                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4977                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4978 release:
4979                 if (ret_val)
4980                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
4981                 hw->phy.ops.release(hw);
4982         }
4983 }
4984
4985 /**
4986  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4987  *  @hw: pointer to the HW structure
4988  *
4989  *  Return the LED back to the default configuration.
4990  **/
4991 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4992 {
4993         DEBUGFUNC("e1000_cleanup_led_ich8lan");
4994
4995         if (hw->phy.type == e1000_phy_ife)
4996                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4997                                              0);
4998
4999         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5000         return E1000_SUCCESS;
5001 }
5002
5003 /**
5004  *  e1000_led_on_ich8lan - Turn LEDs on
5005  *  @hw: pointer to the HW structure
5006  *
5007  *  Turn on the LEDs.
5008  **/
5009 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5010 {
5011         DEBUGFUNC("e1000_led_on_ich8lan");
5012
5013         if (hw->phy.type == e1000_phy_ife)
5014                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5015                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5016
5017         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5018         return E1000_SUCCESS;
5019 }
5020
5021 /**
5022  *  e1000_led_off_ich8lan - Turn LEDs off
5023  *  @hw: pointer to the HW structure
5024  *
5025  *  Turn off the LEDs.
5026  **/
5027 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5028 {
5029         DEBUGFUNC("e1000_led_off_ich8lan");
5030
5031         if (hw->phy.type == e1000_phy_ife)
5032                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5033                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5034
5035         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5036         return E1000_SUCCESS;
5037 }
5038
5039 /**
5040  *  e1000_setup_led_pchlan - Configures SW controllable LED
5041  *  @hw: pointer to the HW structure
5042  *
5043  *  This prepares the SW controllable LED for use.
5044  **/
5045 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5046 {
5047         DEBUGFUNC("e1000_setup_led_pchlan");
5048
5049         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5050                                      (u16)hw->mac.ledctl_mode1);
5051 }
5052
5053 /**
5054  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5055  *  @hw: pointer to the HW structure
5056  *
5057  *  Return the LED back to the default configuration.
5058  **/
5059 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5060 {
5061         DEBUGFUNC("e1000_cleanup_led_pchlan");
5062
5063         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5064                                      (u16)hw->mac.ledctl_default);
5065 }
5066
5067 /**
5068  *  e1000_led_on_pchlan - Turn LEDs on
5069  *  @hw: pointer to the HW structure
5070  *
5071  *  Turn on the LEDs.
5072  **/
5073 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5074 {
5075         u16 data = (u16)hw->mac.ledctl_mode2;
5076         u32 i, led;
5077
5078         DEBUGFUNC("e1000_led_on_pchlan");
5079
5080         /* If no link, then turn LED on by setting the invert bit
5081          * for each LED that's mode is "link_up" in ledctl_mode2.
5082          */
5083         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5084                 for (i = 0; i < 3; i++) {
5085                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5086                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5087                             E1000_LEDCTL_MODE_LINK_UP)
5088                                 continue;
5089                         if (led & E1000_PHY_LED0_IVRT)
5090                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5091                         else
5092                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5093                 }
5094         }
5095
5096         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5097 }
5098
5099 /**
5100  *  e1000_led_off_pchlan - Turn LEDs off
5101  *  @hw: pointer to the HW structure
5102  *
5103  *  Turn off the LEDs.
5104  **/
5105 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5106 {
5107         u16 data = (u16)hw->mac.ledctl_mode1;
5108         u32 i, led;
5109
5110         DEBUGFUNC("e1000_led_off_pchlan");
5111
5112         /* If no link, then turn LED off by clearing the invert bit
5113          * for each LED that's mode is "link_up" in ledctl_mode1.
5114          */
5115         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5116                 for (i = 0; i < 3; i++) {
5117                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5118                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5119                             E1000_LEDCTL_MODE_LINK_UP)
5120                                 continue;
5121                         if (led & E1000_PHY_LED0_IVRT)
5122                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5123                         else
5124                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5125                 }
5126         }
5127
5128         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5129 }
5130
5131 /**
5132  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5133  *  @hw: pointer to the HW structure
5134  *
5135  *  Read appropriate register for the config done bit for completion status
5136  *  and configure the PHY through s/w for EEPROM-less parts.
5137  *
5138  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5139  *  config done bit, so only an error is logged and continues.  If we were
5140  *  to return with error, EEPROM-less silicon would not be able to be reset
5141  *  or change link.
5142  **/
5143 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5144 {
5145         s32 ret_val = E1000_SUCCESS;
5146         u32 bank = 0;
5147         u32 status;
5148
5149         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5150
5151         e1000_get_cfg_done_generic(hw);
5152
5153         /* Wait for indication from h/w that it has completed basic config */
5154         if (hw->mac.type >= e1000_ich10lan) {
5155                 e1000_lan_init_done_ich8lan(hw);
5156         } else {
5157                 ret_val = e1000_get_auto_rd_done_generic(hw);
5158                 if (ret_val) {
5159                         /* When auto config read does not complete, do not
5160                          * return with an error. This can happen in situations
5161                          * where there is no eeprom and prevents getting link.
5162                          */
5163                         DEBUGOUT("Auto Read Done did not complete\n");
5164                         ret_val = E1000_SUCCESS;
5165                 }
5166         }
5167
5168         /* Clear PHY Reset Asserted bit */
5169         status = E1000_READ_REG(hw, E1000_STATUS);
5170         if (status & E1000_STATUS_PHYRA)
5171                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5172         else
5173                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5174
5175         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5176         if (hw->mac.type <= e1000_ich9lan) {
5177                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5178                     (hw->phy.type == e1000_phy_igp_3)) {
5179                         e1000_phy_init_script_igp3(hw);
5180                 }
5181         } else {
5182                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5183                         /* Maybe we should do a basic PHY config */
5184                         DEBUGOUT("EEPROM not present\n");
5185                         ret_val = -E1000_ERR_CONFIG;
5186                 }
5187         }
5188
5189         return ret_val;
5190 }
5191
5192 /**
5193  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5194  * @hw: pointer to the HW structure
5195  *
5196  * In the case of a PHY power down to save power, or to turn off link during a
5197  * driver unload, or wake on lan is not enabled, remove the link.
5198  **/
5199 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5200 {
5201         /* If the management interface is not enabled, then power down */
5202         if (!(hw->mac.ops.check_mng_mode(hw) ||
5203               hw->phy.ops.check_reset_block(hw)))
5204                 e1000_power_down_phy_copper(hw);
5205
5206         return;
5207 }
5208
5209 /**
5210  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5211  *  @hw: pointer to the HW structure
5212  *
5213  *  Clears hardware counters specific to the silicon family and calls
5214  *  clear_hw_cntrs_generic to clear all general purpose counters.
5215  **/
5216 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5217 {
5218         u16 phy_data;
5219         s32 ret_val;
5220
5221         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5222
5223         e1000_clear_hw_cntrs_base_generic(hw);
5224
5225         E1000_READ_REG(hw, E1000_ALGNERRC);
5226         E1000_READ_REG(hw, E1000_RXERRC);
5227         E1000_READ_REG(hw, E1000_TNCRS);
5228         E1000_READ_REG(hw, E1000_CEXTERR);
5229         E1000_READ_REG(hw, E1000_TSCTC);
5230         E1000_READ_REG(hw, E1000_TSCTFC);
5231
5232         E1000_READ_REG(hw, E1000_MGTPRC);
5233         E1000_READ_REG(hw, E1000_MGTPDC);
5234         E1000_READ_REG(hw, E1000_MGTPTC);
5235
5236         E1000_READ_REG(hw, E1000_IAC);
5237         E1000_READ_REG(hw, E1000_ICRXOC);
5238
5239         /* Clear PHY statistics registers */
5240         if ((hw->phy.type == e1000_phy_82578) ||
5241             (hw->phy.type == e1000_phy_82579) ||
5242             (hw->phy.type == e1000_phy_i217) ||
5243             (hw->phy.type == e1000_phy_82577)) {
5244                 ret_val = hw->phy.ops.acquire(hw);
5245                 if (ret_val)
5246                         return;
5247                 ret_val = hw->phy.ops.set_page(hw,
5248                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5249                 if (ret_val)
5250                         goto release;
5251                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5252                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5253                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5254                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5255                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5256                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5257                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5258                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5259                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5260                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5261                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5262                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5263                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5264                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5265 release:
5266                 hw->phy.ops.release(hw);
5267         }
5268 }
5269