lib/librte_pmd_e1000/e1000/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  */
  62
  63 #include "e1000_api.h"
  64
  65 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  66 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  67 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  68 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  69 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  70 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  71 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  72 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  73 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  74 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  75 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  76                                             bool active);
  77 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  78                                             bool active);
  79 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  80                                    u16 words, u16 *data);
  81 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  82                                     u16 words, u16 *data);
  83 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  84 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  85 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  86                                             u16 *data);
  87 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
  88 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  90 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  91 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  92 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  93 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  94                                            u16 *speed, u16 *duplex);
  95 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
  96 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
  97 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
  98 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
  99 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 100 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 101 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 102 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 103 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 104 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 105 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 106 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 107 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 108                                           u32 offset, u8 *data);
 109 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 110                                           u8 size, u16 *data);
 111 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 112                                           u32 offset, u16 *data);
 113 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 114                                                  u32 offset, u8 byte);
 115 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 116 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 118 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 119 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 120 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 121
 122 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 123 /* Offset 04h HSFSTS */
 124 union ich8_hws_flash_status {
 125         struct ich8_hsfsts {
 126                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 127                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 128                 u16 dael:1; /* bit 2 Direct Access error Log */
 129                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 130                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 131                 u16 reserved1:2; /* bit 13:6 Reserved */
 132                 u16 reserved2:6; /* bit 13:6 Reserved */
 133                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 134                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 135         } hsf_status;
 136         u16 regval;
 137 };
 138
 139 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 140 /* Offset 06h FLCTL */
 141 union ich8_hws_flash_ctrl {
 142         struct ich8_hsflctl {
 143                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 144                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 145                 u16 reserved:5;   /* 7:3 Reserved  */
 146                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 147                 u16 flockdn:6;   /* 15:10 Reserved */
 148         } hsf_ctrl;
 149         u16 regval;
 150 };
 151
 152 /* ICH Flash Region Access Permissions */
 153 union ich8_hws_flash_regacc {
 154         struct ich8_flracc {
 155                 u32 grra:8; /* 0:7 GbE region Read Access */
 156                 u32 grwa:8; /* 8:15 GbE region Write Access */
 157                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 158                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 159         } hsf_flregacc;
 160         u16 regval;
 161 };
 162
 163 /**
 164  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 165  *  @hw: pointer to the HW structure
 166  *
 167  *  Test access to the PHY registers by reading the PHY ID registers.  If
 168  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 169  *  otherwise assume the read PHY ID is correct if it is valid.
 170  *
 171  *  Assumes the sw/fw/hw semaphore is already acquired.
 172  **/
 173 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 174 {
 175         u16 phy_reg = 0;
 176         u32 phy_id = 0;
 177         s32 ret_val;
 178         u16 retry_count;
 179
 180         for (retry_count = 0; retry_count < 2; retry_count++) {
 181                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 182                 if (ret_val || (phy_reg == 0xFFFF))
 183                         continue;
 184                 phy_id = (u32)(phy_reg << 16);
 185
 186                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 187                 if (ret_val || (phy_reg == 0xFFFF)) {
 188                         phy_id = 0;
 189                         continue;
 190                 }
 191                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 192                 break;
 193         }
 194
 195         if (hw->phy.id) {
 196                 if  (hw->phy.id == phy_id)
 197                         return true;
 198         } else if (phy_id) {
 199                 hw->phy.id = phy_id;
 200                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 201                 return true;
 202         }
 203
 204         /*
 205          * In case the PHY needs to be in mdio slow mode,
 206          * set slow mode and try to get the PHY id again.
 207          */
 208         hw->phy.ops.release(hw);
 209         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 210         if (!ret_val)
 211                 ret_val = e1000_get_phy_id(hw);
 212         hw->phy.ops.acquire(hw);
 213
 214         return !ret_val;
 215 }
 216
 217 /**
 218  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 219  *  @hw: pointer to the HW structure
 220  *
 221  *  Workarounds/flow necessary for PHY initialization during driver load
 222  *  and resume paths.
 223  **/
 224 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 225 {
 226         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 227         s32 ret_val;
 228
 229         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 230
 231         ret_val = hw->phy.ops.acquire(hw);
 232         if (ret_val) {
 233                 DEBUGOUT("Failed to initialize PHY flow\n");
 234                 return ret_val;
 235         }
 236
 237         /*
 238          * The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 239          * inaccessible and resetting the PHY is not blocked, toggle the
 240          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 241          */
 242         switch (hw->mac.type) {
 243         case e1000_pch2lan:
 244                 /*
 245                  * Gate automatic PHY configuration by hardware on
 246                  * non-managed 82579
 247                  */
 248                 if ((hw->mac.type == e1000_pch2lan) &&
 249                     !(fwsm & E1000_ICH_FWSM_FW_VALID))
 250                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 251
 252                 if (e1000_phy_is_accessible_pchlan(hw)) {
 253                         break;
 254                 }
 255
 256                 /* fall-through */
 257         case e1000_pchlan:
 258                 if ((hw->mac.type == e1000_pchlan) &&
 259                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 260                         break;
 261
 262                 if (hw->phy.ops.check_reset_block(hw)) {
 263                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 264                         break;
 265                 }
 266
 267                 DEBUGOUT("Toggling LANPHYPC\n");
 268
 269                 /* Set Phy Config Counter to 50msec */
 270                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 271                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 272                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 273                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 274
 275                 /* Toggle LANPHYPC Value bit */
 276                 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 277                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 278                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 279                 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 280                 E1000_WRITE_FLUSH(hw);
 281                 usec_delay(10);
 282                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 283                 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 284                 E1000_WRITE_FLUSH(hw);
 285                 msec_delay(50);
 286                 break;
 287         default:
 288                 break;
 289         }
 290
 291         hw->phy.ops.release(hw);
 292
 293         /*
 294          * Reset the PHY before any access to it.  Doing so, ensures
 295          * that the PHY is in a known good state before we read/write
 296          * PHY registers.  The generic reset is sufficient here,
 297          * because we haven't determined the PHY type yet.
 298          */
 299         ret_val = e1000_phy_hw_reset_generic(hw);
 300
 301         /* Ungate automatic PHY configuration on non-managed 82579 */
 302         if ((hw->mac.type == e1000_pch2lan) &&
 303             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 304                 msec_delay(10);
 305                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 306         }
 307
 308         return ret_val;
 309 }
 310
 311 /**
 312  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 313  *  @hw: pointer to the HW structure
 314  *
 315  *  Initialize family-specific PHY parameters and function pointers.
 316  **/
 317 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 318 {
 319         struct e1000_phy_info *phy = &hw->phy;
 320         s32 ret_val;
 321
 322         DEBUGFUNC("e1000_init_phy_params_pchlan");
 323
 324         phy->addr               = 1;
 325         phy->reset_delay_us     = 100;
 326
 327         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 328         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 329         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 330         phy->ops.set_page       = e1000_set_page_igp;
 331         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 332         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 333         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 334         phy->ops.release        = e1000_release_swflag_ich8lan;
 335         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 336         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 337         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 338         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 339         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 340         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 341         phy->ops.power_up       = e1000_power_up_phy_copper;
 342         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 343         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 344
 345         phy->id = e1000_phy_unknown;
 346
 347         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 348         if (ret_val)
 349                 return ret_val;
 350
 351         if (phy->id == e1000_phy_unknown)
 352                 switch (hw->mac.type) {
 353                 default:
 354                         ret_val = e1000_get_phy_id(hw);
 355                         if (ret_val)
 356                                 return ret_val;
 357                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 358                                 break;
 359                         /* fall-through */
 360                 case e1000_pch2lan:
 361                 case e1000_pch_lpt:
 362                         /* In case the PHY needs to be in mdio slow mode,
 363                          * set slow mode and try to get the PHY id again.
 364                          */
 365                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 366                         if (ret_val)
 367                                 return ret_val;
 368                         ret_val = e1000_get_phy_id(hw);
 369                         if (ret_val)
 370                                 return ret_val;
 371                         break;
 372                 }
 373         phy->type = e1000_get_phy_type_from_id(phy->id);
 374
 375         switch (phy->type) {
 376         case e1000_phy_82577:
 377         case e1000_phy_82579:
 378         case e1000_phy_i217:
 379                 phy->ops.check_polarity = e1000_check_polarity_82577;
 380                 phy->ops.force_speed_duplex =
 381                         e1000_phy_force_speed_duplex_82577;
 382                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 383                 phy->ops.get_info = e1000_get_phy_info_82577;
 384                 phy->ops.commit = e1000_phy_sw_reset_generic;
 385                 break;
 386         case e1000_phy_82578:
 387                 phy->ops.check_polarity = e1000_check_polarity_m88;
 388                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 389                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 390                 phy->ops.get_info = e1000_get_phy_info_m88;
 391                 break;
 392         default:
 393                 ret_val = -E1000_ERR_PHY;
 394                 break;
 395         }
 396
 397         return ret_val;
 398 }
 399
 400 /**
 401  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 402  *  @hw: pointer to the HW structure
 403  *
 404  *  Initialize family-specific PHY parameters and function pointers.
 405  **/
 406 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 407 {
 408         struct e1000_phy_info *phy = &hw->phy;
 409         s32 ret_val;
 410         u16 i = 0;
 411
 412         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 413
 414         phy->addr               = 1;
 415         phy->reset_delay_us     = 100;
 416
 417         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 418         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 419         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 420         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 421         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 422         phy->ops.release        = e1000_release_swflag_ich8lan;
 423         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 424         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 425         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 426         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 427         phy->ops.power_up       = e1000_power_up_phy_copper;
 428         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 429
 430         /* We may need to do this twice - once for IGP and if that fails,
 431          * we'll set BM func pointers and try again
 432          */
 433         ret_val = e1000_determine_phy_address(hw);
 434         if (ret_val) {
 435                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 436                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 437                 ret_val = e1000_determine_phy_address(hw);
 438                 if (ret_val) {
 439                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 440                         return ret_val;
 441                 }
 442         }
 443
 444         phy->id = 0;
 445         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 446                (i++ < 100)) {
 447                 msec_delay(1);
 448                 ret_val = e1000_get_phy_id(hw);
 449                 if (ret_val)
 450                         return ret_val;
 451         }
 452
 453         /* Verify phy id */
 454         switch (phy->id) {
 455         case IGP03E1000_E_PHY_ID:
 456                 phy->type = e1000_phy_igp_3;
 457                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 459                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 460                 phy->ops.get_info = e1000_get_phy_info_igp;
 461                 phy->ops.check_polarity = e1000_check_polarity_igp;
 462                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 463                 break;
 464         case IFE_E_PHY_ID:
 465         case IFE_PLUS_E_PHY_ID:
 466         case IFE_C_E_PHY_ID:
 467                 phy->type = e1000_phy_ife;
 468                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 469                 phy->ops.get_info = e1000_get_phy_info_ife;
 470                 phy->ops.check_polarity = e1000_check_polarity_ife;
 471                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 472                 break;
 473         case BME1000_E_PHY_ID:
 474                 phy->type = e1000_phy_bm;
 475                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 476                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 477                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 478                 phy->ops.commit = e1000_phy_sw_reset_generic;
 479                 phy->ops.get_info = e1000_get_phy_info_m88;
 480                 phy->ops.check_polarity = e1000_check_polarity_m88;
 481                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 482                 break;
 483         default:
 484                 return -E1000_ERR_PHY;
 485                 break;
 486         }
 487
 488         return E1000_SUCCESS;
 489 }
 490
 491 /**
 492  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Initialize family-specific NVM parameters and function
 496  *  pointers.
 497  **/
 498 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 499 {
 500         struct e1000_nvm_info *nvm = &hw->nvm;
 501         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 502         u32 gfpreg, sector_base_addr, sector_end_addr;
 503         u16 i;
 504
 505         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 506
 507         /* Can't read flash registers if the register set isn't mapped. */
 508         if (!hw->flash_address) {
 509                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 510                 return -E1000_ERR_CONFIG;
 511         }
 512
 513         nvm->type = e1000_nvm_flash_sw;
 514
 515         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 516
 517         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 518          * Add 1 to sector_end_addr since this sector is included in
 519          * the overall size.
 520          */
 521         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 522         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 523
 524         /* flash_base_addr is byte-aligned */
 525         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 526
 527         /* find total size of the NVM, then cut in half since the total
 528          * size represents two separate NVM banks.
 529          */
 530         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 531                                 << FLASH_SECTOR_ADDR_SHIFT);
 532         nvm->flash_bank_size /= 2;
 533         /* Adjust to word count */
 534         nvm->flash_bank_size /= sizeof(u16);
 535
 536         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 537
 538         /* Clear shadow ram */
 539         for (i = 0; i < nvm->word_size; i++) {
 540                 dev_spec->shadow_ram[i].modified = false;
 541                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 542         }
 543
 544         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 545         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 546
 547         /* Function Pointers */
 548         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 549         nvm->ops.release        = e1000_release_nvm_ich8lan;
 550         nvm->ops.read           = e1000_read_nvm_ich8lan;
 551         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 552         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 553         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 554         nvm->ops.write          = e1000_write_nvm_ich8lan;
 555
 556         return E1000_SUCCESS;
 557 }
 558
 559 /**
 560  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 561  *  @hw: pointer to the HW structure
 562  *
 563  *  Initialize family-specific MAC parameters and function
 564  *  pointers.
 565  **/
 566 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 567 {
 568         struct e1000_mac_info *mac = &hw->mac;
 569
 570         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 571
 572         /* Set media type function pointer */
 573         hw->phy.media_type = e1000_media_type_copper;
 574
 575         /* Set mta register count */
 576         mac->mta_reg_count = 32;
 577         /* Set rar entry count */
 578         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 579         if (mac->type == e1000_ich8lan)
 580                 mac->rar_entry_count--;
 581         /* Set if part includes ASF firmware */
 582         mac->asf_firmware_present = true;
 583         /* FWSM register */
 584         mac->has_fwsm = true;
 585         /* ARC subsystem not supported */
 586         mac->arc_subsystem_valid = false;
 587         /* Adaptive IFS supported */
 588         mac->adaptive_ifs = true;
 589
 590         /* Function pointers */
 591
 592         /* bus type/speed/width */
 593         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 594         /* function id */
 595         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 596         /* reset */
 597         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 598         /* hw initialization */
 599         mac->ops.init_hw = e1000_init_hw_ich8lan;
 600         /* link setup */
 601         mac->ops.setup_link = e1000_setup_link_ich8lan;
 602         /* physical interface setup */
 603         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 604         /* check for link */
 605         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 606         /* link info */
 607         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 608         /* multicast address update */
 609         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 610         /* clear hardware counters */
 611         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 612
 613         /* LED and other operations */
 614         switch (mac->type) {
 615         case e1000_ich8lan:
 616         case e1000_ich9lan:
 617         case e1000_ich10lan:
 618                 /* check management mode */
 619                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 620                 /* ID LED init */
 621                 mac->ops.id_led_init = e1000_id_led_init_generic;
 622                 /* blink LED */
 623                 mac->ops.blink_led = e1000_blink_led_generic;
 624                 /* setup LED */
 625                 mac->ops.setup_led = e1000_setup_led_generic;
 626                 /* cleanup LED */
 627                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 628                 /* turn on/off LED */
 629                 mac->ops.led_on = e1000_led_on_ich8lan;
 630                 mac->ops.led_off = e1000_led_off_ich8lan;
 631                 break;
 632         case e1000_pch2lan:
 633                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 634                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 635                 /* fall-through */
 636         case e1000_pchlan:
 637                 /* check management mode */
 638                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 639                 /* ID LED init */
 640                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 641                 /* setup LED */
 642                 mac->ops.setup_led = e1000_setup_led_pchlan;
 643                 /* cleanup LED */
 644                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 645                 /* turn on/off LED */
 646                 mac->ops.led_on = e1000_led_on_pchlan;
 647                 mac->ops.led_off = e1000_led_off_pchlan;
 648                 break;
 649         default:
 650                 break;
 651         }
 652
 653         /* Enable PCS Lock-loss workaround for ICH8 */
 654         if (mac->type == e1000_ich8lan)
 655                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 656
 657         /* Gate automatic PHY configuration by hardware on managed 82579 */
 658         if ((mac->type == e1000_pch2lan) &&
 659             (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
 660                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 661
 662         return E1000_SUCCESS;
 663 }
 664
 665 /**
 666  *  __e1000_access_emi_reg_locked - Read/write EMI register
 667  *  @hw: pointer to the HW structure
 668  *  @addr: EMI address to program
 669  *  @data: pointer to value to read/write from/to the EMI address
 670  *  @read: boolean flag to indicate read or write
 671  *
 672  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 673  **/
 674 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 675                                          u16 *data, bool read)
 676 {
 677         s32 ret_val;
 678
 679         DEBUGFUNC("__e1000_access_emi_reg_locked");
 680
 681         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 682         if (ret_val)
 683                 return ret_val;
 684
 685         if (read)
 686                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 687                                                       data);
 688         else
 689                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 690                                                        *data);
 691
 692         return ret_val;
 693 }
 694
 695 /**
 696  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 697  *  @hw: pointer to the HW structure
 698  *  @addr: EMI address to program
 699  *  @data: value to be read from the EMI address
 700  *
 701  *  Assumes the SW/FW/HW Semaphore is already acquired.
 702  **/
 703 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 704 {
 705         DEBUGFUNC("e1000_read_emi_reg_locked");
 706
 707         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 708 }
 709
 710 /**
 711  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 712  *  @hw: pointer to the HW structure
 713  *  @addr: EMI address to program
 714  *  @data: value to be written to the EMI address
 715  *
 716  *  Assumes the SW/FW/HW Semaphore is already acquired.
 717  **/
 718 STATIC s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 719 {
 720         DEBUGFUNC("e1000_read_emi_reg_locked");
 721
 722         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 723 }
 724
 725 /**
 726  *  e1000_set_eee_pchlan - Enable/disable EEE support
 727  *  @hw: pointer to the HW structure
 728  *
 729  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 730  *  the link and the EEE capabilities of the link partner.  The LPI Control
 731  *  register bits will remain set only if/when link is up.
 732  **/
 733 STATIC s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 734 {
 735         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 736         s32 ret_val;
 737         u16 lpi_ctrl;
 738
 739         DEBUGFUNC("e1000_set_eee_pchlan");
 740
 741         if ((hw->phy.type != e1000_phy_82579) &&
 742             (hw->phy.type != e1000_phy_i217))
 743                 return E1000_SUCCESS;
 744
 745         ret_val = hw->phy.ops.acquire(hw);
 746         if (ret_val)
 747                 return ret_val;
 748
 749         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 750         if (ret_val)
 751                 goto release;
 752
 753         /* Clear bits that enable EEE in various speeds */
 754         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 755
 756         /* Enable EEE if not disabled by user */
 757         if (!dev_spec->eee_disable) {
 758                 u16 lpa, pcs_status, data;
 759
 760                 /* Save off link partner's EEE ability */
 761                 switch (hw->phy.type) {
 762                 case e1000_phy_82579:
 763                         lpa = I82579_EEE_LP_ABILITY;
 764                         pcs_status = I82579_EEE_PCS_STATUS;
 765                         break;
 766                 case e1000_phy_i217:
 767                         lpa = I217_EEE_LP_ABILITY;
 768                         pcs_status = I217_EEE_PCS_STATUS;
 769                         break;
 770                 default:
 771                         ret_val = -E1000_ERR_PHY;
 772                         goto release;
 773                 }
 774                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 775                                                     &dev_spec->eee_lp_ability);
 776                 if (ret_val)
 777                         goto release;
 778
 779                 /*
 780                  * Enable EEE only for speeds in which the link partner is
 781                  * EEE capable.
 782                  */
 783                 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 784                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 785
 786                 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 787                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 788                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 789                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 790                         else
 791                                 /*
 792                                  * EEE is not supported in 100Half, so ignore
 793                                  * partner's EEE in 100 ability if full-duplex
 794                                  * is not advertised.
 795                                  */
 796                                 dev_spec->eee_lp_ability &=
 797                                     ~I82579_EEE_100_SUPPORTED;
 798                 }
 799
 800                 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 801                 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 802                 if (ret_val)
 803                         goto release;
 804         }
 805
 806         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 807 release:
 808         hw->phy.ops.release(hw);
 809
 810         return ret_val;
 811 }
 812
 813 /**
 814  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 815  *  @hw: pointer to the HW structure
 816  *
 817  *  Checks to see of the link status of the hardware has changed.  If a
 818  *  change in link status has been detected, then we read the PHY registers
 819  *  to get the current speed/duplex if link exists.
 820  **/
 821 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 822 {
 823         struct e1000_mac_info *mac = &hw->mac;
 824         s32 ret_val;
 825         bool link;
 826         u16 phy_reg;
 827
 828         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
 829
 830         /* We only want to go out to the PHY registers to see if Auto-Neg
 831          * has completed and/or if our link status has changed.  The
 832          * get_link_status flag is set upon receiving a Link Status
 833          * Change or Rx Sequence Error interrupt.
 834          */
 835         if (!mac->get_link_status)
 836                 return E1000_SUCCESS;
 837
 838         /*
 839          * First we want to see if the MII Status Register reports
 840          * link.  If so, then we want to get the current speed/duplex
 841          * of the PHY.
 842          */
 843         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 844         if (ret_val)
 845                 return ret_val;
 846
 847         if (hw->mac.type == e1000_pchlan) {
 848                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 849                 if (ret_val)
 850                         return ret_val;
 851         }
 852
 853         /* Clear link partner's EEE ability */
 854         hw->dev_spec.ich8lan.eee_lp_ability = 0;
 855
 856         if (!link)
 857                 return E1000_SUCCESS; /* No link detected */
 858
 859         mac->get_link_status = false;
 860
 861         switch (hw->mac.type) {
 862         case e1000_pch2lan:
 863                 ret_val = e1000_k1_workaround_lv(hw);
 864                 if (ret_val)
 865                         return ret_val;
 866                 /* fall-thru */
 867         case e1000_pchlan:
 868                 if (hw->phy.type == e1000_phy_82578) {
 869                         ret_val = e1000_link_stall_workaround_hv(hw);
 870                         if (ret_val)
 871                                 return ret_val;
 872                 }
 873
 874                 /* Workaround for PCHx parts in half-duplex:
 875                  * Set the number of preambles removed from the packet
 876                  * when it is passed from the PHY to the MAC to prevent
 877                  * the MAC from misinterpreting the packet type.
 878                  */
 879                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 880                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 881
 882                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
 883                     E1000_STATUS_FD)
 884                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 885
 886                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 887                 break;
 888         default:
 889                 break;
 890         }
 891
 892         /* Check if there was DownShift, must be checked
 893          * immediately after link-up
 894          */
 895         e1000_check_downshift_generic(hw);
 896
 897         /* Enable/Disable EEE after link up */
 898         ret_val = e1000_set_eee_pchlan(hw);
 899         if (ret_val)
 900                 return ret_val;
 901
 902         /* If we are forcing speed/duplex, then we simply return since
 903          * we have already determined whether we have link or not.
 904          */
 905         if (!mac->autoneg)
 906                 return -E1000_ERR_CONFIG;
 907
 908         /* Auto-Neg is enabled.  Auto Speed Detection takes care
 909          * of MAC speed/duplex configuration.  So we only need to
 910          * configure Collision Distance in the MAC.
 911          */
 912         mac->ops.config_collision_dist(hw);
 913
 914         /* Configure Flow Control now that Auto-Neg has completed.
 915          * First, we need to restore the desired flow control
 916          * settings because we may have had to re-autoneg with a
 917          * different link partner.
 918          */
 919         ret_val = e1000_config_fc_after_link_up_generic(hw);
 920         if (ret_val)
 921                 DEBUGOUT("Error configuring flow control\n");
 922
 923         return ret_val;
 924 }
 925
 926 /**
 927  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
 928  *  @hw: pointer to the HW structure
 929  *
 930  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
 931  **/
 932 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
 933 {
 934         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
 935
 936         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
 937         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
 938         switch (hw->mac.type) {
 939         case e1000_ich8lan:
 940         case e1000_ich9lan:
 941         case e1000_ich10lan:
 942                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
 943                 break;
 944         case e1000_pchlan:
 945         case e1000_pch2lan:
 946                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
 947                 break;
 948         default:
 949                 break;
 950         }
 951 }
 952
 953 /**
 954  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 955  *  @hw: pointer to the HW structure
 956  *
 957  *  Acquires the mutex for performing NVM operations.
 958  **/
 959 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 960 {
 961         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
 962
 963         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
 964
 965         return E1000_SUCCESS;
 966 }
 967
 968 /**
 969  *  e1000_release_nvm_ich8lan - Release NVM mutex
 970  *  @hw: pointer to the HW structure
 971  *
 972  *  Releases the mutex used while performing NVM operations.
 973  **/
 974 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 975 {
 976         DEBUGFUNC("e1000_release_nvm_ich8lan");
 977
 978         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
 979
 980         return;
 981 }
 982
 983 /**
 984  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 985  *  @hw: pointer to the HW structure
 986  *
 987  *  Acquires the software control flag for performing PHY and select
 988  *  MAC CSR accesses.
 989  **/
 990 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 991 {
 992         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 993         s32 ret_val = E1000_SUCCESS;
 994
 995         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
 996
 997         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
 998
 999         while (timeout) {
1000                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1001                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1002                         break;
1003
1004                 msec_delay_irq(1);
1005                 timeout--;
1006         }
1007
1008         if (!timeout) {
1009                 DEBUGOUT("SW has already locked the resource.\n");
1010                 ret_val = -E1000_ERR_CONFIG;
1011                 goto out;
1012         }
1013
1014         timeout = SW_FLAG_TIMEOUT;
1015
1016         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1017         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1018
1019         while (timeout) {
1020                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1021                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1022                         break;
1023
1024                 msec_delay_irq(1);
1025                 timeout--;
1026         }
1027
1028         if (!timeout) {
1029                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1030                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1031                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1032                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1033                 ret_val = -E1000_ERR_CONFIG;
1034                 goto out;
1035         }
1036
1037 out:
1038         if (ret_val)
1039                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1040
1041         return ret_val;
1042 }
1043
1044 /**
1045  *  e1000_release_swflag_ich8lan - Release software control flag
1046  *  @hw: pointer to the HW structure
1047  *
1048  *  Releases the software control flag for performing PHY and select
1049  *  MAC CSR accesses.
1050  **/
1051 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1052 {
1053         u32 extcnf_ctrl;
1054
1055         DEBUGFUNC("e1000_release_swflag_ich8lan");
1056
1057         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1058
1059         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1060                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1061                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1062         } else {
1063                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1064         }
1065
1066         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1067
1068         return;
1069 }
1070
1071 /**
1072  *  e1000_check_mng_mode_ich8lan - Checks management mode
1073  *  @hw: pointer to the HW structure
1074  *
1075  *  This checks if the adapter has any manageability enabled.
1076  *  This is a function pointer entry point only called by read/write
1077  *  routines for the PHY and NVM parts.
1078  **/
1079 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1080 {
1081         u32 fwsm;
1082
1083         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1084
1085         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1086
1087         return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1088                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1089                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1090 }
1091
1092 /**
1093  *  e1000_check_mng_mode_pchlan - Checks management mode
1094  *  @hw: pointer to the HW structure
1095  *
1096  *  This checks if the adapter has iAMT enabled.
1097  *  This is a function pointer entry point only called by read/write
1098  *  routines for the PHY and NVM parts.
1099  **/
1100 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1101 {
1102         u32 fwsm;
1103
1104         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1105
1106         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1107
1108         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1109                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1110 }
1111
1112 /**
1113  *  e1000_rar_set_pch2lan - Set receive address register
1114  *  @hw: pointer to the HW structure
1115  *  @addr: pointer to the receive address
1116  *  @index: receive address array register
1117  *
1118  *  Sets the receive address array register at index to the address passed
1119  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1120  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1121  *  Use SHRA[0-3] in place of those reserved for ME.
1122  **/
1123 STATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1124 {
1125         u32 rar_low, rar_high;
1126
1127         DEBUGFUNC("e1000_rar_set_pch2lan");
1128
1129         /* HW expects these in little endian so we reverse the byte order
1130          * from network order (big endian) to little endian
1131          */
1132         rar_low = ((u32) addr[0] |
1133                    ((u32) addr[1] << 8) |
1134                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1135
1136         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1137
1138         /* If MAC address zero, no need to set the AV bit */
1139         if (rar_low || rar_high)
1140                 rar_high |= E1000_RAH_AV;
1141
1142         if (index == 0) {
1143                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1144                 E1000_WRITE_FLUSH(hw);
1145                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1146                 E1000_WRITE_FLUSH(hw);
1147                 return;
1148         }
1149
1150         if (index < hw->mac.rar_entry_count) {
1151                 s32 ret_val;
1152
1153                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1154                 if (ret_val)
1155                         goto out;
1156
1157                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1158                 E1000_WRITE_FLUSH(hw);
1159                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1160                 E1000_WRITE_FLUSH(hw);
1161
1162                 e1000_release_swflag_ich8lan(hw);
1163
1164                 /* verify the register updates */
1165                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1166                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1167                         return;
1168
1169                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1170                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1171         }
1172
1173 out:
1174         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1175 }
1176
1177 /**
1178  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1179  *  @hw: pointer to the HW structure
1180  *
1181  *  Checks if firmware is blocking the reset of the PHY.
1182  *  This is a function pointer entry point only called by
1183  *  reset routines.
1184  **/
1185 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1186 {
1187         u32 fwsm;
1188
1189         DEBUGFUNC("e1000_check_reset_block_ich8lan");
1190
1191         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1192
1193         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
1194                                                 : E1000_BLK_PHY_RESET;
1195 }
1196
1197 /**
1198  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1199  *  @hw: pointer to the HW structure
1200  *
1201  *  Assumes semaphore already acquired.
1202  *
1203  **/
1204 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1205 {
1206         u16 phy_data;
1207         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
1208         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1209                 E1000_STRAP_SMT_FREQ_SHIFT;
1210         s32 ret_val;
1211
1212         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1213
1214         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1215         if (ret_val)
1216                 return ret_val;
1217
1218         phy_data &= ~HV_SMB_ADDR_MASK;
1219         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1220         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1221
1222         if (hw->phy.type == e1000_phy_i217) {
1223                 /* Restore SMBus frequency */
1224                 if (freq--) {
1225                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1226                         phy_data |= (freq & (1 << 0)) <<
1227                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1228                         phy_data |= (freq & (1 << 1)) <<
1229                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1230                 } else {
1231                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
1232                 }
1233         }
1234
1235         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1236 }
1237
1238 /**
1239  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1240  *  @hw:   pointer to the HW structure
1241  *
1242  *  SW should configure the LCD from the NVM extended configuration region
1243  *  as a workaround for certain parts.
1244  **/
1245 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1246 {
1247         struct e1000_phy_info *phy = &hw->phy;
1248         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1249         s32 ret_val = E1000_SUCCESS;
1250         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1251
1252         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
1253
1254         /* Initialize the PHY from the NVM on ICH platforms.  This
1255          * is needed due to an issue where the NVM configuration is
1256          * not properly autoloaded after power transitions.
1257          * Therefore, after each PHY reset, we will load the
1258          * configuration data out of the NVM manually.
1259          */
1260         switch (hw->mac.type) {
1261         case e1000_ich8lan:
1262                 if (phy->type != e1000_phy_igp_3)
1263                         return ret_val;
1264
1265                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
1266                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
1267                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1268                         break;
1269                 }
1270                 /* Fall-thru */
1271         case e1000_pchlan:
1272         case e1000_pch2lan:
1273                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1274                 break;
1275         default:
1276                 return ret_val;
1277         }
1278
1279         ret_val = hw->phy.ops.acquire(hw);
1280         if (ret_val)
1281                 return ret_val;
1282
1283         data = E1000_READ_REG(hw, E1000_FEXTNVM);
1284         if (!(data & sw_cfg_mask))
1285                 goto release;
1286
1287         /* Make sure HW does not configure LCD from PHY
1288          * extended configuration before SW configuration
1289          */
1290         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1291         if ((hw->mac.type < e1000_pch2lan) &&
1292             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1293                         goto release;
1294
1295         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
1296         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1297         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1298         if (!cnf_size)
1299                 goto release;
1300
1301         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1302         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1303
1304         if (((hw->mac.type == e1000_pchlan) &&
1305              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1306             (hw->mac.type > e1000_pchlan)) {
1307                 /* HW configures the SMBus address and LEDs when the
1308                  * OEM and LCD Write Enable bits are set in the NVM.
1309                  * When both NVM bits are cleared, SW will configure
1310                  * them instead.
1311                  */
1312                 ret_val = e1000_write_smbus_addr(hw);
1313                 if (ret_val)
1314                         goto release;
1315
1316                 data = E1000_READ_REG(hw, E1000_LEDCTL);
1317                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1318                                                         (u16)data);
1319                 if (ret_val)
1320                         goto release;
1321         }
1322
1323         /* Configure LCD from extended configuration region. */
1324
1325         /* cnf_base_addr is in DWORD */
1326         word_addr = (u16)(cnf_base_addr << 1);
1327
1328         for (i = 0; i < cnf_size; i++) {
1329                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
1330                                            &reg_data);
1331                 if (ret_val)
1332                         goto release;
1333
1334                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
1335                                            1, &reg_addr);
1336                 if (ret_val)
1337                         goto release;
1338
1339                 /* Save off the PHY page for future writes. */
1340                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1341                         phy_page = reg_data;
1342                         continue;
1343                 }
1344
1345                 reg_addr &= PHY_REG_MASK;
1346                 reg_addr |= phy_page;
1347
1348                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1349                                                     reg_data);
1350                 if (ret_val)
1351                         goto release;
1352         }
1353
1354 release:
1355         hw->phy.ops.release(hw);
1356         return ret_val;
1357 }
1358
1359 /**
1360  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1361  *  @hw:   pointer to the HW structure
1362  *  @link: link up bool flag
1363  *
1364  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1365  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1366  *  If link is down, the function will restore the default K1 setting located
1367  *  in the NVM.
1368  **/
1369 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1370 {
1371         s32 ret_val = E1000_SUCCESS;
1372         u16 status_reg = 0;
1373         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1374
1375         DEBUGFUNC("e1000_k1_gig_workaround_hv");
1376
1377         if (hw->mac.type != e1000_pchlan)
1378                 return E1000_SUCCESS;
1379
1380         /* Wrap the whole flow with the sw flag */
1381         ret_val = hw->phy.ops.acquire(hw);
1382         if (ret_val)
1383                 return ret_val;
1384
1385         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1386         if (link) {
1387                 if (hw->phy.type == e1000_phy_82578) {
1388                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1389                                                               &status_reg);
1390                         if (ret_val)
1391                                 goto release;
1392
1393                         status_reg &= (BM_CS_STATUS_LINK_UP |
1394                                        BM_CS_STATUS_RESOLVED |
1395                                        BM_CS_STATUS_SPEED_MASK);
1396
1397                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1398                                            BM_CS_STATUS_RESOLVED |
1399                                            BM_CS_STATUS_SPEED_1000))
1400                                 k1_enable = false;
1401                 }
1402
1403                 if (hw->phy.type == e1000_phy_82577) {
1404                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1405                                                               &status_reg);
1406                         if (ret_val)
1407                                 goto release;
1408
1409                         status_reg &= (HV_M_STATUS_LINK_UP |
1410                                        HV_M_STATUS_AUTONEG_COMPLETE |
1411                                        HV_M_STATUS_SPEED_MASK);
1412
1413                         if (status_reg == (HV_M_STATUS_LINK_UP |
1414                                            HV_M_STATUS_AUTONEG_COMPLETE |
1415                                            HV_M_STATUS_SPEED_1000))
1416                                 k1_enable = false;
1417                 }
1418
1419                 /* Link stall fix for link up */
1420                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1421                                                        0x0100);
1422                 if (ret_val)
1423                         goto release;
1424
1425         } else {
1426                 /* Link stall fix for link down */
1427                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1428                                                        0x4100);
1429                 if (ret_val)
1430                         goto release;
1431         }
1432
1433         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1434
1435 release:
1436         hw->phy.ops.release(hw);
1437
1438         return ret_val;
1439 }
1440
1441 /**
1442  *  e1000_configure_k1_ich8lan - Configure K1 power state
1443  *  @hw: pointer to the HW structure
1444  *  @enable: K1 state to configure
1445  *
1446  *  Configure the K1 power state based on the provided parameter.
1447  *  Assumes semaphore already acquired.
1448  *
1449  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1450  **/
1451 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1452 {
1453         s32 ret_val;
1454         u32 ctrl_reg = 0;
1455         u32 ctrl_ext = 0;
1456         u32 reg = 0;
1457         u16 kmrn_reg = 0;
1458
1459         DEBUGFUNC("e1000_configure_k1_ich8lan");
1460
1461         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1462                                              &kmrn_reg);
1463         if (ret_val)
1464                 return ret_val;
1465
1466         if (k1_enable)
1467                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1468         else
1469                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1470
1471         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1472                                               kmrn_reg);
1473         if (ret_val)
1474                 return ret_val;
1475
1476         usec_delay(20);
1477         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1478         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1479
1480         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1481         reg |= E1000_CTRL_FRCSPD;
1482         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1483
1484         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1485         E1000_WRITE_FLUSH(hw);
1486         usec_delay(20);
1487         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1488         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1489         E1000_WRITE_FLUSH(hw);
1490         usec_delay(20);
1491
1492         return E1000_SUCCESS;
1493 }
1494
1495 /**
1496  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1497  *  @hw:       pointer to the HW structure
1498  *  @d0_state: boolean if entering d0 or d3 device state
1499  *
1500  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1501  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1502  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1503  **/
1504 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1505 {
1506         s32 ret_val = 0;
1507         u32 mac_reg;
1508         u16 oem_reg;
1509
1510         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
1511
1512         if (hw->mac.type < e1000_pchlan)
1513                 return ret_val;
1514
1515         ret_val = hw->phy.ops.acquire(hw);
1516         if (ret_val)
1517                 return ret_val;
1518
1519         if (hw->mac.type == e1000_pchlan) {
1520                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1521                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1522                         goto release;
1523         }
1524
1525         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
1526         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1527                 goto release;
1528
1529         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
1530
1531         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1532         if (ret_val)
1533                 goto release;
1534
1535         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1536
1537         if (d0_state) {
1538                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1539                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1540
1541                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1542                         oem_reg |= HV_OEM_BITS_LPLU;
1543         } else {
1544                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1545                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1546                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1547
1548                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1549                     E1000_PHY_CTRL_NOND0A_LPLU))
1550                         oem_reg |= HV_OEM_BITS_LPLU;
1551         }
1552
1553         /* Set Restart auto-neg to activate the bits */
1554         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1555             !hw->phy.ops.check_reset_block(hw))
1556                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1557
1558         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1559
1560 release:
1561         hw->phy.ops.release(hw);
1562
1563         return ret_val;
1564 }
1565
1566
1567 /**
1568  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1569  *  @hw:   pointer to the HW structure
1570  **/
1571 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1572 {
1573         s32 ret_val;
1574         u16 data;
1575
1576         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
1577
1578         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
1579         if (ret_val)
1580                 return ret_val;
1581
1582         data |= HV_KMRN_MDIO_SLOW;
1583
1584         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
1585
1586         return ret_val;
1587 }
1588
1589 /**
1590  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1591  *  done after every PHY reset.
1592  **/
1593 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1594 {
1595         s32 ret_val = E1000_SUCCESS;
1596         u16 phy_data;
1597
1598         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
1599
1600         if (hw->mac.type != e1000_pchlan)
1601                 return E1000_SUCCESS;
1602
1603         /* Set MDIO slow mode before any other MDIO access */
1604         if (hw->phy.type == e1000_phy_82577) {
1605                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1606                 if (ret_val)
1607                         return ret_val;
1608         }
1609
1610         if (((hw->phy.type == e1000_phy_82577) &&
1611              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1612             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1613                 /* Disable generation of early preamble */
1614                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1615                 if (ret_val)
1616                         return ret_val;
1617
1618                 /* Preamble tuning for SSC */
1619                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
1620                                                 0xA204);
1621                 if (ret_val)
1622                         return ret_val;
1623         }
1624
1625         if (hw->phy.type == e1000_phy_82578) {
1626                 /* Return registers to default by doing a soft reset then
1627                  * writing 0x3140 to the control register.
1628                  */
1629                 if (hw->phy.revision < 2) {
1630                         e1000_phy_sw_reset_generic(hw);
1631                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
1632                                                         0x3140);
1633                 }
1634         }
1635
1636         /* Select page 0 */
1637         ret_val = hw->phy.ops.acquire(hw);
1638         if (ret_val)
1639                 return ret_val;
1640
1641         hw->phy.addr = 1;
1642         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1643         hw->phy.ops.release(hw);
1644         if (ret_val)
1645                 return ret_val;
1646
1647         /* Configure the K1 Si workaround during phy reset assuming there is
1648          * link so that it disables K1 if link is in 1Gbps.
1649          */
1650         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1651         if (ret_val)
1652                 return ret_val;
1653
1654         /* Workaround for link disconnects on a busy hub in half duplex */
1655         ret_val = hw->phy.ops.acquire(hw);
1656         if (ret_val)
1657                 return ret_val;
1658         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1659         if (ret_val)
1660                 goto release;
1661         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1662                                                phy_data & 0x00FF);
1663         if (ret_val)
1664                 goto release;
1665
1666         /* set MSE higher to enable link to stay up when noise is high */
1667         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1668 release:
1669         hw->phy.ops.release(hw);
1670
1671         return ret_val;
1672 }
1673
1674 /**
1675  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1676  *  @hw:   pointer to the HW structure
1677  **/
1678 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1679 {
1680         u32 mac_reg;
1681         u16 i, phy_reg = 0;
1682         s32 ret_val;
1683
1684         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
1685
1686         ret_val = hw->phy.ops.acquire(hw);
1687         if (ret_val)
1688                 return;
1689         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1690         if (ret_val)
1691                 goto release;
1692
1693         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1694         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1695                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
1696                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1697                                            (u16)(mac_reg & 0xFFFF));
1698                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1699                                            (u16)((mac_reg >> 16) & 0xFFFF));
1700
1701                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
1702                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1703                                            (u16)(mac_reg & 0xFFFF));
1704                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1705                                            (u16)((mac_reg & E1000_RAH_AV)
1706                                                  >> 16));
1707         }
1708
1709         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1710
1711 release:
1712         hw->phy.ops.release(hw);
1713 }
1714
1715 static u32 e1000_calc_rx_da_crc(u8 mac[])
1716 {
1717         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
1718         u32 i, j, mask, crc;
1719
1720         DEBUGFUNC("e1000_calc_rx_da_crc");
1721
1722         crc = 0xffffffff;
1723         for (i = 0; i < 6; i++) {
1724                 crc = crc ^ mac[i];
1725                 for (j = 8; j > 0; j--) {
1726                         mask = (crc & 1) * (-1);
1727                         crc = (crc >> 1) ^ (poly & mask);
1728                 }
1729         }
1730         return ~crc;
1731 }
1732
1733 /**
1734  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1735  *  with 82579 PHY
1736  *  @hw: pointer to the HW structure
1737  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1738  **/
1739 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1740 {
1741         s32 ret_val = E1000_SUCCESS;
1742         u16 phy_reg, data;
1743         u32 mac_reg;
1744         u16 i;
1745
1746         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
1747
1748         if (hw->mac.type != e1000_pch2lan)
1749                 return E1000_SUCCESS;
1750
1751         /* disable Rx path while enabling/disabling workaround */
1752         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
1753         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
1754                                         phy_reg | (1 << 14));
1755         if (ret_val)
1756                 return ret_val;
1757
1758         if (enable) {
1759                 /* Write Rx addresses (rar_entry_count for RAL/H, and
1760                  * SHRAL/H) and initial CRC values to the MAC
1761                  */
1762                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1763                         u8 mac_addr[ETH_ADDR_LEN] = {0};
1764                         u32 addr_high, addr_low;
1765
1766                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
1767                         if (!(addr_high & E1000_RAH_AV))
1768                                 continue;
1769                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
1770                         mac_addr[0] = (addr_low & 0xFF);
1771                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1772                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1773                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1774                         mac_addr[4] = (addr_high & 0xFF);
1775                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1776
1777                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
1778                                         e1000_calc_rx_da_crc(mac_addr));
1779                 }
1780
1781                 /* Write Rx addresses to the PHY */
1782                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1783
1784                 /* Enable jumbo frame workaround in the MAC */
1785                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
1786                 mac_reg &= ~(1 << 14);
1787                 mac_reg |= (7 << 15);
1788                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
1789
1790                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
1791                 mac_reg |= E1000_RCTL_SECRC;
1792                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
1793
1794                 ret_val = e1000_read_kmrn_reg_generic(hw,
1795                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1796                                                 &data);
1797                 if (ret_val)
1798                         return ret_val;
1799                 ret_val = e1000_write_kmrn_reg_generic(hw,
1800                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1801                                                 data | (1 << 0));
1802                 if (ret_val)
1803                         return ret_val;
1804                 ret_val = e1000_read_kmrn_reg_generic(hw,
1805                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1806                                                 &data);
1807                 if (ret_val)
1808                         return ret_val;
1809                 data &= ~(0xF << 8);
1810                 data |= (0xB << 8);
1811                 ret_val = e1000_write_kmrn_reg_generic(hw,
1812                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1813                                                 data);
1814                 if (ret_val)
1815                         return ret_val;
1816
1817                 /* Enable jumbo frame workaround in the PHY */
1818                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
1819                 data &= ~(0x7F << 5);
1820                 data |= (0x37 << 5);
1821                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
1822                 if (ret_val)
1823                         return ret_val;
1824                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
1825                 data &= ~(1 << 13);
1826                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
1827                 if (ret_val)
1828                         return ret_val;
1829                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
1830                 data &= ~(0x3FF << 2);
1831                 data |= (0x1A << 2);
1832                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1833                 if (ret_val)
1834                         return ret_val;
1835                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
1836                 if (ret_val)
1837                         return ret_val;
1838                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1839                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
1840                                                 (1 << 10));
1841                 if (ret_val)
1842                         return ret_val;
1843         } else {
1844                 /* Write MAC register values back to h/w defaults */
1845                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
1846                 mac_reg &= ~(0xF << 14);
1847                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
1848
1849                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
1850                 mac_reg &= ~E1000_RCTL_SECRC;
1851                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
1852
1853                 ret_val = e1000_read_kmrn_reg_generic(hw,
1854                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1855                                                 &data);
1856                 if (ret_val)
1857                         return ret_val;
1858                 ret_val = e1000_write_kmrn_reg_generic(hw,
1859                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1860                                                 data & ~(1 << 0));
1861                 if (ret_val)
1862                         return ret_val;
1863                 ret_val = e1000_read_kmrn_reg_generic(hw,
1864                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1865                                                 &data);
1866                 if (ret_val)
1867                         return ret_val;
1868                 data &= ~(0xF << 8);
1869                 data |= (0xB << 8);
1870                 ret_val = e1000_write_kmrn_reg_generic(hw,
1871                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1872                                                 data);
1873                 if (ret_val)
1874                         return ret_val;
1875
1876                 /* Write PHY register values back to h/w defaults */
1877                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
1878                 data &= ~(0x7F << 5);
1879                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
1880                 if (ret_val)
1881                         return ret_val;
1882                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
1883                 data |= (1 << 13);
1884                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
1885                 if (ret_val)
1886                         return ret_val;
1887                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
1888                 data &= ~(0x3FF << 2);
1889                 data |= (0x8 << 2);
1890                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
1891                 if (ret_val)
1892                         return ret_val;
1893                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
1894                 if (ret_val)
1895                         return ret_val;
1896                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
1897                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
1898                                                 ~(1 << 10));
1899                 if (ret_val)
1900                         return ret_val;
1901         }
1902
1903         /* re-enable Rx path after enabling/disabling workaround */
1904         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
1905                                      ~(1 << 14));
1906 }
1907
1908 /**
1909  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1910  *  done after every PHY reset.
1911  **/
1912 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1913 {
1914         s32 ret_val = E1000_SUCCESS;
1915
1916         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
1917
1918         if (hw->mac.type != e1000_pch2lan)
1919                 return E1000_SUCCESS;
1920
1921         /* Set MDIO slow mode before any other MDIO access */
1922         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1923         if (ret_val)
1924                 return ret_val;
1925
1926         ret_val = hw->phy.ops.acquire(hw);
1927         if (ret_val)
1928                 return ret_val;
1929         /* set MSE higher to enable link to stay up when noise is high */
1930         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
1931         if (ret_val)
1932                 goto release;
1933         /* drop link after 5 times MSE threshold was reached */
1934         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
1935 release:
1936         hw->phy.ops.release(hw);
1937
1938         return ret_val;
1939 }
1940
1941 /**
1942  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1943  *  @hw:   pointer to the HW structure
1944  *
1945  *  Workaround to set the K1 beacon duration for 82579 parts
1946  **/
1947 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1948 {
1949         s32 ret_val = E1000_SUCCESS;
1950         u16 status_reg = 0;
1951         u32 mac_reg;
1952         u16 phy_reg;
1953
1954         DEBUGFUNC("e1000_k1_workaround_lv");
1955
1956         if (hw->mac.type != e1000_pch2lan)
1957                 return E1000_SUCCESS;
1958
1959         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1960         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
1961         if (ret_val)
1962                 return ret_val;
1963
1964         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1965             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1966                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1967                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1968
1969                 ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
1970                 if (ret_val)
1971                         return ret_val;
1972
1973                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1974                         u16 pm_phy_reg;
1975
1976                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1977                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1978                         /* LV 1G Packet drop issue wa  */
1979                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
1980                                                        &pm_phy_reg);
1981                         if (ret_val)
1982                                 return ret_val;
1983                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
1984                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
1985                                                         pm_phy_reg);
1986                         if (ret_val)
1987                                 return ret_val;
1988                 } else {
1989                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1990                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1991                 }
1992                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1993                 ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
1994         }
1995
1996         return ret_val;
1997 }
1998
1999 /**
2000  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2001  *  @hw:   pointer to the HW structure
2002  *  @gate: boolean set to true to gate, false to ungate
2003  *
2004  *  Gate/ungate the automatic PHY configuration via hardware; perform
2005  *  the configuration via software instead.
2006  **/
2007 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2008 {
2009         u32 extcnf_ctrl;
2010
2011         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2012
2013         if (hw->mac.type != e1000_pch2lan)
2014                 return;
2015
2016         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2017
2018         if (gate)
2019                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2020         else
2021                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2022
2023         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2024 }
2025
2026 /**
2027  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2028  *  @hw: pointer to the HW structure
2029  *
2030  *  Check the appropriate indication the MAC has finished configuring the
2031  *  PHY after a software reset.
2032  **/
2033 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2034 {
2035         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2036
2037         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2038
2039         /* Wait for basic configuration completes before proceeding */
2040         do {
2041                 data = E1000_READ_REG(hw, E1000_STATUS);
2042                 data &= E1000_STATUS_LAN_INIT_DONE;
2043                 usec_delay(100);
2044         } while ((!data) && --loop);
2045
2046         /* If basic configuration is incomplete before the above loop
2047          * count reaches 0, loading the configuration from NVM will
2048          * leave the PHY in a bad state possibly resulting in no link.
2049          */
2050         if (loop == 0)
2051                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2052
2053         /* Clear the Init Done bit for the next init event */
2054         data = E1000_READ_REG(hw, E1000_STATUS);
2055         data &= ~E1000_STATUS_LAN_INIT_DONE;
2056         E1000_WRITE_REG(hw, E1000_STATUS, data);
2057 }
2058
2059 /**
2060  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2061  *  @hw: pointer to the HW structure
2062  **/
2063 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2064 {
2065         s32 ret_val = E1000_SUCCESS;
2066         u16 reg;
2067
2068         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2069
2070         if (hw->phy.ops.check_reset_block(hw))
2071                 return E1000_SUCCESS;
2072
2073         /* Allow time for h/w to get to quiescent state after reset */
2074         msec_delay(10);
2075
2076         /* Perform any necessary post-reset workarounds */
2077         switch (hw->mac.type) {
2078         case e1000_pchlan:
2079                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2080                 if (ret_val)
2081                         return ret_val;
2082                 break;
2083         case e1000_pch2lan:
2084                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2085                 if (ret_val)
2086                         return ret_val;
2087                 break;
2088         default:
2089                 break;
2090         }
2091
2092         /* Clear the host wakeup bit after lcd reset */
2093         if (hw->mac.type >= e1000_pchlan) {
2094                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2095                 reg &= ~BM_WUC_HOST_WU_BIT;
2096                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2097         }
2098
2099         /* Configure the LCD with the extended configuration region in NVM */
2100         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2101         if (ret_val)
2102                 return ret_val;
2103
2104         /* Configure the LCD with the OEM bits in NVM */
2105         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2106
2107         if (hw->mac.type == e1000_pch2lan) {
2108                 /* Ungate automatic PHY configuration on non-managed 82579 */
2109                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2110                     E1000_ICH_FWSM_FW_VALID)) {
2111                         msec_delay(10);
2112                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2113                 }
2114
2115                 /* Set EEE LPI Update Timer to 200usec */
2116                 ret_val = hw->phy.ops.acquire(hw);
2117                 if (ret_val)
2118                         return ret_val;
2119                 ret_val = e1000_write_emi_reg_locked(hw,
2120                                                      I82579_LPI_UPDATE_TIMER,
2121                                                      0x1387);
2122                 hw->phy.ops.release(hw);
2123         }
2124
2125         return ret_val;
2126 }
2127
2128 /**
2129  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2130  *  @hw: pointer to the HW structure
2131  *
2132  *  Resets the PHY
2133  *  This is a function pointer entry point called by drivers
2134  *  or other shared routines.
2135  **/
2136 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2137 {
2138         s32 ret_val = E1000_SUCCESS;
2139
2140         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2141
2142         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2143         if ((hw->mac.type == e1000_pch2lan) &&
2144             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2145                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2146
2147         ret_val = e1000_phy_hw_reset_generic(hw);
2148         if (ret_val)
2149                 return ret_val;
2150
2151         return e1000_post_phy_reset_ich8lan(hw);
2152 }
2153
2154 /**
2155  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2156  *  @hw: pointer to the HW structure
2157  *  @active: true to enable LPLU, false to disable
2158  *
2159  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2160  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2161  *  the phy speed. This function will manually set the LPLU bit and restart
2162  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2163  *  since it configures the same bit.
2164  **/
2165 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2166 {
2167         s32 ret_val;
2168         u16 oem_reg;
2169
2170         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2171
2172         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2173         if (ret_val)
2174                 return ret_val;
2175
2176         if (active)
2177                 oem_reg |= HV_OEM_BITS_LPLU;
2178         else
2179                 oem_reg &= ~HV_OEM_BITS_LPLU;
2180
2181         if (!hw->phy.ops.check_reset_block(hw))
2182                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2183
2184         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2185 }
2186
2187 /**
2188  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2189  *  @hw: pointer to the HW structure
2190  *  @active: true to enable LPLU, false to disable
2191  *
2192  *  Sets the LPLU D0 state according to the active flag.  When
2193  *  activating LPLU this function also disables smart speed
2194  *  and vice versa.  LPLU will not be activated unless the
2195  *  device autonegotiation advertisement meets standards of
2196  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2197  *  This is a function pointer entry point only called by
2198  *  PHY setup routines.
2199  **/
2200 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2201 {
2202         struct e1000_phy_info *phy = &hw->phy;
2203         u32 phy_ctrl;
2204         s32 ret_val = E1000_SUCCESS;
2205         u16 data;
2206
2207         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
2208
2209         if (phy->type == e1000_phy_ife)
2210                 return E1000_SUCCESS;
2211
2212         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2213
2214         if (active) {
2215                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2216                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2217
2218                 if (phy->type != e1000_phy_igp_3)
2219                         return E1000_SUCCESS;
2220
2221                 /* Call gig speed drop workaround on LPLU before accessing
2222                  * any PHY registers
2223                  */
2224                 if (hw->mac.type == e1000_ich8lan)
2225                         e1000_gig_downshift_workaround_ich8lan(hw);
2226
2227                 /* When LPLU is enabled, we should disable SmartSpeed */
2228                 ret_val = phy->ops.read_reg(hw,
2229                                             IGP01E1000_PHY_PORT_CONFIG,
2230                                             &data);
2231                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2232                 ret_val = phy->ops.write_reg(hw,
2233                                              IGP01E1000_PHY_PORT_CONFIG,
2234                                              data);
2235                 if (ret_val)
2236                         return ret_val;
2237         } else {
2238                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2239                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2240
2241                 if (phy->type != e1000_phy_igp_3)
2242                         return E1000_SUCCESS;
2243
2244                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2245                  * during Dx states where the power conservation is most
2246                  * important.  During driver activity we should enable
2247                  * SmartSpeed, so performance is maintained.
2248                  */
2249                 if (phy->smart_speed == e1000_smart_speed_on) {
2250                         ret_val = phy->ops.read_reg(hw,
2251                                                     IGP01E1000_PHY_PORT_CONFIG,
2252                                                     &data);
2253                         if (ret_val)
2254                                 return ret_val;
2255
2256                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2257                         ret_val = phy->ops.write_reg(hw,
2258                                                      IGP01E1000_PHY_PORT_CONFIG,
2259                                                      data);
2260                         if (ret_val)
2261                                 return ret_val;
2262                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2263                         ret_val = phy->ops.read_reg(hw,
2264                                                     IGP01E1000_PHY_PORT_CONFIG,
2265                                                     &data);
2266                         if (ret_val)
2267                                 return ret_val;
2268
2269                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2270                         ret_val = phy->ops.write_reg(hw,
2271                                                      IGP01E1000_PHY_PORT_CONFIG,
2272                                                      data);
2273                         if (ret_val)
2274                                 return ret_val;
2275                 }
2276         }
2277
2278         return E1000_SUCCESS;
2279 }
2280
2281 /**
2282  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2283  *  @hw: pointer to the HW structure
2284  *  @active: true to enable LPLU, false to disable
2285  *
2286  *  Sets the LPLU D3 state according to the active flag.  When
2287  *  activating LPLU this function also disables smart speed
2288  *  and vice versa.  LPLU will not be activated unless the
2289  *  device autonegotiation advertisement meets standards of
2290  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2291  *  This is a function pointer entry point only called by
2292  *  PHY setup routines.
2293  **/
2294 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2295 {
2296         struct e1000_phy_info *phy = &hw->phy;
2297         u32 phy_ctrl;
2298         s32 ret_val = E1000_SUCCESS;
2299         u16 data;
2300
2301         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
2302
2303         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2304
2305         if (!active) {
2306                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2307                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2308
2309                 if (phy->type != e1000_phy_igp_3)
2310                         return E1000_SUCCESS;
2311
2312                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2313                  * during Dx states where the power conservation is most
2314                  * important.  During driver activity we should enable
2315                  * SmartSpeed, so performance is maintained.
2316                  */
2317                 if (phy->smart_speed == e1000_smart_speed_on) {
2318                         ret_val = phy->ops.read_reg(hw,
2319                                                     IGP01E1000_PHY_PORT_CONFIG,
2320                                                     &data);
2321                         if (ret_val)
2322                                 return ret_val;
2323
2324                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2325                         ret_val = phy->ops.write_reg(hw,
2326                                                      IGP01E1000_PHY_PORT_CONFIG,
2327                                                      data);
2328                         if (ret_val)
2329                                 return ret_val;
2330                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2331                         ret_val = phy->ops.read_reg(hw,
2332                                                     IGP01E1000_PHY_PORT_CONFIG,
2333                                                     &data);
2334                         if (ret_val)
2335                                 return ret_val;
2336
2337                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2338                         ret_val = phy->ops.write_reg(hw,
2339                                                      IGP01E1000_PHY_PORT_CONFIG,
2340                                                      data);
2341                         if (ret_val)
2342                                 return ret_val;
2343                 }
2344         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2345                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2346                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2347                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2348                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2349
2350                 if (phy->type != e1000_phy_igp_3)
2351                         return E1000_SUCCESS;
2352
2353                 /* Call gig speed drop workaround on LPLU before accessing
2354                  * any PHY registers
2355                  */
2356                 if (hw->mac.type == e1000_ich8lan)
2357                         e1000_gig_downshift_workaround_ich8lan(hw);
2358
2359                 /* When LPLU is enabled, we should disable SmartSpeed */
2360                 ret_val = phy->ops.read_reg(hw,
2361                                             IGP01E1000_PHY_PORT_CONFIG,
2362                                             &data);
2363                 if (ret_val)
2364                         return ret_val;
2365
2366                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2367                 ret_val = phy->ops.write_reg(hw,
2368                                              IGP01E1000_PHY_PORT_CONFIG,
2369                                              data);
2370         }
2371
2372         return ret_val;
2373 }
2374
2375 /**
2376  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2377  *  @hw: pointer to the HW structure
2378  *  @bank:  pointer to the variable that returns the active bank
2379  *
2380  *  Reads signature byte from the NVM using the flash access registers.
2381  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2382  **/
2383 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2384 {
2385         u32 eecd;
2386         struct e1000_nvm_info *nvm = &hw->nvm;
2387         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2388         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2389         u8 sig_byte = 0;
2390         s32 ret_val;
2391
2392         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
2393
2394         switch (hw->mac.type) {
2395         case e1000_ich8lan:
2396         case e1000_ich9lan:
2397                 eecd = E1000_READ_REG(hw, E1000_EECD);
2398                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2399                     E1000_EECD_SEC1VAL_VALID_MASK) {
2400                         if (eecd & E1000_EECD_SEC1VAL)
2401                                 *bank = 1;
2402                         else
2403                                 *bank = 0;
2404
2405                         return E1000_SUCCESS;
2406                 }
2407                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2408                 /* fall-thru */
2409         default:
2410                 /* set bank to 0 in case flash read fails */
2411                 *bank = 0;
2412
2413                 /* Check bank 0 */
2414                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2415                                                         &sig_byte);
2416                 if (ret_val)
2417                         return ret_val;
2418                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2419                     E1000_ICH_NVM_SIG_VALUE) {
2420                         *bank = 0;
2421                         return E1000_SUCCESS;
2422                 }
2423
2424                 /* Check bank 1 */
2425                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2426                                                         bank1_offset,
2427                                                         &sig_byte);
2428                 if (ret_val)
2429                         return ret_val;
2430                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2431                     E1000_ICH_NVM_SIG_VALUE) {
2432                         *bank = 1;
2433                         return E1000_SUCCESS;
2434                 }
2435
2436                 DEBUGOUT("ERROR: No valid NVM bank present\n");
2437                 return -E1000_ERR_NVM;
2438         }
2439 }
2440
2441 /**
2442  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2443  *  @hw: pointer to the HW structure
2444  *  @offset: The offset (in bytes) of the word(s) to read.
2445  *  @words: Size of data to read in words
2446  *  @data: Pointer to the word(s) to read at offset.
2447  *
2448  *  Reads a word(s) from the NVM using the flash access registers.
2449  **/
2450 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2451                                   u16 *data)
2452 {
2453         struct e1000_nvm_info *nvm = &hw->nvm;
2454         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2455         u32 act_offset;
2456         s32 ret_val = E1000_SUCCESS;
2457         u32 bank = 0;
2458         u16 i, word;
2459
2460         DEBUGFUNC("e1000_read_nvm_ich8lan");
2461
2462         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2463             (words == 0)) {
2464                 DEBUGOUT("nvm parameter(s) out of bounds\n");
2465                 ret_val = -E1000_ERR_NVM;
2466                 goto out;
2467         }
2468
2469         nvm->ops.acquire(hw);
2470
2471         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2472         if (ret_val != E1000_SUCCESS) {
2473                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
2474                 bank = 0;
2475         }
2476
2477         act_offset = (bank) ? nvm->flash_bank_size : 0;
2478         act_offset += offset;
2479
2480         ret_val = E1000_SUCCESS;
2481         for (i = 0; i < words; i++) {
2482                 if (dev_spec->shadow_ram[offset+i].modified) {
2483                         data[i] = dev_spec->shadow_ram[offset+i].value;
2484                 } else {
2485                         ret_val = e1000_read_flash_word_ich8lan(hw,
2486                                                                 act_offset + i,
2487                                                                 &word);
2488                         if (ret_val)
2489                                 break;
2490                         data[i] = word;
2491                 }
2492         }
2493
2494         nvm->ops.release(hw);
2495
2496 out:
2497         if (ret_val)
2498                 DEBUGOUT1("NVM read error: %d\n", ret_val);
2499
2500         return ret_val;
2501 }
2502
2503 /**
2504  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2505  *  @hw: pointer to the HW structure
2506  *
2507  *  This function does initial flash setup so that a new read/write/erase cycle
2508  *  can be started.
2509  **/
2510 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2511 {
2512         union ich8_hws_flash_status hsfsts;
2513         s32 ret_val = -E1000_ERR_NVM;
2514
2515         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
2516
2517         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2518
2519         /* Check if the flash descriptor is valid */
2520         if (!hsfsts.hsf_status.fldesvalid) {
2521                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
2522                 return -E1000_ERR_NVM;
2523         }
2524
2525         /* Clear FCERR and DAEL in hw status by writing 1 */
2526         hsfsts.hsf_status.flcerr = 1;
2527         hsfsts.hsf_status.dael = 1;
2528
2529         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
2530
2531         /* Either we should have a hardware SPI cycle in progress
2532          * bit to check against, in order to start a new cycle or
2533          * FDONE bit should be changed in the hardware so that it
2534          * is 1 after hardware reset, which can then be used as an
2535          * indication whether a cycle is in progress or has been
2536          * completed.
2537          */
2538
2539         if (!hsfsts.hsf_status.flcinprog) {
2540                 /* There is no cycle running at present,
2541                  * so we can start a cycle.
2542                  * Begin by setting Flash Cycle Done.
2543                  */
2544                 hsfsts.hsf_status.flcdone = 1;
2545                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
2546                 ret_val = E1000_SUCCESS;
2547         } else {
2548                 s32 i;
2549
2550                 /* Otherwise poll for sometime so the current
2551                  * cycle has a chance to end before giving up.
2552                  */
2553                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2554                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2555                                                               ICH_FLASH_HSFSTS);
2556                         if (!hsfsts.hsf_status.flcinprog) {
2557                                 ret_val = E1000_SUCCESS;
2558                                 break;
2559                         }
2560                         usec_delay(1);
2561                 }
2562                 if (ret_val == E1000_SUCCESS) {
2563                         /* Successful in waiting for previous cycle to timeout,
2564                          * now set the Flash Cycle Done.
2565                          */
2566                         hsfsts.hsf_status.flcdone = 1;
2567                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
2568                                                 hsfsts.regval);
2569                 } else {
2570                         DEBUGOUT("Flash controller busy, cannot get access\n");
2571                 }
2572         }
2573
2574         return ret_val;
2575 }
2576
2577 /**
2578  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2579  *  @hw: pointer to the HW structure
2580  *  @timeout: maximum time to wait for completion
2581  *
2582  *  This function starts a flash cycle and waits for its completion.
2583  **/
2584 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2585 {
2586         union ich8_hws_flash_ctrl hsflctl;
2587         union ich8_hws_flash_status hsfsts;
2588         u32 i = 0;
2589
2590         DEBUGFUNC("e1000_flash_cycle_ich8lan");
2591
2592         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2593         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
2594         hsflctl.hsf_ctrl.flcgo = 1;
2595         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
2596
2597         /* wait till FDONE bit is set to 1 */
2598         do {
2599                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2600                 if (hsfsts.hsf_status.flcdone)
2601                         break;
2602                 usec_delay(1);
2603         } while (i++ < timeout);
2604
2605         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2606                 return E1000_SUCCESS;
2607
2608         return -E1000_ERR_NVM;
2609 }
2610
2611 /**
2612  *  e1000_read_flash_word_ich8lan - Read word from flash
2613  *  @hw: pointer to the HW structure
2614  *  @offset: offset to data location
2615  *  @data: pointer to the location for storing the data
2616  *
2617  *  Reads the flash word at offset into data.  Offset is converted
2618  *  to bytes before read.
2619  **/
2620 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2621                                          u16 *data)
2622 {
2623         DEBUGFUNC("e1000_read_flash_word_ich8lan");
2624
2625         if (!data)
2626                 return -E1000_ERR_NVM;
2627
2628         /* Must convert offset into bytes. */
2629         offset <<= 1;
2630
2631         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2632 }
2633
2634 /**
2635  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2636  *  @hw: pointer to the HW structure
2637  *  @offset: The offset of the byte to read.
2638  *  @data: Pointer to a byte to store the value read.
2639  *
2640  *  Reads a single byte from the NVM using the flash access registers.
2641  **/
2642 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2643                                          u8 *data)
2644 {
2645         s32 ret_val;
2646         u16 word = 0;
2647
2648         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2649         if (ret_val)
2650                 return ret_val;
2651
2652         *data = (u8)word;
2653
2654         return E1000_SUCCESS;
2655 }
2656
2657 /**
2658  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2659  *  @hw: pointer to the HW structure
2660  *  @offset: The offset (in bytes) of the byte or word to read.
2661  *  @size: Size of data to read, 1=byte 2=word
2662  *  @data: Pointer to the word to store the value read.
2663  *
2664  *  Reads a byte or word from the NVM using the flash access registers.
2665  **/
2666 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2667                                          u8 size, u16 *data)
2668 {
2669         union ich8_hws_flash_status hsfsts;
2670         union ich8_hws_flash_ctrl hsflctl;
2671         u32 flash_linear_addr;
2672         u32 flash_data = 0;
2673         s32 ret_val = -E1000_ERR_NVM;
2674         u8 count = 0;
2675
2676         DEBUGFUNC("e1000_read_flash_data_ich8lan");
2677
2678         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2679                 return -E1000_ERR_NVM;
2680
2681         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2682                              hw->nvm.flash_base_addr);
2683
2684         do {
2685                 usec_delay(1);
2686                 /* Steps */
2687                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2688                 if (ret_val != E1000_SUCCESS)
2689                         break;
2690
2691                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
2692                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2693                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2694                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2695                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
2696
2697                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
2698
2699                 ret_val =
2700                     e1000_flash_cycle_ich8lan(hw,
2701                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
2702
2703                 /* Check if FCERR is set to 1, if set to 1, clear it
2704                  * and try the whole sequence a few more times, else
2705                  * read in (shift in) the Flash Data0, the order is
2706                  * least significant byte first msb to lsb
2707                  */
2708                 if (ret_val == E1000_SUCCESS) {
2709                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
2710                         if (size == 1)
2711                                 *data = (u8)(flash_data & 0x000000FF);
2712                         else if (size == 2)
2713                                 *data = (u16)(flash_data & 0x0000FFFF);
2714                         break;
2715                 } else {
2716                         /* If we've gotten here, then things are probably
2717                          * completely hosed, but if the error condition is
2718                          * detected, it won't hurt to give it another try...
2719                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2720                          */
2721                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
2722                                                               ICH_FLASH_HSFSTS);
2723                         if (hsfsts.hsf_status.flcerr) {
2724                                 /* Repeat for some time before giving up. */
2725                                 continue;
2726                         } else if (!hsfsts.hsf_status.flcdone) {
2727                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
2728                                 break;
2729                         }
2730                 }
2731         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2732
2733         return ret_val;
2734 }
2735
2736 /**
2737  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2738  *  @hw: pointer to the HW structure
2739  *  @offset: The offset (in bytes) of the word(s) to write.
2740  *  @words: Size of data to write in words
2741  *  @data: Pointer to the word(s) to write at offset.
2742  *
2743  *  Writes a byte or word to the NVM using the flash access registers.
2744  **/
2745 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2746                                    u16 *data)
2747 {
2748         struct e1000_nvm_info *nvm = &hw->nvm;
2749         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2750         u16 i;
2751
2752         DEBUGFUNC("e1000_write_nvm_ich8lan");
2753
2754         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2755             (words == 0)) {
2756                 DEBUGOUT("nvm parameter(s) out of bounds\n");
2757                 return -E1000_ERR_NVM;
2758         }
2759
2760         nvm->ops.acquire(hw);
2761
2762         for (i = 0; i < words; i++) {
2763                 dev_spec->shadow_ram[offset+i].modified = true;
2764                 dev_spec->shadow_ram[offset+i].value = data[i];
2765         }
2766
2767         nvm->ops.release(hw);
2768
2769         return E1000_SUCCESS;
2770 }
2771
2772 /**
2773  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2774  *  @hw: pointer to the HW structure
2775  *
2776  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2777  *  which writes the checksum to the shadow ram.  The changes in the shadow
2778  *  ram are then committed to the EEPROM by processing each bank at a time
2779  *  checking for the modified bit and writing only the pending changes.
2780  *  After a successful commit, the shadow ram is cleared and is ready for
2781  *  future writes.
2782  **/
2783 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2784 {
2785         struct e1000_nvm_info *nvm = &hw->nvm;
2786         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2787         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2788         s32 ret_val;
2789         u16 data;
2790
2791         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
2792
2793         ret_val = e1000_update_nvm_checksum_generic(hw);
2794         if (ret_val)
2795                 goto out;
2796
2797         if (nvm->type != e1000_nvm_flash_sw)
2798                 goto out;
2799
2800         nvm->ops.acquire(hw);
2801
2802         /* We're writing to the opposite bank so if we're on bank 1,
2803          * write to bank 0 etc.  We also need to erase the segment that
2804          * is going to be written
2805          */
2806         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2807         if (ret_val != E1000_SUCCESS) {
2808                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
2809                 bank = 0;
2810         }
2811
2812         if (bank == 0) {
2813                 new_bank_offset = nvm->flash_bank_size;
2814                 old_bank_offset = 0;
2815                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2816                 if (ret_val)
2817                         goto release;
2818         } else {
2819                 old_bank_offset = nvm->flash_bank_size;
2820                 new_bank_offset = 0;
2821                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2822                 if (ret_val)
2823                         goto release;
2824         }
2825
2826         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
2827                 /* Determine whether to write the value stored
2828                  * in the other NVM bank or a modified value stored
2829                  * in the shadow RAM
2830                  */
2831                 if (dev_spec->shadow_ram[i].modified) {
2832                         data = dev_spec->shadow_ram[i].value;
2833                 } else {
2834                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2835                                                                 old_bank_offset,
2836                                                                 &data);
2837                         if (ret_val)
2838                                 break;
2839                 }
2840
2841                 /* If the word is 0x13, then make sure the signature bits
2842                  * (15:14) are 11b until the commit has completed.
2843                  * This will allow us to write 10b which indicates the
2844                  * signature is valid.  We want to do this after the write
2845                  * has completed so that we don't mark the segment valid
2846                  * while the write is still in progress
2847                  */
2848                 if (i == E1000_ICH_NVM_SIG_WORD)
2849                         data |= E1000_ICH_NVM_SIG_MASK;
2850
2851                 /* Convert offset to bytes. */
2852                 act_offset = (i + new_bank_offset) << 1;
2853
2854                 usec_delay(100);
2855                 /* Write the bytes to the new bank. */
2856                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2857                                                                act_offset,
2858                                                                (u8)data);
2859                 if (ret_val)
2860                         break;
2861
2862                 usec_delay(100);
2863                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2864                                                           act_offset + 1,
2865                                                           (u8)(data >> 8));
2866                 if (ret_val)
2867                         break;
2868         }
2869
2870         /* Don't bother writing the segment valid bits if sector
2871          * programming failed.
2872          */
2873         if (ret_val) {
2874                 DEBUGOUT("Flash commit failed.\n");
2875                 goto release;
2876         }
2877
2878         /* Finally validate the new segment by setting bit 15:14
2879          * to 10b in word 0x13 , this can be done without an
2880          * erase as well since these bits are 11 to start with
2881          * and we need to change bit 14 to 0b
2882          */
2883         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2884         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2885         if (ret_val)
2886                 goto release;
2887
2888         data &= 0xBFFF;
2889         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2890                                                        act_offset * 2 + 1,
2891                                                        (u8)(data >> 8));
2892         if (ret_val)
2893                 goto release;
2894
2895         /* And invalidate the previously valid segment by setting
2896          * its signature word (0x13) high_byte to 0b. This can be
2897          * done without an erase because flash erase sets all bits
2898          * to 1's. We can write 1's to 0's without an erase
2899          */
2900         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2901         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2902         if (ret_val)
2903                 goto release;
2904
2905         /* Great!  Everything worked, we can now clear the cached entries. */
2906         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
2907                 dev_spec->shadow_ram[i].modified = false;
2908                 dev_spec->shadow_ram[i].value = 0xFFFF;
2909         }
2910
2911 release:
2912         nvm->ops.release(hw);
2913
2914         /* Reload the EEPROM, or else modifications will not appear
2915          * until after the next adapter reset.
2916          */
2917         if (!ret_val) {
2918                 nvm->ops.reload(hw);
2919                 msec_delay(10);
2920         }
2921
2922 out:
2923         if (ret_val)
2924                 DEBUGOUT1("NVM update error: %d\n", ret_val);
2925
2926         return ret_val;
2927 }
2928
2929 /**
2930  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2931  *  @hw: pointer to the HW structure
2932  *
2933  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2934  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2935  *  calculated, in which case we need to calculate the checksum and set bit 6.
2936  **/
2937 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2938 {
2939         s32 ret_val;
2940         u16 data;
2941         u16 word;
2942         u16 valid_csum_mask;
2943
2944         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
2945
2946         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
2947          * the checksum needs to be fixed.  This bit is an indication that
2948          * the NVM was prepared by OEM software and did not calculate
2949          * the checksum...a likely scenario.
2950          */
2951         switch (hw->mac.type) {
2952         default:
2953                 word = NVM_FUTURE_INIT_WORD1;
2954                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
2955                 break;
2956         }
2957
2958         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
2959         if (ret_val)
2960                 return ret_val;
2961
2962         if (!(data & valid_csum_mask)) {
2963                 data |= valid_csum_mask;
2964                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
2965                 if (ret_val)
2966                         return ret_val;
2967                 ret_val = hw->nvm.ops.update(hw);
2968                 if (ret_val)
2969                         return ret_val;
2970         }
2971
2972         return e1000_validate_nvm_checksum_generic(hw);
2973 }
2974
2975 /**
2976  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2977  *  @hw: pointer to the HW structure
2978  *  @offset: The offset (in bytes) of the byte/word to read.
2979  *  @size: Size of data to read, 1=byte 2=word
2980  *  @data: The byte(s) to write to the NVM.
2981  *
2982  *  Writes one/two bytes to the NVM using the flash access registers.
2983  **/
2984 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2985                                           u8 size, u16 data)
2986 {
2987         union ich8_hws_flash_status hsfsts;
2988         union ich8_hws_flash_ctrl hsflctl;
2989         u32 flash_linear_addr;
2990         u32 flash_data = 0;
2991         s32 ret_val;
2992         u8 count = 0;
2993
2994         DEBUGFUNC("e1000_write_ich8_data");
2995
2996         if (size < 1 || size > 2 || data > size * 0xff ||
2997             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2998                 return -E1000_ERR_NVM;
2999
3000         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3001                              hw->nvm.flash_base_addr);
3002
3003         do {
3004                 usec_delay(1);
3005                 /* Steps */
3006                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3007                 if (ret_val != E1000_SUCCESS)
3008                         break;
3009
3010                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3011                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3012                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3013                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3014                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3015
3016                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3017
3018                 if (size == 1)
3019                         flash_data = (u32)data & 0x00FF;
3020                 else
3021                         flash_data = (u32)data;
3022
3023                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3024
3025                 /* check if FCERR is set to 1 , if set to 1, clear it
3026                  * and try the whole sequence a few more times else done
3027                  */
3028                 ret_val =
3029                     e1000_flash_cycle_ich8lan(hw,
3030                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3031                 if (ret_val == E1000_SUCCESS)
3032                         break;
3033
3034                 /* If we're here, then things are most likely
3035                  * completely hosed, but if the error condition
3036                  * is detected, it won't hurt to give it another
3037                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3038                  */
3039                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3040                 if (hsfsts.hsf_status.flcerr)
3041                         /* Repeat for some time before giving up. */
3042                         continue;
3043                 if (!hsfsts.hsf_status.flcdone) {
3044                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3045                         break;
3046                 }
3047         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3048
3049         return ret_val;
3050 }
3051
3052 /**
3053  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3054  *  @hw: pointer to the HW structure
3055  *  @offset: The index of the byte to read.
3056  *  @data: The byte to write to the NVM.
3057  *
3058  *  Writes a single byte to the NVM using the flash access registers.
3059  **/
3060 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3061                                           u8 data)
3062 {
3063         u16 word = (u16)data;
3064
3065         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3066
3067         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3068 }
3069
3070 /**
3071  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3072  *  @hw: pointer to the HW structure
3073  *  @offset: The offset of the byte to write.
3074  *  @byte: The byte to write to the NVM.
3075  *
3076  *  Writes a single byte to the NVM using the flash access registers.
3077  *  Goes through a retry algorithm before giving up.
3078  **/
3079 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3080                                                 u32 offset, u8 byte)
3081 {
3082         s32 ret_val;
3083         u16 program_retries;
3084
3085         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3086
3087         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3088         if (!ret_val)
3089                 return ret_val;
3090
3091         for (program_retries = 0; program_retries < 100; program_retries++) {
3092                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3093                 usec_delay(100);
3094                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3095                 if (ret_val == E1000_SUCCESS)
3096                         break;
3097         }
3098         if (program_retries == 100)
3099                 return -E1000_ERR_NVM;
3100
3101         return E1000_SUCCESS;
3102 }
3103
3104 /**
3105  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3106  *  @hw: pointer to the HW structure
3107  *  @bank: 0 for first bank, 1 for second bank, etc.
3108  *
3109  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3110  *  bank N is 4096 * N + flash_reg_addr.
3111  **/
3112 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3113 {
3114         struct e1000_nvm_info *nvm = &hw->nvm;
3115         union ich8_hws_flash_status hsfsts;
3116         union ich8_hws_flash_ctrl hsflctl;
3117         u32 flash_linear_addr;
3118         /* bank size is in 16bit words - adjust to bytes */
3119         u32 flash_bank_size = nvm->flash_bank_size * 2;
3120         s32 ret_val;
3121         s32 count = 0;
3122         s32 j, iteration, sector_size;
3123
3124         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3125
3126         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3127
3128         /* Determine HW Sector size: Read BERASE bits of hw flash status
3129          * register
3130          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3131          *     consecutive sectors.  The start index for the nth Hw sector
3132          *     can be calculated as = bank * 4096 + n * 256
3133          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3134          *     The start index for the nth Hw sector can be calculated
3135          *     as = bank * 4096
3136          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3137          *     (ich9 only, otherwise error condition)
3138          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3139          */
3140         switch (hsfsts.hsf_status.berasesz) {
3141         case 0:
3142                 /* Hw sector size 256 */
3143                 sector_size = ICH_FLASH_SEG_SIZE_256;
3144                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3145                 break;
3146         case 1:
3147                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3148                 iteration = 1;
3149                 break;
3150         case 2:
3151                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3152                 iteration = 1;
3153                 break;
3154         case 3:
3155                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3156                 iteration = 1;
3157                 break;
3158         default:
3159                 return -E1000_ERR_NVM;
3160         }
3161
3162         /* Start with the base address, then add the sector offset. */
3163         flash_linear_addr = hw->nvm.flash_base_addr;
3164         flash_linear_addr += (bank) ? flash_bank_size : 0;
3165
3166         for (j = 0; j < iteration; j++) {
3167                 do {
3168                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3169
3170                         /* Steps */
3171                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3172                         if (ret_val)
3173                                 return ret_val;
3174
3175                         /* Write a value 11 (block Erase) in Flash
3176                          * Cycle field in hw flash control
3177                          */
3178                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
3179                                                               ICH_FLASH_HSFCTL);
3180                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3181                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3182                                                 hsflctl.regval);
3183
3184                         /* Write the last 24 bits of an index within the
3185                          * block into Flash Linear address field in Flash
3186                          * Address.
3187                          */
3188                         flash_linear_addr += (j * sector_size);
3189                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
3190                                               flash_linear_addr);
3191
3192                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3193                         if (ret_val == E1000_SUCCESS)
3194                                 break;
3195
3196                         /* Check if FCERR is set to 1.  If 1,
3197                          * clear it and try the whole sequence
3198                          * a few more times else Done
3199                          */
3200                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3201                                                       ICH_FLASH_HSFSTS);
3202                         if (hsfsts.hsf_status.flcerr)
3203                                 /* repeat for some time before giving up */
3204                                 continue;
3205                         else if (!hsfsts.hsf_status.flcdone)
3206                                 return ret_val;
3207                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3208         }
3209
3210         return E1000_SUCCESS;
3211 }
3212
3213 /**
3214  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3215  *  @hw: pointer to the HW structure
3216  *  @data: Pointer to the LED settings
3217  *
3218  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3219  *  settings is all 0's or F's, set the LED default to a valid LED default
3220  *  setting.
3221  **/
3222 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3223 {
3224         s32 ret_val;
3225
3226         DEBUGFUNC("e1000_valid_led_default_ich8lan");
3227
3228         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
3229         if (ret_val) {
3230                 DEBUGOUT("NVM Read Error\n");
3231                 return ret_val;
3232         }
3233
3234         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3235                 *data = ID_LED_DEFAULT_ICH8LAN;
3236
3237         return E1000_SUCCESS;
3238 }
3239
3240 /**
3241  *  e1000_id_led_init_pchlan - store LED configurations
3242  *  @hw: pointer to the HW structure
3243  *
3244  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3245  *  the PHY LED configuration register.
3246  *
3247  *  PCH also does not have an "always on" or "always off" mode which
3248  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3249  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
3250  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3251  *  link based on logic in e1000_led_[on|off]_pchlan().
3252  **/
3253 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3254 {
3255         struct e1000_mac_info *mac = &hw->mac;
3256         s32 ret_val;
3257         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3258         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3259         u16 data, i, temp, shift;
3260
3261         DEBUGFUNC("e1000_id_led_init_pchlan");
3262
3263         /* Get default ID LED modes */
3264         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3265         if (ret_val)
3266                 return ret_val;
3267
3268         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
3269         mac->ledctl_mode1 = mac->ledctl_default;
3270         mac->ledctl_mode2 = mac->ledctl_default;
3271
3272         for (i = 0; i < 4; i++) {
3273                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3274                 shift = (i * 5);
3275                 switch (temp) {
3276                 case ID_LED_ON1_DEF2:
3277                 case ID_LED_ON1_ON2:
3278                 case ID_LED_ON1_OFF2:
3279                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3280                         mac->ledctl_mode1 |= (ledctl_on << shift);
3281                         break;
3282                 case ID_LED_OFF1_DEF2:
3283                 case ID_LED_OFF1_ON2:
3284                 case ID_LED_OFF1_OFF2:
3285                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3286                         mac->ledctl_mode1 |= (ledctl_off << shift);
3287                         break;
3288                 default:
3289                         /* Do nothing */
3290                         break;
3291                 }
3292                 switch (temp) {
3293                 case ID_LED_DEF1_ON2:
3294                 case ID_LED_ON1_ON2:
3295                 case ID_LED_OFF1_ON2:
3296                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3297                         mac->ledctl_mode2 |= (ledctl_on << shift);
3298                         break;
3299                 case ID_LED_DEF1_OFF2:
3300                 case ID_LED_ON1_OFF2:
3301                 case ID_LED_OFF1_OFF2:
3302                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3303                         mac->ledctl_mode2 |= (ledctl_off << shift);
3304                         break;
3305                 default:
3306                         /* Do nothing */
3307                         break;
3308                 }
3309         }
3310
3311         return E1000_SUCCESS;
3312 }
3313
3314 /**
3315  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3316  *  @hw: pointer to the HW structure
3317  *
3318  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3319  *  register, so the the bus width is hard coded.
3320  **/
3321 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3322 {
3323         struct e1000_bus_info *bus = &hw->bus;
3324         s32 ret_val;
3325
3326         DEBUGFUNC("e1000_get_bus_info_ich8lan");
3327
3328         ret_val = e1000_get_bus_info_pcie_generic(hw);
3329
3330         /* ICH devices are "PCI Express"-ish.  They have
3331          * a configuration space, but do not contain
3332          * PCI Express Capability registers, so bus width
3333          * must be hardcoded.
3334          */
3335         if (bus->width == e1000_bus_width_unknown)
3336                 bus->width = e1000_bus_width_pcie_x1;
3337
3338         return ret_val;
3339 }
3340
3341 /**
3342  *  e1000_reset_hw_ich8lan - Reset the hardware
3343  *  @hw: pointer to the HW structure
3344  *
3345  *  Does a full reset of the hardware which includes a reset of the PHY and
3346  *  MAC.
3347  **/
3348 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3349 {
3350         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3351         u16 kum_cfg;
3352         u32 ctrl, reg;
3353         s32 ret_val;
3354
3355         DEBUGFUNC("e1000_reset_hw_ich8lan");
3356
3357         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3358          * on the last TLP read/write transaction when MAC is reset.
3359          */
3360         ret_val = e1000_disable_pcie_master_generic(hw);
3361         if (ret_val)
3362                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
3363
3364         DEBUGOUT("Masking off all interrupts\n");
3365         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3366
3367         /* Disable the Transmit and Receive units.  Then delay to allow
3368          * any pending transactions to complete before we hit the MAC
3369          * with the global reset.
3370          */
3371         E1000_WRITE_REG(hw, E1000_RCTL, 0);
3372         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
3373         E1000_WRITE_FLUSH(hw);
3374
3375         msec_delay(10);
3376
3377         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3378         if (hw->mac.type == e1000_ich8lan) {
3379                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3380                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
3381                 /* Set Packet Buffer Size to 16k. */
3382                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
3383         }
3384
3385         if (hw->mac.type == e1000_pchlan) {
3386                 /* Save the NVM K1 bit setting*/
3387                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3388                 if (ret_val)
3389                         return ret_val;
3390
3391                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3392                         dev_spec->nvm_k1_enabled = true;
3393                 else
3394                         dev_spec->nvm_k1_enabled = false;
3395         }
3396
3397         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3398
3399         if (!hw->phy.ops.check_reset_block(hw)) {
3400                 /* Full-chip reset requires MAC and PHY reset at the same
3401                  * time to make sure the interface between MAC and the
3402                  * external PHY is reset.
3403                  */
3404                 ctrl |= E1000_CTRL_PHY_RST;
3405
3406                 /* Gate automatic PHY configuration by hardware on
3407                  * non-managed 82579
3408                  */
3409                 if ((hw->mac.type == e1000_pch2lan) &&
3410                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3411                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3412         }
3413         ret_val = e1000_acquire_swflag_ich8lan(hw);
3414         DEBUGOUT("Issuing a global reset to ich8lan\n");
3415         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
3416         /* cannot issue a flush here because it hangs the hardware */
3417         msec_delay(20);
3418
3419         /* Set Phy Config Counter to 50msec */
3420         if (hw->mac.type == e1000_pch2lan) {
3421                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
3422                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3423                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3424                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
3425         }
3426
3427         if (!ret_val)
3428                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
3429
3430         if (ctrl & E1000_CTRL_PHY_RST) {
3431                 ret_val = hw->phy.ops.get_cfg_done(hw);
3432                 if (ret_val)
3433                         return ret_val;
3434
3435                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3436                 if (ret_val)
3437                         return ret_val;
3438         }
3439
3440         /* For PCH, this write will make sure that any noise
3441          * will be detected as a CRC error and be dropped rather than show up
3442          * as a bad packet to the DMA engine.
3443          */
3444         if (hw->mac.type == e1000_pchlan)
3445                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
3446
3447         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
3448         E1000_READ_REG(hw, E1000_ICR);
3449
3450         reg = E1000_READ_REG(hw, E1000_KABGTXD);
3451         reg |= E1000_KABGTXD_BGSQLBIAS;
3452         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
3453
3454         return E1000_SUCCESS;
3455 }
3456
3457 /**
3458  *  e1000_init_hw_ich8lan - Initialize the hardware
3459  *  @hw: pointer to the HW structure
3460  *
3461  *  Prepares the hardware for transmit and receive by doing the following:
3462  *   - initialize hardware bits
3463  *   - initialize LED identification
3464  *   - setup receive address registers
3465  *   - setup flow control
3466  *   - setup transmit descriptors
3467  *   - clear statistics
3468  **/
3469 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3470 {
3471         struct e1000_mac_info *mac = &hw->mac;
3472         u32 ctrl_ext, txdctl, snoop;
3473         s32 ret_val;
3474         u16 i;
3475
3476         DEBUGFUNC("e1000_init_hw_ich8lan");
3477
3478         e1000_initialize_hw_bits_ich8lan(hw);
3479
3480         /* Initialize identification LED */
3481         ret_val = mac->ops.id_led_init(hw);
3482         /* An error is not fatal and we should not stop init due to this */
3483         if (ret_val)
3484                 DEBUGOUT("Error initializing identification LED\n");
3485
3486         /* Setup the receive address. */
3487         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
3488
3489         /* Zero out the Multicast HASH table */
3490         DEBUGOUT("Zeroing the MTA\n");
3491         for (i = 0; i < mac->mta_reg_count; i++)
3492                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3493
3494         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3495          * the ME.  Disable wakeup by clearing the host wakeup bit.
3496          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3497          */
3498         if (hw->phy.type == e1000_phy_82578) {
3499                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
3500                 i &= ~BM_WUC_HOST_WU_BIT;
3501                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
3502                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3503                 if (ret_val)
3504                         return ret_val;
3505         }
3506
3507         /* Setup link and flow control */
3508         ret_val = mac->ops.setup_link(hw);
3509
3510         /* Set the transmit descriptor write-back policy for both queues */
3511         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
3512         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3513                   E1000_TXDCTL_FULL_TX_DESC_WB);
3514         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3515                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3516         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
3517         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
3518         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3519                   E1000_TXDCTL_FULL_TX_DESC_WB);
3520         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3521                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3522         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
3523
3524         /* ICH8 has opposite polarity of no_snoop bits.
3525          * By default, we should use snoop behavior.
3526          */
3527         if (mac->type == e1000_ich8lan)
3528                 snoop = PCIE_ICH8_SNOOP_ALL;
3529         else
3530                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3531         e1000_set_pcie_no_snoop_generic(hw, snoop);
3532
3533         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3534         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3535         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3536
3537         /* Clear all of the statistics registers (clear on read).  It is
3538          * important that we do this after we have tried to establish link
3539          * because the symbol error count will increment wildly if there
3540          * is no link.
3541          */
3542         e1000_clear_hw_cntrs_ich8lan(hw);
3543
3544         return ret_val;
3545 }
3546
3547 /**
3548  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3549  *  @hw: pointer to the HW structure
3550  *
3551  *  Sets/Clears required hardware bits necessary for correctly setting up the
3552  *  hardware for transmit and receive.
3553  **/
3554 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3555 {
3556         u32 reg;
3557
3558         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
3559
3560         /* Extended Device Control */
3561         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3562         reg |= (1 << 22);
3563         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3564         if (hw->mac.type >= e1000_pchlan)
3565                 reg |= E1000_CTRL_EXT_PHYPDEN;
3566         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
3567
3568         /* Transmit Descriptor Control 0 */
3569         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
3570         reg |= (1 << 22);
3571         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
3572
3573         /* Transmit Descriptor Control 1 */
3574         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
3575         reg |= (1 << 22);
3576         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
3577
3578         /* Transmit Arbitration Control 0 */
3579         reg = E1000_READ_REG(hw, E1000_TARC(0));
3580         if (hw->mac.type == e1000_ich8lan)
3581                 reg |= (1 << 28) | (1 << 29);
3582         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3583         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
3584
3585         /* Transmit Arbitration Control 1 */
3586         reg = E1000_READ_REG(hw, E1000_TARC(1));
3587         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
3588                 reg &= ~(1 << 28);
3589         else
3590                 reg |= (1 << 28);
3591         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3592         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
3593
3594         /* Device Status */
3595         if (hw->mac.type == e1000_ich8lan) {
3596                 reg = E1000_READ_REG(hw, E1000_STATUS);
3597                 reg &= ~(1 << 31);
3598                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
3599         }
3600
3601         /* work-around descriptor data corruption issue during nfs v2 udp
3602          * traffic, just disable the nfs filtering capability
3603          */
3604         reg = E1000_READ_REG(hw, E1000_RFCTL);
3605         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3606
3607         /* Disable IPv6 extension header parsing because some malformed
3608          * IPv6 headers can hang the Rx.
3609          */
3610         if (hw->mac.type == e1000_ich8lan)
3611                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3612         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
3613
3614         return;
3615 }
3616
3617 /**
3618  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3619  *  @hw: pointer to the HW structure
3620  *
3621  *  Determines which flow control settings to use, then configures flow
3622  *  control.  Calls the appropriate media-specific link configuration
3623  *  function.  Assuming the adapter has a valid link partner, a valid link
3624  *  should be established.  Assumes the hardware has previously been reset
3625  *  and the transmitter and receiver are not enabled.
3626  **/
3627 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3628 {
3629         s32 ret_val;
3630
3631         DEBUGFUNC("e1000_setup_link_ich8lan");
3632
3633         if (hw->phy.ops.check_reset_block(hw))
3634                 return E1000_SUCCESS;
3635
3636         /* ICH parts do not have a word in the NVM to determine
3637          * the default flow control setting, so we explicitly
3638          * set it to full.
3639          */
3640         if (hw->fc.requested_mode == e1000_fc_default)
3641                 hw->fc.requested_mode = e1000_fc_full;
3642
3643         /* Save off the requested flow control mode for use later.  Depending
3644          * on the link partner's capabilities, we may or may not use this mode.
3645          */
3646         hw->fc.current_mode = hw->fc.requested_mode;
3647
3648         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
3649                 hw->fc.current_mode);
3650
3651         /* Continue to configure the copper link. */
3652         ret_val = hw->mac.ops.setup_physical_interface(hw);
3653         if (ret_val)
3654                 return ret_val;
3655
3656         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
3657         if ((hw->phy.type == e1000_phy_82578) ||
3658             (hw->phy.type == e1000_phy_82579) ||
3659             (hw->phy.type == e1000_phy_i217) ||
3660             (hw->phy.type == e1000_phy_82577)) {
3661                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
3662
3663                 ret_val = hw->phy.ops.write_reg(hw,
3664                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
3665                                              hw->fc.pause_time);
3666                 if (ret_val)
3667                         return ret_val;
3668         }
3669
3670         return e1000_set_fc_watermarks_generic(hw);
3671 }
3672
3673 /**
3674  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3675  *  @hw: pointer to the HW structure
3676  *
3677  *  Configures the kumeran interface to the PHY to wait the appropriate time
3678  *  when polling the PHY, then call the generic setup_copper_link to finish
3679  *  configuring the copper link.
3680  **/
3681 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3682 {
3683         u32 ctrl;
3684         s32 ret_val;
3685         u16 reg_data;
3686
3687         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
3688
3689         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3690         ctrl |= E1000_CTRL_SLU;
3691         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3692         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3693
3694         /* Set the mac to wait the maximum time between each iteration
3695          * and increase the max iterations when polling the phy;
3696          * this fixes erroneous timeouts at 10Mbps.
3697          */
3698         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
3699                                                0xFFFF);
3700         if (ret_val)
3701                 return ret_val;
3702         ret_val = e1000_read_kmrn_reg_generic(hw,
3703                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
3704                                               &reg_data);
3705         if (ret_val)
3706                 return ret_val;
3707         reg_data |= 0x3F;
3708         ret_val = e1000_write_kmrn_reg_generic(hw,
3709                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
3710                                                reg_data);
3711         if (ret_val)
3712                 return ret_val;
3713
3714         switch (hw->phy.type) {
3715         case e1000_phy_igp_3:
3716                 ret_val = e1000_copper_link_setup_igp(hw);
3717                 if (ret_val)
3718                         return ret_val;
3719                 break;
3720         case e1000_phy_bm:
3721         case e1000_phy_82578:
3722                 ret_val = e1000_copper_link_setup_m88(hw);
3723                 if (ret_val)
3724                         return ret_val;
3725                 break;
3726         case e1000_phy_82577:
3727         case e1000_phy_82579:
3728         case e1000_phy_i217:
3729                 ret_val = e1000_copper_link_setup_82577(hw);
3730                 if (ret_val)
3731                         return ret_val;
3732                 break;
3733         case e1000_phy_ife:
3734                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3735                                                &reg_data);
3736                 if (ret_val)
3737                         return ret_val;
3738
3739                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3740
3741                 switch (hw->phy.mdix) {
3742                 case 1:
3743                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3744                         break;
3745                 case 2:
3746                         reg_data |= IFE_PMC_FORCE_MDIX;
3747                         break;
3748                 case 0:
3749                 default:
3750                         reg_data |= IFE_PMC_AUTO_MDIX;
3751                         break;
3752                 }
3753                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3754                                                 reg_data);
3755                 if (ret_val)
3756                         return ret_val;
3757                 break;
3758         default:
3759                 break;
3760         }
3761
3762         return e1000_setup_copper_link_generic(hw);
3763 }
3764
3765 /**
3766  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3767  *  @hw: pointer to the HW structure
3768  *  @speed: pointer to store current link speed
3769  *  @duplex: pointer to store the current link duplex
3770  *
3771  *  Calls the generic get_speed_and_duplex to retrieve the current link
3772  *  information and then calls the Kumeran lock loss workaround for links at
3773  *  gigabit speeds.
3774  **/
3775 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3776                                           u16 *duplex)
3777 {
3778         s32 ret_val;
3779
3780         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
3781
3782         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
3783         if (ret_val)
3784                 return ret_val;
3785
3786         if ((hw->mac.type == e1000_ich8lan) &&
3787             (hw->phy.type == e1000_phy_igp_3) &&
3788             (*speed == SPEED_1000)) {
3789                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3790         }
3791
3792         return ret_val;
3793 }
3794
3795 /**
3796  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3797  *  @hw: pointer to the HW structure
3798  *
3799  *  Work-around for 82566 Kumeran PCS lock loss:
3800  *  On link status change (i.e. PCI reset, speed change) and link is up and
3801  *  speed is gigabit-
3802  *    0) if workaround is optionally disabled do nothing
3803  *    1) wait 1ms for Kumeran link to come up
3804  *    2) check Kumeran Diagnostic register PCS lock loss bit
3805  *    3) if not set the link is locked (all is good), otherwise...
3806  *    4) reset the PHY
3807  *    5) repeat up to 10 times
3808  *  Note: this is only called for IGP3 copper when speed is 1gb.
3809  **/
3810 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3811 {
3812         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3813         u32 phy_ctrl;
3814         s32 ret_val;
3815         u16 i, data;
3816         bool link;
3817
3818         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
3819
3820         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3821                 return E1000_SUCCESS;
3822
3823         /* Make sure link is up before proceeding.  If not just return.
3824          * Attempting this while link is negotiating fouled up link
3825          * stability
3826          */
3827         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3828         if (!link)
3829                 return E1000_SUCCESS;
3830
3831         for (i = 0; i < 10; i++) {
3832                 /* read once to clear */
3833                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
3834                 if (ret_val)
3835                         return ret_val;
3836                 /* and again to get new status */
3837                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
3838                 if (ret_val)
3839                         return ret_val;
3840
3841                 /* check for PCS lock */
3842                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3843                         return E1000_SUCCESS;
3844
3845                 /* Issue PHY reset */
3846                 hw->phy.ops.reset(hw);
3847                 msec_delay_irq(5);
3848         }
3849         /* Disable GigE link negotiation */
3850         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3851         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3852                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3853         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3854
3855         /* Call gig speed drop workaround on Gig disable before accessing
3856          * any PHY registers
3857          */
3858         e1000_gig_downshift_workaround_ich8lan(hw);
3859
3860         /* unable to acquire PCS lock */
3861         return -E1000_ERR_PHY;
3862 }
3863
3864 /**
3865  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3866  *  @hw: pointer to the HW structure
3867  *  @state: boolean value used to set the current Kumeran workaround state
3868  *
3869  *  If ICH8, set the current Kumeran workaround state (enabled - true
3870  *  /disabled - false).
3871  **/
3872 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3873                                                  bool state)
3874 {
3875         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3876
3877         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
3878
3879         if (hw->mac.type != e1000_ich8lan) {
3880                 DEBUGOUT("Workaround applies to ICH8 only.\n");
3881                 return;
3882         }
3883
3884         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3885
3886         return;
3887 }
3888
3889 /**
3890  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3891  *  @hw: pointer to the HW structure
3892  *
3893  *  Workaround for 82566 power-down on D3 entry:
3894  *    1) disable gigabit link
3895  *    2) write VR power-down enable
3896  *    3) read it back
3897  *  Continue if successful, else issue LCD reset and repeat
3898  **/
3899 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3900 {
3901         u32 reg;
3902         u16 data;
3903         u8  retry = 0;
3904
3905         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
3906
3907         if (hw->phy.type != e1000_phy_igp_3)
3908                 return;
3909
3910         /* Try the workaround twice (if needed) */
3911         do {
3912                 /* Disable link */
3913                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
3914                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3915                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3916                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
3917
3918                 /* Call gig speed drop workaround on Gig disable before
3919                  * accessing any PHY registers
3920                  */
3921                 if (hw->mac.type == e1000_ich8lan)
3922                         e1000_gig_downshift_workaround_ich8lan(hw);
3923
3924                 /* Write VR power-down enable */
3925                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3926                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3927                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
3928                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3929
3930                 /* Read it back and test */
3931                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
3932                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3933                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3934                         break;
3935
3936                 /* Issue PHY reset and repeat at most one more time */
3937                 reg = E1000_READ_REG(hw, E1000_CTRL);
3938                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
3939                 retry++;
3940         } while (retry);
3941 }
3942
3943 /**
3944  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3945  *  @hw: pointer to the HW structure
3946  *
3947  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3948  *  LPLU, Gig disable, MDIC PHY reset):
3949  *    1) Set Kumeran Near-end loopback
3950  *    2) Clear Kumeran Near-end loopback
3951  *  Should only be called for ICH8[m] devices with any 1G Phy.
3952  **/
3953 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3954 {
3955         s32 ret_val;
3956         u16 reg_data;
3957
3958         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
3959
3960         if ((hw->mac.type != e1000_ich8lan) ||
3961             (hw->phy.type == e1000_phy_ife))
3962                 return;
3963
3964         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3965                                               &reg_data);
3966         if (ret_val)
3967                 return;
3968         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3969         ret_val = e1000_write_kmrn_reg_generic(hw,
3970                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
3971                                                reg_data);
3972         if (ret_val)
3973                 return;
3974         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3975         ret_val = e1000_write_kmrn_reg_generic(hw,
3976                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
3977                                                reg_data);
3978 }
3979
3980 /**
3981  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3982  *  @hw: pointer to the HW structure
3983  *
3984  *  During S0 to Sx transition, it is possible the link remains at gig
3985  *  instead of negotiating to a lower speed.  Before going to Sx, set
3986  *  'Gig Disable' to force link speed negotiation to a lower speed based on
3987  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
3988  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3989  *  needs to be written.
3990  *  Parts that support (and are linked to a partner which support) EEE in
3991  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
3992  *  than 10Mbps w/o EEE.
3993  **/
3994 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3995 {
3996         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3997         u32 phy_ctrl;
3998         s32 ret_val;
3999
4000         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4001
4002         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4003         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4004
4005         if (hw->phy.type == e1000_phy_i217) {
4006                 u16 phy_reg;
4007
4008                 ret_val = hw->phy.ops.acquire(hw);
4009                 if (ret_val)
4010                         goto out;
4011
4012                 if (!dev_spec->eee_disable) {
4013                         u16 eee_advert;
4014
4015                         ret_val =
4016                             e1000_read_emi_reg_locked(hw,
4017                                                       I217_EEE_ADVERTISEMENT,
4018                                                       &eee_advert);
4019                         if (ret_val)
4020                                 goto release;
4021
4022                         /* Disable LPLU if both link partners support 100BaseT
4023                          * EEE and 100Full is advertised on both ends of the
4024                          * link.
4025                          */
4026                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4027                             (dev_spec->eee_lp_ability &
4028                              I82579_EEE_100_SUPPORTED) &&
4029                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4030                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4031                                               E1000_PHY_CTRL_NOND0A_LPLU);
4032                 }
4033
4034                 /* For i217 Intel Rapid Start Technology support,
4035                  * when the system is going into Sx and no manageability engine
4036                  * is present, the driver must configure proxy to reset only on
4037                  * power good.  LPI (Low Power Idle) state must also reset only
4038                  * on power good, as well as the MTA (Multicast table array).
4039                  * The SMBus release must also be disabled on LCD reset.
4040                  */
4041                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4042                         E1000_ICH_FWSM_FW_VALID)) {
4043                         /* Enable proxy to reset only on power good. */
4044                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4045                                                     &phy_reg);
4046                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4047                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4048                                                      phy_reg);
4049
4050                         /* Set bit enable LPI (EEE) to reset only on
4051                          * power good.
4052                         */
4053                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4054                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4055                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4056
4057                         /* Disable the SMB release on LCD reset. */
4058                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4059                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4060                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4061                 }
4062
4063                 /* Enable MTA to reset for Intel Rapid Start Technology
4064                  * Support
4065                  */
4066                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4067                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4068                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4069
4070 release:
4071                 hw->phy.ops.release(hw);
4072         }
4073 out:
4074         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4075
4076         if (hw->mac.type == e1000_ich8lan)
4077                 e1000_gig_downshift_workaround_ich8lan(hw);
4078
4079         if (hw->mac.type >= e1000_pchlan) {
4080                 e1000_oem_bits_config_ich8lan(hw, false);
4081
4082                 /* Reset PHY to activate OEM bits on 82577/8 */
4083                 if (hw->mac.type == e1000_pchlan)
4084                         e1000_phy_hw_reset_generic(hw);
4085
4086                 ret_val = hw->phy.ops.acquire(hw);
4087                 if (ret_val)
4088                         return;
4089                 e1000_write_smbus_addr(hw);
4090                 hw->phy.ops.release(hw);
4091         }
4092
4093         return;
4094 }
4095
4096 /**
4097  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4098  *  @hw: pointer to the HW structure
4099  *
4100  *  During Sx to S0 transitions on non-managed devices or managed devices
4101  *  on which PHY resets are not blocked, if the PHY registers cannot be
4102  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4103  *  the PHY.
4104  *  On i217, setup Intel Rapid Start Technology.
4105  **/
4106 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4107 {
4108         s32 ret_val;
4109
4110         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4111
4112         if (hw->mac.type < e1000_pch2lan)
4113                 return;
4114
4115         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4116         if (ret_val) {
4117                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4118                 return;
4119         }
4120
4121         /* For i217 Intel Rapid Start Technology support when the system
4122          * is transitioning from Sx and no manageability engine is present
4123          * configure SMBus to restore on reset, disable proxy, and enable
4124          * the reset on MTA (Multicast table array).
4125          */
4126         if (hw->phy.type == e1000_phy_i217) {
4127                 u16 phy_reg;
4128
4129                 ret_val = hw->phy.ops.acquire(hw);
4130                 if (ret_val) {
4131                         DEBUGOUT("Failed to setup iRST\n");
4132                         return;
4133                 }
4134
4135                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4136                     E1000_ICH_FWSM_FW_VALID)) {
4137                         /* Restore clear on SMB if no manageability engine
4138                          * is present
4139                          */
4140                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
4141                                                               &phy_reg);
4142                         if (ret_val)
4143                                 goto release;
4144                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4145                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4146
4147                         /* Disable Proxy */
4148                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
4149                 }
4150                 /* Enable reset on MTA */
4151                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
4152                                                       &phy_reg);
4153                 if (ret_val)
4154                         goto release;
4155                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4156                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4157 release:
4158                 if (ret_val)
4159                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
4160                 hw->phy.ops.release(hw);
4161         }
4162 }
4163
4164 /**
4165  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4166  *  @hw: pointer to the HW structure
4167  *
4168  *  Return the LED back to the default configuration.
4169  **/
4170 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4171 {
4172         DEBUGFUNC("e1000_cleanup_led_ich8lan");
4173
4174         if (hw->phy.type == e1000_phy_ife)
4175                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4176                                              0);
4177
4178         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
4179         return E1000_SUCCESS;
4180 }
4181
4182 /**
4183  *  e1000_led_on_ich8lan - Turn LEDs on
4184  *  @hw: pointer to the HW structure
4185  *
4186  *  Turn on the LEDs.
4187  **/
4188 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4189 {
4190         DEBUGFUNC("e1000_led_on_ich8lan");
4191
4192         if (hw->phy.type == e1000_phy_ife)
4193                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4194                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4195
4196         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
4197         return E1000_SUCCESS;
4198 }
4199
4200 /**
4201  *  e1000_led_off_ich8lan - Turn LEDs off
4202  *  @hw: pointer to the HW structure
4203  *
4204  *  Turn off the LEDs.
4205  **/
4206 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4207 {
4208         DEBUGFUNC("e1000_led_off_ich8lan");
4209
4210         if (hw->phy.type == e1000_phy_ife)
4211                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4212                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
4213
4214         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
4215         return E1000_SUCCESS;
4216 }
4217
4218 /**
4219  *  e1000_setup_led_pchlan - Configures SW controllable LED
4220  *  @hw: pointer to the HW structure
4221  *
4222  *  This prepares the SW controllable LED for use.
4223  **/
4224 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4225 {
4226         DEBUGFUNC("e1000_setup_led_pchlan");
4227
4228         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4229                                      (u16)hw->mac.ledctl_mode1);
4230 }
4231
4232 /**
4233  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4234  *  @hw: pointer to the HW structure
4235  *
4236  *  Return the LED back to the default configuration.
4237  **/
4238 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4239 {
4240         DEBUGFUNC("e1000_cleanup_led_pchlan");
4241
4242         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
4243                                      (u16)hw->mac.ledctl_default);
4244 }
4245
4246 /**
4247  *  e1000_led_on_pchlan - Turn LEDs on
4248  *  @hw: pointer to the HW structure
4249  *
4250  *  Turn on the LEDs.
4251  **/
4252 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4253 {
4254         u16 data = (u16)hw->mac.ledctl_mode2;
4255         u32 i, led;
4256
4257         DEBUGFUNC("e1000_led_on_pchlan");
4258
4259         /* If no link, then turn LED on by setting the invert bit
4260          * for each LED that's mode is "link_up" in ledctl_mode2.
4261          */
4262         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
4263                 for (i = 0; i < 3; i++) {
4264                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4265                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4266                             E1000_LEDCTL_MODE_LINK_UP)
4267                                 continue;
4268                         if (led & E1000_PHY_LED0_IVRT)
4269                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4270                         else
4271                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4272                 }
4273         }
4274
4275         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
4276 }
4277
4278 /**
4279  *  e1000_led_off_pchlan - Turn LEDs off
4280  *  @hw: pointer to the HW structure
4281  *
4282  *  Turn off the LEDs.
4283  **/
4284 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4285 {
4286         u16 data = (u16)hw->mac.ledctl_mode1;
4287         u32 i, led;
4288
4289         DEBUGFUNC("e1000_led_off_pchlan");
4290
4291         /* If no link, then turn LED off by clearing the invert bit
4292          * for each LED that's mode is "link_up" in ledctl_mode1.
4293          */
4294         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
4295                 for (i = 0; i < 3; i++) {
4296                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4297                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4298                             E1000_LEDCTL_MODE_LINK_UP)
4299                                 continue;
4300                         if (led & E1000_PHY_LED0_IVRT)
4301                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4302                         else
4303                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4304                 }
4305         }
4306
4307         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
4308 }
4309
4310 /**
4311  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4312  *  @hw: pointer to the HW structure
4313  *
4314  *  Read appropriate register for the config done bit for completion status
4315  *  and configure the PHY through s/w for EEPROM-less parts.
4316  *
4317  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4318  *  config done bit, so only an error is logged and continues.  If we were
4319  *  to return with error, EEPROM-less silicon would not be able to be reset
4320  *  or change link.
4321  **/
4322 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4323 {
4324         s32 ret_val = E1000_SUCCESS;
4325         u32 bank = 0;
4326         u32 status;
4327
4328         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
4329
4330         e1000_get_cfg_done_generic(hw);
4331
4332         /* Wait for indication from h/w that it has completed basic config */
4333         if (hw->mac.type >= e1000_ich10lan) {
4334                 e1000_lan_init_done_ich8lan(hw);
4335         } else {
4336                 ret_val = e1000_get_auto_rd_done_generic(hw);
4337                 if (ret_val) {
4338                         /* When auto config read does not complete, do not
4339                          * return with an error. This can happen in situations
4340                          * where there is no eeprom and prevents getting link.
4341                          */
4342                         DEBUGOUT("Auto Read Done did not complete\n");
4343                         ret_val = E1000_SUCCESS;
4344                 }
4345         }
4346
4347         /* Clear PHY Reset Asserted bit */
4348         status = E1000_READ_REG(hw, E1000_STATUS);
4349         if (status & E1000_STATUS_PHYRA)
4350                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
4351         else
4352                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
4353
4354         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4355         if (hw->mac.type <= e1000_ich9lan) {
4356                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
4357                     (hw->phy.type == e1000_phy_igp_3)) {
4358                         e1000_phy_init_script_igp3(hw);
4359                 }
4360         } else {
4361                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4362                         /* Maybe we should do a basic PHY config */
4363                         DEBUGOUT("EEPROM not present\n");
4364                         ret_val = -E1000_ERR_CONFIG;
4365                 }
4366         }
4367
4368         return ret_val;
4369 }
4370
4371 /**
4372  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4373  * @hw: pointer to the HW structure
4374  *
4375  * In the case of a PHY power down to save power, or to turn off link during a
4376  * driver unload, or wake on lan is not enabled, remove the link.
4377  **/
4378 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4379 {
4380         /* If the management interface is not enabled, then power down */
4381         if (!(hw->mac.ops.check_mng_mode(hw) ||
4382               hw->phy.ops.check_reset_block(hw)))
4383                 e1000_power_down_phy_copper(hw);
4384
4385         return;
4386 }
4387
4388 /**
4389  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4390  *  @hw: pointer to the HW structure
4391  *
4392  *  Clears hardware counters specific to the silicon family and calls
4393  *  clear_hw_cntrs_generic to clear all general purpose counters.
4394  **/
4395 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4396 {
4397         u16 phy_data;
4398         s32 ret_val;
4399
4400         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
4401
4402         e1000_clear_hw_cntrs_base_generic(hw);
4403
4404         E1000_READ_REG(hw, E1000_ALGNERRC);
4405         E1000_READ_REG(hw, E1000_RXERRC);
4406         E1000_READ_REG(hw, E1000_TNCRS);
4407         E1000_READ_REG(hw, E1000_CEXTERR);
4408         E1000_READ_REG(hw, E1000_TSCTC);
4409         E1000_READ_REG(hw, E1000_TSCTFC);
4410
4411         E1000_READ_REG(hw, E1000_MGTPRC);
4412         E1000_READ_REG(hw, E1000_MGTPDC);
4413         E1000_READ_REG(hw, E1000_MGTPTC);
4414
4415         E1000_READ_REG(hw, E1000_IAC);
4416         E1000_READ_REG(hw, E1000_ICRXOC);
4417
4418         /* Clear PHY statistics registers */
4419         if ((hw->phy.type == e1000_phy_82578) ||
4420             (hw->phy.type == e1000_phy_82579) ||
4421             (hw->phy.type == e1000_phy_i217) ||
4422             (hw->phy.type == e1000_phy_82577)) {
4423                 ret_val = hw->phy.ops.acquire(hw);
4424                 if (ret_val)
4425                         return;
4426                 ret_val = hw->phy.ops.set_page(hw,
4427                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4428                 if (ret_val)
4429                         goto release;
4430                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4431                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4432                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4433                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4434                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4435                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4436                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4437                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4438                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4439                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4440                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4441                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4442                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4443                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4444 release:
4445                 hw->phy.ops.release(hw);
4446         }
4447 }
4448