1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw);
37 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw);
38 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw);
39 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
40 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
43 * e1000_init_mac_ops_generic - Initialize MAC function pointers
44 * @hw: pointer to the HW structure
46 * Setups up the function pointers to no-op functions
48 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
50 struct e1000_mac_info *mac = &hw->mac;
51 DEBUGFUNC("e1000_init_mac_ops_generic");
54 mac->ops.init_params = e1000_null_ops_generic;
55 mac->ops.init_hw = e1000_null_ops_generic;
56 mac->ops.reset_hw = e1000_null_ops_generic;
57 mac->ops.setup_physical_interface = e1000_null_ops_generic;
58 mac->ops.get_bus_info = e1000_null_ops_generic;
59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
64 mac->ops.cleanup_led = e1000_null_ops_generic;
65 mac->ops.setup_led = e1000_null_ops_generic;
66 mac->ops.blink_led = e1000_null_ops_generic;
67 mac->ops.led_on = e1000_null_ops_generic;
68 mac->ops.led_off = e1000_null_ops_generic;
70 mac->ops.setup_link = e1000_null_ops_generic;
71 mac->ops.get_link_up_info = e1000_null_link_info;
72 mac->ops.check_for_link = e1000_null_ops_generic;
73 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
75 mac->ops.check_mng_mode = e1000_null_mng_mode;
76 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
77 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
78 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
80 mac->ops.update_mc_addr_list = e1000_null_update_mc;
81 mac->ops.clear_vfta = e1000_null_mac_generic;
82 mac->ops.write_vfta = e1000_null_write_vfta;
83 mac->ops.rar_set = e1000_rar_set_generic;
84 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
88 * e1000_null_ops_generic - No-op function, returns 0
89 * @hw: pointer to the HW structure
91 s32 e1000_null_ops_generic(struct e1000_hw *hw)
93 DEBUGFUNC("e1000_null_ops_generic");
98 * e1000_null_mac_generic - No-op function, return void
99 * @hw: pointer to the HW structure
101 void e1000_null_mac_generic(struct e1000_hw *hw)
103 DEBUGFUNC("e1000_null_mac_generic");
108 * e1000_null_link_info - No-op function, return 0
109 * @hw: pointer to the HW structure
111 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
113 DEBUGFUNC("e1000_null_link_info");
114 return E1000_SUCCESS;
118 * e1000_null_mng_mode - No-op function, return false
119 * @hw: pointer to the HW structure
121 bool e1000_null_mng_mode(struct e1000_hw *hw)
123 DEBUGFUNC("e1000_null_mng_mode");
128 * e1000_null_update_mc - No-op function, return void
129 * @hw: pointer to the HW structure
131 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
133 DEBUGFUNC("e1000_null_update_mc");
138 * e1000_null_write_vfta - No-op function, return void
139 * @hw: pointer to the HW structure
141 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
143 DEBUGFUNC("e1000_null_write_vfta");
148 * e1000_null_rar_set - No-op function, return void
149 * @hw: pointer to the HW structure
151 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
153 DEBUGFUNC("e1000_null_rar_set");
158 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
159 * @hw: pointer to the HW structure
161 * Determines and stores the system bus information for a particular
162 * network interface. The following bus information is determined and stored:
163 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
165 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
167 struct e1000_mac_info *mac = &hw->mac;
168 struct e1000_bus_info *bus = &hw->bus;
169 u32 status = E1000_READ_REG(hw, E1000_STATUS);
170 s32 ret_val = E1000_SUCCESS;
172 DEBUGFUNC("e1000_get_bus_info_pci_generic");
175 bus->type = (status & E1000_STATUS_PCIX_MODE)
176 ? e1000_bus_type_pcix
177 : e1000_bus_type_pci;
180 if (bus->type == e1000_bus_type_pci) {
181 bus->speed = (status & E1000_STATUS_PCI66)
183 : e1000_bus_speed_33;
185 switch (status & E1000_STATUS_PCIX_SPEED) {
186 case E1000_STATUS_PCIX_SPEED_66:
187 bus->speed = e1000_bus_speed_66;
189 case E1000_STATUS_PCIX_SPEED_100:
190 bus->speed = e1000_bus_speed_100;
192 case E1000_STATUS_PCIX_SPEED_133:
193 bus->speed = e1000_bus_speed_133;
196 bus->speed = e1000_bus_speed_reserved;
202 bus->width = (status & E1000_STATUS_BUS64)
204 : e1000_bus_width_32;
206 /* Which PCI(-X) function? */
207 mac->ops.set_lan_id(hw);
213 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
214 * @hw: pointer to the HW structure
216 * Determines and stores the system bus information for a particular
217 * network interface. The following bus information is determined and stored:
218 * bus speed, bus width, type (PCIe), and PCIe function.
220 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
222 struct e1000_mac_info *mac = &hw->mac;
223 struct e1000_bus_info *bus = &hw->bus;
225 u16 pcie_link_status;
227 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
229 bus->type = e1000_bus_type_pci_express;
231 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
234 bus->width = e1000_bus_width_unknown;
235 bus->speed = e1000_bus_speed_unknown;
237 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
238 case PCIE_LINK_SPEED_2500:
239 bus->speed = e1000_bus_speed_2500;
241 case PCIE_LINK_SPEED_5000:
242 bus->speed = e1000_bus_speed_5000;
245 bus->speed = e1000_bus_speed_unknown;
249 bus->width = (enum e1000_bus_width)((pcie_link_status &
250 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
253 mac->ops.set_lan_id(hw);
255 return E1000_SUCCESS;
259 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
261 * @hw: pointer to the HW structure
263 * Determines the LAN function id by reading memory-mapped registers
264 * and swaps the port value if requested.
266 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
268 struct e1000_bus_info *bus = &hw->bus;
272 * The status register reports the correct function number
273 * for the device regardless of function swap state.
275 reg = E1000_READ_REG(hw, E1000_STATUS);
276 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
280 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
281 * @hw: pointer to the HW structure
283 * Determines the LAN function id by reading PCI config space.
285 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
287 struct e1000_bus_info *bus = &hw->bus;
291 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
292 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
293 status = E1000_READ_REG(hw, E1000_STATUS);
294 bus->func = (status & E1000_STATUS_FUNC_MASK)
295 >> E1000_STATUS_FUNC_SHIFT;
302 * e1000_set_lan_id_single_port - Set LAN id for a single port device
303 * @hw: pointer to the HW structure
305 * Sets the LAN function id to zero for a single port device.
307 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
309 struct e1000_bus_info *bus = &hw->bus;
315 * e1000_clear_vfta_generic - Clear VLAN filter table
316 * @hw: pointer to the HW structure
318 * Clears the register array which contains the VLAN filter table by
319 * setting all the values to 0.
321 void e1000_clear_vfta_generic(struct e1000_hw *hw)
325 DEBUGFUNC("e1000_clear_vfta_generic");
327 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
328 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
329 E1000_WRITE_FLUSH(hw);
334 * e1000_write_vfta_generic - Write value to VLAN filter table
335 * @hw: pointer to the HW structure
336 * @offset: register offset in VLAN filter table
337 * @value: register value written to VLAN filter table
339 * Writes value at the given offset in the register array which stores
340 * the VLAN filter table.
342 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
344 DEBUGFUNC("e1000_write_vfta_generic");
346 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
347 E1000_WRITE_FLUSH(hw);
351 * e1000_init_rx_addrs_generic - Initialize receive address's
352 * @hw: pointer to the HW structure
353 * @rar_count: receive address registers
355 * Setup the receive address registers by setting the base receive address
356 * register to the devices MAC address and clearing all the other receive
357 * address registers to 0.
359 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
362 u8 mac_addr[ETH_ADDR_LEN] = {0};
364 DEBUGFUNC("e1000_init_rx_addrs_generic");
366 /* Setup the receive address */
367 DEBUGOUT("Programming MAC Address into RAR[0]\n");
369 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
371 /* Zero out the other (rar_entry_count - 1) receive addresses */
372 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
373 for (i = 1; i < rar_count; i++)
374 hw->mac.ops.rar_set(hw, mac_addr, i);
378 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
379 * @hw: pointer to the HW structure
381 * Checks the nvm for an alternate MAC address. An alternate MAC address
382 * can be setup by pre-boot software and must be treated like a permanent
383 * address and must override the actual permanent MAC address. If an
384 * alternate MAC address is found it is programmed into RAR0, replacing
385 * the permanent address that was installed into RAR0 by the Si on reset.
386 * This function will return SUCCESS unless it encounters an error while
387 * reading the EEPROM.
389 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
392 s32 ret_val = E1000_SUCCESS;
393 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
394 u8 alt_mac_addr[ETH_ADDR_LEN];
396 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
398 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
402 if (!(nvm_data & NVM_COMPAT_LOM))
405 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
406 &nvm_alt_mac_addr_offset);
408 DEBUGOUT("NVM Read Error\n");
412 if (nvm_alt_mac_addr_offset == 0xFFFF) {
413 /* There is no Alternate MAC Address */
417 if (hw->bus.func == E1000_FUNC_1)
418 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
419 if (hw->bus.func == E1000_FUNC_2)
420 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
422 if (hw->bus.func == E1000_FUNC_3)
423 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
424 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
425 offset = nvm_alt_mac_addr_offset + (i >> 1);
426 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
428 DEBUGOUT("NVM Read Error\n");
432 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
433 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
436 /* if multicast bit is set, the alternate address will not be used */
437 if (alt_mac_addr[0] & 0x01) {
438 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
443 * We have a valid alternate MAC address, and we want to treat it the
444 * same as the normal permanent MAC address stored by the HW into the
445 * RAR. Do this by mapping this address into RAR0.
447 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
454 * e1000_rar_set_generic - Set receive address register
455 * @hw: pointer to the HW structure
456 * @addr: pointer to the receive address
457 * @index: receive address array register
459 * Sets the receive address array register at index to the address passed
462 STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
464 u32 rar_low, rar_high;
466 DEBUGFUNC("e1000_rar_set_generic");
469 * HW expects these in little endian so we reverse the byte order
470 * from network order (big endian) to little endian
472 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
473 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
475 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
477 /* If MAC address zero, no need to set the AV bit */
478 if (rar_low || rar_high)
479 rar_high |= E1000_RAH_AV;
482 * Some bridges will combine consecutive 32-bit writes into
483 * a single burst write, which will malfunction on some parts.
484 * The flushes avoid this.
486 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
487 E1000_WRITE_FLUSH(hw);
488 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
489 E1000_WRITE_FLUSH(hw);
493 * e1000_update_mc_addr_list_generic - Update Multicast addresses
494 * @hw: pointer to the HW structure
495 * @mc_addr_list: array of multicast addresses to program
496 * @mc_addr_count: number of multicast addresses to program
498 * Updates entire Multicast Table Array.
499 * The caller must have a packed mc_addr_list of multicast addresses.
501 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
502 u8 *mc_addr_list, u32 mc_addr_count)
504 u32 hash_value, hash_bit, hash_reg;
507 DEBUGFUNC("e1000_update_mc_addr_list_generic");
509 /* clear mta_shadow */
510 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
512 /* update mta_shadow from mc_addr_list */
513 for (i = 0; (u32) i < mc_addr_count; i++) {
514 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
516 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
517 hash_bit = hash_value & 0x1F;
519 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
520 mc_addr_list += (ETH_ADDR_LEN);
523 /* replace the entire MTA table */
524 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
525 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
526 E1000_WRITE_FLUSH(hw);
530 * e1000_hash_mc_addr_generic - Generate a multicast hash value
531 * @hw: pointer to the HW structure
532 * @mc_addr: pointer to a multicast address
534 * Generates a multicast address hash value which is used to determine
535 * the multicast filter table array address and new table value.
537 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
539 u32 hash_value, hash_mask;
542 DEBUGFUNC("e1000_hash_mc_addr_generic");
544 /* Register count multiplied by bits per register */
545 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
548 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
549 * where 0xFF would still fall within the hash mask.
551 while (hash_mask >> bit_shift != 0xFF)
555 * The portion of the address that is used for the hash table
556 * is determined by the mc_filter_type setting.
557 * The algorithm is such that there is a total of 8 bits of shifting.
558 * The bit_shift for a mc_filter_type of 0 represents the number of
559 * left-shifts where the MSB of mc_addr[5] would still fall within
560 * the hash_mask. Case 0 does this exactly. Since there are a total
561 * of 8 bits of shifting, then mc_addr[4] will shift right the
562 * remaining number of bits. Thus 8 - bit_shift. The rest of the
563 * cases are a variation of this algorithm...essentially raising the
564 * number of bits to shift mc_addr[5] left, while still keeping the
565 * 8-bit shifting total.
567 * For example, given the following Destination MAC Address and an
568 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
569 * we can see that the bit_shift for case 0 is 4. These are the hash
570 * values resulting from each mc_filter_type...
571 * [0] [1] [2] [3] [4] [5]
575 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
576 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
577 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
578 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
580 switch (hw->mac.mc_filter_type) {
595 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
596 (((u16) mc_addr[5]) << bit_shift)));
602 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
603 * @hw: pointer to the HW structure
605 * In certain situations, a system BIOS may report that the PCIx maximum
606 * memory read byte count (MMRBC) value is higher than than the actual
607 * value. We check the PCIx command register with the current PCIx status
610 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
614 u16 pcix_stat_hi_word;
617 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
619 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
620 if (hw->bus.type != e1000_bus_type_pcix)
623 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
624 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
625 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
626 PCIX_COMMAND_MMRBC_SHIFT;
627 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
628 PCIX_STATUS_HI_MMRBC_SHIFT;
629 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
630 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
631 if (cmd_mmrbc > stat_mmrbc) {
632 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
633 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
634 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
639 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
640 * @hw: pointer to the HW structure
642 * Clears the base hardware counters by reading the counter registers.
644 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
646 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
648 E1000_READ_REG(hw, E1000_CRCERRS);
649 E1000_READ_REG(hw, E1000_SYMERRS);
650 E1000_READ_REG(hw, E1000_MPC);
651 E1000_READ_REG(hw, E1000_SCC);
652 E1000_READ_REG(hw, E1000_ECOL);
653 E1000_READ_REG(hw, E1000_MCC);
654 E1000_READ_REG(hw, E1000_LATECOL);
655 E1000_READ_REG(hw, E1000_COLC);
656 E1000_READ_REG(hw, E1000_DC);
657 E1000_READ_REG(hw, E1000_SEC);
658 E1000_READ_REG(hw, E1000_RLEC);
659 E1000_READ_REG(hw, E1000_XONRXC);
660 E1000_READ_REG(hw, E1000_XONTXC);
661 E1000_READ_REG(hw, E1000_XOFFRXC);
662 E1000_READ_REG(hw, E1000_XOFFTXC);
663 E1000_READ_REG(hw, E1000_FCRUC);
664 E1000_READ_REG(hw, E1000_GPRC);
665 E1000_READ_REG(hw, E1000_BPRC);
666 E1000_READ_REG(hw, E1000_MPRC);
667 E1000_READ_REG(hw, E1000_GPTC);
668 E1000_READ_REG(hw, E1000_GORCL);
669 E1000_READ_REG(hw, E1000_GORCH);
670 E1000_READ_REG(hw, E1000_GOTCL);
671 E1000_READ_REG(hw, E1000_GOTCH);
672 E1000_READ_REG(hw, E1000_RNBC);
673 E1000_READ_REG(hw, E1000_RUC);
674 E1000_READ_REG(hw, E1000_RFC);
675 E1000_READ_REG(hw, E1000_ROC);
676 E1000_READ_REG(hw, E1000_RJC);
677 E1000_READ_REG(hw, E1000_TORL);
678 E1000_READ_REG(hw, E1000_TORH);
679 E1000_READ_REG(hw, E1000_TOTL);
680 E1000_READ_REG(hw, E1000_TOTH);
681 E1000_READ_REG(hw, E1000_TPR);
682 E1000_READ_REG(hw, E1000_TPT);
683 E1000_READ_REG(hw, E1000_MPTC);
684 E1000_READ_REG(hw, E1000_BPTC);
688 * e1000_check_for_copper_link_generic - Check for link (Copper)
689 * @hw: pointer to the HW structure
691 * Checks to see of the link status of the hardware has changed. If a
692 * change in link status has been detected, then we read the PHY registers
693 * to get the current speed/duplex if link exists.
695 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
697 struct e1000_mac_info *mac = &hw->mac;
701 DEBUGFUNC("e1000_check_for_copper_link");
704 * We only want to go out to the PHY registers to see if Auto-Neg
705 * has completed and/or if our link status has changed. The
706 * get_link_status flag is set upon receiving a Link Status
707 * Change or Rx Sequence Error interrupt.
709 if (!mac->get_link_status) {
710 ret_val = E1000_SUCCESS;
715 * First we want to see if the MII Status Register reports
716 * link. If so, then we want to get the current speed/duplex
719 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
724 goto out; /* No link detected */
726 mac->get_link_status = false;
729 * Check if there was DownShift, must be checked
730 * immediately after link-up
732 e1000_check_downshift_generic(hw);
735 * If we are forcing speed/duplex, then we simply return since
736 * we have already determined whether we have link or not.
739 ret_val = -E1000_ERR_CONFIG;
744 * Auto-Neg is enabled. Auto Speed Detection takes care
745 * of MAC speed/duplex configuration. So we only need to
746 * configure Collision Distance in the MAC.
748 mac->ops.config_collision_dist(hw);
751 * Configure Flow Control now that Auto-Neg has completed.
752 * First, we need to restore the desired flow control
753 * settings because we may have had to re-autoneg with a
754 * different link partner.
756 ret_val = e1000_config_fc_after_link_up_generic(hw);
758 DEBUGOUT("Error configuring flow control\n");
765 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
766 * @hw: pointer to the HW structure
768 * Checks for link up on the hardware. If link is not up and we have
769 * a signal, then we need to force link up.
771 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
773 struct e1000_mac_info *mac = &hw->mac;
777 s32 ret_val = E1000_SUCCESS;
779 DEBUGFUNC("e1000_check_for_fiber_link_generic");
781 ctrl = E1000_READ_REG(hw, E1000_CTRL);
782 status = E1000_READ_REG(hw, E1000_STATUS);
783 rxcw = E1000_READ_REG(hw, E1000_RXCW);
786 * If we don't have link (auto-negotiation failed or link partner
787 * cannot auto-negotiate), the cable is plugged in (we have signal),
788 * and our link partner is not trying to auto-negotiate with us (we
789 * are receiving idles or data), we need to force link up. We also
790 * need to give auto-negotiation time to complete, in case the cable
791 * was just plugged in. The autoneg_failed flag does this.
793 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
794 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
795 (!(rxcw & E1000_RXCW_C))) {
796 if (mac->autoneg_failed == 0) {
797 mac->autoneg_failed = 1;
800 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
802 /* Disable auto-negotiation in the TXCW register */
803 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
805 /* Force link-up and also force full-duplex. */
806 ctrl = E1000_READ_REG(hw, E1000_CTRL);
807 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
808 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
810 /* Configure Flow Control after forcing link up. */
811 ret_val = e1000_config_fc_after_link_up_generic(hw);
813 DEBUGOUT("Error configuring flow control\n");
816 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
818 * If we are forcing link and we are receiving /C/ ordered
819 * sets, re-enable auto-negotiation in the TXCW register
820 * and disable forced link in the Device Control register
821 * in an attempt to auto-negotiate with our link partner.
823 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
824 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
825 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
827 mac->serdes_has_link = true;
835 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
836 * @hw: pointer to the HW structure
838 * Checks for link up on the hardware. If link is not up and we have
839 * a signal, then we need to force link up.
841 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
843 struct e1000_mac_info *mac = &hw->mac;
847 s32 ret_val = E1000_SUCCESS;
849 DEBUGFUNC("e1000_check_for_serdes_link_generic");
851 ctrl = E1000_READ_REG(hw, E1000_CTRL);
852 status = E1000_READ_REG(hw, E1000_STATUS);
853 rxcw = E1000_READ_REG(hw, E1000_RXCW);
856 * If we don't have link (auto-negotiation failed or link partner
857 * cannot auto-negotiate), and our link partner is not trying to
858 * auto-negotiate with us (we are receiving idles or data),
859 * we need to force link up. We also need to give auto-negotiation
862 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
863 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
864 if (mac->autoneg_failed == 0) {
865 mac->autoneg_failed = 1;
868 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
870 /* Disable auto-negotiation in the TXCW register */
871 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
873 /* Force link-up and also force full-duplex. */
874 ctrl = E1000_READ_REG(hw, E1000_CTRL);
875 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
876 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
878 /* Configure Flow Control after forcing link up. */
879 ret_val = e1000_config_fc_after_link_up_generic(hw);
881 DEBUGOUT("Error configuring flow control\n");
884 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
886 * If we are forcing link and we are receiving /C/ ordered
887 * sets, re-enable auto-negotiation in the TXCW register
888 * and disable forced link in the Device Control register
889 * in an attempt to auto-negotiate with our link partner.
891 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
892 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
893 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
895 mac->serdes_has_link = true;
896 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
898 * If we force link for non-auto-negotiation switch, check
899 * link status based on MAC synchronization for internal
902 /* SYNCH bit and IV bit are sticky. */
904 rxcw = E1000_READ_REG(hw, E1000_RXCW);
905 if (rxcw & E1000_RXCW_SYNCH) {
906 if (!(rxcw & E1000_RXCW_IV)) {
907 mac->serdes_has_link = true;
908 DEBUGOUT("SERDES: Link up - forced.\n");
911 mac->serdes_has_link = false;
912 DEBUGOUT("SERDES: Link down - force failed.\n");
916 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
917 status = E1000_READ_REG(hw, E1000_STATUS);
918 if (status & E1000_STATUS_LU) {
919 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
921 rxcw = E1000_READ_REG(hw, E1000_RXCW);
922 if (rxcw & E1000_RXCW_SYNCH) {
923 if (!(rxcw & E1000_RXCW_IV)) {
924 mac->serdes_has_link = TRUE;
925 DEBUGOUT("SERDES: Link up - autoneg "
926 "completed sucessfully.\n");
928 mac->serdes_has_link = FALSE;
929 DEBUGOUT("SERDES: Link down - invalid"
930 "codewords detected in autoneg.\n");
933 mac->serdes_has_link = FALSE;
934 DEBUGOUT("SERDES: Link down - no sync.\n");
937 mac->serdes_has_link = FALSE;
938 DEBUGOUT("SERDES: Link down - autoneg failed\n");
947 * e1000_setup_link_generic - Setup flow control and link settings
948 * @hw: pointer to the HW structure
950 * Determines which flow control settings to use, then configures flow
951 * control. Calls the appropriate media-specific link configuration
952 * function. Assuming the adapter has a valid link partner, a valid link
953 * should be established. Assumes the hardware has previously been reset
954 * and the transmitter and receiver are not enabled.
956 s32 e1000_setup_link_generic(struct e1000_hw *hw)
958 s32 ret_val = E1000_SUCCESS;
960 DEBUGFUNC("e1000_setup_link_generic");
963 * In the case of the phy reset being blocked, we already have a link.
964 * We do not need to set it up again.
966 if (e1000_check_reset_block(hw))
970 * If requested flow control is set to default, set flow control
971 * based on the EEPROM flow control settings.
973 if (hw->fc.requested_mode == e1000_fc_default) {
974 ret_val = e1000_set_default_fc_generic(hw);
980 * Save off the requested flow control mode for use later. Depending
981 * on the link partner's capabilities, we may or may not use this mode.
983 hw->fc.current_mode = hw->fc.requested_mode;
985 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
986 hw->fc.current_mode);
988 /* Call the necessary media_type subroutine to configure the link. */
989 ret_val = hw->mac.ops.setup_physical_interface(hw);
994 * Initialize the flow control address, type, and PAUSE timer
995 * registers to their default values. This is done even if flow
996 * control is disabled, because it does not hurt anything to
997 * initialize these registers.
999 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1000 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1001 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1002 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1004 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1006 ret_val = e1000_set_fc_watermarks_generic(hw);
1013 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1014 * @hw: pointer to the HW structure
1016 * Configures collision distance and flow control for fiber and serdes
1017 * links. Upon successful setup, poll for link.
1019 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1021 struct e1000_mac_info *mac = &hw->mac;
1023 s32 ret_val = E1000_SUCCESS;
1025 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1027 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1029 /* Take the link out of reset */
1030 ctrl &= ~E1000_CTRL_LRST;
1032 mac->ops.config_collision_dist(hw);
1034 ret_val = e1000_commit_fc_settings_generic(hw);
1039 * Since auto-negotiation is enabled, take the link out of reset (the
1040 * link will be in reset, because we previously reset the chip). This
1041 * will restart auto-negotiation. If auto-negotiation is successful
1042 * then the link-up status bit will be set and the flow control enable
1043 * bits (RFCE and TFCE) will be set according to their negotiated value.
1045 DEBUGOUT("Auto-negotiation enabled\n");
1047 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1048 E1000_WRITE_FLUSH(hw);
1052 * For these adapters, the SW definable pin 1 is set when the optics
1053 * detect a signal. If we have a signal, then poll for a "Link-Up"
1056 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1057 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1058 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1060 DEBUGOUT("No signal detected\n");
1068 * e1000_config_collision_dist_generic - Configure collision distance
1069 * @hw: pointer to the HW structure
1071 * Configures the collision distance to the default value and is used
1072 * during link setup.
1074 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1078 DEBUGFUNC("e1000_config_collision_dist_generic");
1080 tctl = E1000_READ_REG(hw, E1000_TCTL);
1082 tctl &= ~E1000_TCTL_COLD;
1083 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1085 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1086 E1000_WRITE_FLUSH(hw);
1090 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1091 * @hw: pointer to the HW structure
1093 * Polls for link up by reading the status register, if link fails to come
1094 * up with auto-negotiation, then the link is forced if a signal is detected.
1096 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1098 struct e1000_mac_info *mac = &hw->mac;
1100 s32 ret_val = E1000_SUCCESS;
1102 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1105 * If we have a signal (the cable is plugged in, or assumed true for
1106 * serdes media) then poll for a "Link-Up" indication in the Device
1107 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1108 * seconds (Auto-negotiation should complete in less than 500
1109 * milliseconds even if the other end is doing it in SW).
1111 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1113 status = E1000_READ_REG(hw, E1000_STATUS);
1114 if (status & E1000_STATUS_LU)
1117 if (i == FIBER_LINK_UP_LIMIT) {
1118 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1119 mac->autoneg_failed = 1;
1121 * AutoNeg failed to achieve a link, so we'll call
1122 * mac->check_for_link. This routine will force the
1123 * link up if we detect a signal. This will allow us to
1124 * communicate with non-autonegotiating link partners.
1126 ret_val = mac->ops.check_for_link(hw);
1128 DEBUGOUT("Error while checking for link\n");
1131 mac->autoneg_failed = 0;
1133 mac->autoneg_failed = 0;
1134 DEBUGOUT("Valid Link Found\n");
1142 * e1000_commit_fc_settings_generic - Configure flow control
1143 * @hw: pointer to the HW structure
1145 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1146 * base on the flow control settings in e1000_mac_info.
1148 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1150 struct e1000_mac_info *mac = &hw->mac;
1152 s32 ret_val = E1000_SUCCESS;
1154 DEBUGFUNC("e1000_commit_fc_settings_generic");
1157 * Check for a software override of the flow control settings, and
1158 * setup the device accordingly. If auto-negotiation is enabled, then
1159 * software will have to set the "PAUSE" bits to the correct value in
1160 * the Transmit Config Word Register (TXCW) and re-start auto-
1161 * negotiation. However, if auto-negotiation is disabled, then
1162 * software will have to manually configure the two flow control enable
1163 * bits in the CTRL register.
1165 * The possible values of the "fc" parameter are:
1166 * 0: Flow control is completely disabled
1167 * 1: Rx flow control is enabled (we can receive pause frames,
1168 * but not send pause frames).
1169 * 2: Tx flow control is enabled (we can send pause frames but we
1170 * do not support receiving pause frames).
1171 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1173 switch (hw->fc.current_mode) {
1175 /* Flow control completely disabled by a software over-ride. */
1176 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1178 case e1000_fc_rx_pause:
1180 * Rx Flow control is enabled and Tx Flow control is disabled
1181 * by a software over-ride. Since there really isn't a way to
1182 * advertise that we are capable of Rx Pause ONLY, we will
1183 * advertise that we support both symmetric and asymmetric Rx
1184 * PAUSE. Later, we will disable the adapter's ability to send
1187 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1189 case e1000_fc_tx_pause:
1191 * Tx Flow control is enabled, and Rx Flow control is disabled,
1192 * by a software over-ride.
1194 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1198 * Flow control (both Rx and Tx) is enabled by a software
1201 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1204 DEBUGOUT("Flow control param set incorrectly\n");
1205 ret_val = -E1000_ERR_CONFIG;
1210 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1218 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1219 * @hw: pointer to the HW structure
1221 * Sets the flow control high/low threshold (watermark) registers. If
1222 * flow control XON frame transmission is enabled, then set XON frame
1223 * transmission as well.
1225 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1227 u32 fcrtl = 0, fcrth = 0;
1229 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1232 * Set the flow control receive threshold registers. Normally,
1233 * these registers will be set to a default threshold that may be
1234 * adjusted later by the driver's runtime code. However, if the
1235 * ability to transmit pause frames is not enabled, then these
1236 * registers will be set to 0.
1238 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1240 * We need to set up the Receive Threshold high and low water
1241 * marks as well as (optionally) enabling the transmission of
1244 fcrtl = hw->fc.low_water;
1245 if (hw->fc.send_xon)
1246 fcrtl |= E1000_FCRTL_XONE;
1248 fcrth = hw->fc.high_water;
1250 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1251 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1253 return E1000_SUCCESS;
1257 * e1000_set_default_fc_generic - Set flow control default values
1258 * @hw: pointer to the HW structure
1260 * Read the EEPROM for the default values for flow control and store the
1263 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1265 s32 ret_val = E1000_SUCCESS;
1268 DEBUGFUNC("e1000_set_default_fc_generic");
1271 * Read and store word 0x0F of the EEPROM. This word contains bits
1272 * that determine the hardware's default PAUSE (flow control) mode,
1273 * a bit that determines whether the HW defaults to enabling or
1274 * disabling auto-negotiation, and the direction of the
1275 * SW defined pins. If there is no SW over-ride of the flow
1276 * control setting, then the variable hw->fc will
1277 * be initialized based on a value in the EEPROM.
1279 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1282 DEBUGOUT("NVM Read Error\n");
1286 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1287 hw->fc.requested_mode = e1000_fc_none;
1288 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1290 hw->fc.requested_mode = e1000_fc_tx_pause;
1292 hw->fc.requested_mode = e1000_fc_full;
1299 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1300 * @hw: pointer to the HW structure
1302 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1303 * device control register to reflect the adapter settings. TFCE and RFCE
1304 * need to be explicitly set by software when a copper PHY is used because
1305 * autonegotiation is managed by the PHY rather than the MAC. Software must
1306 * also configure these bits when link is forced on a fiber connection.
1308 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1311 s32 ret_val = E1000_SUCCESS;
1313 DEBUGFUNC("e1000_force_mac_fc_generic");
1315 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1318 * Because we didn't get link via the internal auto-negotiation
1319 * mechanism (we either forced link or we got link via PHY
1320 * auto-neg), we have to manually enable/disable transmit an
1321 * receive flow control.
1323 * The "Case" statement below enables/disable flow control
1324 * according to the "hw->fc.current_mode" parameter.
1326 * The possible values of the "fc" parameter are:
1327 * 0: Flow control is completely disabled
1328 * 1: Rx flow control is enabled (we can receive pause
1329 * frames but not send pause frames).
1330 * 2: Tx flow control is enabled (we can send pause frames
1331 * frames but we do not receive pause frames).
1332 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1333 * other: No other values should be possible at this point.
1335 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1337 switch (hw->fc.current_mode) {
1339 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1341 case e1000_fc_rx_pause:
1342 ctrl &= (~E1000_CTRL_TFCE);
1343 ctrl |= E1000_CTRL_RFCE;
1345 case e1000_fc_tx_pause:
1346 ctrl &= (~E1000_CTRL_RFCE);
1347 ctrl |= E1000_CTRL_TFCE;
1350 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1353 DEBUGOUT("Flow control param set incorrectly\n");
1354 ret_val = -E1000_ERR_CONFIG;
1358 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1365 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1366 * @hw: pointer to the HW structure
1368 * Checks the status of auto-negotiation after link up to ensure that the
1369 * speed and duplex were not forced. If the link needed to be forced, then
1370 * flow control needs to be forced also. If auto-negotiation is enabled
1371 * and did not fail, then we configure flow control based on our link
1374 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1376 struct e1000_mac_info *mac = &hw->mac;
1377 s32 ret_val = E1000_SUCCESS;
1378 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1381 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1384 * Check for the case where we have fiber media and auto-neg failed
1385 * so we had to force link. In this case, we need to force the
1386 * configuration of the MAC to match the "fc" parameter.
1388 if (mac->autoneg_failed) {
1389 if (hw->phy.media_type == e1000_media_type_fiber ||
1390 hw->phy.media_type == e1000_media_type_internal_serdes)
1391 ret_val = e1000_force_mac_fc_generic(hw);
1393 if (hw->phy.media_type == e1000_media_type_copper)
1394 ret_val = e1000_force_mac_fc_generic(hw);
1398 DEBUGOUT("Error forcing flow control settings\n");
1403 * Check for the case where we have copper media and auto-neg is
1404 * enabled. In this case, we need to check and see if Auto-Neg
1405 * has completed, and if so, how the PHY and link partner has
1406 * flow control configured.
1408 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1410 * Read the MII Status Register and check to see if AutoNeg
1411 * has completed. We read this twice because this reg has
1412 * some "sticky" (latched) bits.
1414 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1417 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1421 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1422 DEBUGOUT("Copper PHY and Auto Neg "
1423 "has not completed.\n");
1428 * The AutoNeg process has completed, so we now need to
1429 * read both the Auto Negotiation Advertisement
1430 * Register (Address 4) and the Auto_Negotiation Base
1431 * Page Ability Register (Address 5) to determine how
1432 * flow control was negotiated.
1434 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1438 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1439 &mii_nway_lp_ability_reg);
1444 * Two bits in the Auto Negotiation Advertisement Register
1445 * (Address 4) and two bits in the Auto Negotiation Base
1446 * Page Ability Register (Address 5) determine flow control
1447 * for both the PHY and the link partner. The following
1448 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1449 * 1999, describes these PAUSE resolution bits and how flow
1450 * control is determined based upon these settings.
1451 * NOTE: DC = Don't Care
1453 * LOCAL DEVICE | LINK PARTNER
1454 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1455 *-------|---------|-------|---------|--------------------
1456 * 0 | 0 | DC | DC | e1000_fc_none
1457 * 0 | 1 | 0 | DC | e1000_fc_none
1458 * 0 | 1 | 1 | 0 | e1000_fc_none
1459 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1460 * 1 | 0 | 0 | DC | e1000_fc_none
1461 * 1 | DC | 1 | DC | e1000_fc_full
1462 * 1 | 1 | 0 | 0 | e1000_fc_none
1463 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1465 * Are both PAUSE bits set to 1? If so, this implies
1466 * Symmetric Flow Control is enabled at both ends. The
1467 * ASM_DIR bits are irrelevant per the spec.
1469 * For Symmetric Flow Control:
1471 * LOCAL DEVICE | LINK PARTNER
1472 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1473 *-------|---------|-------|---------|--------------------
1474 * 1 | DC | 1 | DC | E1000_fc_full
1477 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1478 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1480 * Now we need to check if the user selected Rx ONLY
1481 * of pause frames. In this case, we had to advertise
1482 * FULL flow control because we could not advertise Rx
1483 * ONLY. Hence, we must now check to see if we need to
1484 * turn OFF the TRANSMISSION of PAUSE frames.
1486 if (hw->fc.requested_mode == e1000_fc_full) {
1487 hw->fc.current_mode = e1000_fc_full;
1488 DEBUGOUT("Flow Control = FULL.\n");
1490 hw->fc.current_mode = e1000_fc_rx_pause;
1491 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1495 * For receiving PAUSE frames ONLY.
1497 * LOCAL DEVICE | LINK PARTNER
1498 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1499 *-------|---------|-------|---------|--------------------
1500 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1502 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1503 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1504 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1505 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1506 hw->fc.current_mode = e1000_fc_tx_pause;
1507 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1510 * For transmitting PAUSE frames ONLY.
1512 * LOCAL DEVICE | LINK PARTNER
1513 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1514 *-------|---------|-------|---------|--------------------
1515 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1517 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1518 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1519 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1520 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1521 hw->fc.current_mode = e1000_fc_rx_pause;
1522 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1525 * Per the IEEE spec, at this point flow control
1526 * should be disabled.
1528 hw->fc.current_mode = e1000_fc_none;
1529 DEBUGOUT("Flow Control = NONE.\n");
1533 * Now we need to do one last check... If we auto-
1534 * negotiated to HALF DUPLEX, flow control should not be
1535 * enabled per IEEE 802.3 spec.
1537 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1539 DEBUGOUT("Error getting link speed and duplex\n");
1543 if (duplex == HALF_DUPLEX)
1544 hw->fc.current_mode = e1000_fc_none;
1547 * Now we call a subroutine to actually force the MAC
1548 * controller to use the correct flow control settings.
1550 ret_val = e1000_force_mac_fc_generic(hw);
1552 DEBUGOUT("Error forcing flow control settings\n");
1562 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1563 * @hw: pointer to the HW structure
1564 * @speed: stores the current speed
1565 * @duplex: stores the current duplex
1567 * Read the status register for the current speed/duplex and store the current
1568 * speed and duplex for copper connections.
1570 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1575 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1577 status = E1000_READ_REG(hw, E1000_STATUS);
1578 if (status & E1000_STATUS_SPEED_1000) {
1579 *speed = SPEED_1000;
1580 DEBUGOUT("1000 Mbs, ");
1581 } else if (status & E1000_STATUS_SPEED_100) {
1583 DEBUGOUT("100 Mbs, ");
1586 DEBUGOUT("10 Mbs, ");
1589 if (status & E1000_STATUS_FD) {
1590 *duplex = FULL_DUPLEX;
1591 DEBUGOUT("Full Duplex\n");
1593 *duplex = HALF_DUPLEX;
1594 DEBUGOUT("Half Duplex\n");
1597 return E1000_SUCCESS;
1601 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1602 * @hw: pointer to the HW structure
1603 * @speed: stores the current speed
1604 * @duplex: stores the current duplex
1606 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1607 * for fiber/serdes links.
1609 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1610 u16 *speed, u16 *duplex)
1612 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1614 *speed = SPEED_1000;
1615 *duplex = FULL_DUPLEX;
1617 return E1000_SUCCESS;
1621 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1622 * @hw: pointer to the HW structure
1624 * Acquire the HW semaphore to access the PHY or NVM
1626 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1629 s32 ret_val = E1000_SUCCESS;
1630 s32 timeout = hw->nvm.word_size + 1;
1633 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1635 /* Get the SW semaphore */
1636 while (i < timeout) {
1637 swsm = E1000_READ_REG(hw, E1000_SWSM);
1638 if (!(swsm & E1000_SWSM_SMBI))
1646 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1647 ret_val = -E1000_ERR_NVM;
1651 /* Get the FW semaphore. */
1652 for (i = 0; i < timeout; i++) {
1653 swsm = E1000_READ_REG(hw, E1000_SWSM);
1654 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1656 /* Semaphore acquired if bit latched */
1657 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1664 /* Release semaphores */
1665 e1000_put_hw_semaphore_generic(hw);
1666 DEBUGOUT("Driver can't access the NVM\n");
1667 ret_val = -E1000_ERR_NVM;
1676 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1677 * @hw: pointer to the HW structure
1679 * Release hardware semaphore used to access the PHY or NVM
1681 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1685 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1687 swsm = E1000_READ_REG(hw, E1000_SWSM);
1689 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1691 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1695 * e1000_get_auto_rd_done_generic - Check for auto read completion
1696 * @hw: pointer to the HW structure
1698 * Check EEPROM for Auto Read done bit.
1700 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1703 s32 ret_val = E1000_SUCCESS;
1705 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1707 while (i < AUTO_READ_DONE_TIMEOUT) {
1708 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1714 if (i == AUTO_READ_DONE_TIMEOUT) {
1715 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1716 ret_val = -E1000_ERR_RESET;
1725 * e1000_valid_led_default_generic - Verify a valid default LED config
1726 * @hw: pointer to the HW structure
1727 * @data: pointer to the NVM (EEPROM)
1729 * Read the EEPROM for the current default LED configuration. If the
1730 * LED configuration is not valid, set to a valid LED configuration.
1732 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1736 DEBUGFUNC("e1000_valid_led_default_generic");
1738 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1740 DEBUGOUT("NVM Read Error\n");
1744 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1745 *data = ID_LED_DEFAULT;
1752 * e1000_id_led_init_generic -
1753 * @hw: pointer to the HW structure
1756 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1758 struct e1000_mac_info *mac = &hw->mac;
1760 const u32 ledctl_mask = 0x000000FF;
1761 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1762 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1764 const u16 led_mask = 0x0F;
1766 DEBUGFUNC("e1000_id_led_init_generic");
1768 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1772 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1773 mac->ledctl_mode1 = mac->ledctl_default;
1774 mac->ledctl_mode2 = mac->ledctl_default;
1776 for (i = 0; i < 4; i++) {
1777 temp = (data >> (i << 2)) & led_mask;
1779 case ID_LED_ON1_DEF2:
1780 case ID_LED_ON1_ON2:
1781 case ID_LED_ON1_OFF2:
1782 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1783 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1785 case ID_LED_OFF1_DEF2:
1786 case ID_LED_OFF1_ON2:
1787 case ID_LED_OFF1_OFF2:
1788 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1789 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1796 case ID_LED_DEF1_ON2:
1797 case ID_LED_ON1_ON2:
1798 case ID_LED_OFF1_ON2:
1799 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1800 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1802 case ID_LED_DEF1_OFF2:
1803 case ID_LED_ON1_OFF2:
1804 case ID_LED_OFF1_OFF2:
1805 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1806 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1819 * e1000_setup_led_generic - Configures SW controllable LED
1820 * @hw: pointer to the HW structure
1822 * This prepares the SW controllable LED for use and saves the current state
1823 * of the LED so it can be later restored.
1825 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1828 s32 ret_val = E1000_SUCCESS;
1830 DEBUGFUNC("e1000_setup_led_generic");
1832 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1833 ret_val = -E1000_ERR_CONFIG;
1837 if (hw->phy.media_type == e1000_media_type_fiber) {
1838 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1839 hw->mac.ledctl_default = ledctl;
1841 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1842 E1000_LEDCTL_LED0_MODE_MASK);
1843 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1844 E1000_LEDCTL_LED0_MODE_SHIFT);
1845 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1846 } else if (hw->phy.media_type == e1000_media_type_copper) {
1847 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1855 * e1000_cleanup_led_generic - Set LED config to default operation
1856 * @hw: pointer to the HW structure
1858 * Remove the current LED configuration and set the LED configuration
1859 * to the default value, saved from the EEPROM.
1861 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1863 DEBUGFUNC("e1000_cleanup_led_generic");
1865 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1866 return E1000_SUCCESS;
1870 * e1000_blink_led_generic - Blink LED
1871 * @hw: pointer to the HW structure
1873 * Blink the LEDs which are set to be on.
1875 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1877 u32 ledctl_blink = 0;
1880 DEBUGFUNC("e1000_blink_led_generic");
1882 if (hw->phy.media_type == e1000_media_type_fiber) {
1883 /* always blink LED0 for PCI-E fiber */
1884 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1885 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1888 * set the blink bit for each LED that's "on" (0x0E)
1891 ledctl_blink = hw->mac.ledctl_mode2;
1892 for (i = 0; i < 4; i++)
1893 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1894 E1000_LEDCTL_MODE_LED_ON)
1895 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1899 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1901 return E1000_SUCCESS;
1905 * e1000_led_on_generic - Turn LED on
1906 * @hw: pointer to the HW structure
1910 s32 e1000_led_on_generic(struct e1000_hw *hw)
1914 DEBUGFUNC("e1000_led_on_generic");
1916 switch (hw->phy.media_type) {
1917 case e1000_media_type_fiber:
1918 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1919 ctrl &= ~E1000_CTRL_SWDPIN0;
1920 ctrl |= E1000_CTRL_SWDPIO0;
1921 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1923 case e1000_media_type_copper:
1924 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1930 return E1000_SUCCESS;
1934 * e1000_led_off_generic - Turn LED off
1935 * @hw: pointer to the HW structure
1939 s32 e1000_led_off_generic(struct e1000_hw *hw)
1943 DEBUGFUNC("e1000_led_off_generic");
1945 switch (hw->phy.media_type) {
1946 case e1000_media_type_fiber:
1947 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1948 ctrl |= E1000_CTRL_SWDPIN0;
1949 ctrl |= E1000_CTRL_SWDPIO0;
1950 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1952 case e1000_media_type_copper:
1953 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1959 return E1000_SUCCESS;
1963 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1964 * @hw: pointer to the HW structure
1965 * @no_snoop: bitmap of snoop events
1967 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1969 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1973 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1975 if (hw->bus.type != e1000_bus_type_pci_express)
1979 gcr = E1000_READ_REG(hw, E1000_GCR);
1980 gcr &= ~(PCIE_NO_SNOOP_ALL);
1982 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1989 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1990 * @hw: pointer to the HW structure
1992 * Returns E1000_SUCCESS if successful, else returns -10
1993 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1994 * the master requests to be disabled.
1996 * Disables PCI-Express master access and verifies there are no pending
1999 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2002 s32 timeout = MASTER_DISABLE_TIMEOUT;
2003 s32 ret_val = E1000_SUCCESS;
2005 DEBUGFUNC("e1000_disable_pcie_master_generic");
2007 if (hw->bus.type != e1000_bus_type_pci_express)
2010 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2011 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2012 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2015 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2016 E1000_STATUS_GIO_MASTER_ENABLE))
2023 DEBUGOUT("Master requests are pending.\n");
2024 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2032 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2033 * @hw: pointer to the HW structure
2035 * Reset the Adaptive Interframe Spacing throttle to default values.
2037 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2039 struct e1000_mac_info *mac = &hw->mac;
2041 DEBUGFUNC("e1000_reset_adaptive_generic");
2043 if (!mac->adaptive_ifs) {
2044 DEBUGOUT("Not in Adaptive IFS mode!\n");
2048 mac->current_ifs_val = 0;
2049 mac->ifs_min_val = IFS_MIN;
2050 mac->ifs_max_val = IFS_MAX;
2051 mac->ifs_step_size = IFS_STEP;
2052 mac->ifs_ratio = IFS_RATIO;
2054 mac->in_ifs_mode = false;
2055 E1000_WRITE_REG(hw, E1000_AIT, 0);
2061 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2062 * @hw: pointer to the HW structure
2064 * Update the Adaptive Interframe Spacing Throttle value based on the
2065 * time between transmitted packets and time between collisions.
2067 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2069 struct e1000_mac_info *mac = &hw->mac;
2071 DEBUGFUNC("e1000_update_adaptive_generic");
2073 if (!mac->adaptive_ifs) {
2074 DEBUGOUT("Not in Adaptive IFS mode!\n");
2078 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2079 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2080 mac->in_ifs_mode = true;
2081 if (mac->current_ifs_val < mac->ifs_max_val) {
2082 if (!mac->current_ifs_val)
2083 mac->current_ifs_val = mac->ifs_min_val;
2085 mac->current_ifs_val +=
2087 E1000_WRITE_REG(hw, E1000_AIT,
2088 mac->current_ifs_val);
2092 if (mac->in_ifs_mode &&
2093 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2094 mac->current_ifs_val = 0;
2095 mac->in_ifs_mode = false;
2096 E1000_WRITE_REG(hw, E1000_AIT, 0);
2104 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2105 * @hw: pointer to the HW structure
2107 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2108 * set, which is forced to MDI mode only.
2110 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2112 s32 ret_val = E1000_SUCCESS;
2114 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2116 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2117 DEBUGOUT("Invalid MDI setting detected\n");
2119 ret_val = -E1000_ERR_CONFIG;
2128 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2129 * @hw: pointer to the HW structure
2130 * @reg: 32bit register offset such as E1000_SCTL
2131 * @offset: register offset to write to
2132 * @data: data to write at register offset
2134 * Writes an address/data control type register. There are several of these
2135 * and they all have the format address << 8 | data and bit 31 is polled for
2138 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2139 u32 offset, u8 data)
2141 u32 i, regvalue = 0;
2142 s32 ret_val = E1000_SUCCESS;
2144 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2146 /* Set up the address and data */
2147 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2148 E1000_WRITE_REG(hw, reg, regvalue);
2150 /* Poll the ready bit to see if the MDI read completed */
2151 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2153 regvalue = E1000_READ_REG(hw, reg);
2154 if (regvalue & E1000_GEN_CTL_READY)
2157 if (!(regvalue & E1000_GEN_CTL_READY)) {
2158 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2159 ret_val = -E1000_ERR_PHY;