1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
37 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
38 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw);
39 STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
43 * @hw: pointer to the HW structure
45 * Setups up the function pointers to no-op functions
47 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
49 struct e1000_mac_info *mac = &hw->mac;
50 DEBUGFUNC("e1000_init_mac_ops_generic");
53 mac->ops.init_params = e1000_null_ops_generic;
54 mac->ops.init_hw = e1000_null_ops_generic;
55 mac->ops.reset_hw = e1000_null_ops_generic;
56 mac->ops.setup_physical_interface = e1000_null_ops_generic;
57 mac->ops.get_bus_info = e1000_null_ops_generic;
58 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
59 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
60 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
61 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
63 mac->ops.cleanup_led = e1000_null_ops_generic;
64 mac->ops.setup_led = e1000_null_ops_generic;
65 mac->ops.blink_led = e1000_null_ops_generic;
66 mac->ops.led_on = e1000_null_ops_generic;
67 mac->ops.led_off = e1000_null_ops_generic;
69 mac->ops.setup_link = e1000_null_ops_generic;
70 mac->ops.get_link_up_info = e1000_null_link_info;
71 mac->ops.check_for_link = e1000_null_ops_generic;
72 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
74 mac->ops.check_mng_mode = e1000_null_mng_mode;
75 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
76 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
77 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
79 mac->ops.update_mc_addr_list = e1000_null_update_mc;
80 mac->ops.clear_vfta = e1000_null_mac_generic;
81 mac->ops.write_vfta = e1000_null_write_vfta;
82 mac->ops.rar_set = e1000_rar_set_generic;
83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
87 * e1000_null_ops_generic - No-op function, returns 0
88 * @hw: pointer to the HW structure
90 s32 e1000_null_ops_generic(struct e1000_hw *hw)
92 DEBUGFUNC("e1000_null_ops_generic");
97 * e1000_null_mac_generic - No-op function, return void
98 * @hw: pointer to the HW structure
100 void e1000_null_mac_generic(struct e1000_hw *hw)
102 DEBUGFUNC("e1000_null_mac_generic");
107 * e1000_null_link_info - No-op function, return 0
108 * @hw: pointer to the HW structure
110 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
112 DEBUGFUNC("e1000_null_link_info");
113 return E1000_SUCCESS;
117 * e1000_null_mng_mode - No-op function, return false
118 * @hw: pointer to the HW structure
120 bool e1000_null_mng_mode(struct e1000_hw *hw)
122 DEBUGFUNC("e1000_null_mng_mode");
127 * e1000_null_update_mc - No-op function, return void
128 * @hw: pointer to the HW structure
130 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
132 DEBUGFUNC("e1000_null_update_mc");
137 * e1000_null_write_vfta - No-op function, return void
138 * @hw: pointer to the HW structure
140 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
142 DEBUGFUNC("e1000_null_write_vfta");
147 * e1000_null_rar_set - No-op function, return void
148 * @hw: pointer to the HW structure
150 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
152 DEBUGFUNC("e1000_null_rar_set");
157 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
158 * @hw: pointer to the HW structure
160 * Determines and stores the system bus information for a particular
161 * network interface. The following bus information is determined and stored:
162 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
164 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
166 struct e1000_mac_info *mac = &hw->mac;
167 struct e1000_bus_info *bus = &hw->bus;
168 u32 status = E1000_READ_REG(hw, E1000_STATUS);
169 s32 ret_val = E1000_SUCCESS;
171 DEBUGFUNC("e1000_get_bus_info_pci_generic");
174 bus->type = (status & E1000_STATUS_PCIX_MODE)
175 ? e1000_bus_type_pcix
176 : e1000_bus_type_pci;
179 if (bus->type == e1000_bus_type_pci) {
180 bus->speed = (status & E1000_STATUS_PCI66)
182 : e1000_bus_speed_33;
184 switch (status & E1000_STATUS_PCIX_SPEED) {
185 case E1000_STATUS_PCIX_SPEED_66:
186 bus->speed = e1000_bus_speed_66;
188 case E1000_STATUS_PCIX_SPEED_100:
189 bus->speed = e1000_bus_speed_100;
191 case E1000_STATUS_PCIX_SPEED_133:
192 bus->speed = e1000_bus_speed_133;
195 bus->speed = e1000_bus_speed_reserved;
201 bus->width = (status & E1000_STATUS_BUS64)
203 : e1000_bus_width_32;
205 /* Which PCI(-X) function? */
206 mac->ops.set_lan_id(hw);
212 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
213 * @hw: pointer to the HW structure
215 * Determines and stores the system bus information for a particular
216 * network interface. The following bus information is determined and stored:
217 * bus speed, bus width, type (PCIe), and PCIe function.
219 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
221 struct e1000_mac_info *mac = &hw->mac;
222 struct e1000_bus_info *bus = &hw->bus;
224 u16 pcie_link_status;
226 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
228 bus->type = e1000_bus_type_pci_express;
230 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
233 bus->width = e1000_bus_width_unknown;
234 bus->speed = e1000_bus_speed_unknown;
236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
237 case PCIE_LINK_SPEED_2500:
238 bus->speed = e1000_bus_speed_2500;
240 case PCIE_LINK_SPEED_5000:
241 bus->speed = e1000_bus_speed_5000;
244 bus->speed = e1000_bus_speed_unknown;
248 bus->width = (enum e1000_bus_width)((pcie_link_status &
249 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
252 mac->ops.set_lan_id(hw);
254 return E1000_SUCCESS;
258 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
260 * @hw: pointer to the HW structure
262 * Determines the LAN function id by reading memory-mapped registers
263 * and swaps the port value if requested.
265 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
267 struct e1000_bus_info *bus = &hw->bus;
270 /* The status register reports the correct function number
271 * for the device regardless of function swap state.
273 reg = E1000_READ_REG(hw, E1000_STATUS);
274 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
278 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
279 * @hw: pointer to the HW structure
281 * Determines the LAN function id by reading PCI config space.
283 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
285 struct e1000_bus_info *bus = &hw->bus;
289 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
290 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
291 status = E1000_READ_REG(hw, E1000_STATUS);
292 bus->func = (status & E1000_STATUS_FUNC_MASK)
293 >> E1000_STATUS_FUNC_SHIFT;
300 * e1000_set_lan_id_single_port - Set LAN id for a single port device
301 * @hw: pointer to the HW structure
303 * Sets the LAN function id to zero for a single port device.
305 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
307 struct e1000_bus_info *bus = &hw->bus;
313 * e1000_clear_vfta_generic - Clear VLAN filter table
314 * @hw: pointer to the HW structure
316 * Clears the register array which contains the VLAN filter table by
317 * setting all the values to 0.
319 void e1000_clear_vfta_generic(struct e1000_hw *hw)
323 DEBUGFUNC("e1000_clear_vfta_generic");
325 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
326 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
327 E1000_WRITE_FLUSH(hw);
332 * e1000_write_vfta_generic - Write value to VLAN filter table
333 * @hw: pointer to the HW structure
334 * @offset: register offset in VLAN filter table
335 * @value: register value written to VLAN filter table
337 * Writes value at the given offset in the register array which stores
338 * the VLAN filter table.
340 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
342 DEBUGFUNC("e1000_write_vfta_generic");
344 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
345 E1000_WRITE_FLUSH(hw);
349 * e1000_init_rx_addrs_generic - Initialize receive address's
350 * @hw: pointer to the HW structure
351 * @rar_count: receive address registers
353 * Setup the receive address registers by setting the base receive address
354 * register to the devices MAC address and clearing all the other receive
355 * address registers to 0.
357 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
360 u8 mac_addr[ETH_ADDR_LEN] = {0};
362 DEBUGFUNC("e1000_init_rx_addrs_generic");
364 /* Setup the receive address */
365 DEBUGOUT("Programming MAC Address into RAR[0]\n");
367 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
369 /* Zero out the other (rar_entry_count - 1) receive addresses */
370 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
371 for (i = 1; i < rar_count; i++)
372 hw->mac.ops.rar_set(hw, mac_addr, i);
376 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
377 * @hw: pointer to the HW structure
379 * Checks the nvm for an alternate MAC address. An alternate MAC address
380 * can be setup by pre-boot software and must be treated like a permanent
381 * address and must override the actual permanent MAC address. If an
382 * alternate MAC address is found it is programmed into RAR0, replacing
383 * the permanent address that was installed into RAR0 by the Si on reset.
384 * This function will return SUCCESS unless it encounters an error while
385 * reading the EEPROM.
387 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
391 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
392 u8 alt_mac_addr[ETH_ADDR_LEN];
394 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
396 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
400 /* not supported on older hardware or 82573 */
401 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
402 return E1000_SUCCESS;
404 /* Alternate MAC address is handled by the option ROM for 82580
405 * and newer. SW support not required.
407 if (hw->mac.type >= e1000_82580)
408 return E1000_SUCCESS;
410 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
411 &nvm_alt_mac_addr_offset);
413 DEBUGOUT("NVM Read Error\n");
417 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
418 (nvm_alt_mac_addr_offset == 0x0000))
419 /* There is no Alternate MAC Address */
420 return E1000_SUCCESS;
422 if (hw->bus.func == E1000_FUNC_1)
423 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
424 if (hw->bus.func == E1000_FUNC_2)
425 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
427 if (hw->bus.func == E1000_FUNC_3)
428 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
429 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
430 offset = nvm_alt_mac_addr_offset + (i >> 1);
431 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
433 DEBUGOUT("NVM Read Error\n");
437 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
438 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
441 /* if multicast bit is set, the alternate address will not be used */
442 if (alt_mac_addr[0] & 0x01) {
443 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
444 return E1000_SUCCESS;
447 /* We have a valid alternate MAC address, and we want to treat it the
448 * same as the normal permanent MAC address stored by the HW into the
449 * RAR. Do this by mapping this address into RAR0.
451 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
453 return E1000_SUCCESS;
457 * e1000_rar_set_generic - Set receive address register
458 * @hw: pointer to the HW structure
459 * @addr: pointer to the receive address
460 * @index: receive address array register
462 * Sets the receive address array register at index to the address passed
465 STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
467 u32 rar_low, rar_high;
469 DEBUGFUNC("e1000_rar_set_generic");
471 /* HW expects these in little endian so we reverse the byte order
472 * from network order (big endian) to little endian
474 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
475 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
477 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
479 /* If MAC address zero, no need to set the AV bit */
480 if (rar_low || rar_high)
481 rar_high |= E1000_RAH_AV;
483 /* Some bridges will combine consecutive 32-bit writes into
484 * a single burst write, which will malfunction on some parts.
485 * The flushes avoid this.
487 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
488 E1000_WRITE_FLUSH(hw);
489 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
490 E1000_WRITE_FLUSH(hw);
494 * e1000_hash_mc_addr_generic - Generate a multicast hash value
495 * @hw: pointer to the HW structure
496 * @mc_addr: pointer to a multicast address
498 * Generates a multicast address hash value which is used to determine
499 * the multicast filter table array address and new table value.
501 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
503 u32 hash_value, hash_mask;
506 DEBUGFUNC("e1000_hash_mc_addr_generic");
508 /* Register count multiplied by bits per register */
509 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
511 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
512 * where 0xFF would still fall within the hash mask.
514 while (hash_mask >> bit_shift != 0xFF)
517 /* The portion of the address that is used for the hash table
518 * is determined by the mc_filter_type setting.
519 * The algorithm is such that there is a total of 8 bits of shifting.
520 * The bit_shift for a mc_filter_type of 0 represents the number of
521 * left-shifts where the MSB of mc_addr[5] would still fall within
522 * the hash_mask. Case 0 does this exactly. Since there are a total
523 * of 8 bits of shifting, then mc_addr[4] will shift right the
524 * remaining number of bits. Thus 8 - bit_shift. The rest of the
525 * cases are a variation of this algorithm...essentially raising the
526 * number of bits to shift mc_addr[5] left, while still keeping the
527 * 8-bit shifting total.
529 * For example, given the following Destination MAC Address and an
530 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
531 * we can see that the bit_shift for case 0 is 4. These are the hash
532 * values resulting from each mc_filter_type...
533 * [0] [1] [2] [3] [4] [5]
537 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
538 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
539 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
540 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
542 switch (hw->mac.mc_filter_type) {
557 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
558 (((u16) mc_addr[5]) << bit_shift)));
564 * e1000_update_mc_addr_list_generic - Update Multicast addresses
565 * @hw: pointer to the HW structure
566 * @mc_addr_list: array of multicast addresses to program
567 * @mc_addr_count: number of multicast addresses to program
569 * Updates entire Multicast Table Array.
570 * The caller must have a packed mc_addr_list of multicast addresses.
572 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
573 u8 *mc_addr_list, u32 mc_addr_count)
575 u32 hash_value, hash_bit, hash_reg;
578 DEBUGFUNC("e1000_update_mc_addr_list_generic");
580 /* clear mta_shadow */
581 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
583 /* update mta_shadow from mc_addr_list */
584 for (i = 0; (u32) i < mc_addr_count; i++) {
585 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
587 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
588 hash_bit = hash_value & 0x1F;
590 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
591 mc_addr_list += (ETH_ADDR_LEN);
594 /* replace the entire MTA table */
595 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
596 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
597 E1000_WRITE_FLUSH(hw);
601 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
602 * @hw: pointer to the HW structure
604 * In certain situations, a system BIOS may report that the PCIx maximum
605 * memory read byte count (MMRBC) value is higher than than the actual
606 * value. We check the PCIx command register with the current PCIx status
609 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
613 u16 pcix_stat_hi_word;
616 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
618 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
619 if (hw->bus.type != e1000_bus_type_pcix)
622 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
623 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
624 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
625 PCIX_COMMAND_MMRBC_SHIFT;
626 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
627 PCIX_STATUS_HI_MMRBC_SHIFT;
628 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
629 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
630 if (cmd_mmrbc > stat_mmrbc) {
631 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
632 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
633 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
638 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
639 * @hw: pointer to the HW structure
641 * Clears the base hardware counters by reading the counter registers.
643 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
645 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
647 E1000_READ_REG(hw, E1000_CRCERRS);
648 E1000_READ_REG(hw, E1000_SYMERRS);
649 E1000_READ_REG(hw, E1000_MPC);
650 E1000_READ_REG(hw, E1000_SCC);
651 E1000_READ_REG(hw, E1000_ECOL);
652 E1000_READ_REG(hw, E1000_MCC);
653 E1000_READ_REG(hw, E1000_LATECOL);
654 E1000_READ_REG(hw, E1000_COLC);
655 E1000_READ_REG(hw, E1000_DC);
656 E1000_READ_REG(hw, E1000_SEC);
657 E1000_READ_REG(hw, E1000_RLEC);
658 E1000_READ_REG(hw, E1000_XONRXC);
659 E1000_READ_REG(hw, E1000_XONTXC);
660 E1000_READ_REG(hw, E1000_XOFFRXC);
661 E1000_READ_REG(hw, E1000_XOFFTXC);
662 E1000_READ_REG(hw, E1000_FCRUC);
663 E1000_READ_REG(hw, E1000_GPRC);
664 E1000_READ_REG(hw, E1000_BPRC);
665 E1000_READ_REG(hw, E1000_MPRC);
666 E1000_READ_REG(hw, E1000_GPTC);
667 E1000_READ_REG(hw, E1000_GORCL);
668 E1000_READ_REG(hw, E1000_GORCH);
669 E1000_READ_REG(hw, E1000_GOTCL);
670 E1000_READ_REG(hw, E1000_GOTCH);
671 E1000_READ_REG(hw, E1000_RNBC);
672 E1000_READ_REG(hw, E1000_RUC);
673 E1000_READ_REG(hw, E1000_RFC);
674 E1000_READ_REG(hw, E1000_ROC);
675 E1000_READ_REG(hw, E1000_RJC);
676 E1000_READ_REG(hw, E1000_TORL);
677 E1000_READ_REG(hw, E1000_TORH);
678 E1000_READ_REG(hw, E1000_TOTL);
679 E1000_READ_REG(hw, E1000_TOTH);
680 E1000_READ_REG(hw, E1000_TPR);
681 E1000_READ_REG(hw, E1000_TPT);
682 E1000_READ_REG(hw, E1000_MPTC);
683 E1000_READ_REG(hw, E1000_BPTC);
687 * e1000_check_for_copper_link_generic - Check for link (Copper)
688 * @hw: pointer to the HW structure
690 * Checks to see of the link status of the hardware has changed. If a
691 * change in link status has been detected, then we read the PHY registers
692 * to get the current speed/duplex if link exists.
694 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
696 struct e1000_mac_info *mac = &hw->mac;
700 DEBUGFUNC("e1000_check_for_copper_link");
702 /* We only want to go out to the PHY registers to see if Auto-Neg
703 * has completed and/or if our link status has changed. The
704 * get_link_status flag is set upon receiving a Link Status
705 * Change or Rx Sequence Error interrupt.
707 if (!mac->get_link_status)
708 return E1000_SUCCESS;
710 /* First we want to see if the MII Status Register reports
711 * link. If so, then we want to get the current speed/duplex
714 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
719 return E1000_SUCCESS; /* No link detected */
721 mac->get_link_status = false;
723 /* Check if there was DownShift, must be checked
724 * immediately after link-up
726 e1000_check_downshift_generic(hw);
728 /* If we are forcing speed/duplex, then we simply return since
729 * we have already determined whether we have link or not.
732 return -E1000_ERR_CONFIG;
734 /* Auto-Neg is enabled. Auto Speed Detection takes care
735 * of MAC speed/duplex configuration. So we only need to
736 * configure Collision Distance in the MAC.
738 mac->ops.config_collision_dist(hw);
740 /* Configure Flow Control now that Auto-Neg has completed.
741 * First, we need to restore the desired flow control
742 * settings because we may have had to re-autoneg with a
743 * different link partner.
745 ret_val = e1000_config_fc_after_link_up_generic(hw);
747 DEBUGOUT("Error configuring flow control\n");
753 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
754 * @hw: pointer to the HW structure
756 * Checks for link up on the hardware. If link is not up and we have
757 * a signal, then we need to force link up.
759 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
761 struct e1000_mac_info *mac = &hw->mac;
767 DEBUGFUNC("e1000_check_for_fiber_link_generic");
769 ctrl = E1000_READ_REG(hw, E1000_CTRL);
770 status = E1000_READ_REG(hw, E1000_STATUS);
771 rxcw = E1000_READ_REG(hw, E1000_RXCW);
773 /* If we don't have link (auto-negotiation failed or link partner
774 * cannot auto-negotiate), the cable is plugged in (we have signal),
775 * and our link partner is not trying to auto-negotiate with us (we
776 * are receiving idles or data), we need to force link up. We also
777 * need to give auto-negotiation time to complete, in case the cable
778 * was just plugged in. The autoneg_failed flag does this.
780 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
781 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
782 !(rxcw & E1000_RXCW_C)) {
783 if (!mac->autoneg_failed) {
784 mac->autoneg_failed = true;
785 return E1000_SUCCESS;
787 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
789 /* Disable auto-negotiation in the TXCW register */
790 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
792 /* Force link-up and also force full-duplex. */
793 ctrl = E1000_READ_REG(hw, E1000_CTRL);
794 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
795 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
797 /* Configure Flow Control after forcing link up. */
798 ret_val = e1000_config_fc_after_link_up_generic(hw);
800 DEBUGOUT("Error configuring flow control\n");
803 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
804 /* If we are forcing link and we are receiving /C/ ordered
805 * sets, re-enable auto-negotiation in the TXCW register
806 * and disable forced link in the Device Control register
807 * in an attempt to auto-negotiate with our link partner.
809 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
810 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
811 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
813 mac->serdes_has_link = true;
816 return E1000_SUCCESS;
820 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
821 * @hw: pointer to the HW structure
823 * Checks for link up on the hardware. If link is not up and we have
824 * a signal, then we need to force link up.
826 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
828 struct e1000_mac_info *mac = &hw->mac;
834 DEBUGFUNC("e1000_check_for_serdes_link_generic");
836 ctrl = E1000_READ_REG(hw, E1000_CTRL);
837 status = E1000_READ_REG(hw, E1000_STATUS);
838 rxcw = E1000_READ_REG(hw, E1000_RXCW);
840 /* If we don't have link (auto-negotiation failed or link partner
841 * cannot auto-negotiate), and our link partner is not trying to
842 * auto-negotiate with us (we are receiving idles or data),
843 * we need to force link up. We also need to give auto-negotiation
846 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
847 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
848 if (!mac->autoneg_failed) {
849 mac->autoneg_failed = true;
850 return E1000_SUCCESS;
852 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
854 /* Disable auto-negotiation in the TXCW register */
855 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
857 /* Force link-up and also force full-duplex. */
858 ctrl = E1000_READ_REG(hw, E1000_CTRL);
859 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
860 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
862 /* Configure Flow Control after forcing link up. */
863 ret_val = e1000_config_fc_after_link_up_generic(hw);
865 DEBUGOUT("Error configuring flow control\n");
868 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
869 /* If we are forcing link and we are receiving /C/ ordered
870 * sets, re-enable auto-negotiation in the TXCW register
871 * and disable forced link in the Device Control register
872 * in an attempt to auto-negotiate with our link partner.
874 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
875 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
876 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
878 mac->serdes_has_link = true;
879 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
880 /* If we force link for non-auto-negotiation switch, check
881 * link status based on MAC synchronization for internal
884 /* SYNCH bit and IV bit are sticky. */
886 rxcw = E1000_READ_REG(hw, E1000_RXCW);
887 if (rxcw & E1000_RXCW_SYNCH) {
888 if (!(rxcw & E1000_RXCW_IV)) {
889 mac->serdes_has_link = true;
890 DEBUGOUT("SERDES: Link up - forced.\n");
893 mac->serdes_has_link = false;
894 DEBUGOUT("SERDES: Link down - force failed.\n");
898 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
899 status = E1000_READ_REG(hw, E1000_STATUS);
900 if (status & E1000_STATUS_LU) {
901 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
903 rxcw = E1000_READ_REG(hw, E1000_RXCW);
904 if (rxcw & E1000_RXCW_SYNCH) {
905 if (!(rxcw & E1000_RXCW_IV)) {
906 mac->serdes_has_link = true;
907 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
909 mac->serdes_has_link = false;
910 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
913 mac->serdes_has_link = false;
914 DEBUGOUT("SERDES: Link down - no sync.\n");
917 mac->serdes_has_link = false;
918 DEBUGOUT("SERDES: Link down - autoneg failed\n");
922 return E1000_SUCCESS;
926 * e1000_set_default_fc_generic - Set flow control default values
927 * @hw: pointer to the HW structure
929 * Read the EEPROM for the default values for flow control and store the
932 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
937 DEBUGFUNC("e1000_set_default_fc_generic");
939 /* Read and store word 0x0F of the EEPROM. This word contains bits
940 * that determine the hardware's default PAUSE (flow control) mode,
941 * a bit that determines whether the HW defaults to enabling or
942 * disabling auto-negotiation, and the direction of the
943 * SW defined pins. If there is no SW over-ride of the flow
944 * control setting, then the variable hw->fc will
945 * be initialized based on a value in the EEPROM.
947 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
950 DEBUGOUT("NVM Read Error\n");
954 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
955 hw->fc.requested_mode = e1000_fc_none;
956 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
958 hw->fc.requested_mode = e1000_fc_tx_pause;
960 hw->fc.requested_mode = e1000_fc_full;
962 return E1000_SUCCESS;
966 * e1000_setup_link_generic - Setup flow control and link settings
967 * @hw: pointer to the HW structure
969 * Determines which flow control settings to use, then configures flow
970 * control. Calls the appropriate media-specific link configuration
971 * function. Assuming the adapter has a valid link partner, a valid link
972 * should be established. Assumes the hardware has previously been reset
973 * and the transmitter and receiver are not enabled.
975 s32 e1000_setup_link_generic(struct e1000_hw *hw)
979 DEBUGFUNC("e1000_setup_link_generic");
981 /* In the case of the phy reset being blocked, we already have a link.
982 * We do not need to set it up again.
984 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
985 return E1000_SUCCESS;
987 /* If requested flow control is set to default, set flow control
988 * based on the EEPROM flow control settings.
990 if (hw->fc.requested_mode == e1000_fc_default) {
991 ret_val = e1000_set_default_fc_generic(hw);
996 /* Save off the requested flow control mode for use later. Depending
997 * on the link partner's capabilities, we may or may not use this mode.
999 hw->fc.current_mode = hw->fc.requested_mode;
1001 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1002 hw->fc.current_mode);
1004 /* Call the necessary media_type subroutine to configure the link. */
1005 ret_val = hw->mac.ops.setup_physical_interface(hw);
1009 /* Initialize the flow control address, type, and PAUSE timer
1010 * registers to their default values. This is done even if flow
1011 * control is disabled, because it does not hurt anything to
1012 * initialize these registers.
1014 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1015 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1016 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1017 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1019 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1021 return e1000_set_fc_watermarks_generic(hw);
1025 * e1000_commit_fc_settings_generic - Configure flow control
1026 * @hw: pointer to the HW structure
1028 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1029 * base on the flow control settings in e1000_mac_info.
1031 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1033 struct e1000_mac_info *mac = &hw->mac;
1036 DEBUGFUNC("e1000_commit_fc_settings_generic");
1038 /* Check for a software override of the flow control settings, and
1039 * setup the device accordingly. If auto-negotiation is enabled, then
1040 * software will have to set the "PAUSE" bits to the correct value in
1041 * the Transmit Config Word Register (TXCW) and re-start auto-
1042 * negotiation. However, if auto-negotiation is disabled, then
1043 * software will have to manually configure the two flow control enable
1044 * bits in the CTRL register.
1046 * The possible values of the "fc" parameter are:
1047 * 0: Flow control is completely disabled
1048 * 1: Rx flow control is enabled (we can receive pause frames,
1049 * but not send pause frames).
1050 * 2: Tx flow control is enabled (we can send pause frames but we
1051 * do not support receiving pause frames).
1052 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1054 switch (hw->fc.current_mode) {
1056 /* Flow control completely disabled by a software over-ride. */
1057 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1059 case e1000_fc_rx_pause:
1060 /* Rx Flow control is enabled and Tx Flow control is disabled
1061 * by a software over-ride. Since there really isn't a way to
1062 * advertise that we are capable of Rx Pause ONLY, we will
1063 * advertise that we support both symmetric and asymmetric Rx
1064 * PAUSE. Later, we will disable the adapter's ability to send
1067 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1069 case e1000_fc_tx_pause:
1070 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1071 * by a software over-ride.
1073 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1076 /* Flow control (both Rx and Tx) is enabled by a software
1079 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1082 DEBUGOUT("Flow control param set incorrectly\n");
1083 return -E1000_ERR_CONFIG;
1087 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1090 return E1000_SUCCESS;
1094 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1095 * @hw: pointer to the HW structure
1097 * Polls for link up by reading the status register, if link fails to come
1098 * up with auto-negotiation, then the link is forced if a signal is detected.
1100 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1102 struct e1000_mac_info *mac = &hw->mac;
1106 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1108 /* If we have a signal (the cable is plugged in, or assumed true for
1109 * serdes media) then poll for a "Link-Up" indication in the Device
1110 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1111 * seconds (Auto-negotiation should complete in less than 500
1112 * milliseconds even if the other end is doing it in SW).
1114 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1116 status = E1000_READ_REG(hw, E1000_STATUS);
1117 if (status & E1000_STATUS_LU)
1120 if (i == FIBER_LINK_UP_LIMIT) {
1121 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1122 mac->autoneg_failed = true;
1123 /* AutoNeg failed to achieve a link, so we'll call
1124 * mac->check_for_link. This routine will force the
1125 * link up if we detect a signal. This will allow us to
1126 * communicate with non-autonegotiating link partners.
1128 ret_val = mac->ops.check_for_link(hw);
1130 DEBUGOUT("Error while checking for link\n");
1133 mac->autoneg_failed = false;
1135 mac->autoneg_failed = false;
1136 DEBUGOUT("Valid Link Found\n");
1139 return E1000_SUCCESS;
1143 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1144 * @hw: pointer to the HW structure
1146 * Configures collision distance and flow control for fiber and serdes
1147 * links. Upon successful setup, poll for link.
1149 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1154 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1156 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1158 /* Take the link out of reset */
1159 ctrl &= ~E1000_CTRL_LRST;
1161 hw->mac.ops.config_collision_dist(hw);
1163 ret_val = e1000_commit_fc_settings_generic(hw);
1167 /* Since auto-negotiation is enabled, take the link out of reset (the
1168 * link will be in reset, because we previously reset the chip). This
1169 * will restart auto-negotiation. If auto-negotiation is successful
1170 * then the link-up status bit will be set and the flow control enable
1171 * bits (RFCE and TFCE) will be set according to their negotiated value.
1173 DEBUGOUT("Auto-negotiation enabled\n");
1175 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1176 E1000_WRITE_FLUSH(hw);
1179 /* For these adapters, the SW definable pin 1 is set when the optics
1180 * detect a signal. If we have a signal, then poll for a "Link-Up"
1183 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1184 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1185 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1187 DEBUGOUT("No signal detected\n");
1194 * e1000_config_collision_dist_generic - Configure collision distance
1195 * @hw: pointer to the HW structure
1197 * Configures the collision distance to the default value and is used
1198 * during link setup.
1200 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1204 DEBUGFUNC("e1000_config_collision_dist_generic");
1206 tctl = E1000_READ_REG(hw, E1000_TCTL);
1208 tctl &= ~E1000_TCTL_COLD;
1209 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1211 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1212 E1000_WRITE_FLUSH(hw);
1216 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1217 * @hw: pointer to the HW structure
1219 * Sets the flow control high/low threshold (watermark) registers. If
1220 * flow control XON frame transmission is enabled, then set XON frame
1221 * transmission as well.
1223 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1225 u32 fcrtl = 0, fcrth = 0;
1227 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1229 /* Set the flow control receive threshold registers. Normally,
1230 * these registers will be set to a default threshold that may be
1231 * adjusted later by the driver's runtime code. However, if the
1232 * ability to transmit pause frames is not enabled, then these
1233 * registers will be set to 0.
1235 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1236 /* We need to set up the Receive Threshold high and low water
1237 * marks as well as (optionally) enabling the transmission of
1240 fcrtl = hw->fc.low_water;
1241 if (hw->fc.send_xon)
1242 fcrtl |= E1000_FCRTL_XONE;
1244 fcrth = hw->fc.high_water;
1246 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1247 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1249 return E1000_SUCCESS;
1253 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1254 * @hw: pointer to the HW structure
1256 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1257 * device control register to reflect the adapter settings. TFCE and RFCE
1258 * need to be explicitly set by software when a copper PHY is used because
1259 * autonegotiation is managed by the PHY rather than the MAC. Software must
1260 * also configure these bits when link is forced on a fiber connection.
1262 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1266 DEBUGFUNC("e1000_force_mac_fc_generic");
1268 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1270 /* Because we didn't get link via the internal auto-negotiation
1271 * mechanism (we either forced link or we got link via PHY
1272 * auto-neg), we have to manually enable/disable transmit an
1273 * receive flow control.
1275 * The "Case" statement below enables/disable flow control
1276 * according to the "hw->fc.current_mode" parameter.
1278 * The possible values of the "fc" parameter are:
1279 * 0: Flow control is completely disabled
1280 * 1: Rx flow control is enabled (we can receive pause
1281 * frames but not send pause frames).
1282 * 2: Tx flow control is enabled (we can send pause frames
1283 * frames but we do not receive pause frames).
1284 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1285 * other: No other values should be possible at this point.
1287 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1289 switch (hw->fc.current_mode) {
1291 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1293 case e1000_fc_rx_pause:
1294 ctrl &= (~E1000_CTRL_TFCE);
1295 ctrl |= E1000_CTRL_RFCE;
1297 case e1000_fc_tx_pause:
1298 ctrl &= (~E1000_CTRL_RFCE);
1299 ctrl |= E1000_CTRL_TFCE;
1302 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1305 DEBUGOUT("Flow control param set incorrectly\n");
1306 return -E1000_ERR_CONFIG;
1309 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1311 return E1000_SUCCESS;
1315 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1316 * @hw: pointer to the HW structure
1318 * Checks the status of auto-negotiation after link up to ensure that the
1319 * speed and duplex were not forced. If the link needed to be forced, then
1320 * flow control needs to be forced also. If auto-negotiation is enabled
1321 * and did not fail, then we configure flow control based on our link
1324 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1326 struct e1000_mac_info *mac = &hw->mac;
1327 s32 ret_val = E1000_SUCCESS;
1328 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1329 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1332 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1334 /* Check for the case where we have fiber media and auto-neg failed
1335 * so we had to force link. In this case, we need to force the
1336 * configuration of the MAC to match the "fc" parameter.
1338 if (mac->autoneg_failed) {
1339 if (hw->phy.media_type == e1000_media_type_fiber ||
1340 hw->phy.media_type == e1000_media_type_internal_serdes)
1341 ret_val = e1000_force_mac_fc_generic(hw);
1343 if (hw->phy.media_type == e1000_media_type_copper)
1344 ret_val = e1000_force_mac_fc_generic(hw);
1348 DEBUGOUT("Error forcing flow control settings\n");
1352 /* Check for the case where we have copper media and auto-neg is
1353 * enabled. In this case, we need to check and see if Auto-Neg
1354 * has completed, and if so, how the PHY and link partner has
1355 * flow control configured.
1357 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1358 /* Read the MII Status Register and check to see if AutoNeg
1359 * has completed. We read this twice because this reg has
1360 * some "sticky" (latched) bits.
1362 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1365 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1369 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1370 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1374 /* The AutoNeg process has completed, so we now need to
1375 * read both the Auto Negotiation Advertisement
1376 * Register (Address 4) and the Auto_Negotiation Base
1377 * Page Ability Register (Address 5) to determine how
1378 * flow control was negotiated.
1380 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1384 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1385 &mii_nway_lp_ability_reg);
1389 /* Two bits in the Auto Negotiation Advertisement Register
1390 * (Address 4) and two bits in the Auto Negotiation Base
1391 * Page Ability Register (Address 5) determine flow control
1392 * for both the PHY and the link partner. The following
1393 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1394 * 1999, describes these PAUSE resolution bits and how flow
1395 * control is determined based upon these settings.
1396 * NOTE: DC = Don't Care
1398 * LOCAL DEVICE | LINK PARTNER
1399 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1400 *-------|---------|-------|---------|--------------------
1401 * 0 | 0 | DC | DC | e1000_fc_none
1402 * 0 | 1 | 0 | DC | e1000_fc_none
1403 * 0 | 1 | 1 | 0 | e1000_fc_none
1404 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1405 * 1 | 0 | 0 | DC | e1000_fc_none
1406 * 1 | DC | 1 | DC | e1000_fc_full
1407 * 1 | 1 | 0 | 0 | e1000_fc_none
1408 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1410 * Are both PAUSE bits set to 1? If so, this implies
1411 * Symmetric Flow Control is enabled at both ends. The
1412 * ASM_DIR bits are irrelevant per the spec.
1414 * For Symmetric Flow Control:
1416 * LOCAL DEVICE | LINK PARTNER
1417 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1418 *-------|---------|-------|---------|--------------------
1419 * 1 | DC | 1 | DC | E1000_fc_full
1422 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1423 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1424 /* Now we need to check if the user selected Rx ONLY
1425 * of pause frames. In this case, we had to advertise
1426 * FULL flow control because we could not advertise Rx
1427 * ONLY. Hence, we must now check to see if we need to
1428 * turn OFF the TRANSMISSION of PAUSE frames.
1430 if (hw->fc.requested_mode == e1000_fc_full) {
1431 hw->fc.current_mode = e1000_fc_full;
1432 DEBUGOUT("Flow Control = FULL.\n");
1434 hw->fc.current_mode = e1000_fc_rx_pause;
1435 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1438 /* For receiving PAUSE frames ONLY.
1440 * LOCAL DEVICE | LINK PARTNER
1441 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1442 *-------|---------|-------|---------|--------------------
1443 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1445 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1446 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1447 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1448 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1449 hw->fc.current_mode = e1000_fc_tx_pause;
1450 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1452 /* For transmitting PAUSE frames ONLY.
1454 * LOCAL DEVICE | LINK PARTNER
1455 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1456 *-------|---------|-------|---------|--------------------
1457 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1459 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1460 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1461 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1462 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1463 hw->fc.current_mode = e1000_fc_rx_pause;
1464 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1466 /* Per the IEEE spec, at this point flow control
1467 * should be disabled.
1469 hw->fc.current_mode = e1000_fc_none;
1470 DEBUGOUT("Flow Control = NONE.\n");
1473 /* Now we need to do one last check... If we auto-
1474 * negotiated to HALF DUPLEX, flow control should not be
1475 * enabled per IEEE 802.3 spec.
1477 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1479 DEBUGOUT("Error getting link speed and duplex\n");
1483 if (duplex == HALF_DUPLEX)
1484 hw->fc.current_mode = e1000_fc_none;
1486 /* Now we call a subroutine to actually force the MAC
1487 * controller to use the correct flow control settings.
1489 ret_val = e1000_force_mac_fc_generic(hw);
1491 DEBUGOUT("Error forcing flow control settings\n");
1496 /* Check for the case where we have SerDes media and auto-neg is
1497 * enabled. In this case, we need to check and see if Auto-Neg
1498 * has completed, and if so, how the PHY and link partner has
1499 * flow control configured.
1501 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1503 /* Read the PCS_LSTS and check to see if AutoNeg
1506 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1508 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1509 DEBUGOUT("PCS Auto Neg has not completed.\n");
1513 /* The AutoNeg process has completed, so we now need to
1514 * read both the Auto Negotiation Advertisement
1515 * Register (PCS_ANADV) and the Auto_Negotiation Base
1516 * Page Ability Register (PCS_LPAB) to determine how
1517 * flow control was negotiated.
1519 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1520 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1522 /* Two bits in the Auto Negotiation Advertisement Register
1523 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1524 * Page Ability Register (PCS_LPAB) determine flow control
1525 * for both the PHY and the link partner. The following
1526 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1527 * 1999, describes these PAUSE resolution bits and how flow
1528 * control is determined based upon these settings.
1529 * NOTE: DC = Don't Care
1531 * LOCAL DEVICE | LINK PARTNER
1532 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1533 *-------|---------|-------|---------|--------------------
1534 * 0 | 0 | DC | DC | e1000_fc_none
1535 * 0 | 1 | 0 | DC | e1000_fc_none
1536 * 0 | 1 | 1 | 0 | e1000_fc_none
1537 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1538 * 1 | 0 | 0 | DC | e1000_fc_none
1539 * 1 | DC | 1 | DC | e1000_fc_full
1540 * 1 | 1 | 0 | 0 | e1000_fc_none
1541 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1543 * Are both PAUSE bits set to 1? If so, this implies
1544 * Symmetric Flow Control is enabled at both ends. The
1545 * ASM_DIR bits are irrelevant per the spec.
1547 * For Symmetric Flow Control:
1549 * LOCAL DEVICE | LINK PARTNER
1550 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1551 *-------|---------|-------|---------|--------------------
1552 * 1 | DC | 1 | DC | e1000_fc_full
1555 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1556 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1557 /* Now we need to check if the user selected Rx ONLY
1558 * of pause frames. In this case, we had to advertise
1559 * FULL flow control because we could not advertise Rx
1560 * ONLY. Hence, we must now check to see if we need to
1561 * turn OFF the TRANSMISSION of PAUSE frames.
1563 if (hw->fc.requested_mode == e1000_fc_full) {
1564 hw->fc.current_mode = e1000_fc_full;
1565 DEBUGOUT("Flow Control = FULL.\n");
1567 hw->fc.current_mode = e1000_fc_rx_pause;
1568 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1571 /* For receiving PAUSE frames ONLY.
1573 * LOCAL DEVICE | LINK PARTNER
1574 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1575 *-------|---------|-------|---------|--------------------
1576 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1578 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1579 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1580 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1581 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1582 hw->fc.current_mode = e1000_fc_tx_pause;
1583 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1585 /* For transmitting PAUSE frames ONLY.
1587 * LOCAL DEVICE | LINK PARTNER
1588 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1589 *-------|---------|-------|---------|--------------------
1590 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1592 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1593 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1594 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1595 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1596 hw->fc.current_mode = e1000_fc_rx_pause;
1597 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1599 /* Per the IEEE spec, at this point flow control
1600 * should be disabled.
1602 hw->fc.current_mode = e1000_fc_none;
1603 DEBUGOUT("Flow Control = NONE.\n");
1606 /* Now we call a subroutine to actually force the MAC
1607 * controller to use the correct flow control settings.
1609 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1610 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1611 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1613 ret_val = e1000_force_mac_fc_generic(hw);
1615 DEBUGOUT("Error forcing flow control settings\n");
1620 return E1000_SUCCESS;
1624 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1625 * @hw: pointer to the HW structure
1626 * @speed: stores the current speed
1627 * @duplex: stores the current duplex
1629 * Read the status register for the current speed/duplex and store the current
1630 * speed and duplex for copper connections.
1632 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1637 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1639 status = E1000_READ_REG(hw, E1000_STATUS);
1640 if (status & E1000_STATUS_SPEED_1000) {
1641 *speed = SPEED_1000;
1642 DEBUGOUT("1000 Mbs, ");
1643 } else if (status & E1000_STATUS_SPEED_100) {
1645 DEBUGOUT("100 Mbs, ");
1648 DEBUGOUT("10 Mbs, ");
1651 if (status & E1000_STATUS_FD) {
1652 *duplex = FULL_DUPLEX;
1653 DEBUGOUT("Full Duplex\n");
1655 *duplex = HALF_DUPLEX;
1656 DEBUGOUT("Half Duplex\n");
1659 return E1000_SUCCESS;
1663 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1664 * @hw: pointer to the HW structure
1665 * @speed: stores the current speed
1666 * @duplex: stores the current duplex
1668 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1669 * for fiber/serdes links.
1671 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1672 u16 *speed, u16 *duplex)
1674 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1676 *speed = SPEED_1000;
1677 *duplex = FULL_DUPLEX;
1679 return E1000_SUCCESS;
1683 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1684 * @hw: pointer to the HW structure
1686 * Acquire the HW semaphore to access the PHY or NVM
1688 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1691 s32 timeout = hw->nvm.word_size + 1;
1694 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1696 /* Get the SW semaphore */
1697 while (i < timeout) {
1698 swsm = E1000_READ_REG(hw, E1000_SWSM);
1699 if (!(swsm & E1000_SWSM_SMBI))
1707 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1708 return -E1000_ERR_NVM;
1711 /* Get the FW semaphore. */
1712 for (i = 0; i < timeout; i++) {
1713 swsm = E1000_READ_REG(hw, E1000_SWSM);
1714 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1716 /* Semaphore acquired if bit latched */
1717 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1724 /* Release semaphores */
1725 e1000_put_hw_semaphore_generic(hw);
1726 DEBUGOUT("Driver can't access the NVM\n");
1727 return -E1000_ERR_NVM;
1730 return E1000_SUCCESS;
1734 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1735 * @hw: pointer to the HW structure
1737 * Release hardware semaphore used to access the PHY or NVM
1739 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1743 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1745 swsm = E1000_READ_REG(hw, E1000_SWSM);
1747 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1749 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1753 * e1000_get_auto_rd_done_generic - Check for auto read completion
1754 * @hw: pointer to the HW structure
1756 * Check EEPROM for Auto Read done bit.
1758 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1762 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1764 while (i < AUTO_READ_DONE_TIMEOUT) {
1765 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1771 if (i == AUTO_READ_DONE_TIMEOUT) {
1772 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1773 return -E1000_ERR_RESET;
1776 return E1000_SUCCESS;
1780 * e1000_valid_led_default_generic - Verify a valid default LED config
1781 * @hw: pointer to the HW structure
1782 * @data: pointer to the NVM (EEPROM)
1784 * Read the EEPROM for the current default LED configuration. If the
1785 * LED configuration is not valid, set to a valid LED configuration.
1787 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1791 DEBUGFUNC("e1000_valid_led_default_generic");
1793 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1795 DEBUGOUT("NVM Read Error\n");
1799 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1800 *data = ID_LED_DEFAULT;
1802 return E1000_SUCCESS;
1806 * e1000_id_led_init_generic -
1807 * @hw: pointer to the HW structure
1810 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1812 struct e1000_mac_info *mac = &hw->mac;
1814 const u32 ledctl_mask = 0x000000FF;
1815 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1816 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1818 const u16 led_mask = 0x0F;
1820 DEBUGFUNC("e1000_id_led_init_generic");
1822 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1826 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1827 mac->ledctl_mode1 = mac->ledctl_default;
1828 mac->ledctl_mode2 = mac->ledctl_default;
1830 for (i = 0; i < 4; i++) {
1831 temp = (data >> (i << 2)) & led_mask;
1833 case ID_LED_ON1_DEF2:
1834 case ID_LED_ON1_ON2:
1835 case ID_LED_ON1_OFF2:
1836 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1837 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1839 case ID_LED_OFF1_DEF2:
1840 case ID_LED_OFF1_ON2:
1841 case ID_LED_OFF1_OFF2:
1842 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1843 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1850 case ID_LED_DEF1_ON2:
1851 case ID_LED_ON1_ON2:
1852 case ID_LED_OFF1_ON2:
1853 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1854 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1856 case ID_LED_DEF1_OFF2:
1857 case ID_LED_ON1_OFF2:
1858 case ID_LED_OFF1_OFF2:
1859 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1860 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1868 return E1000_SUCCESS;
1872 * e1000_setup_led_generic - Configures SW controllable LED
1873 * @hw: pointer to the HW structure
1875 * This prepares the SW controllable LED for use and saves the current state
1876 * of the LED so it can be later restored.
1878 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1882 DEBUGFUNC("e1000_setup_led_generic");
1884 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1885 return -E1000_ERR_CONFIG;
1887 if (hw->phy.media_type == e1000_media_type_fiber) {
1888 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1889 hw->mac.ledctl_default = ledctl;
1891 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1892 E1000_LEDCTL_LED0_MODE_MASK);
1893 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1894 E1000_LEDCTL_LED0_MODE_SHIFT);
1895 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1896 } else if (hw->phy.media_type == e1000_media_type_copper) {
1897 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1900 return E1000_SUCCESS;
1904 * e1000_cleanup_led_generic - Set LED config to default operation
1905 * @hw: pointer to the HW structure
1907 * Remove the current LED configuration and set the LED configuration
1908 * to the default value, saved from the EEPROM.
1910 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1912 DEBUGFUNC("e1000_cleanup_led_generic");
1914 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1915 return E1000_SUCCESS;
1919 * e1000_blink_led_generic - Blink LED
1920 * @hw: pointer to the HW structure
1922 * Blink the LEDs which are set to be on.
1924 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1926 u32 ledctl_blink = 0;
1929 DEBUGFUNC("e1000_blink_led_generic");
1931 if (hw->phy.media_type == e1000_media_type_fiber) {
1932 /* always blink LED0 for PCI-E fiber */
1933 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1934 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1937 * set the blink bit for each LED that's "on" (0x0E)
1940 ledctl_blink = hw->mac.ledctl_mode2;
1941 for (i = 0; i < 4; i++)
1942 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1943 E1000_LEDCTL_MODE_LED_ON)
1944 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1948 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1950 return E1000_SUCCESS;
1954 * e1000_led_on_generic - Turn LED on
1955 * @hw: pointer to the HW structure
1959 s32 e1000_led_on_generic(struct e1000_hw *hw)
1963 DEBUGFUNC("e1000_led_on_generic");
1965 switch (hw->phy.media_type) {
1966 case e1000_media_type_fiber:
1967 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1968 ctrl &= ~E1000_CTRL_SWDPIN0;
1969 ctrl |= E1000_CTRL_SWDPIO0;
1970 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1972 case e1000_media_type_copper:
1973 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1979 return E1000_SUCCESS;
1983 * e1000_led_off_generic - Turn LED off
1984 * @hw: pointer to the HW structure
1988 s32 e1000_led_off_generic(struct e1000_hw *hw)
1992 DEBUGFUNC("e1000_led_off_generic");
1994 switch (hw->phy.media_type) {
1995 case e1000_media_type_fiber:
1996 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1997 ctrl |= E1000_CTRL_SWDPIN0;
1998 ctrl |= E1000_CTRL_SWDPIO0;
1999 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2001 case e1000_media_type_copper:
2002 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2008 return E1000_SUCCESS;
2012 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2013 * @hw: pointer to the HW structure
2014 * @no_snoop: bitmap of snoop events
2016 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2018 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2022 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2024 if (hw->bus.type != e1000_bus_type_pci_express)
2028 gcr = E1000_READ_REG(hw, E1000_GCR);
2029 gcr &= ~(PCIE_NO_SNOOP_ALL);
2031 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2036 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2037 * @hw: pointer to the HW structure
2039 * Returns E1000_SUCCESS if successful, else returns -10
2040 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2041 * the master requests to be disabled.
2043 * Disables PCI-Express master access and verifies there are no pending
2046 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2049 s32 timeout = MASTER_DISABLE_TIMEOUT;
2051 DEBUGFUNC("e1000_disable_pcie_master_generic");
2053 if (hw->bus.type != e1000_bus_type_pci_express)
2054 return E1000_SUCCESS;
2056 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2057 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2058 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2061 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2062 E1000_STATUS_GIO_MASTER_ENABLE))
2069 DEBUGOUT("Master requests are pending.\n");
2070 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2073 return E1000_SUCCESS;
2077 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2078 * @hw: pointer to the HW structure
2080 * Reset the Adaptive Interframe Spacing throttle to default values.
2082 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2084 struct e1000_mac_info *mac = &hw->mac;
2086 DEBUGFUNC("e1000_reset_adaptive_generic");
2088 if (!mac->adaptive_ifs) {
2089 DEBUGOUT("Not in Adaptive IFS mode!\n");
2093 mac->current_ifs_val = 0;
2094 mac->ifs_min_val = IFS_MIN;
2095 mac->ifs_max_val = IFS_MAX;
2096 mac->ifs_step_size = IFS_STEP;
2097 mac->ifs_ratio = IFS_RATIO;
2099 mac->in_ifs_mode = false;
2100 E1000_WRITE_REG(hw, E1000_AIT, 0);
2104 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2105 * @hw: pointer to the HW structure
2107 * Update the Adaptive Interframe Spacing Throttle value based on the
2108 * time between transmitted packets and time between collisions.
2110 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2112 struct e1000_mac_info *mac = &hw->mac;
2114 DEBUGFUNC("e1000_update_adaptive_generic");
2116 if (!mac->adaptive_ifs) {
2117 DEBUGOUT("Not in Adaptive IFS mode!\n");
2121 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2122 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2123 mac->in_ifs_mode = true;
2124 if (mac->current_ifs_val < mac->ifs_max_val) {
2125 if (!mac->current_ifs_val)
2126 mac->current_ifs_val = mac->ifs_min_val;
2128 mac->current_ifs_val +=
2130 E1000_WRITE_REG(hw, E1000_AIT,
2131 mac->current_ifs_val);
2135 if (mac->in_ifs_mode &&
2136 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2137 mac->current_ifs_val = 0;
2138 mac->in_ifs_mode = false;
2139 E1000_WRITE_REG(hw, E1000_AIT, 0);
2145 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2146 * @hw: pointer to the HW structure
2148 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2149 * set, which is forced to MDI mode only.
2151 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2153 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2155 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2156 DEBUGOUT("Invalid MDI setting detected\n");
2158 return -E1000_ERR_CONFIG;
2161 return E1000_SUCCESS;
2165 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2166 * @hw: pointer to the HW structure
2168 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2171 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw)
2173 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2175 return E1000_SUCCESS;
2179 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2180 * @hw: pointer to the HW structure
2181 * @reg: 32bit register offset such as E1000_SCTL
2182 * @offset: register offset to write to
2183 * @data: data to write at register offset
2185 * Writes an address/data control type register. There are several of these
2186 * and they all have the format address << 8 | data and bit 31 is polled for
2189 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2190 u32 offset, u8 data)
2192 u32 i, regvalue = 0;
2194 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2196 /* Set up the address and data */
2197 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2198 E1000_WRITE_REG(hw, reg, regvalue);
2200 /* Poll the ready bit to see if the MDI read completed */
2201 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2203 regvalue = E1000_READ_REG(hw, reg);
2204 if (regvalue & E1000_GEN_CTL_READY)
2207 if (!(regvalue & E1000_GEN_CTL_READY)) {
2208 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2209 return -E1000_ERR_PHY;
2212 return E1000_SUCCESS;