1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "e1000_api.h"
37 * e1000_calculate_checksum - Calculate checksum for buffer
38 * @buffer: pointer to EEPROM
39 * @length: size of EEPROM to calculate a checksum for
41 * Calculates the checksum for some buffer on a specified length. The
42 * checksum calculated is returned.
44 u8 e1000_calculate_checksum(u8 *buffer, u32 length)
49 DEBUGFUNC("e1000_calculate_checksum");
54 for (i = 0; i < length; i++)
57 return (u8) (0 - sum);
61 * e1000_mng_enable_host_if_generic - Checks host interface is enabled
62 * @hw: pointer to the HW structure
64 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
66 * This function checks whether the HOST IF is enabled for command operation
67 * and also checks whether the previous command is completed. It busy waits
68 * in case of previous command is not completed.
70 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
75 DEBUGFUNC("e1000_mng_enable_host_if_generic");
77 if (!hw->mac.arc_subsystem_valid) {
78 DEBUGOUT("ARC subsystem not valid.\n");
79 return -E1000_ERR_HOST_INTERFACE_COMMAND;
82 /* Check that the host interface is enabled. */
83 hicr = E1000_READ_REG(hw, E1000_HICR);
84 if (!(hicr & E1000_HICR_EN)) {
85 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
86 return -E1000_ERR_HOST_INTERFACE_COMMAND;
88 /* check the previous command is completed */
89 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
90 hicr = E1000_READ_REG(hw, E1000_HICR);
91 if (!(hicr & E1000_HICR_C))
96 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
97 DEBUGOUT("Previous command timeout failed .\n");
98 return -E1000_ERR_HOST_INTERFACE_COMMAND;
101 return E1000_SUCCESS;
105 * e1000_check_mng_mode_generic - Generic check management mode
106 * @hw: pointer to the HW structure
108 * Reads the firmware semaphore register and returns true (>0) if
109 * manageability is enabled, else false (0).
111 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
113 u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
115 DEBUGFUNC("e1000_check_mng_mode_generic");
118 return (fwsm & E1000_FWSM_MODE_MASK) ==
119 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
123 * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
124 * @hw: pointer to the HW structure
126 * Enables packet filtering on transmit packets if manageability is enabled
127 * and host interface is enabled.
129 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
131 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
132 u32 *buffer = (u32 *)&hw->mng_cookie;
134 s32 ret_val, hdr_csum, csum;
137 DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
139 hw->mac.tx_pkt_filtering = true;
141 /* No manageability, no filtering */
142 if (!hw->mac.ops.check_mng_mode(hw)) {
143 hw->mac.tx_pkt_filtering = false;
144 return hw->mac.tx_pkt_filtering;
147 /* If we can't read from the host interface for whatever
148 * reason, disable filtering.
150 ret_val = e1000_mng_enable_host_if_generic(hw);
151 if (ret_val != E1000_SUCCESS) {
152 hw->mac.tx_pkt_filtering = false;
153 return hw->mac.tx_pkt_filtering;
156 /* Read in the header. Length and offset are in dwords. */
157 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
158 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
159 for (i = 0; i < len; i++)
160 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
162 hdr_csum = hdr->checksum;
164 csum = e1000_calculate_checksum((u8 *)hdr,
165 E1000_MNG_DHCP_COOKIE_LENGTH);
166 /* If either the checksums or signature don't match, then
167 * the cookie area isn't considered valid, in which case we
168 * take the safe route of assuming Tx filtering is enabled.
170 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
171 hw->mac.tx_pkt_filtering = true;
172 return hw->mac.tx_pkt_filtering;
175 /* Cookie area is valid, make the final check for filtering. */
176 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
177 hw->mac.tx_pkt_filtering = false;
179 return hw->mac.tx_pkt_filtering;
183 * e1000_mng_write_cmd_header_generic - Writes manageability command header
184 * @hw: pointer to the HW structure
185 * @hdr: pointer to the host interface command header
187 * Writes the command header after does the checksum calculation.
189 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
190 struct e1000_host_mng_command_header *hdr)
192 u16 i, length = sizeof(struct e1000_host_mng_command_header);
194 DEBUGFUNC("e1000_mng_write_cmd_header_generic");
196 /* Write the whole command header structure with new checksum. */
198 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
201 /* Write the relevant command block into the ram area. */
202 for (i = 0; i < length; i++) {
203 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
205 E1000_WRITE_FLUSH(hw);
208 return E1000_SUCCESS;
212 * e1000_mng_host_if_write_generic - Write to the manageability host interface
213 * @hw: pointer to the HW structure
214 * @buffer: pointer to the host interface buffer
215 * @length: size of the buffer
216 * @offset: location in the buffer to write to
217 * @sum: sum of the data (not checksum)
219 * This function writes the buffer content at the offset given on the host if.
220 * It also does alignment considerations to do the writes in most efficient
221 * way. Also fills up the sum of the buffer in *buffer parameter.
223 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
224 u16 length, u16 offset, u8 *sum)
229 u16 remaining, i, j, prev_bytes;
231 DEBUGFUNC("e1000_mng_host_if_write_generic");
233 /* sum = only sum of the data and it is not checksum */
235 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
236 return -E1000_ERR_PARAM;
239 prev_bytes = offset & 0x3;
243 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
244 for (j = prev_bytes; j < sizeof(u32); j++) {
245 *(tmp + j) = *bufptr++;
248 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
249 length -= j - prev_bytes;
253 remaining = length & 0x3;
256 /* Calculate length in DWORDs */
259 /* The device driver writes the relevant command block into the
262 for (i = 0; i < length; i++) {
263 for (j = 0; j < sizeof(u32); j++) {
264 *(tmp + j) = *bufptr++;
268 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
272 for (j = 0; j < sizeof(u32); j++) {
274 *(tmp + j) = *bufptr++;
280 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
284 return E1000_SUCCESS;
288 * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
289 * @hw: pointer to the HW structure
290 * @buffer: pointer to the host interface
291 * @length: size of the buffer
293 * Writes the DHCP information to the host interface.
295 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
298 struct e1000_host_mng_command_header hdr;
302 DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
304 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
305 hdr.command_length = length;
310 /* Enable the host interface */
311 ret_val = e1000_mng_enable_host_if_generic(hw);
315 /* Populate the host interface with the contents of "buffer". */
316 ret_val = e1000_mng_host_if_write_generic(hw, buffer, length,
317 sizeof(hdr), &(hdr.checksum));
321 /* Write the manageability command header */
322 ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);
326 /* Tell the ARC a new command is pending. */
327 hicr = E1000_READ_REG(hw, E1000_HICR);
328 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
330 return E1000_SUCCESS;
334 * e1000_enable_mng_pass_thru - Check if management passthrough is needed
335 * @hw: pointer to the HW structure
337 * Verifies the hardware needs to leave interface enabled so that frames can
338 * be directed to and from the management interface.
340 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
345 DEBUGFUNC("e1000_enable_mng_pass_thru");
347 if (!hw->mac.asf_firmware_present)
350 manc = E1000_READ_REG(hw, E1000_MANC);
352 if (!(manc & E1000_MANC_RCV_TCO_EN))
355 if (hw->mac.has_fwsm) {
356 fwsm = E1000_READ_REG(hw, E1000_FWSM);
357 factps = E1000_READ_REG(hw, E1000_FACTPS);
359 if (!(factps & E1000_FACTPS_MNGCG) &&
360 ((fwsm & E1000_FWSM_MODE_MASK) ==
361 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
363 } else if ((hw->mac.type == e1000_82574) ||
364 (hw->mac.type == e1000_82583)) {
367 factps = E1000_READ_REG(hw, E1000_FACTPS);
368 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
370 if (!(factps & E1000_FACTPS_MNGCG) &&
371 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
372 (e1000_mng_mode_pt << 13)))
374 } else if ((manc & E1000_MANC_SMBUS_EN) &&
375 !(manc & E1000_MANC_ASF_EN)) {
383 * e1000_host_interface_command - Writes buffer to host interface
384 * @hw: pointer to the HW structure
385 * @buffer: contains a command to write
386 * @length: the byte length of the buffer, must be multiple of 4 bytes
388 * Writes a buffer to the Host Interface. Upon success, returns E1000_SUCCESS
389 * else returns E1000_ERR_HOST_INTERFACE_COMMAND.
391 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
395 DEBUGFUNC("e1000_host_interface_command");
397 if (!(hw->mac.arc_subsystem_valid)) {
398 DEBUGOUT("Hardware doesn't support host interface command.\n");
399 return E1000_SUCCESS;
402 if (!hw->mac.asf_firmware_present) {
403 DEBUGOUT("Firmware is not present.\n");
404 return E1000_SUCCESS;
407 if (length == 0 || length & 0x3 ||
408 length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
409 DEBUGOUT("Buffer length failure.\n");
410 return -E1000_ERR_HOST_INTERFACE_COMMAND;
413 /* Check that the host interface is enabled. */
414 hicr = E1000_READ_REG(hw, E1000_HICR);
415 if (!(hicr & E1000_HICR_EN)) {
416 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
417 return -E1000_ERR_HOST_INTERFACE_COMMAND;
420 /* Calculate length in DWORDs */
423 /* The device driver writes the relevant command block
426 for (i = 0; i < length; i++)
427 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
428 *((u32 *)buffer + i));
430 /* Setting this bit tells the ARC that a new command is pending. */
431 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
433 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
434 hicr = E1000_READ_REG(hw, E1000_HICR);
435 if (!(hicr & E1000_HICR_C))
440 /* Check command successful completion. */
441 if (i == E1000_HI_COMMAND_TIMEOUT ||
442 (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
443 DEBUGOUT("Command has failed with no status valid.\n");
444 return -E1000_ERR_HOST_INTERFACE_COMMAND;
447 for (i = 0; i < length; i++)
448 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
452 return E1000_SUCCESS;
455 * e1000_load_firmware - Writes proxy FW code buffer to host interface
457 * @hw: pointer to the HW structure
458 * @buffer: contains a firmware to write
459 * @length: the byte length of the buffer, must be multiple of 4 bytes
461 * Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
462 * in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
464 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
466 u32 hicr, hibba, fwsm, icr, i;
468 DEBUGFUNC("e1000_load_firmware");
470 if (hw->mac.type < e1000_i210) {
471 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
472 return -E1000_ERR_CONFIG;
475 /* Check that the host interface is enabled. */
476 hicr = E1000_READ_REG(hw, E1000_HICR);
477 if (!(hicr & E1000_HICR_EN)) {
478 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
479 return -E1000_ERR_CONFIG;
481 if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
482 DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
483 return -E1000_ERR_CONFIG;
486 if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
487 DEBUGOUT("Buffer length failure.\n");
488 return -E1000_ERR_INVALID_ARGUMENT;
491 /* Clear notification from ROM-FW by reading ICR register */
492 icr = E1000_READ_REG(hw, E1000_ICR_V2);
495 hicr = E1000_READ_REG(hw, E1000_HICR);
496 hicr |= E1000_HICR_FW_RESET_ENABLE;
497 E1000_WRITE_REG(hw, E1000_HICR, hicr);
498 hicr |= E1000_HICR_FW_RESET;
499 E1000_WRITE_REG(hw, E1000_HICR, hicr);
500 E1000_WRITE_FLUSH(hw);
502 /* Wait till MAC notifies about its readiness after ROM-FW reset */
503 for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
504 icr = E1000_READ_REG(hw, E1000_ICR_V2);
505 if (icr & E1000_ICR_MNG)
510 /* Check for timeout */
511 if (i == E1000_HI_COMMAND_TIMEOUT) {
512 DEBUGOUT("FW reset failed.\n");
513 return -E1000_ERR_HOST_INTERFACE_COMMAND;
516 /* Wait till MAC is ready to accept new FW code */
517 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
518 fwsm = E1000_READ_REG(hw, E1000_FWSM);
519 if ((fwsm & E1000_FWSM_FW_VALID) &&
520 ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
521 E1000_FWSM_HI_EN_ONLY_MODE))
526 /* Check for timeout */
527 if (i == E1000_HI_COMMAND_TIMEOUT) {
528 DEBUGOUT("FW reset failed.\n");
529 return -E1000_ERR_HOST_INTERFACE_COMMAND;
532 /* Calculate length in DWORDs */
535 /* The device driver writes the relevant FW code block
536 * into the ram area in DWORDs via 1kB ram addressing window.
538 for (i = 0; i < length; i++) {
539 if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
540 /* Point to correct 1kB ram window */
541 hibba = E1000_HI_FW_BASE_ADDRESS +
542 ((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
543 (i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
545 E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
548 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
549 i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
550 *((u32 *)buffer + i));
553 /* Setting this bit tells the ARC that a new FW is ready to execute. */
554 hicr = E1000_READ_REG(hw, E1000_HICR);
555 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
557 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
558 hicr = E1000_READ_REG(hw, E1000_HICR);
559 if (!(hicr & E1000_HICR_C))
564 /* Check for successful FW start. */
565 if (i == E1000_HI_COMMAND_TIMEOUT) {
566 DEBUGOUT("New FW did not start within timeout period.\n");
567 return -E1000_ERR_HOST_INTERFACE_COMMAND;
570 return E1000_SUCCESS;