lib/librte_pmd_e1000/e1000/e1000_manage.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "e1000_api.h"
  35
  36 /**
  37  *  e1000_calculate_checksum - Calculate checksum for buffer
  38  *  @buffer: pointer to EEPROM
  39  *  @length: size of EEPROM to calculate a checksum for
  40  *
  41  *  Calculates the checksum for some buffer on a specified length.  The
  42  *  checksum calculated is returned.
  43  **/
  44 u8 e1000_calculate_checksum(u8 *buffer, u32 length)
  45 {
  46         u32 i;
  47         u8 sum = 0;
  48
  49         DEBUGFUNC("e1000_calculate_checksum");
  50
  51         if (!buffer)
  52                 return 0;
  53
  54         for (i = 0; i < length; i++)
  55                 sum += buffer[i];
  56
  57         return (u8) (0 - sum);
  58 }
  59
  60 /**
  61  *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
  62  *  @hw: pointer to the HW structure
  63  *
  64  *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
  65  *
  66  *  This function checks whether the HOST IF is enabled for command operation
  67  *  and also checks whether the previous command is completed.  It busy waits
  68  *  in case of previous command is not completed.
  69  **/
  70 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
  71 {
  72         u32 hicr;
  73         u8 i;
  74
  75         DEBUGFUNC("e1000_mng_enable_host_if_generic");
  76
  77         if (!hw->mac.arc_subsystem_valid) {
  78                 DEBUGOUT("ARC subsystem not valid.\n");
  79                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  80         }
  81
  82         /* Check that the host interface is enabled. */
  83         hicr = E1000_READ_REG(hw, E1000_HICR);
  84         if (!(hicr & E1000_HICR_EN)) {
  85                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
  86                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  87         }
  88         /* check the previous command is completed */
  89         for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
  90                 hicr = E1000_READ_REG(hw, E1000_HICR);
  91                 if (!(hicr & E1000_HICR_C))
  92                         break;
  93                 msec_delay_irq(1);
  94         }
  95
  96         if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
  97                 DEBUGOUT("Previous command timeout failed .\n");
  98                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  99         }
 100
 101         return E1000_SUCCESS;
 102 }
 103
 104 /**
 105  *  e1000_check_mng_mode_generic - Generic check management mode
 106  *  @hw: pointer to the HW structure
 107  *
 108  *  Reads the firmware semaphore register and returns true (>0) if
 109  *  manageability is enabled, else false (0).
 110  **/
 111 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
 112 {
 113         u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 114
 115         DEBUGFUNC("e1000_check_mng_mode_generic");
 116
 117
 118         return (fwsm & E1000_FWSM_MODE_MASK) ==
 119                 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 120 }
 121
 122 /**
 123  *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
 124  *  @hw: pointer to the HW structure
 125  *
 126  *  Enables packet filtering on transmit packets if manageability is enabled
 127  *  and host interface is enabled.
 128  **/
 129 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
 130 {
 131         struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
 132         u32 *buffer = (u32 *)&hw->mng_cookie;
 133         u32 offset;
 134         s32 ret_val, hdr_csum, csum;
 135         u8 i, len;
 136
 137         DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
 138
 139         hw->mac.tx_pkt_filtering = true;
 140
 141         /* No manageability, no filtering */
 142         if (!hw->mac.ops.check_mng_mode(hw)) {
 143                 hw->mac.tx_pkt_filtering = false;
 144                 return hw->mac.tx_pkt_filtering;
 145         }
 146
 147         /*
 148          * If we can't read from the host interface for whatever
 149          * reason, disable filtering.
 150          */
 151         ret_val = hw->mac.ops.mng_enable_host_if(hw);
 152         if (ret_val != E1000_SUCCESS) {
 153                 hw->mac.tx_pkt_filtering = false;
 154                 return hw->mac.tx_pkt_filtering;
 155         }
 156
 157         /* Read in the header.  Length and offset are in dwords. */
 158         len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
 159         offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
 160         for (i = 0; i < len; i++)
 161                 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
 162                                                            offset + i);
 163         hdr_csum = hdr->checksum;
 164         hdr->checksum = 0;
 165         csum = e1000_calculate_checksum((u8 *)hdr,
 166                                         E1000_MNG_DHCP_COOKIE_LENGTH);
 167         /*
 168          * If either the checksums or signature don't match, then
 169          * the cookie area isn't considered valid, in which case we
 170          * take the safe route of assuming Tx filtering is enabled.
 171          */
 172         if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
 173                 hw->mac.tx_pkt_filtering = true;
 174                 return hw->mac.tx_pkt_filtering;
 175         }
 176
 177         /* Cookie area is valid, make the final check for filtering. */
 178         if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
 179                 hw->mac.tx_pkt_filtering = false;
 180
 181         return hw->mac.tx_pkt_filtering;
 182 }
 183
 184 /**
 185  *  e1000_mng_write_cmd_header_generic - Writes manageability command header
 186  *  @hw: pointer to the HW structure
 187  *  @hdr: pointer to the host interface command header
 188  *
 189  *  Writes the command header after does the checksum calculation.
 190  **/
 191 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
 192                                       struct e1000_host_mng_command_header *hdr)
 193 {
 194         u16 i, length = sizeof(struct e1000_host_mng_command_header);
 195
 196         DEBUGFUNC("e1000_mng_write_cmd_header_generic");
 197
 198         /* Write the whole command header structure with new checksum. */
 199
 200         hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
 201
 202         length >>= 2;
 203         /* Write the relevant command block into the ram area. */
 204         for (i = 0; i < length; i++) {
 205                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 206                                             *((u32 *) hdr + i));
 207                 E1000_WRITE_FLUSH(hw);
 208         }
 209
 210         return E1000_SUCCESS;
 211 }
 212
 213 /**
 214  *  e1000_mng_host_if_write_generic - Write to the manageability host interface
 215  *  @hw: pointer to the HW structure
 216  *  @buffer: pointer to the host interface buffer
 217  *  @length: size of the buffer
 218  *  @offset: location in the buffer to write to
 219  *  @sum: sum of the data (not checksum)
 220  *
 221  *  This function writes the buffer content at the offset given on the host if.
 222  *  It also does alignment considerations to do the writes in most efficient
 223  *  way.  Also fills up the sum of the buffer in *buffer parameter.
 224  **/
 225 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
 226                                     u16 length, u16 offset, u8 *sum)
 227 {
 228         u8 *tmp;
 229         u8 *bufptr = buffer;
 230         u32 data = 0;
 231         u16 remaining, i, j, prev_bytes;
 232
 233         DEBUGFUNC("e1000_mng_host_if_write_generic");
 234
 235         /* sum = only sum of the data and it is not checksum */
 236
 237         if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
 238                 return -E1000_ERR_PARAM;
 239
 240         tmp = (u8 *)&data;
 241         prev_bytes = offset & 0x3;
 242         offset >>= 2;
 243
 244         if (prev_bytes) {
 245                 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
 246                 for (j = prev_bytes; j < sizeof(u32); j++) {
 247                         *(tmp + j) = *bufptr++;
 248                         *sum += *(tmp + j);
 249                 }
 250                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
 251                 length -= j - prev_bytes;
 252                 offset++;
 253         }
 254
 255         remaining = length & 0x3;
 256         length -= remaining;
 257
 258         /* Calculate length in DWORDs */
 259         length >>= 2;
 260
 261         /*
 262          * The device driver writes the relevant command block into the
 263          * ram area.
 264          */
 265         for (i = 0; i < length; i++) {
 266                 for (j = 0; j < sizeof(u32); j++) {
 267                         *(tmp + j) = *bufptr++;
 268                         *sum += *(tmp + j);
 269                 }
 270
 271                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
 272                                             data);
 273         }
 274         if (remaining) {
 275                 for (j = 0; j < sizeof(u32); j++) {
 276                         if (j < remaining)
 277                                 *(tmp + j) = *bufptr++;
 278                         else
 279                                 *(tmp + j) = 0;
 280
 281                         *sum += *(tmp + j);
 282                 }
 283                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
 284                                             data);
 285         }
 286
 287         return E1000_SUCCESS;
 288 }
 289
 290 /**
 291  *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
 292  *  @hw: pointer to the HW structure
 293  *  @buffer: pointer to the host interface
 294  *  @length: size of the buffer
 295  *
 296  *  Writes the DHCP information to the host interface.
 297  **/
 298 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
 299                                       u16 length)
 300 {
 301         struct e1000_host_mng_command_header hdr;
 302         s32 ret_val;
 303         u32 hicr;
 304
 305         DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
 306
 307         hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
 308         hdr.command_length = length;
 309         hdr.reserved1 = 0;
 310         hdr.reserved2 = 0;
 311         hdr.checksum = 0;
 312
 313         /* Enable the host interface */
 314         ret_val = hw->mac.ops.mng_enable_host_if(hw);
 315         if (ret_val)
 316                 return ret_val;
 317
 318         /* Populate the host interface with the contents of "buffer". */
 319         ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
 320                                                 sizeof(hdr), &(hdr.checksum));
 321         if (ret_val)
 322                 return ret_val;
 323
 324         /* Write the manageability command header */
 325         ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
 326         if (ret_val)
 327                 return ret_val;
 328
 329         /* Tell the ARC a new command is pending. */
 330         hicr = E1000_READ_REG(hw, E1000_HICR);
 331         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 332
 333         return E1000_SUCCESS;
 334 }
 335
 336 /**
 337  *  e1000_enable_mng_pass_thru - Check if management passthrough is needed
 338  *  @hw: pointer to the HW structure
 339  *
 340  *  Verifies the hardware needs to leave interface enabled so that frames can
 341  *  be directed to and from the management interface.
 342  **/
 343 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
 344 {
 345         u32 manc;
 346         u32 fwsm, factps;
 347
 348         DEBUGFUNC("e1000_enable_mng_pass_thru");
 349
 350         if (!hw->mac.asf_firmware_present)
 351                 return false;
 352
 353         manc = E1000_READ_REG(hw, E1000_MANC);
 354
 355         if (!(manc & E1000_MANC_RCV_TCO_EN))
 356                 return false;
 357
 358         if (hw->mac.has_fwsm) {
 359                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 360                 factps = E1000_READ_REG(hw, E1000_FACTPS);
 361
 362                 if (!(factps & E1000_FACTPS_MNGCG) &&
 363                     ((fwsm & E1000_FWSM_MODE_MASK) ==
 364                      (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
 365                         return true;
 366         } else if ((hw->mac.type == e1000_82574) ||
 367                    (hw->mac.type == e1000_82583)) {
 368                 u16 data;
 369
 370                 factps = E1000_READ_REG(hw, E1000_FACTPS);
 371                 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
 372
 373                 if (!(factps & E1000_FACTPS_MNGCG) &&
 374                     ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
 375                      (e1000_mng_mode_pt << 13)))
 376                         return true;
 377         } else if ((manc & E1000_MANC_SMBUS_EN) &&
 378                    !(manc & E1000_MANC_ASF_EN)) {
 379                         return true;
 380         }
 381
 382         return false;
 383 }
 384
 385 /**
 386  *  e1000_host_interface_command - Writes buffer to host interface
 387  *  @hw: pointer to the HW structure
 388  *  @buffer: contains a command to write
 389  *  @length: the byte length of the buffer, must be multiple of 4 bytes
 390  *
 391  *  Writes a buffer to the Host Interface.  Upon success, returns E1000_SUCCESS
 392  *  else returns E1000_ERR_HOST_INTERFACE_COMMAND.
 393  **/
 394 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
 395 {
 396         u32 hicr, i;
 397
 398         DEBUGFUNC("e1000_host_interface_command");
 399
 400         if (!(hw->mac.arc_subsystem_valid)) {
 401                 DEBUGOUT("Hardware doesn't support host interface command.\n");
 402                 return E1000_SUCCESS;
 403         }
 404
 405         if (!hw->mac.asf_firmware_present) {
 406                 DEBUGOUT("Firmware is not present.\n");
 407                 return E1000_SUCCESS;
 408         }
 409
 410         if (length == 0 || length & 0x3 ||
 411             length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
 412                 DEBUGOUT("Buffer length failure.\n");
 413                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 414         }
 415
 416         /* Check that the host interface is enabled. */
 417         hicr = E1000_READ_REG(hw, E1000_HICR);
 418         if (!(hicr & E1000_HICR_EN)) {
 419                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
 420                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 421         }
 422
 423         /* Calculate length in DWORDs */
 424         length >>= 2;
 425
 426         /*
 427          * The device driver writes the relevant command block
 428          * into the ram area.
 429          */
 430         for (i = 0; i < length; i++)
 431                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 432                                             *((u32 *)buffer + i));
 433
 434         /* Setting this bit tells the ARC that a new command is pending. */
 435         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 436
 437         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 438                 hicr = E1000_READ_REG(hw, E1000_HICR);
 439                 if (!(hicr & E1000_HICR_C))
 440                         break;
 441                 msec_delay(1);
 442         }
 443
 444         /* Check command successful completion. */
 445         if (i == E1000_HI_COMMAND_TIMEOUT ||
 446             (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
 447                 DEBUGOUT("Command has failed with no status valid.\n");
 448                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 449         }
 450
 451         for (i = 0; i < length; i++)
 452                 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
 453                                                                   E1000_HOST_IF,
 454                                                                   i);
 455
 456         return E1000_SUCCESS;
 457 }
 458 /**
 459  *  e1000_load_firmware - Writes proxy FW code buffer to host interface
 460  *                        and execute.
 461  *  @hw: pointer to the HW structure
 462  *  @buffer: contains a firmware to write
 463  *  @length: the byte length of the buffer, must be multiple of 4 bytes
 464  *
 465  *  Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
 466  *  in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
 467  **/
 468 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
 469 {
 470         u32 hicr, hibba, fwsm, icr, i;
 471
 472         DEBUGFUNC("e1000_load_firmware");
 473
 474         if (hw->mac.type < e1000_i210) {
 475                 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
 476                 return -E1000_ERR_CONFIG;
 477         }
 478
 479         /* Check that the host interface is enabled. */
 480         hicr = E1000_READ_REG(hw, E1000_HICR);
 481         if (!(hicr & E1000_HICR_EN)) {
 482                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
 483                 return -E1000_ERR_CONFIG;
 484         }
 485         if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
 486                 DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
 487                 return -E1000_ERR_CONFIG;
 488         }
 489
 490         if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
 491                 DEBUGOUT("Buffer length failure.\n");
 492                 return -E1000_ERR_INVALID_ARGUMENT;
 493         }
 494
 495         /* Clear notification from ROM-FW by reading ICR register */
 496         icr = E1000_READ_REG(hw, E1000_ICR_V2);
 497
 498         /* Reset ROM-FW */
 499         hicr = E1000_READ_REG(hw, E1000_HICR);
 500         hicr |= E1000_HICR_FW_RESET_ENABLE;
 501         E1000_WRITE_REG(hw, E1000_HICR, hicr);
 502         hicr |= E1000_HICR_FW_RESET;
 503         E1000_WRITE_REG(hw, E1000_HICR, hicr);
 504         E1000_WRITE_FLUSH(hw);
 505
 506         /* Wait till MAC notifies about its readiness after ROM-FW reset */
 507         for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
 508                 icr = E1000_READ_REG(hw, E1000_ICR_V2);
 509                 if (icr & E1000_ICR_MNG)
 510                         break;
 511                 msec_delay(1);
 512         }
 513
 514         /* Check for timeout */
 515         if (i == E1000_HI_COMMAND_TIMEOUT) {
 516                 DEBUGOUT("FW reset failed.\n");
 517                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 518         }
 519
 520         /* Wait till MAC is ready to accept new FW code */
 521         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 522                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 523                 if ((fwsm & E1000_FWSM_FW_VALID) &&
 524                     ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
 525                     E1000_FWSM_HI_EN_ONLY_MODE))
 526                         break;
 527                 msec_delay(1);
 528         }
 529
 530         /* Check for timeout */
 531         if (i == E1000_HI_COMMAND_TIMEOUT) {
 532                 DEBUGOUT("FW reset failed.\n");
 533                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 534         }
 535
 536         /* Calculate length in DWORDs */
 537         length >>= 2;
 538
 539         /*
 540          * The device driver writes the relevant FW code block
 541          * into the ram area in DWORDs via 1kB ram addressing window.
 542          */
 543         for (i = 0; i < length; i++) {
 544                 if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
 545                         /* Point to correct 1kB ram window */
 546                         hibba = E1000_HI_FW_BASE_ADDRESS +
 547                                 ((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
 548                                 (i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
 549
 550                         E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
 551                 }
 552
 553                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
 554                                             i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
 555                                             *((u32 *)buffer + i));
 556         }
 557
 558         /* Setting this bit tells the ARC that a new FW is ready to execute. */
 559         hicr = E1000_READ_REG(hw, E1000_HICR);
 560         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 561
 562         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 563                 hicr = E1000_READ_REG(hw, E1000_HICR);
 564                 if (!(hicr & E1000_HICR_C))
 565                         break;
 566                 msec_delay(1);
 567         }
 568
 569         /* Check for successful FW start. */
 570         if (i == E1000_HI_COMMAND_TIMEOUT) {
 571                 DEBUGOUT("New FW did not start within timeout period.\n");
 572                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 573         }
 574
 575         return E1000_SUCCESS;
 576 }
 577
 578