1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "e1000_api.h"
37 * e1000_calculate_checksum - Calculate checksum for buffer
38 * @buffer: pointer to EEPROM
39 * @length: size of EEPROM to calculate a checksum for
41 * Calculates the checksum for some buffer on a specified length. The
42 * checksum calculated is returned.
44 u8 e1000_calculate_checksum(u8 *buffer, u32 length)
49 DEBUGFUNC("e1000_calculate_checksum");
54 for (i = 0; i < length; i++)
57 return (u8) (0 - sum);
61 * e1000_mng_enable_host_if_generic - Checks host interface is enabled
62 * @hw: pointer to the HW structure
64 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
66 * This function checks whether the HOST IF is enabled for command operation
67 * and also checks whether the previous command is completed. It busy waits
68 * in case of previous command is not completed.
70 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
75 DEBUGFUNC("e1000_mng_enable_host_if_generic");
77 if (!hw->mac.arc_subsystem_valid) {
78 DEBUGOUT("ARC subsystem not valid.\n");
79 return -E1000_ERR_HOST_INTERFACE_COMMAND;
82 /* Check that the host interface is enabled. */
83 hicr = E1000_READ_REG(hw, E1000_HICR);
84 if (!(hicr & E1000_HICR_EN)) {
85 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
86 return -E1000_ERR_HOST_INTERFACE_COMMAND;
88 /* check the previous command is completed */
89 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
90 hicr = E1000_READ_REG(hw, E1000_HICR);
91 if (!(hicr & E1000_HICR_C))
96 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
97 DEBUGOUT("Previous command timeout failed .\n");
98 return -E1000_ERR_HOST_INTERFACE_COMMAND;
101 return E1000_SUCCESS;
105 * e1000_check_mng_mode_generic - Generic check management mode
106 * @hw: pointer to the HW structure
108 * Reads the firmware semaphore register and returns true (>0) if
109 * manageability is enabled, else false (0).
111 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
113 u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
115 DEBUGFUNC("e1000_check_mng_mode_generic");
118 return (fwsm & E1000_FWSM_MODE_MASK) ==
119 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
123 * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
124 * @hw: pointer to the HW structure
126 * Enables packet filtering on transmit packets if manageability is enabled
127 * and host interface is enabled.
129 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
131 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
132 u32 *buffer = (u32 *)&hw->mng_cookie;
134 s32 ret_val, hdr_csum, csum;
137 DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
139 hw->mac.tx_pkt_filtering = true;
141 /* No manageability, no filtering */
142 if (!hw->mac.ops.check_mng_mode(hw)) {
143 hw->mac.tx_pkt_filtering = false;
144 return hw->mac.tx_pkt_filtering;
148 * If we can't read from the host interface for whatever
149 * reason, disable filtering.
151 ret_val = hw->mac.ops.mng_enable_host_if(hw);
152 if (ret_val != E1000_SUCCESS) {
153 hw->mac.tx_pkt_filtering = false;
154 return hw->mac.tx_pkt_filtering;
157 /* Read in the header. Length and offset are in dwords. */
158 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
159 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
160 for (i = 0; i < len; i++)
161 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
163 hdr_csum = hdr->checksum;
165 csum = e1000_calculate_checksum((u8 *)hdr,
166 E1000_MNG_DHCP_COOKIE_LENGTH);
168 * If either the checksums or signature don't match, then
169 * the cookie area isn't considered valid, in which case we
170 * take the safe route of assuming Tx filtering is enabled.
172 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
173 hw->mac.tx_pkt_filtering = true;
174 return hw->mac.tx_pkt_filtering;
177 /* Cookie area is valid, make the final check for filtering. */
178 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
179 hw->mac.tx_pkt_filtering = false;
181 return hw->mac.tx_pkt_filtering;
185 * e1000_mng_write_cmd_header_generic - Writes manageability command header
186 * @hw: pointer to the HW structure
187 * @hdr: pointer to the host interface command header
189 * Writes the command header after does the checksum calculation.
191 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
192 struct e1000_host_mng_command_header *hdr)
194 u16 i, length = sizeof(struct e1000_host_mng_command_header);
196 DEBUGFUNC("e1000_mng_write_cmd_header_generic");
198 /* Write the whole command header structure with new checksum. */
200 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
203 /* Write the relevant command block into the ram area. */
204 for (i = 0; i < length; i++) {
205 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
207 E1000_WRITE_FLUSH(hw);
210 return E1000_SUCCESS;
214 * e1000_mng_host_if_write_generic - Write to the manageability host interface
215 * @hw: pointer to the HW structure
216 * @buffer: pointer to the host interface buffer
217 * @length: size of the buffer
218 * @offset: location in the buffer to write to
219 * @sum: sum of the data (not checksum)
221 * This function writes the buffer content at the offset given on the host if.
222 * It also does alignment considerations to do the writes in most efficient
223 * way. Also fills up the sum of the buffer in *buffer parameter.
225 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
226 u16 length, u16 offset, u8 *sum)
231 u16 remaining, i, j, prev_bytes;
233 DEBUGFUNC("e1000_mng_host_if_write_generic");
235 /* sum = only sum of the data and it is not checksum */
237 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
238 return -E1000_ERR_PARAM;
241 prev_bytes = offset & 0x3;
245 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
246 for (j = prev_bytes; j < sizeof(u32); j++) {
247 *(tmp + j) = *bufptr++;
250 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
251 length -= j - prev_bytes;
255 remaining = length & 0x3;
258 /* Calculate length in DWORDs */
262 * The device driver writes the relevant command block into the
265 for (i = 0; i < length; i++) {
266 for (j = 0; j < sizeof(u32); j++) {
267 *(tmp + j) = *bufptr++;
271 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
275 for (j = 0; j < sizeof(u32); j++) {
277 *(tmp + j) = *bufptr++;
283 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
287 return E1000_SUCCESS;
291 * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
292 * @hw: pointer to the HW structure
293 * @buffer: pointer to the host interface
294 * @length: size of the buffer
296 * Writes the DHCP information to the host interface.
298 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
301 struct e1000_host_mng_command_header hdr;
305 DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
307 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
308 hdr.command_length = length;
313 /* Enable the host interface */
314 ret_val = hw->mac.ops.mng_enable_host_if(hw);
318 /* Populate the host interface with the contents of "buffer". */
319 ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
320 sizeof(hdr), &(hdr.checksum));
324 /* Write the manageability command header */
325 ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
329 /* Tell the ARC a new command is pending. */
330 hicr = E1000_READ_REG(hw, E1000_HICR);
331 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
333 return E1000_SUCCESS;
337 * e1000_enable_mng_pass_thru - Check if management passthrough is needed
338 * @hw: pointer to the HW structure
340 * Verifies the hardware needs to leave interface enabled so that frames can
341 * be directed to and from the management interface.
343 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
348 DEBUGFUNC("e1000_enable_mng_pass_thru");
350 if (!hw->mac.asf_firmware_present)
353 manc = E1000_READ_REG(hw, E1000_MANC);
355 if (!(manc & E1000_MANC_RCV_TCO_EN))
358 if (hw->mac.has_fwsm) {
359 fwsm = E1000_READ_REG(hw, E1000_FWSM);
360 factps = E1000_READ_REG(hw, E1000_FACTPS);
362 if (!(factps & E1000_FACTPS_MNGCG) &&
363 ((fwsm & E1000_FWSM_MODE_MASK) ==
364 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
366 } else if ((hw->mac.type == e1000_82574) ||
367 (hw->mac.type == e1000_82583)) {
370 factps = E1000_READ_REG(hw, E1000_FACTPS);
371 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
373 if (!(factps & E1000_FACTPS_MNGCG) &&
374 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
375 (e1000_mng_mode_pt << 13)))
377 } else if ((manc & E1000_MANC_SMBUS_EN) &&
378 !(manc & E1000_MANC_ASF_EN)) {
386 * e1000_host_interface_command - Writes buffer to host interface
387 * @hw: pointer to the HW structure
388 * @buffer: contains a command to write
389 * @length: the byte length of the buffer, must be multiple of 4 bytes
391 * Writes a buffer to the Host Interface. Upon success, returns E1000_SUCCESS
392 * else returns E1000_ERR_HOST_INTERFACE_COMMAND.
394 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
398 DEBUGFUNC("e1000_host_interface_command");
400 if (!(hw->mac.arc_subsystem_valid)) {
401 DEBUGOUT("Hardware doesn't support host interface command.\n");
402 return E1000_SUCCESS;
405 if (!hw->mac.asf_firmware_present) {
406 DEBUGOUT("Firmware is not present.\n");
407 return E1000_SUCCESS;
410 if (length == 0 || length & 0x3 ||
411 length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
412 DEBUGOUT("Buffer length failure.\n");
413 return -E1000_ERR_HOST_INTERFACE_COMMAND;
416 /* Check that the host interface is enabled. */
417 hicr = E1000_READ_REG(hw, E1000_HICR);
418 if (!(hicr & E1000_HICR_EN)) {
419 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
420 return -E1000_ERR_HOST_INTERFACE_COMMAND;
423 /* Calculate length in DWORDs */
427 * The device driver writes the relevant command block
430 for (i = 0; i < length; i++)
431 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
432 *((u32 *)buffer + i));
434 /* Setting this bit tells the ARC that a new command is pending. */
435 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
437 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
438 hicr = E1000_READ_REG(hw, E1000_HICR);
439 if (!(hicr & E1000_HICR_C))
444 /* Check command successful completion. */
445 if (i == E1000_HI_COMMAND_TIMEOUT ||
446 (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
447 DEBUGOUT("Command has failed with no status valid.\n");
448 return -E1000_ERR_HOST_INTERFACE_COMMAND;
451 for (i = 0; i < length; i++)
452 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
456 return E1000_SUCCESS;
459 * e1000_load_firmware - Writes proxy FW code buffer to host interface
461 * @hw: pointer to the HW structure
462 * @buffer: contains a firmware to write
463 * @length: the byte length of the buffer, must be multiple of 4 bytes
465 * Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
466 * in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
468 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
470 u32 hicr, hibba, fwsm, icr, i;
472 DEBUGFUNC("e1000_load_firmware");
474 if (hw->mac.type < e1000_i210) {
475 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
476 return -E1000_ERR_CONFIG;
479 /* Check that the host interface is enabled. */
480 hicr = E1000_READ_REG(hw, E1000_HICR);
481 if (!(hicr & E1000_HICR_EN)) {
482 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
483 return -E1000_ERR_CONFIG;
485 if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
486 DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
487 return -E1000_ERR_CONFIG;
490 if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
491 DEBUGOUT("Buffer length failure.\n");
492 return -E1000_ERR_INVALID_ARGUMENT;
495 /* Clear notification from ROM-FW by reading ICR register */
496 icr = E1000_READ_REG(hw, E1000_ICR_V2);
499 hicr = E1000_READ_REG(hw, E1000_HICR);
500 hicr |= E1000_HICR_FW_RESET_ENABLE;
501 E1000_WRITE_REG(hw, E1000_HICR, hicr);
502 hicr |= E1000_HICR_FW_RESET;
503 E1000_WRITE_REG(hw, E1000_HICR, hicr);
504 E1000_WRITE_FLUSH(hw);
506 /* Wait till MAC notifies about its readiness after ROM-FW reset */
507 for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
508 icr = E1000_READ_REG(hw, E1000_ICR_V2);
509 if (icr & E1000_ICR_MNG)
514 /* Check for timeout */
515 if (i == E1000_HI_COMMAND_TIMEOUT) {
516 DEBUGOUT("FW reset failed.\n");
517 return -E1000_ERR_HOST_INTERFACE_COMMAND;
520 /* Wait till MAC is ready to accept new FW code */
521 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
522 fwsm = E1000_READ_REG(hw, E1000_FWSM);
523 if ((fwsm & E1000_FWSM_FW_VALID) &&
524 ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
525 E1000_FWSM_HI_EN_ONLY_MODE))
530 /* Check for timeout */
531 if (i == E1000_HI_COMMAND_TIMEOUT) {
532 DEBUGOUT("FW reset failed.\n");
533 return -E1000_ERR_HOST_INTERFACE_COMMAND;
536 /* Calculate length in DWORDs */
540 * The device driver writes the relevant FW code block
541 * into the ram area in DWORDs via 1kB ram addressing window.
543 for (i = 0; i < length; i++) {
544 if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
545 /* Point to correct 1kB ram window */
546 hibba = E1000_HI_FW_BASE_ADDRESS +
547 ((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
548 (i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
550 E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
553 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
554 i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
555 *((u32 *)buffer + i));
558 /* Setting this bit tells the ARC that a new FW is ready to execute. */
559 hicr = E1000_READ_REG(hw, E1000_HICR);
560 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
562 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
563 hicr = E1000_READ_REG(hw, E1000_HICR);
564 if (!(hicr & E1000_HICR_C))
569 /* Check for successful FW start. */
570 if (i == E1000_HI_COMMAND_TIMEOUT) {
571 DEBUGOUT("New FW did not start within timeout period.\n");
572 return -E1000_ERR_HOST_INTERFACE_COMMAND;
575 return E1000_SUCCESS;