1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static void e1000_stop_nvm(struct e1000_hw *hw);
38 static void e1000_reload_nvm_generic(struct e1000_hw *hw);
41 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
42 * @hw: pointer to the HW structure
44 * Setups up the function pointers to no-op functions
46 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
48 struct e1000_nvm_info *nvm = &hw->nvm;
49 DEBUGFUNC("e1000_init_nvm_ops_generic");
51 /* Initialize function pointers */
52 nvm->ops.init_params = e1000_null_ops_generic;
53 nvm->ops.acquire = e1000_null_ops_generic;
54 nvm->ops.read = e1000_null_read_nvm;
55 nvm->ops.release = e1000_null_nvm_generic;
56 nvm->ops.reload = e1000_reload_nvm_generic;
57 nvm->ops.update = e1000_null_ops_generic;
58 nvm->ops.valid_led_default = e1000_null_led_default;
59 nvm->ops.validate = e1000_null_ops_generic;
60 nvm->ops.write = e1000_null_write_nvm;
64 * e1000_null_nvm_read - No-op function, return 0
65 * @hw: pointer to the HW structure
67 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
69 DEBUGFUNC("e1000_null_read_nvm");
74 * e1000_null_nvm_generic - No-op function, return void
75 * @hw: pointer to the HW structure
77 void e1000_null_nvm_generic(struct e1000_hw *hw)
79 DEBUGFUNC("e1000_null_nvm_generic");
84 * e1000_null_led_default - No-op function, return 0
85 * @hw: pointer to the HW structure
87 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
89 DEBUGFUNC("e1000_null_led_default");
94 * e1000_null_write_nvm - No-op function, return 0
95 * @hw: pointer to the HW structure
97 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
99 DEBUGFUNC("e1000_null_write_nvm");
100 return E1000_SUCCESS;
104 * e1000_raise_eec_clk - Raise EEPROM clock
105 * @hw: pointer to the HW structure
106 * @eecd: pointer to the EEPROM
108 * Enable/Raise the EEPROM clock bit.
110 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
112 *eecd = *eecd | E1000_EECD_SK;
113 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
114 E1000_WRITE_FLUSH(hw);
115 usec_delay(hw->nvm.delay_usec);
119 * e1000_lower_eec_clk - Lower EEPROM clock
120 * @hw: pointer to the HW structure
121 * @eecd: pointer to the EEPROM
123 * Clear/Lower the EEPROM clock bit.
125 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
127 *eecd = *eecd & ~E1000_EECD_SK;
128 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
129 E1000_WRITE_FLUSH(hw);
130 usec_delay(hw->nvm.delay_usec);
134 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
135 * @hw: pointer to the HW structure
136 * @data: data to send to the EEPROM
137 * @count: number of bits to shift out
139 * We need to shift 'count' bits out to the EEPROM. So, the value in the
140 * "data" parameter will be shifted out to the EEPROM one bit at a time.
141 * In order to do this, "data" must be broken down into bits.
143 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
145 struct e1000_nvm_info *nvm = &hw->nvm;
146 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
149 DEBUGFUNC("e1000_shift_out_eec_bits");
151 mask = 0x01 << (count - 1);
152 if (nvm->type == e1000_nvm_eeprom_microwire)
153 eecd &= ~E1000_EECD_DO;
155 if (nvm->type == e1000_nvm_eeprom_spi)
156 eecd |= E1000_EECD_DO;
159 eecd &= ~E1000_EECD_DI;
162 eecd |= E1000_EECD_DI;
164 E1000_WRITE_REG(hw, E1000_EECD, eecd);
165 E1000_WRITE_FLUSH(hw);
167 usec_delay(nvm->delay_usec);
169 e1000_raise_eec_clk(hw, &eecd);
170 e1000_lower_eec_clk(hw, &eecd);
175 eecd &= ~E1000_EECD_DI;
176 E1000_WRITE_REG(hw, E1000_EECD, eecd);
180 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
181 * @hw: pointer to the HW structure
182 * @count: number of bits to shift in
184 * In order to read a register from the EEPROM, we need to shift 'count' bits
185 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
186 * the EEPROM (setting the SK bit), and then reading the value of the data out
187 * "DO" bit. During this "shifting in" process the data in "DI" bit should
190 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
196 DEBUGFUNC("e1000_shift_in_eec_bits");
198 eecd = E1000_READ_REG(hw, E1000_EECD);
200 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
203 for (i = 0; i < count; i++) {
205 e1000_raise_eec_clk(hw, &eecd);
207 eecd = E1000_READ_REG(hw, E1000_EECD);
209 eecd &= ~E1000_EECD_DI;
210 if (eecd & E1000_EECD_DO)
213 e1000_lower_eec_clk(hw, &eecd);
220 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
221 * @hw: pointer to the HW structure
222 * @ee_reg: EEPROM flag for polling
224 * Polls the EEPROM status bit for either read or write completion based
225 * upon the value of 'ee_reg'.
227 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
229 u32 attempts = 100000;
231 s32 ret_val = -E1000_ERR_NVM;
233 DEBUGFUNC("e1000_poll_eerd_eewr_done");
235 for (i = 0; i < attempts; i++) {
236 if (ee_reg == E1000_NVM_POLL_READ)
237 reg = E1000_READ_REG(hw, E1000_EERD);
239 reg = E1000_READ_REG(hw, E1000_EEWR);
241 if (reg & E1000_NVM_RW_REG_DONE) {
242 ret_val = E1000_SUCCESS;
253 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
254 * @hw: pointer to the HW structure
256 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
257 * Return successful if access grant bit set, else clear the request for
258 * EEPROM access and return -E1000_ERR_NVM (-1).
260 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
262 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
263 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
264 s32 ret_val = E1000_SUCCESS;
266 DEBUGFUNC("e1000_acquire_nvm_generic");
268 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
269 eecd = E1000_READ_REG(hw, E1000_EECD);
272 if (eecd & E1000_EECD_GNT)
275 eecd = E1000_READ_REG(hw, E1000_EECD);
280 eecd &= ~E1000_EECD_REQ;
281 E1000_WRITE_REG(hw, E1000_EECD, eecd);
282 DEBUGOUT("Could not acquire NVM grant\n");
283 ret_val = -E1000_ERR_NVM;
290 * e1000_standby_nvm - Return EEPROM to standby state
291 * @hw: pointer to the HW structure
293 * Return the EEPROM to a standby state.
295 static void e1000_standby_nvm(struct e1000_hw *hw)
297 struct e1000_nvm_info *nvm = &hw->nvm;
298 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
300 DEBUGFUNC("e1000_standby_nvm");
302 if (nvm->type == e1000_nvm_eeprom_microwire) {
303 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
304 E1000_WRITE_REG(hw, E1000_EECD, eecd);
305 E1000_WRITE_FLUSH(hw);
306 usec_delay(nvm->delay_usec);
308 e1000_raise_eec_clk(hw, &eecd);
311 eecd |= E1000_EECD_CS;
312 E1000_WRITE_REG(hw, E1000_EECD, eecd);
313 E1000_WRITE_FLUSH(hw);
314 usec_delay(nvm->delay_usec);
316 e1000_lower_eec_clk(hw, &eecd);
318 if (nvm->type == e1000_nvm_eeprom_spi) {
319 /* Toggle CS to flush commands */
320 eecd |= E1000_EECD_CS;
321 E1000_WRITE_REG(hw, E1000_EECD, eecd);
322 E1000_WRITE_FLUSH(hw);
323 usec_delay(nvm->delay_usec);
324 eecd &= ~E1000_EECD_CS;
325 E1000_WRITE_REG(hw, E1000_EECD, eecd);
326 E1000_WRITE_FLUSH(hw);
327 usec_delay(nvm->delay_usec);
332 * e1000_stop_nvm - Terminate EEPROM command
333 * @hw: pointer to the HW structure
335 * Terminates the current command by inverting the EEPROM's chip select pin.
337 static void e1000_stop_nvm(struct e1000_hw *hw)
341 DEBUGFUNC("e1000_stop_nvm");
343 eecd = E1000_READ_REG(hw, E1000_EECD);
344 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
346 eecd |= E1000_EECD_CS;
347 e1000_lower_eec_clk(hw, &eecd);
348 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
349 /* CS on Microwire is active-high */
350 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
351 E1000_WRITE_REG(hw, E1000_EECD, eecd);
352 e1000_raise_eec_clk(hw, &eecd);
353 e1000_lower_eec_clk(hw, &eecd);
358 * e1000_release_nvm_generic - Release exclusive access to EEPROM
359 * @hw: pointer to the HW structure
361 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
363 void e1000_release_nvm_generic(struct e1000_hw *hw)
367 DEBUGFUNC("e1000_release_nvm_generic");
371 eecd = E1000_READ_REG(hw, E1000_EECD);
372 eecd &= ~E1000_EECD_REQ;
373 E1000_WRITE_REG(hw, E1000_EECD, eecd);
377 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
378 * @hw: pointer to the HW structure
380 * Setups the EEPROM for reading and writing.
382 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
384 struct e1000_nvm_info *nvm = &hw->nvm;
385 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
386 s32 ret_val = E1000_SUCCESS;
389 DEBUGFUNC("e1000_ready_nvm_eeprom");
391 if (nvm->type == e1000_nvm_eeprom_microwire) {
392 /* Clear SK and DI */
393 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
394 E1000_WRITE_REG(hw, E1000_EECD, eecd);
396 eecd |= E1000_EECD_CS;
397 E1000_WRITE_REG(hw, E1000_EECD, eecd);
399 if (nvm->type == e1000_nvm_eeprom_spi) {
400 u16 timeout = NVM_MAX_RETRY_SPI;
402 /* Clear SK and CS */
403 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
404 E1000_WRITE_REG(hw, E1000_EECD, eecd);
408 * Read "Status Register" repeatedly until the LSB is cleared.
409 * The EEPROM will signal that the command has been completed
410 * by clearing bit 0 of the internal status register. If it's
411 * not cleared within 'timeout', then error out.
414 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
415 hw->nvm.opcode_bits);
416 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
417 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
421 e1000_standby_nvm(hw);
426 DEBUGOUT("SPI NVM Status error\n");
427 ret_val = -E1000_ERR_NVM;
437 * e1000_read_nvm_spi - Read EEPROM's using SPI
438 * @hw: pointer to the HW structure
439 * @offset: offset of word in the EEPROM to read
440 * @words: number of words to read
441 * @data: word read from the EEPROM
443 * Reads a 16 bit word from the EEPROM.
445 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
447 struct e1000_nvm_info *nvm = &hw->nvm;
451 u8 read_opcode = NVM_READ_OPCODE_SPI;
453 DEBUGFUNC("e1000_read_nvm_spi");
456 * A check for invalid values: offset too large, too many words,
457 * and not enough words.
459 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
461 DEBUGOUT("nvm parameter(s) out of bounds\n");
462 ret_val = -E1000_ERR_NVM;
466 ret_val = nvm->ops.acquire(hw);
470 ret_val = e1000_ready_nvm_eeprom(hw);
474 e1000_standby_nvm(hw);
476 if ((nvm->address_bits == 8) && (offset >= 128))
477 read_opcode |= NVM_A8_OPCODE_SPI;
479 /* Send the READ command (opcode + addr) */
480 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
481 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
484 * Read the data. SPI NVMs increment the address with each byte
485 * read and will roll over if reading beyond the end. This allows
486 * us to read the whole NVM from any offset
488 for (i = 0; i < words; i++) {
489 word_in = e1000_shift_in_eec_bits(hw, 16);
490 data[i] = (word_in >> 8) | (word_in << 8);
494 nvm->ops.release(hw);
501 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
502 * @hw: pointer to the HW structure
503 * @offset: offset of word in the EEPROM to read
504 * @words: number of words to read
505 * @data: word read from the EEPROM
507 * Reads a 16 bit word from the EEPROM.
509 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
512 struct e1000_nvm_info *nvm = &hw->nvm;
515 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
517 DEBUGFUNC("e1000_read_nvm_microwire");
520 * A check for invalid values: offset too large, too many words,
521 * and not enough words.
523 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
525 DEBUGOUT("nvm parameter(s) out of bounds\n");
526 ret_val = -E1000_ERR_NVM;
530 ret_val = nvm->ops.acquire(hw);
534 ret_val = e1000_ready_nvm_eeprom(hw);
538 for (i = 0; i < words; i++) {
539 /* Send the READ command (opcode + addr) */
540 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
541 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
545 * Read the data. For microwire, each word requires the
546 * overhead of setup and tear-down.
548 data[i] = e1000_shift_in_eec_bits(hw, 16);
549 e1000_standby_nvm(hw);
553 nvm->ops.release(hw);
560 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
561 * @hw: pointer to the HW structure
562 * @offset: offset of word in the EEPROM to read
563 * @words: number of words to read
564 * @data: word read from the EEPROM
566 * Reads a 16 bit word from the EEPROM using the EERD register.
568 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
570 struct e1000_nvm_info *nvm = &hw->nvm;
572 s32 ret_val = E1000_SUCCESS;
574 DEBUGFUNC("e1000_read_nvm_eerd");
577 * A check for invalid values: offset too large, too many words,
578 * too many words for the offset, and not enough words.
580 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
582 DEBUGOUT("nvm parameter(s) out of bounds\n");
583 ret_val = -E1000_ERR_NVM;
587 for (i = 0; i < words; i++) {
588 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
589 E1000_NVM_RW_REG_START;
591 E1000_WRITE_REG(hw, E1000_EERD, eerd);
592 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
596 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
597 E1000_NVM_RW_REG_DATA);
605 * e1000_write_nvm_spi - Write to EEPROM using SPI
606 * @hw: pointer to the HW structure
607 * @offset: offset within the EEPROM to be written to
608 * @words: number of words to write
609 * @data: 16 bit word(s) to be written to the EEPROM
611 * Writes data to EEPROM at offset using SPI interface.
613 * If e1000_update_nvm_checksum is not called after this function , the
614 * EEPROM will most likely contain an invalid checksum.
616 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
618 struct e1000_nvm_info *nvm = &hw->nvm;
622 DEBUGFUNC("e1000_write_nvm_spi");
625 * A check for invalid values: offset too large, too many words,
626 * and not enough words.
628 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
630 DEBUGOUT("nvm parameter(s) out of bounds\n");
631 ret_val = -E1000_ERR_NVM;
635 ret_val = nvm->ops.acquire(hw);
639 while (widx < words) {
640 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
642 ret_val = e1000_ready_nvm_eeprom(hw);
646 e1000_standby_nvm(hw);
648 /* Send the WRITE ENABLE command (8 bit opcode) */
649 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
652 e1000_standby_nvm(hw);
655 * Some SPI eeproms use the 8th address bit embedded in the
658 if ((nvm->address_bits == 8) && (offset >= 128))
659 write_opcode |= NVM_A8_OPCODE_SPI;
661 /* Send the Write command (8-bit opcode + addr) */
662 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
663 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
666 /* Loop to allow for up to whole page write of eeprom */
667 while (widx < words) {
668 u16 word_out = data[widx];
669 word_out = (word_out >> 8) | (word_out << 8);
670 e1000_shift_out_eec_bits(hw, word_out, 16);
673 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
674 e1000_standby_nvm(hw);
682 nvm->ops.release(hw);
689 * e1000_write_nvm_microwire - Writes EEPROM using microwire
690 * @hw: pointer to the HW structure
691 * @offset: offset within the EEPROM to be written to
692 * @words: number of words to write
693 * @data: 16 bit word(s) to be written to the EEPROM
695 * Writes data to EEPROM at offset using microwire interface.
697 * If e1000_update_nvm_checksum is not called after this function , the
698 * EEPROM will most likely contain an invalid checksum.
700 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
703 struct e1000_nvm_info *nvm = &hw->nvm;
706 u16 words_written = 0;
709 DEBUGFUNC("e1000_write_nvm_microwire");
712 * A check for invalid values: offset too large, too many words,
713 * and not enough words.
715 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
717 DEBUGOUT("nvm parameter(s) out of bounds\n");
718 ret_val = -E1000_ERR_NVM;
722 ret_val = nvm->ops.acquire(hw);
726 ret_val = e1000_ready_nvm_eeprom(hw);
730 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
731 (u16)(nvm->opcode_bits + 2));
733 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
735 e1000_standby_nvm(hw);
737 while (words_written < words) {
738 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
741 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
744 e1000_shift_out_eec_bits(hw, data[words_written], 16);
746 e1000_standby_nvm(hw);
748 for (widx = 0; widx < 200; widx++) {
749 eecd = E1000_READ_REG(hw, E1000_EECD);
750 if (eecd & E1000_EECD_DO)
756 DEBUGOUT("NVM Write did not complete\n");
757 ret_val = -E1000_ERR_NVM;
761 e1000_standby_nvm(hw);
766 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
767 (u16)(nvm->opcode_bits + 2));
769 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
772 nvm->ops.release(hw);
779 * e1000_read_pba_string_generic - Read device part number
780 * @hw: pointer to the HW structure
781 * @pba_num: pointer to device part number
782 * @pba_num_size: size of part number buffer
784 * Reads the product board assembly (PBA) number from the EEPROM and stores
785 * the value in pba_num.
787 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
796 DEBUGFUNC("e1000_read_pba_string_generic");
798 if (pba_num == NULL) {
799 DEBUGOUT("PBA string buffer was null\n");
800 ret_val = E1000_ERR_INVALID_ARGUMENT;
804 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
806 DEBUGOUT("NVM Read Error\n");
810 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
812 DEBUGOUT("NVM Read Error\n");
817 * if nvm_data is not ptr guard the PBA must be in legacy format which
818 * means pba_ptr is actually our second data word for the PBA number
819 * and we can decode it into an ascii string
821 if (nvm_data != NVM_PBA_PTR_GUARD) {
822 DEBUGOUT("NVM PBA number is not stored as string\n");
824 /* we will need 11 characters to store the PBA */
825 if (pba_num_size < 11) {
826 DEBUGOUT("PBA string buffer too small\n");
827 return E1000_ERR_NO_SPACE;
830 /* extract hex string from data and pba_ptr */
831 pba_num[0] = (nvm_data >> 12) & 0xF;
832 pba_num[1] = (nvm_data >> 8) & 0xF;
833 pba_num[2] = (nvm_data >> 4) & 0xF;
834 pba_num[3] = nvm_data & 0xF;
835 pba_num[4] = (pba_ptr >> 12) & 0xF;
836 pba_num[5] = (pba_ptr >> 8) & 0xF;
839 pba_num[8] = (pba_ptr >> 4) & 0xF;
840 pba_num[9] = pba_ptr & 0xF;
842 /* put a null character on the end of our string */
845 /* switch all the data but the '-' to hex char */
846 for (offset = 0; offset < 10; offset++) {
847 if (pba_num[offset] < 0xA)
848 pba_num[offset] += '0';
849 else if (pba_num[offset] < 0x10)
850 pba_num[offset] += 'A' - 0xA;
856 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
858 DEBUGOUT("NVM Read Error\n");
862 if (length == 0xFFFF || length == 0) {
863 DEBUGOUT("NVM PBA number section invalid length\n");
864 ret_val = E1000_ERR_NVM_PBA_SECTION;
867 /* check if pba_num buffer is big enough */
868 if (pba_num_size < (((u32)length * 2) - 1)) {
869 DEBUGOUT("PBA string buffer too small\n");
870 ret_val = E1000_ERR_NO_SPACE;
874 /* trim pba length from start of string */
878 for (offset = 0; offset < length; offset++) {
879 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
881 DEBUGOUT("NVM Read Error\n");
884 pba_num[offset * 2] = (u8)(nvm_data >> 8);
885 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
887 pba_num[offset * 2] = '\0';
894 * e1000_read_pba_length_generic - Read device part number length
895 * @hw: pointer to the HW structure
896 * @pba_num_size: size of part number buffer
898 * Reads the product board assembly (PBA) number length from the EEPROM and
899 * stores the value in pba_num_size.
901 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
908 DEBUGFUNC("e1000_read_pba_length_generic");
910 if (pba_num_size == NULL) {
911 DEBUGOUT("PBA buffer size was null\n");
912 ret_val = E1000_ERR_INVALID_ARGUMENT;
916 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
918 DEBUGOUT("NVM Read Error\n");
922 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
924 DEBUGOUT("NVM Read Error\n");
928 /* if data is not ptr guard the PBA must be in legacy format */
929 if (nvm_data != NVM_PBA_PTR_GUARD) {
934 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
936 DEBUGOUT("NVM Read Error\n");
940 if (length == 0xFFFF || length == 0) {
941 DEBUGOUT("NVM PBA number section invalid length\n");
942 ret_val = E1000_ERR_NVM_PBA_SECTION;
947 * Convert from length in u16 values to u8 chars, add 1 for NULL,
948 * and subtract 2 because length field is included in length.
950 *pba_num_size = ((u32)length * 2) - 1;
957 * e1000_read_mac_addr_generic - Read device MAC address
958 * @hw: pointer to the HW structure
960 * Reads the device MAC address from the EEPROM and stores the value.
961 * Since devices with two ports use the same EEPROM, we increment the
962 * last bit in the MAC address for the second port.
964 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
970 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
971 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
973 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
974 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
976 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
977 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
979 for (i = 0; i < ETH_ADDR_LEN; i++)
980 hw->mac.addr[i] = hw->mac.perm_addr[i];
982 return E1000_SUCCESS;
986 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
987 * @hw: pointer to the HW structure
989 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
990 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
992 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
994 s32 ret_val = E1000_SUCCESS;
998 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1000 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1001 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1003 DEBUGOUT("NVM Read Error\n");
1006 checksum += nvm_data;
1009 if (checksum != (u16) NVM_SUM) {
1010 DEBUGOUT("NVM Checksum Invalid\n");
1011 ret_val = -E1000_ERR_NVM;
1020 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1021 * @hw: pointer to the HW structure
1023 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1024 * up to the checksum. Then calculates the EEPROM checksum and writes the
1025 * value to the EEPROM.
1027 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1033 DEBUGFUNC("e1000_update_nvm_checksum");
1035 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1036 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1038 DEBUGOUT("NVM Read Error while updating checksum.\n");
1041 checksum += nvm_data;
1043 checksum = (u16) NVM_SUM - checksum;
1044 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1046 DEBUGOUT("NVM Write Error while updating checksum.\n");
1053 * e1000_reload_nvm_generic - Reloads EEPROM
1054 * @hw: pointer to the HW structure
1056 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1057 * extended control register.
1059 static void e1000_reload_nvm_generic(struct e1000_hw *hw)
1063 DEBUGFUNC("e1000_reload_nvm_generic");
1066 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1067 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1068 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1069 E1000_WRITE_FLUSH(hw);