lib/librte_pmd_e1000/e1000/e1000_nvm.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "e1000_api.h"
  35
  36 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
  37
  38 /**
  39  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  40  *  @hw: pointer to the HW structure
  41  *
  42  *  Setups up the function pointers to no-op functions
  43  **/
  44 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  45 {
  46         struct e1000_nvm_info *nvm = &hw->nvm;
  47         DEBUGFUNC("e1000_init_nvm_ops_generic");
  48
  49         /* Initialize function pointers */
  50         nvm->ops.init_params = e1000_null_ops_generic;
  51         nvm->ops.acquire = e1000_null_ops_generic;
  52         nvm->ops.read = e1000_null_read_nvm;
  53         nvm->ops.release = e1000_null_nvm_generic;
  54         nvm->ops.reload = e1000_reload_nvm_generic;
  55         nvm->ops.update = e1000_null_ops_generic;
  56         nvm->ops.valid_led_default = e1000_null_led_default;
  57         nvm->ops.validate = e1000_null_ops_generic;
  58         nvm->ops.write = e1000_null_write_nvm;
  59 }
  60
  61 /**
  62  *  e1000_null_nvm_read - No-op function, return 0
  63  *  @hw: pointer to the HW structure
  64  **/
  65 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
  66 {
  67         DEBUGFUNC("e1000_null_read_nvm");
  68         return E1000_SUCCESS;
  69 }
  70
  71 /**
  72  *  e1000_null_nvm_generic - No-op function, return void
  73  *  @hw: pointer to the HW structure
  74  **/
  75 void e1000_null_nvm_generic(struct e1000_hw *hw)
  76 {
  77         DEBUGFUNC("e1000_null_nvm_generic");
  78         return;
  79 }
  80
  81 /**
  82  *  e1000_null_led_default - No-op function, return 0
  83  *  @hw: pointer to the HW structure
  84  **/
  85 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
  86 {
  87         DEBUGFUNC("e1000_null_led_default");
  88         return E1000_SUCCESS;
  89 }
  90
  91 /**
  92  *  e1000_null_write_nvm - No-op function, return 0
  93  *  @hw: pointer to the HW structure
  94  **/
  95 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
  96 {
  97         DEBUGFUNC("e1000_null_write_nvm");
  98         return E1000_SUCCESS;
  99 }
 100
 101 /**
 102  *  e1000_raise_eec_clk - Raise EEPROM clock
 103  *  @hw: pointer to the HW structure
 104  *  @eecd: pointer to the EEPROM
 105  *
 106  *  Enable/Raise the EEPROM clock bit.
 107  **/
 108 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
 109 {
 110         *eecd = *eecd | E1000_EECD_SK;
 111         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 112         E1000_WRITE_FLUSH(hw);
 113         usec_delay(hw->nvm.delay_usec);
 114 }
 115
 116 /**
 117  *  e1000_lower_eec_clk - Lower EEPROM clock
 118  *  @hw: pointer to the HW structure
 119  *  @eecd: pointer to the EEPROM
 120  *
 121  *  Clear/Lower the EEPROM clock bit.
 122  **/
 123 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 124 {
 125         *eecd = *eecd & ~E1000_EECD_SK;
 126         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 127         E1000_WRITE_FLUSH(hw);
 128         usec_delay(hw->nvm.delay_usec);
 129 }
 130
 131 /**
 132  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 133  *  @hw: pointer to the HW structure
 134  *  @data: data to send to the EEPROM
 135  *  @count: number of bits to shift out
 136  *
 137  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 138  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 139  *  In order to do this, "data" must be broken down into bits.
 140  **/
 141 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 142 {
 143         struct e1000_nvm_info *nvm = &hw->nvm;
 144         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 145         u32 mask;
 146
 147         DEBUGFUNC("e1000_shift_out_eec_bits");
 148
 149         mask = 0x01 << (count - 1);
 150         if (nvm->type == e1000_nvm_eeprom_microwire)
 151                 eecd &= ~E1000_EECD_DO;
 152         else
 153         if (nvm->type == e1000_nvm_eeprom_spi)
 154                 eecd |= E1000_EECD_DO;
 155
 156         do {
 157                 eecd &= ~E1000_EECD_DI;
 158
 159                 if (data & mask)
 160                         eecd |= E1000_EECD_DI;
 161
 162                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 163                 E1000_WRITE_FLUSH(hw);
 164
 165                 usec_delay(nvm->delay_usec);
 166
 167                 e1000_raise_eec_clk(hw, &eecd);
 168                 e1000_lower_eec_clk(hw, &eecd);
 169
 170                 mask >>= 1;
 171         } while (mask);
 172
 173         eecd &= ~E1000_EECD_DI;
 174         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 175 }
 176
 177 /**
 178  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 179  *  @hw: pointer to the HW structure
 180  *  @count: number of bits to shift in
 181  *
 182  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 183  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 184  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 185  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 186  *  always be clear.
 187  **/
 188 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 189 {
 190         u32 eecd;
 191         u32 i;
 192         u16 data;
 193
 194         DEBUGFUNC("e1000_shift_in_eec_bits");
 195
 196         eecd = E1000_READ_REG(hw, E1000_EECD);
 197
 198         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 199         data = 0;
 200
 201         for (i = 0; i < count; i++) {
 202                 data <<= 1;
 203                 e1000_raise_eec_clk(hw, &eecd);
 204
 205                 eecd = E1000_READ_REG(hw, E1000_EECD);
 206
 207                 eecd &= ~E1000_EECD_DI;
 208                 if (eecd & E1000_EECD_DO)
 209                         data |= 1;
 210
 211                 e1000_lower_eec_clk(hw, &eecd);
 212         }
 213
 214         return data;
 215 }
 216
 217 /**
 218  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 219  *  @hw: pointer to the HW structure
 220  *  @ee_reg: EEPROM flag for polling
 221  *
 222  *  Polls the EEPROM status bit for either read or write completion based
 223  *  upon the value of 'ee_reg'.
 224  **/
 225 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 226 {
 227         u32 attempts = 100000;
 228         u32 i, reg = 0;
 229
 230         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 231
 232         for (i = 0; i < attempts; i++) {
 233                 if (ee_reg == E1000_NVM_POLL_READ)
 234                         reg = E1000_READ_REG(hw, E1000_EERD);
 235                 else
 236                         reg = E1000_READ_REG(hw, E1000_EEWR);
 237
 238                 if (reg & E1000_NVM_RW_REG_DONE)
 239                         return E1000_SUCCESS;
 240
 241                 usec_delay(5);
 242         }
 243
 244         return -E1000_ERR_NVM;
 245 }
 246
 247 /**
 248  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 249  *  @hw: pointer to the HW structure
 250  *
 251  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 252  *  Return successful if access grant bit set, else clear the request for
 253  *  EEPROM access and return -E1000_ERR_NVM (-1).
 254  **/
 255 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 256 {
 257         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 258         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 259
 260         DEBUGFUNC("e1000_acquire_nvm_generic");
 261
 262         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 263         eecd = E1000_READ_REG(hw, E1000_EECD);
 264
 265         while (timeout) {
 266                 if (eecd & E1000_EECD_GNT)
 267                         break;
 268                 usec_delay(5);
 269                 eecd = E1000_READ_REG(hw, E1000_EECD);
 270                 timeout--;
 271         }
 272
 273         if (!timeout) {
 274                 eecd &= ~E1000_EECD_REQ;
 275                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 276                 DEBUGOUT("Could not acquire NVM grant\n");
 277                 return -E1000_ERR_NVM;
 278         }
 279
 280         return E1000_SUCCESS;
 281 }
 282
 283 /**
 284  *  e1000_standby_nvm - Return EEPROM to standby state
 285  *  @hw: pointer to the HW structure
 286  *
 287  *  Return the EEPROM to a standby state.
 288  **/
 289 static void e1000_standby_nvm(struct e1000_hw *hw)
 290 {
 291         struct e1000_nvm_info *nvm = &hw->nvm;
 292         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 293
 294         DEBUGFUNC("e1000_standby_nvm");
 295
 296         if (nvm->type == e1000_nvm_eeprom_microwire) {
 297                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 298                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 299                 E1000_WRITE_FLUSH(hw);
 300                 usec_delay(nvm->delay_usec);
 301
 302                 e1000_raise_eec_clk(hw, &eecd);
 303
 304                 /* Select EEPROM */
 305                 eecd |= E1000_EECD_CS;
 306                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 307                 E1000_WRITE_FLUSH(hw);
 308                 usec_delay(nvm->delay_usec);
 309
 310                 e1000_lower_eec_clk(hw, &eecd);
 311         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 312                 /* Toggle CS to flush commands */
 313                 eecd |= E1000_EECD_CS;
 314                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 315                 E1000_WRITE_FLUSH(hw);
 316                 usec_delay(nvm->delay_usec);
 317                 eecd &= ~E1000_EECD_CS;
 318                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 319                 E1000_WRITE_FLUSH(hw);
 320                 usec_delay(nvm->delay_usec);
 321         }
 322 }
 323
 324 /**
 325  *  e1000_stop_nvm - Terminate EEPROM command
 326  *  @hw: pointer to the HW structure
 327  *
 328  *  Terminates the current command by inverting the EEPROM's chip select pin.
 329  **/
 330 void e1000_stop_nvm(struct e1000_hw *hw)
 331 {
 332         u32 eecd;
 333
 334         DEBUGFUNC("e1000_stop_nvm");
 335
 336         eecd = E1000_READ_REG(hw, E1000_EECD);
 337         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 338                 /* Pull CS high */
 339                 eecd |= E1000_EECD_CS;
 340                 e1000_lower_eec_clk(hw, &eecd);
 341         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 342                 /* CS on Microwire is active-high */
 343                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 344                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 345                 e1000_raise_eec_clk(hw, &eecd);
 346                 e1000_lower_eec_clk(hw, &eecd);
 347         }
 348 }
 349
 350 /**
 351  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 352  *  @hw: pointer to the HW structure
 353  *
 354  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 355  **/
 356 void e1000_release_nvm_generic(struct e1000_hw *hw)
 357 {
 358         u32 eecd;
 359
 360         DEBUGFUNC("e1000_release_nvm_generic");
 361
 362         e1000_stop_nvm(hw);
 363
 364         eecd = E1000_READ_REG(hw, E1000_EECD);
 365         eecd &= ~E1000_EECD_REQ;
 366         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 367 }
 368
 369 /**
 370  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 371  *  @hw: pointer to the HW structure
 372  *
 373  *  Setups the EEPROM for reading and writing.
 374  **/
 375 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 376 {
 377         struct e1000_nvm_info *nvm = &hw->nvm;
 378         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 379         u8 spi_stat_reg;
 380
 381         DEBUGFUNC("e1000_ready_nvm_eeprom");
 382
 383         if (nvm->type == e1000_nvm_eeprom_microwire) {
 384                 /* Clear SK and DI */
 385                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 386                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 387                 /* Set CS */
 388                 eecd |= E1000_EECD_CS;
 389                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 390         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 391                 u16 timeout = NVM_MAX_RETRY_SPI;
 392
 393                 /* Clear SK and CS */
 394                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 395                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 396                 E1000_WRITE_FLUSH(hw);
 397                 usec_delay(1);
 398
 399                 /* Read "Status Register" repeatedly until the LSB is cleared.
 400                  * The EEPROM will signal that the command has been completed
 401                  * by clearing bit 0 of the internal status register.  If it's
 402                  * not cleared within 'timeout', then error out.
 403                  */
 404                 while (timeout) {
 405                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 406                                                  hw->nvm.opcode_bits);
 407                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 408                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 409                                 break;
 410
 411                         usec_delay(5);
 412                         e1000_standby_nvm(hw);
 413                         timeout--;
 414                 }
 415
 416                 if (!timeout) {
 417                         DEBUGOUT("SPI NVM Status error\n");
 418                         return -E1000_ERR_NVM;
 419                 }
 420         }
 421
 422         return E1000_SUCCESS;
 423 }
 424
 425 /**
 426  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 427  *  @hw: pointer to the HW structure
 428  *  @offset: offset of word in the EEPROM to read
 429  *  @words: number of words to read
 430  *  @data: word read from the EEPROM
 431  *
 432  *  Reads a 16 bit word from the EEPROM.
 433  **/
 434 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 435 {
 436         struct e1000_nvm_info *nvm = &hw->nvm;
 437         u32 i = 0;
 438         s32 ret_val;
 439         u16 word_in;
 440         u8 read_opcode = NVM_READ_OPCODE_SPI;
 441
 442         DEBUGFUNC("e1000_read_nvm_spi");
 443
 444         /* A check for invalid values:  offset too large, too many words,
 445          * and not enough words.
 446          */
 447         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 448             (words == 0)) {
 449                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 450                 return -E1000_ERR_NVM;
 451         }
 452
 453         ret_val = nvm->ops.acquire(hw);
 454         if (ret_val)
 455                 return ret_val;
 456
 457         ret_val = e1000_ready_nvm_eeprom(hw);
 458         if (ret_val)
 459                 goto release;
 460
 461         e1000_standby_nvm(hw);
 462
 463         if ((nvm->address_bits == 8) && (offset >= 128))
 464                 read_opcode |= NVM_A8_OPCODE_SPI;
 465
 466         /* Send the READ command (opcode + addr) */
 467         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 468         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 469
 470         /* Read the data.  SPI NVMs increment the address with each byte
 471          * read and will roll over if reading beyond the end.  This allows
 472          * us to read the whole NVM from any offset
 473          */
 474         for (i = 0; i < words; i++) {
 475                 word_in = e1000_shift_in_eec_bits(hw, 16);
 476                 data[i] = (word_in >> 8) | (word_in << 8);
 477         }
 478
 479 release:
 480         nvm->ops.release(hw);
 481
 482         return ret_val;
 483 }
 484
 485 /**
 486  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 487  *  @hw: pointer to the HW structure
 488  *  @offset: offset of word in the EEPROM to read
 489  *  @words: number of words to read
 490  *  @data: word read from the EEPROM
 491  *
 492  *  Reads a 16 bit word from the EEPROM.
 493  **/
 494 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 495                              u16 *data)
 496 {
 497         struct e1000_nvm_info *nvm = &hw->nvm;
 498         u32 i = 0;
 499         s32 ret_val;
 500         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 501
 502         DEBUGFUNC("e1000_read_nvm_microwire");
 503
 504         /* A check for invalid values:  offset too large, too many words,
 505          * and not enough words.
 506          */
 507         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 508             (words == 0)) {
 509                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 510                 return -E1000_ERR_NVM;
 511         }
 512
 513         ret_val = nvm->ops.acquire(hw);
 514         if (ret_val)
 515                 return ret_val;
 516
 517         ret_val = e1000_ready_nvm_eeprom(hw);
 518         if (ret_val)
 519                 goto release;
 520
 521         for (i = 0; i < words; i++) {
 522                 /* Send the READ command (opcode + addr) */
 523                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 524                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 525                                         nvm->address_bits);
 526
 527                 /* Read the data.  For microwire, each word requires the
 528                  * overhead of setup and tear-down.
 529                  */
 530                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 531                 e1000_standby_nvm(hw);
 532         }
 533
 534 release:
 535         nvm->ops.release(hw);
 536
 537         return ret_val;
 538 }
 539
 540 /**
 541  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 542  *  @hw: pointer to the HW structure
 543  *  @offset: offset of word in the EEPROM to read
 544  *  @words: number of words to read
 545  *  @data: word read from the EEPROM
 546  *
 547  *  Reads a 16 bit word from the EEPROM using the EERD register.
 548  **/
 549 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 550 {
 551         struct e1000_nvm_info *nvm = &hw->nvm;
 552         u32 i, eerd = 0;
 553         s32 ret_val = E1000_SUCCESS;
 554
 555         DEBUGFUNC("e1000_read_nvm_eerd");
 556
 557         /* A check for invalid values:  offset too large, too many words,
 558          * too many words for the offset, and not enough words.
 559          */
 560         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 561             (words == 0)) {
 562                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 563                 return -E1000_ERR_NVM;
 564         }
 565
 566         for (i = 0; i < words; i++) {
 567                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 568                        E1000_NVM_RW_REG_START;
 569
 570                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 571                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 572                 if (ret_val)
 573                         break;
 574
 575                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 576                            E1000_NVM_RW_REG_DATA);
 577         }
 578
 579         return ret_val;
 580 }
 581
 582 /**
 583  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 584  *  @hw: pointer to the HW structure
 585  *  @offset: offset within the EEPROM to be written to
 586  *  @words: number of words to write
 587  *  @data: 16 bit word(s) to be written to the EEPROM
 588  *
 589  *  Writes data to EEPROM at offset using SPI interface.
 590  *
 591  *  If e1000_update_nvm_checksum is not called after this function , the
 592  *  EEPROM will most likely contain an invalid checksum.
 593  **/
 594 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 595 {
 596         struct e1000_nvm_info *nvm = &hw->nvm;
 597         s32 ret_val = -E1000_ERR_NVM;
 598         u16 widx = 0;
 599
 600         DEBUGFUNC("e1000_write_nvm_spi");
 601
 602         /* A check for invalid values:  offset too large, too many words,
 603          * and not enough words.
 604          */
 605         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 606             (words == 0)) {
 607                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 608                 return -E1000_ERR_NVM;
 609         }
 610
 611         while (widx < words) {
 612                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 613
 614                 ret_val = nvm->ops.acquire(hw);
 615                 if (ret_val)
 616                         return ret_val;
 617
 618                 ret_val = e1000_ready_nvm_eeprom(hw);
 619                 if (ret_val) {
 620                         nvm->ops.release(hw);
 621                         return ret_val;
 622                 }
 623
 624                 e1000_standby_nvm(hw);
 625
 626                 /* Send the WRITE ENABLE command (8 bit opcode) */
 627                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 628                                          nvm->opcode_bits);
 629
 630                 e1000_standby_nvm(hw);
 631
 632                 /* Some SPI eeproms use the 8th address bit embedded in the
 633                  * opcode
 634                  */
 635                 if ((nvm->address_bits == 8) && (offset >= 128))
 636                         write_opcode |= NVM_A8_OPCODE_SPI;
 637
 638                 /* Send the Write command (8-bit opcode + addr) */
 639                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 640                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 641                                          nvm->address_bits);
 642
 643                 /* Loop to allow for up to whole page write of eeprom */
 644                 while (widx < words) {
 645                         u16 word_out = data[widx];
 646                         word_out = (word_out >> 8) | (word_out << 8);
 647                         e1000_shift_out_eec_bits(hw, word_out, 16);
 648                         widx++;
 649
 650                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 651                                 e1000_standby_nvm(hw);
 652                                 break;
 653                         }
 654                 }
 655                 msec_delay(10);
 656                 nvm->ops.release(hw);
 657         }
 658
 659         return ret_val;
 660 }
 661
 662 /**
 663  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 664  *  @hw: pointer to the HW structure
 665  *  @offset: offset within the EEPROM to be written to
 666  *  @words: number of words to write
 667  *  @data: 16 bit word(s) to be written to the EEPROM
 668  *
 669  *  Writes data to EEPROM at offset using microwire interface.
 670  *
 671  *  If e1000_update_nvm_checksum is not called after this function , the
 672  *  EEPROM will most likely contain an invalid checksum.
 673  **/
 674 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 675                               u16 *data)
 676 {
 677         struct e1000_nvm_info *nvm = &hw->nvm;
 678         s32  ret_val;
 679         u32 eecd;
 680         u16 words_written = 0;
 681         u16 widx = 0;
 682
 683         DEBUGFUNC("e1000_write_nvm_microwire");
 684
 685         /* A check for invalid values:  offset too large, too many words,
 686          * and not enough words.
 687          */
 688         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 689             (words == 0)) {
 690                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 691                 return -E1000_ERR_NVM;
 692         }
 693
 694         ret_val = nvm->ops.acquire(hw);
 695         if (ret_val)
 696                 return ret_val;
 697
 698         ret_val = e1000_ready_nvm_eeprom(hw);
 699         if (ret_val)
 700                 goto release;
 701
 702         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 703                                  (u16)(nvm->opcode_bits + 2));
 704
 705         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 706
 707         e1000_standby_nvm(hw);
 708
 709         while (words_written < words) {
 710                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 711                                          nvm->opcode_bits);
 712
 713                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 714                                          nvm->address_bits);
 715
 716                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 717
 718                 e1000_standby_nvm(hw);
 719
 720                 for (widx = 0; widx < 200; widx++) {
 721                         eecd = E1000_READ_REG(hw, E1000_EECD);
 722                         if (eecd & E1000_EECD_DO)
 723                                 break;
 724                         usec_delay(50);
 725                 }
 726
 727                 if (widx == 200) {
 728                         DEBUGOUT("NVM Write did not complete\n");
 729                         ret_val = -E1000_ERR_NVM;
 730                         goto release;
 731                 }
 732
 733                 e1000_standby_nvm(hw);
 734
 735                 words_written++;
 736         }
 737
 738         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 739                                  (u16)(nvm->opcode_bits + 2));
 740
 741         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 742
 743 release:
 744         nvm->ops.release(hw);
 745
 746         return ret_val;
 747 }
 748
 749 /**
 750  *  e1000_read_pba_string_generic - Read device part number
 751  *  @hw: pointer to the HW structure
 752  *  @pba_num: pointer to device part number
 753  *  @pba_num_size: size of part number buffer
 754  *
 755  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 756  *  the value in pba_num.
 757  **/
 758 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 759                                   u32 pba_num_size)
 760 {
 761         s32 ret_val;
 762         u16 nvm_data;
 763         u16 pba_ptr;
 764         u16 offset;
 765         u16 length;
 766
 767         DEBUGFUNC("e1000_read_pba_string_generic");
 768
 769         if (pba_num == NULL) {
 770                 DEBUGOUT("PBA string buffer was null\n");
 771                 return -E1000_ERR_INVALID_ARGUMENT;
 772         }
 773
 774         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 775         if (ret_val) {
 776                 DEBUGOUT("NVM Read Error\n");
 777                 return ret_val;
 778         }
 779
 780         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 781         if (ret_val) {
 782                 DEBUGOUT("NVM Read Error\n");
 783                 return ret_val;
 784         }
 785
 786         /* if nvm_data is not ptr guard the PBA must be in legacy format which
 787          * means pba_ptr is actually our second data word for the PBA number
 788          * and we can decode it into an ascii string
 789          */
 790         if (nvm_data != NVM_PBA_PTR_GUARD) {
 791                 DEBUGOUT("NVM PBA number is not stored as string\n");
 792
 793                 /* make sure callers buffer is big enough to store the PBA */
 794                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 795                         DEBUGOUT("PBA string buffer too small\n");
 796                         return E1000_ERR_NO_SPACE;
 797                 }
 798
 799                 /* extract hex string from data and pba_ptr */
 800                 pba_num[0] = (nvm_data >> 12) & 0xF;
 801                 pba_num[1] = (nvm_data >> 8) & 0xF;
 802                 pba_num[2] = (nvm_data >> 4) & 0xF;
 803                 pba_num[3] = nvm_data & 0xF;
 804                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 805                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 806                 pba_num[6] = '-';
 807                 pba_num[7] = 0;
 808                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 809                 pba_num[9] = pba_ptr & 0xF;
 810
 811                 /* put a null character on the end of our string */
 812                 pba_num[10] = '\0';
 813
 814                 /* switch all the data but the '-' to hex char */
 815                 for (offset = 0; offset < 10; offset++) {
 816                         if (pba_num[offset] < 0xA)
 817                                 pba_num[offset] += '0';
 818                         else if (pba_num[offset] < 0x10)
 819                                 pba_num[offset] += 'A' - 0xA;
 820                 }
 821
 822                 return E1000_SUCCESS;
 823         }
 824
 825         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 826         if (ret_val) {
 827                 DEBUGOUT("NVM Read Error\n");
 828                 return ret_val;
 829         }
 830
 831         if (length == 0xFFFF || length == 0) {
 832                 DEBUGOUT("NVM PBA number section invalid length\n");
 833                 return -E1000_ERR_NVM_PBA_SECTION;
 834         }
 835         /* check if pba_num buffer is big enough */
 836         if (pba_num_size < (((u32)length * 2) - 1)) {
 837                 DEBUGOUT("PBA string buffer too small\n");
 838                 return -E1000_ERR_NO_SPACE;
 839         }
 840
 841         /* trim pba length from start of string */
 842         pba_ptr++;
 843         length--;
 844
 845         for (offset = 0; offset < length; offset++) {
 846                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 847                 if (ret_val) {
 848                         DEBUGOUT("NVM Read Error\n");
 849                         return ret_val;
 850                 }
 851                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 852                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 853         }
 854         pba_num[offset * 2] = '\0';
 855
 856         return E1000_SUCCESS;
 857 }
 858
 859 /**
 860  *  e1000_read_pba_length_generic - Read device part number length
 861  *  @hw: pointer to the HW structure
 862  *  @pba_num_size: size of part number buffer
 863  *
 864  *  Reads the product board assembly (PBA) number length from the EEPROM and
 865  *  stores the value in pba_num_size.
 866  **/
 867 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 868 {
 869         s32 ret_val;
 870         u16 nvm_data;
 871         u16 pba_ptr;
 872         u16 length;
 873
 874         DEBUGFUNC("e1000_read_pba_length_generic");
 875
 876         if (pba_num_size == NULL) {
 877                 DEBUGOUT("PBA buffer size was null\n");
 878                 return -E1000_ERR_INVALID_ARGUMENT;
 879         }
 880
 881         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 882         if (ret_val) {
 883                 DEBUGOUT("NVM Read Error\n");
 884                 return ret_val;
 885         }
 886
 887         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 888         if (ret_val) {
 889                 DEBUGOUT("NVM Read Error\n");
 890                 return ret_val;
 891         }
 892
 893          /* if data is not ptr guard the PBA must be in legacy format */
 894         if (nvm_data != NVM_PBA_PTR_GUARD) {
 895                 *pba_num_size = E1000_PBANUM_LENGTH;
 896                 return E1000_SUCCESS;
 897         }
 898
 899         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 900         if (ret_val) {
 901                 DEBUGOUT("NVM Read Error\n");
 902                 return ret_val;
 903         }
 904
 905         if (length == 0xFFFF || length == 0) {
 906                 DEBUGOUT("NVM PBA number section invalid length\n");
 907                 return -E1000_ERR_NVM_PBA_SECTION;
 908         }
 909
 910         /* Convert from length in u16 values to u8 chars, add 1 for NULL,
 911          * and subtract 2 because length field is included in length.
 912          */
 913         *pba_num_size = ((u32)length * 2) - 1;
 914
 915         return E1000_SUCCESS;
 916 }
 917
 918
 919 /**
 920  *  e1000_read_pba_raw
 921  *  @hw: pointer to the HW structure
 922  *  @eeprom_buf: optional pointer to EEPROM image
 923  *  @eeprom_buf_size: size of EEPROM image in words
 924  *  @max_pba_block_size: PBA block size limit
 925  *  @pba: pointer to output PBA structure
 926  *
 927  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 928  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 929  *
 930  **/
 931 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 932                        u32 eeprom_buf_size, u16 max_pba_block_size,
 933                        struct e1000_pba *pba)
 934 {
 935         s32 ret_val;
 936         u16 pba_block_size;
 937
 938         if (pba == NULL)
 939                 return -E1000_ERR_PARAM;
 940
 941         if (eeprom_buf == NULL) {
 942                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 943                                          &pba->word[0]);
 944                 if (ret_val)
 945                         return ret_val;
 946         } else {
 947                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
 948                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
 949                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
 950                 } else {
 951                         return -E1000_ERR_PARAM;
 952                 }
 953         }
 954
 955         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
 956                 if (pba->pba_block == NULL)
 957                         return -E1000_ERR_PARAM;
 958
 959                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
 960                                                    eeprom_buf_size,
 961                                                    &pba_block_size);
 962                 if (ret_val)
 963                         return ret_val;
 964
 965                 if (pba_block_size > max_pba_block_size)
 966                         return -E1000_ERR_PARAM;
 967
 968                 if (eeprom_buf == NULL) {
 969                         ret_val = e1000_read_nvm(hw, pba->word[1],
 970                                                  pba_block_size,
 971                                                  pba->pba_block);
 972                         if (ret_val)
 973                                 return ret_val;
 974                 } else {
 975                         if (eeprom_buf_size > (u32)(pba->word[1] +
 976                                               pba->pba_block[0])) {
 977                                 memcpy(pba->pba_block,
 978                                        &eeprom_buf[pba->word[1]],
 979                                        pba_block_size * sizeof(u16));
 980                         } else {
 981                                 return -E1000_ERR_PARAM;
 982                         }
 983                 }
 984         }
 985
 986         return E1000_SUCCESS;
 987 }
 988
 989 /**
 990  *  e1000_write_pba_raw
 991  *  @hw: pointer to the HW structure
 992  *  @eeprom_buf: optional pointer to EEPROM image
 993  *  @eeprom_buf_size: size of EEPROM image in words
 994  *  @pba: pointer to PBA structure
 995  *
 996  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
 997  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
 998  *
 999  **/
1000 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1001                         u32 eeprom_buf_size, struct e1000_pba *pba)
1002 {
1003         s32 ret_val;
1004
1005         if (pba == NULL)
1006                 return -E1000_ERR_PARAM;
1007
1008         if (eeprom_buf == NULL) {
1009                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1010                                           &pba->word[0]);
1011                 if (ret_val)
1012                         return ret_val;
1013         } else {
1014                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1015                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1016                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1017                 } else {
1018                         return -E1000_ERR_PARAM;
1019                 }
1020         }
1021
1022         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1023                 if (pba->pba_block == NULL)
1024                         return -E1000_ERR_PARAM;
1025
1026                 if (eeprom_buf == NULL) {
1027                         ret_val = e1000_write_nvm(hw, pba->word[1],
1028                                                   pba->pba_block[0],
1029                                                   pba->pba_block);
1030                         if (ret_val)
1031                                 return ret_val;
1032                 } else {
1033                         if (eeprom_buf_size > (u32)(pba->word[1] +
1034                                               pba->pba_block[0])) {
1035                                 memcpy(&eeprom_buf[pba->word[1]],
1036                                        pba->pba_block,
1037                                        pba->pba_block[0] * sizeof(u16));
1038                         } else {
1039                                 return -E1000_ERR_PARAM;
1040                         }
1041                 }
1042         }
1043
1044         return E1000_SUCCESS;
1045 }
1046
1047 /**
1048  *  e1000_get_pba_block_size
1049  *  @hw: pointer to the HW structure
1050  *  @eeprom_buf: optional pointer to EEPROM image
1051  *  @eeprom_buf_size: size of EEPROM image in words
1052  *  @pba_data_size: pointer to output variable
1053  *
1054  *  Returns the size of the PBA block in words. Function operates on EEPROM
1055  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1056  *  EEPROM device.
1057  *
1058  **/
1059 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1060                              u32 eeprom_buf_size, u16 *pba_block_size)
1061 {
1062         s32 ret_val;
1063         u16 pba_word[2];
1064         u16 length;
1065
1066         DEBUGFUNC("e1000_get_pba_block_size");
1067
1068         if (eeprom_buf == NULL) {
1069                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1070                 if (ret_val)
1071                         return ret_val;
1072         } else {
1073                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1074                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1075                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1076                 } else {
1077                         return -E1000_ERR_PARAM;
1078                 }
1079         }
1080
1081         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1082                 if (eeprom_buf == NULL) {
1083                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1084                                                  &length);
1085                         if (ret_val)
1086                                 return ret_val;
1087                 } else {
1088                         if (eeprom_buf_size > pba_word[1])
1089                                 length = eeprom_buf[pba_word[1] + 0];
1090                         else
1091                                 return -E1000_ERR_PARAM;
1092                 }
1093
1094                 if (length == 0xFFFF || length == 0)
1095                         return -E1000_ERR_NVM_PBA_SECTION;
1096         } else {
1097                 /* PBA number in legacy format, there is no PBA Block. */
1098                 length = 0;
1099         }
1100
1101         if (pba_block_size != NULL)
1102                 *pba_block_size = length;
1103
1104         return E1000_SUCCESS;
1105 }
1106
1107 /**
1108  *  e1000_read_mac_addr_generic - Read device MAC address
1109  *  @hw: pointer to the HW structure
1110  *
1111  *  Reads the device MAC address from the EEPROM and stores the value.
1112  *  Since devices with two ports use the same EEPROM, we increment the
1113  *  last bit in the MAC address for the second port.
1114  **/
1115 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1116 {
1117         u32 rar_high;
1118         u32 rar_low;
1119         u16 i;
1120
1121         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1122         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1123
1124         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1125                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1126
1127         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1128                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1129
1130         for (i = 0; i < ETH_ADDR_LEN; i++)
1131                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1132
1133         return E1000_SUCCESS;
1134 }
1135
1136 /**
1137  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1138  *  @hw: pointer to the HW structure
1139  *
1140  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1141  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1142  **/
1143 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1144 {
1145         s32 ret_val;
1146         u16 checksum = 0;
1147         u16 i, nvm_data;
1148
1149         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1150
1151         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1152                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1153                 if (ret_val) {
1154                         DEBUGOUT("NVM Read Error\n");
1155                         return ret_val;
1156                 }
1157                 checksum += nvm_data;
1158         }
1159
1160         if (checksum != (u16) NVM_SUM) {
1161                 DEBUGOUT("NVM Checksum Invalid\n");
1162                 return -E1000_ERR_NVM;
1163         }
1164
1165         return E1000_SUCCESS;
1166 }
1167
1168 /**
1169  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1170  *  @hw: pointer to the HW structure
1171  *
1172  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1173  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1174  *  value to the EEPROM.
1175  **/
1176 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1177 {
1178         s32 ret_val;
1179         u16 checksum = 0;
1180         u16 i, nvm_data;
1181
1182         DEBUGFUNC("e1000_update_nvm_checksum");
1183
1184         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1185                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1186                 if (ret_val) {
1187                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1188                         return ret_val;
1189                 }
1190                 checksum += nvm_data;
1191         }
1192         checksum = (u16) NVM_SUM - checksum;
1193         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1194         if (ret_val)
1195                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1196
1197         return ret_val;
1198 }
1199
1200 /**
1201  *  e1000_reload_nvm_generic - Reloads EEPROM
1202  *  @hw: pointer to the HW structure
1203  *
1204  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1205  *  extended control register.
1206  **/
1207 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1208 {
1209         u32 ctrl_ext;
1210
1211         DEBUGFUNC("e1000_reload_nvm_generic");
1212
1213         usec_delay(10);
1214         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1215         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1216         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1217         E1000_WRITE_FLUSH(hw);
1218 }
1219
1220 /**
1221  *  e1000_get_fw_version - Get firmware version information
1222  *  @hw: pointer to the HW structure
1223  *  @fw_vers: pointer to output version structure
1224  *
1225  *  unsupported/not present features return 0 in version structure
1226  **/
1227 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1228 {
1229         u16 eeprom_verh, eeprom_verl, fw_version;
1230         u16 comb_verh, comb_verl, comb_offset;
1231
1232         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1233
1234         /* this code only applies to certain mac types */
1235         switch (hw->mac.type) {
1236         case e1000_i211:
1237                 e1000_read_invm_version(hw, fw_vers);
1238                 return;
1239         case e1000_82575:
1240         case e1000_82576:
1241         case e1000_82580:
1242         case e1000_i350:
1243         case e1000_i210:
1244                 break;
1245         default:
1246                 return;
1247         }
1248
1249         /* basic eeprom version numbers */
1250         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1251         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
1252         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK);
1253
1254         /* etrack id */
1255         hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1256         hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1257         fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl;
1258
1259         switch (hw->mac.type) {
1260         case e1000_i210:
1261         case e1000_i350:
1262                 /* find combo image version */
1263                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1264                 if ((comb_offset != 0x0) &&
1265                     (comb_offset != NVM_VER_INVALID)) {
1266
1267                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1268                                          + 1), 1, &comb_verh);
1269                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1270                                          1, &comb_verl);
1271
1272                         /* get Option Rom version if it exists and is valid */
1273                         if ((comb_verh && comb_verl) &&
1274                             ((comb_verh != NVM_VER_INVALID) &&
1275                              (comb_verl != NVM_VER_INVALID))) {
1276
1277                                 fw_vers->or_valid = true;
1278                                 fw_vers->or_major =
1279                                         comb_verl >> NVM_COMB_VER_SHFT;
1280                                 fw_vers->or_build =
1281                                         (comb_verl << NVM_COMB_VER_SHFT)
1282                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1283                                 fw_vers->or_patch =
1284                                         comb_verh & NVM_COMB_VER_MASK;
1285                         }
1286                 }
1287                 break;
1288
1289         default:
1290                 break;
1291         }
1292         return;
1293 }
1294
1295