1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
39 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
40 * @hw: pointer to the HW structure
42 * Setups up the function pointers to no-op functions
44 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
46 struct e1000_nvm_info *nvm = &hw->nvm;
47 DEBUGFUNC("e1000_init_nvm_ops_generic");
49 /* Initialize function pointers */
50 nvm->ops.init_params = e1000_null_ops_generic;
51 nvm->ops.acquire = e1000_null_ops_generic;
52 nvm->ops.read = e1000_null_read_nvm;
53 nvm->ops.release = e1000_null_nvm_generic;
54 nvm->ops.reload = e1000_reload_nvm_generic;
55 nvm->ops.update = e1000_null_ops_generic;
56 nvm->ops.valid_led_default = e1000_null_led_default;
57 nvm->ops.validate = e1000_null_ops_generic;
58 nvm->ops.write = e1000_null_write_nvm;
62 * e1000_null_nvm_read - No-op function, return 0
63 * @hw: pointer to the HW structure
65 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
66 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
67 u16 E1000_UNUSEDARG *c)
69 DEBUGFUNC("e1000_null_read_nvm");
70 UNREFERENCED_4PARAMETER(hw, a, b, c);
75 * e1000_null_nvm_generic - No-op function, return void
76 * @hw: pointer to the HW structure
78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
80 DEBUGFUNC("e1000_null_nvm_generic");
81 UNREFERENCED_1PARAMETER(hw);
86 * e1000_null_led_default - No-op function, return 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
90 u16 E1000_UNUSEDARG *data)
92 DEBUGFUNC("e1000_null_led_default");
93 UNREFERENCED_2PARAMETER(hw, data);
98 * e1000_null_write_nvm - No-op function, return 0
99 * @hw: pointer to the HW structure
101 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
102 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
103 u16 E1000_UNUSEDARG *c)
105 DEBUGFUNC("e1000_null_write_nvm");
106 UNREFERENCED_4PARAMETER(hw, a, b, c);
107 return E1000_SUCCESS;
111 * e1000_raise_eec_clk - Raise EEPROM clock
112 * @hw: pointer to the HW structure
113 * @eecd: pointer to the EEPROM
115 * Enable/Raise the EEPROM clock bit.
117 STATIC void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
119 *eecd = *eecd | E1000_EECD_SK;
120 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
121 E1000_WRITE_FLUSH(hw);
122 usec_delay(hw->nvm.delay_usec);
126 * e1000_lower_eec_clk - Lower EEPROM clock
127 * @hw: pointer to the HW structure
128 * @eecd: pointer to the EEPROM
130 * Clear/Lower the EEPROM clock bit.
132 STATIC void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
134 *eecd = *eecd & ~E1000_EECD_SK;
135 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
136 E1000_WRITE_FLUSH(hw);
137 usec_delay(hw->nvm.delay_usec);
141 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
142 * @hw: pointer to the HW structure
143 * @data: data to send to the EEPROM
144 * @count: number of bits to shift out
146 * We need to shift 'count' bits out to the EEPROM. So, the value in the
147 * "data" parameter will be shifted out to the EEPROM one bit at a time.
148 * In order to do this, "data" must be broken down into bits.
150 STATIC void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
152 struct e1000_nvm_info *nvm = &hw->nvm;
153 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
156 DEBUGFUNC("e1000_shift_out_eec_bits");
158 mask = 0x01 << (count - 1);
159 if (nvm->type == e1000_nvm_eeprom_microwire)
160 eecd &= ~E1000_EECD_DO;
162 if (nvm->type == e1000_nvm_eeprom_spi)
163 eecd |= E1000_EECD_DO;
166 eecd &= ~E1000_EECD_DI;
169 eecd |= E1000_EECD_DI;
171 E1000_WRITE_REG(hw, E1000_EECD, eecd);
172 E1000_WRITE_FLUSH(hw);
174 usec_delay(nvm->delay_usec);
176 e1000_raise_eec_clk(hw, &eecd);
177 e1000_lower_eec_clk(hw, &eecd);
182 eecd &= ~E1000_EECD_DI;
183 E1000_WRITE_REG(hw, E1000_EECD, eecd);
187 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
188 * @hw: pointer to the HW structure
189 * @count: number of bits to shift in
191 * In order to read a register from the EEPROM, we need to shift 'count' bits
192 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
193 * the EEPROM (setting the SK bit), and then reading the value of the data out
194 * "DO" bit. During this "shifting in" process the data in "DI" bit should
197 STATIC u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
203 DEBUGFUNC("e1000_shift_in_eec_bits");
205 eecd = E1000_READ_REG(hw, E1000_EECD);
207 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
210 for (i = 0; i < count; i++) {
212 e1000_raise_eec_clk(hw, &eecd);
214 eecd = E1000_READ_REG(hw, E1000_EECD);
216 eecd &= ~E1000_EECD_DI;
217 if (eecd & E1000_EECD_DO)
220 e1000_lower_eec_clk(hw, &eecd);
227 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
228 * @hw: pointer to the HW structure
229 * @ee_reg: EEPROM flag for polling
231 * Polls the EEPROM status bit for either read or write completion based
232 * upon the value of 'ee_reg'.
234 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
236 u32 attempts = 100000;
239 DEBUGFUNC("e1000_poll_eerd_eewr_done");
241 for (i = 0; i < attempts; i++) {
242 if (ee_reg == E1000_NVM_POLL_READ)
243 reg = E1000_READ_REG(hw, E1000_EERD);
245 reg = E1000_READ_REG(hw, E1000_EEWR);
247 if (reg & E1000_NVM_RW_REG_DONE)
248 return E1000_SUCCESS;
253 return -E1000_ERR_NVM;
257 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
258 * @hw: pointer to the HW structure
260 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
261 * Return successful if access grant bit set, else clear the request for
262 * EEPROM access and return -E1000_ERR_NVM (-1).
264 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
266 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
267 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
269 DEBUGFUNC("e1000_acquire_nvm_generic");
271 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
272 eecd = E1000_READ_REG(hw, E1000_EECD);
275 if (eecd & E1000_EECD_GNT)
278 eecd = E1000_READ_REG(hw, E1000_EECD);
283 eecd &= ~E1000_EECD_REQ;
284 E1000_WRITE_REG(hw, E1000_EECD, eecd);
285 DEBUGOUT("Could not acquire NVM grant\n");
286 return -E1000_ERR_NVM;
289 return E1000_SUCCESS;
293 * e1000_standby_nvm - Return EEPROM to standby state
294 * @hw: pointer to the HW structure
296 * Return the EEPROM to a standby state.
298 STATIC void e1000_standby_nvm(struct e1000_hw *hw)
300 struct e1000_nvm_info *nvm = &hw->nvm;
301 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
303 DEBUGFUNC("e1000_standby_nvm");
305 if (nvm->type == e1000_nvm_eeprom_microwire) {
306 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
307 E1000_WRITE_REG(hw, E1000_EECD, eecd);
308 E1000_WRITE_FLUSH(hw);
309 usec_delay(nvm->delay_usec);
311 e1000_raise_eec_clk(hw, &eecd);
314 eecd |= E1000_EECD_CS;
315 E1000_WRITE_REG(hw, E1000_EECD, eecd);
316 E1000_WRITE_FLUSH(hw);
317 usec_delay(nvm->delay_usec);
319 e1000_lower_eec_clk(hw, &eecd);
320 } else if (nvm->type == e1000_nvm_eeprom_spi) {
321 /* Toggle CS to flush commands */
322 eecd |= E1000_EECD_CS;
323 E1000_WRITE_REG(hw, E1000_EECD, eecd);
324 E1000_WRITE_FLUSH(hw);
325 usec_delay(nvm->delay_usec);
326 eecd &= ~E1000_EECD_CS;
327 E1000_WRITE_REG(hw, E1000_EECD, eecd);
328 E1000_WRITE_FLUSH(hw);
329 usec_delay(nvm->delay_usec);
334 * e1000_stop_nvm - Terminate EEPROM command
335 * @hw: pointer to the HW structure
337 * Terminates the current command by inverting the EEPROM's chip select pin.
339 void e1000_stop_nvm(struct e1000_hw *hw)
343 DEBUGFUNC("e1000_stop_nvm");
345 eecd = E1000_READ_REG(hw, E1000_EECD);
346 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
348 eecd |= E1000_EECD_CS;
349 e1000_lower_eec_clk(hw, &eecd);
350 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
351 /* CS on Microwire is active-high */
352 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
353 E1000_WRITE_REG(hw, E1000_EECD, eecd);
354 e1000_raise_eec_clk(hw, &eecd);
355 e1000_lower_eec_clk(hw, &eecd);
360 * e1000_release_nvm_generic - Release exclusive access to EEPROM
361 * @hw: pointer to the HW structure
363 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
365 void e1000_release_nvm_generic(struct e1000_hw *hw)
369 DEBUGFUNC("e1000_release_nvm_generic");
373 eecd = E1000_READ_REG(hw, E1000_EECD);
374 eecd &= ~E1000_EECD_REQ;
375 E1000_WRITE_REG(hw, E1000_EECD, eecd);
379 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
380 * @hw: pointer to the HW structure
382 * Setups the EEPROM for reading and writing.
384 STATIC s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
386 struct e1000_nvm_info *nvm = &hw->nvm;
387 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
390 DEBUGFUNC("e1000_ready_nvm_eeprom");
392 if (nvm->type == e1000_nvm_eeprom_microwire) {
393 /* Clear SK and DI */
394 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
395 E1000_WRITE_REG(hw, E1000_EECD, eecd);
397 eecd |= E1000_EECD_CS;
398 E1000_WRITE_REG(hw, E1000_EECD, eecd);
399 } else if (nvm->type == e1000_nvm_eeprom_spi) {
400 u16 timeout = NVM_MAX_RETRY_SPI;
402 /* Clear SK and CS */
403 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
404 E1000_WRITE_REG(hw, E1000_EECD, eecd);
405 E1000_WRITE_FLUSH(hw);
408 /* Read "Status Register" repeatedly until the LSB is cleared.
409 * The EEPROM will signal that the command has been completed
410 * by clearing bit 0 of the internal status register. If it's
411 * not cleared within 'timeout', then error out.
414 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
415 hw->nvm.opcode_bits);
416 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
417 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
421 e1000_standby_nvm(hw);
426 DEBUGOUT("SPI NVM Status error\n");
427 return -E1000_ERR_NVM;
431 return E1000_SUCCESS;
435 * e1000_read_nvm_spi - Read EEPROM's using SPI
436 * @hw: pointer to the HW structure
437 * @offset: offset of word in the EEPROM to read
438 * @words: number of words to read
439 * @data: word read from the EEPROM
441 * Reads a 16 bit word from the EEPROM.
443 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
445 struct e1000_nvm_info *nvm = &hw->nvm;
449 u8 read_opcode = NVM_READ_OPCODE_SPI;
451 DEBUGFUNC("e1000_read_nvm_spi");
453 /* A check for invalid values: offset too large, too many words,
454 * and not enough words.
456 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
458 DEBUGOUT("nvm parameter(s) out of bounds\n");
459 return -E1000_ERR_NVM;
462 ret_val = nvm->ops.acquire(hw);
466 ret_val = e1000_ready_nvm_eeprom(hw);
470 e1000_standby_nvm(hw);
472 if ((nvm->address_bits == 8) && (offset >= 128))
473 read_opcode |= NVM_A8_OPCODE_SPI;
475 /* Send the READ command (opcode + addr) */
476 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
477 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
479 /* Read the data. SPI NVMs increment the address with each byte
480 * read and will roll over if reading beyond the end. This allows
481 * us to read the whole NVM from any offset
483 for (i = 0; i < words; i++) {
484 word_in = e1000_shift_in_eec_bits(hw, 16);
485 data[i] = (word_in >> 8) | (word_in << 8);
489 nvm->ops.release(hw);
495 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
496 * @hw: pointer to the HW structure
497 * @offset: offset of word in the EEPROM to read
498 * @words: number of words to read
499 * @data: word read from the EEPROM
501 * Reads a 16 bit word from the EEPROM.
503 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
506 struct e1000_nvm_info *nvm = &hw->nvm;
509 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
511 DEBUGFUNC("e1000_read_nvm_microwire");
513 /* A check for invalid values: offset too large, too many words,
514 * and not enough words.
516 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
518 DEBUGOUT("nvm parameter(s) out of bounds\n");
519 return -E1000_ERR_NVM;
522 ret_val = nvm->ops.acquire(hw);
526 ret_val = e1000_ready_nvm_eeprom(hw);
530 for (i = 0; i < words; i++) {
531 /* Send the READ command (opcode + addr) */
532 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
533 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
536 /* Read the data. For microwire, each word requires the
537 * overhead of setup and tear-down.
539 data[i] = e1000_shift_in_eec_bits(hw, 16);
540 e1000_standby_nvm(hw);
544 nvm->ops.release(hw);
550 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
551 * @hw: pointer to the HW structure
552 * @offset: offset of word in the EEPROM to read
553 * @words: number of words to read
554 * @data: word read from the EEPROM
556 * Reads a 16 bit word from the EEPROM using the EERD register.
558 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
560 struct e1000_nvm_info *nvm = &hw->nvm;
562 s32 ret_val = E1000_SUCCESS;
564 DEBUGFUNC("e1000_read_nvm_eerd");
566 /* A check for invalid values: offset too large, too many words,
567 * too many words for the offset, and not enough words.
569 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
571 DEBUGOUT("nvm parameter(s) out of bounds\n");
572 return -E1000_ERR_NVM;
575 for (i = 0; i < words; i++) {
576 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
577 E1000_NVM_RW_REG_START;
579 E1000_WRITE_REG(hw, E1000_EERD, eerd);
580 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
584 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
585 E1000_NVM_RW_REG_DATA);
592 * e1000_write_nvm_spi - Write to EEPROM using SPI
593 * @hw: pointer to the HW structure
594 * @offset: offset within the EEPROM to be written to
595 * @words: number of words to write
596 * @data: 16 bit word(s) to be written to the EEPROM
598 * Writes data to EEPROM at offset using SPI interface.
600 * If e1000_update_nvm_checksum is not called after this function , the
601 * EEPROM will most likely contain an invalid checksum.
603 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
605 struct e1000_nvm_info *nvm = &hw->nvm;
606 s32 ret_val = -E1000_ERR_NVM;
609 DEBUGFUNC("e1000_write_nvm_spi");
611 /* A check for invalid values: offset too large, too many words,
612 * and not enough words.
614 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
616 DEBUGOUT("nvm parameter(s) out of bounds\n");
617 return -E1000_ERR_NVM;
620 while (widx < words) {
621 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
623 ret_val = nvm->ops.acquire(hw);
627 ret_val = e1000_ready_nvm_eeprom(hw);
629 nvm->ops.release(hw);
633 e1000_standby_nvm(hw);
635 /* Send the WRITE ENABLE command (8 bit opcode) */
636 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
639 e1000_standby_nvm(hw);
641 /* Some SPI eeproms use the 8th address bit embedded in the
644 if ((nvm->address_bits == 8) && (offset >= 128))
645 write_opcode |= NVM_A8_OPCODE_SPI;
647 /* Send the Write command (8-bit opcode + addr) */
648 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
649 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
652 /* Loop to allow for up to whole page write of eeprom */
653 while (widx < words) {
654 u16 word_out = data[widx];
655 word_out = (word_out >> 8) | (word_out << 8);
656 e1000_shift_out_eec_bits(hw, word_out, 16);
659 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
660 e1000_standby_nvm(hw);
665 nvm->ops.release(hw);
672 * e1000_write_nvm_microwire - Writes EEPROM using microwire
673 * @hw: pointer to the HW structure
674 * @offset: offset within the EEPROM to be written to
675 * @words: number of words to write
676 * @data: 16 bit word(s) to be written to the EEPROM
678 * Writes data to EEPROM at offset using microwire interface.
680 * If e1000_update_nvm_checksum is not called after this function , the
681 * EEPROM will most likely contain an invalid checksum.
683 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
686 struct e1000_nvm_info *nvm = &hw->nvm;
689 u16 words_written = 0;
692 DEBUGFUNC("e1000_write_nvm_microwire");
694 /* A check for invalid values: offset too large, too many words,
695 * and not enough words.
697 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
699 DEBUGOUT("nvm parameter(s) out of bounds\n");
700 return -E1000_ERR_NVM;
703 ret_val = nvm->ops.acquire(hw);
707 ret_val = e1000_ready_nvm_eeprom(hw);
711 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
712 (u16)(nvm->opcode_bits + 2));
714 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
716 e1000_standby_nvm(hw);
718 while (words_written < words) {
719 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
722 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
725 e1000_shift_out_eec_bits(hw, data[words_written], 16);
727 e1000_standby_nvm(hw);
729 for (widx = 0; widx < 200; widx++) {
730 eecd = E1000_READ_REG(hw, E1000_EECD);
731 if (eecd & E1000_EECD_DO)
737 DEBUGOUT("NVM Write did not complete\n");
738 ret_val = -E1000_ERR_NVM;
742 e1000_standby_nvm(hw);
747 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
748 (u16)(nvm->opcode_bits + 2));
750 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
753 nvm->ops.release(hw);
759 * e1000_read_pba_string_generic - Read device part number
760 * @hw: pointer to the HW structure
761 * @pba_num: pointer to device part number
762 * @pba_num_size: size of part number buffer
764 * Reads the product board assembly (PBA) number from the EEPROM and stores
765 * the value in pba_num.
767 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
776 DEBUGFUNC("e1000_read_pba_string_generic");
778 if ((hw->mac.type >= e1000_i210) &&
779 !e1000_get_flash_presence_i210(hw)) {
780 DEBUGOUT("Flashless no PBA string\n");
781 return -E1000_ERR_NVM_PBA_SECTION;
784 if (pba_num == NULL) {
785 DEBUGOUT("PBA string buffer was null\n");
786 return -E1000_ERR_INVALID_ARGUMENT;
789 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
791 DEBUGOUT("NVM Read Error\n");
795 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
797 DEBUGOUT("NVM Read Error\n");
801 /* if nvm_data is not ptr guard the PBA must be in legacy format which
802 * means pba_ptr is actually our second data word for the PBA number
803 * and we can decode it into an ascii string
805 if (nvm_data != NVM_PBA_PTR_GUARD) {
806 DEBUGOUT("NVM PBA number is not stored as string\n");
808 /* make sure callers buffer is big enough to store the PBA */
809 if (pba_num_size < E1000_PBANUM_LENGTH) {
810 DEBUGOUT("PBA string buffer too small\n");
811 return E1000_ERR_NO_SPACE;
814 /* extract hex string from data and pba_ptr */
815 pba_num[0] = (nvm_data >> 12) & 0xF;
816 pba_num[1] = (nvm_data >> 8) & 0xF;
817 pba_num[2] = (nvm_data >> 4) & 0xF;
818 pba_num[3] = nvm_data & 0xF;
819 pba_num[4] = (pba_ptr >> 12) & 0xF;
820 pba_num[5] = (pba_ptr >> 8) & 0xF;
823 pba_num[8] = (pba_ptr >> 4) & 0xF;
824 pba_num[9] = pba_ptr & 0xF;
826 /* put a null character on the end of our string */
829 /* switch all the data but the '-' to hex char */
830 for (offset = 0; offset < 10; offset++) {
831 if (pba_num[offset] < 0xA)
832 pba_num[offset] += '0';
833 else if (pba_num[offset] < 0x10)
834 pba_num[offset] += 'A' - 0xA;
837 return E1000_SUCCESS;
840 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
842 DEBUGOUT("NVM Read Error\n");
846 if (length == 0xFFFF || length == 0) {
847 DEBUGOUT("NVM PBA number section invalid length\n");
848 return -E1000_ERR_NVM_PBA_SECTION;
850 /* check if pba_num buffer is big enough */
851 if (pba_num_size < (((u32)length * 2) - 1)) {
852 DEBUGOUT("PBA string buffer too small\n");
853 return -E1000_ERR_NO_SPACE;
856 /* trim pba length from start of string */
860 for (offset = 0; offset < length; offset++) {
861 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
863 DEBUGOUT("NVM Read Error\n");
866 pba_num[offset * 2] = (u8)(nvm_data >> 8);
867 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
869 pba_num[offset * 2] = '\0';
871 return E1000_SUCCESS;
875 * e1000_read_pba_length_generic - Read device part number length
876 * @hw: pointer to the HW structure
877 * @pba_num_size: size of part number buffer
879 * Reads the product board assembly (PBA) number length from the EEPROM and
880 * stores the value in pba_num_size.
882 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
889 DEBUGFUNC("e1000_read_pba_length_generic");
891 if (pba_num_size == NULL) {
892 DEBUGOUT("PBA buffer size was null\n");
893 return -E1000_ERR_INVALID_ARGUMENT;
896 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
898 DEBUGOUT("NVM Read Error\n");
902 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
904 DEBUGOUT("NVM Read Error\n");
908 /* if data is not ptr guard the PBA must be in legacy format */
909 if (nvm_data != NVM_PBA_PTR_GUARD) {
910 *pba_num_size = E1000_PBANUM_LENGTH;
911 return E1000_SUCCESS;
914 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
916 DEBUGOUT("NVM Read Error\n");
920 if (length == 0xFFFF || length == 0) {
921 DEBUGOUT("NVM PBA number section invalid length\n");
922 return -E1000_ERR_NVM_PBA_SECTION;
925 /* Convert from length in u16 values to u8 chars, add 1 for NULL,
926 * and subtract 2 because length field is included in length.
928 *pba_num_size = ((u32)length * 2) - 1;
930 return E1000_SUCCESS;
934 * e1000_read_pba_num_generic - Read device part number
935 * @hw: pointer to the HW structure
936 * @pba_num: pointer to device part number
938 * Reads the product board assembly (PBA) number from the EEPROM and stores
939 * the value in pba_num.
941 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
946 DEBUGFUNC("e1000_read_pba_num_generic");
948 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
950 DEBUGOUT("NVM Read Error\n");
952 } else if (nvm_data == NVM_PBA_PTR_GUARD) {
953 DEBUGOUT("NVM Not Supported\n");
954 return -E1000_NOT_IMPLEMENTED;
956 *pba_num = (u32)(nvm_data << 16);
958 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
960 DEBUGOUT("NVM Read Error\n");
963 *pba_num |= nvm_data;
965 return E1000_SUCCESS;
971 * @hw: pointer to the HW structure
972 * @eeprom_buf: optional pointer to EEPROM image
973 * @eeprom_buf_size: size of EEPROM image in words
974 * @max_pba_block_size: PBA block size limit
975 * @pba: pointer to output PBA structure
977 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
978 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
981 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
982 u32 eeprom_buf_size, u16 max_pba_block_size,
983 struct e1000_pba *pba)
989 return -E1000_ERR_PARAM;
991 if (eeprom_buf == NULL) {
992 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
997 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
998 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
999 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1001 return -E1000_ERR_PARAM;
1005 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1006 if (pba->pba_block == NULL)
1007 return -E1000_ERR_PARAM;
1009 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1015 if (pba_block_size > max_pba_block_size)
1016 return -E1000_ERR_PARAM;
1018 if (eeprom_buf == NULL) {
1019 ret_val = e1000_read_nvm(hw, pba->word[1],
1025 if (eeprom_buf_size > (u32)(pba->word[1] +
1027 memcpy(pba->pba_block,
1028 &eeprom_buf[pba->word[1]],
1029 pba_block_size * sizeof(u16));
1031 return -E1000_ERR_PARAM;
1036 return E1000_SUCCESS;
1040 * e1000_write_pba_raw
1041 * @hw: pointer to the HW structure
1042 * @eeprom_buf: optional pointer to EEPROM image
1043 * @eeprom_buf_size: size of EEPROM image in words
1044 * @pba: pointer to PBA structure
1046 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
1047 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1050 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1051 u32 eeprom_buf_size, struct e1000_pba *pba)
1056 return -E1000_ERR_PARAM;
1058 if (eeprom_buf == NULL) {
1059 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1064 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1065 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1066 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1068 return -E1000_ERR_PARAM;
1072 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1073 if (pba->pba_block == NULL)
1074 return -E1000_ERR_PARAM;
1076 if (eeprom_buf == NULL) {
1077 ret_val = e1000_write_nvm(hw, pba->word[1],
1083 if (eeprom_buf_size > (u32)(pba->word[1] +
1084 pba->pba_block[0])) {
1085 memcpy(&eeprom_buf[pba->word[1]],
1087 pba->pba_block[0] * sizeof(u16));
1089 return -E1000_ERR_PARAM;
1094 return E1000_SUCCESS;
1098 * e1000_get_pba_block_size
1099 * @hw: pointer to the HW structure
1100 * @eeprom_buf: optional pointer to EEPROM image
1101 * @eeprom_buf_size: size of EEPROM image in words
1102 * @pba_data_size: pointer to output variable
1104 * Returns the size of the PBA block in words. Function operates on EEPROM
1105 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1109 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1110 u32 eeprom_buf_size, u16 *pba_block_size)
1116 DEBUGFUNC("e1000_get_pba_block_size");
1118 if (eeprom_buf == NULL) {
1119 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1123 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1124 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1125 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1127 return -E1000_ERR_PARAM;
1131 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1132 if (eeprom_buf == NULL) {
1133 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1138 if (eeprom_buf_size > pba_word[1])
1139 length = eeprom_buf[pba_word[1] + 0];
1141 return -E1000_ERR_PARAM;
1144 if (length == 0xFFFF || length == 0)
1145 return -E1000_ERR_NVM_PBA_SECTION;
1147 /* PBA number in legacy format, there is no PBA Block. */
1151 if (pba_block_size != NULL)
1152 *pba_block_size = length;
1154 return E1000_SUCCESS;
1158 * e1000_read_mac_addr_generic - Read device MAC address
1159 * @hw: pointer to the HW structure
1161 * Reads the device MAC address from the EEPROM and stores the value.
1162 * Since devices with two ports use the same EEPROM, we increment the
1163 * last bit in the MAC address for the second port.
1165 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1171 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1172 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1174 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1175 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1177 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1178 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1180 for (i = 0; i < ETH_ADDR_LEN; i++)
1181 hw->mac.addr[i] = hw->mac.perm_addr[i];
1183 return E1000_SUCCESS;
1187 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1188 * @hw: pointer to the HW structure
1190 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1191 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1193 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1199 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1201 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1202 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1204 DEBUGOUT("NVM Read Error\n");
1207 checksum += nvm_data;
1210 if (checksum != (u16) NVM_SUM) {
1211 DEBUGOUT("NVM Checksum Invalid\n");
1212 return -E1000_ERR_NVM;
1215 return E1000_SUCCESS;
1219 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1220 * @hw: pointer to the HW structure
1222 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1223 * up to the checksum. Then calculates the EEPROM checksum and writes the
1224 * value to the EEPROM.
1226 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1232 DEBUGFUNC("e1000_update_nvm_checksum");
1234 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1235 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1237 DEBUGOUT("NVM Read Error while updating checksum.\n");
1240 checksum += nvm_data;
1242 checksum = (u16) NVM_SUM - checksum;
1243 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1245 DEBUGOUT("NVM Write Error while updating checksum.\n");
1251 * e1000_reload_nvm_generic - Reloads EEPROM
1252 * @hw: pointer to the HW structure
1254 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1255 * extended control register.
1257 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1261 DEBUGFUNC("e1000_reload_nvm_generic");
1264 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1265 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1266 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1267 E1000_WRITE_FLUSH(hw);
1271 * e1000_get_fw_version - Get firmware version information
1272 * @hw: pointer to the HW structure
1273 * @fw_vers: pointer to output version structure
1275 * unsupported/not present features return 0 in version structure
1277 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1279 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1280 u8 q, hval, rem, result;
1281 u16 comb_verh, comb_verl, comb_offset;
1283 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1285 /* basic eeprom version numbers, bits used vary by part and by tool
1286 * used to create the nvm images */
1287 /* Check which data format we have */
1288 switch (hw->mac.type) {
1290 e1000_read_invm_version(hw, fw_vers);
1295 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1296 /* Use this format, unless EETRACK ID exists,
1297 * then use alternate format
1299 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1300 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1301 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1303 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1305 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1310 if (!(e1000_get_flash_presence_i210(hw))) {
1311 e1000_read_invm_version(hw, fw_vers);
1316 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1317 /* find combo image version */
1318 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1319 if ((comb_offset != 0x0) &&
1320 (comb_offset != NVM_VER_INVALID)) {
1322 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1323 + 1), 1, &comb_verh);
1324 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1327 /* get Option Rom version if it exists and is valid */
1328 if ((comb_verh && comb_verl) &&
1329 ((comb_verh != NVM_VER_INVALID) &&
1330 (comb_verl != NVM_VER_INVALID))) {
1332 fw_vers->or_valid = true;
1334 comb_verl >> NVM_COMB_VER_SHFT;
1336 (comb_verl << NVM_COMB_VER_SHFT)
1337 | (comb_verh >> NVM_COMB_VER_SHFT);
1339 comb_verh & NVM_COMB_VER_MASK;
1344 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1347 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1348 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1351 /* check for old style version format in newer images*/
1352 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1353 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1355 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1358 /* Convert minor value to hex before assigning to output struct
1359 * Val to be converted will not be higher than 99, per tool output
1361 q = eeprom_verl / NVM_HEX_CONV;
1362 hval = q * NVM_HEX_TENS;
1363 rem = eeprom_verl % NVM_HEX_CONV;
1364 result = hval + rem;
1365 fw_vers->eep_minor = result;
1368 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1369 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1370 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1371 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)