lib/librte_pmd_e1000/e1000/e1000_nvm.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "e1000_api.h"
  35
  36 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
  37
  38 /**
  39  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  40  *  @hw: pointer to the HW structure
  41  *
  42  *  Setups up the function pointers to no-op functions
  43  **/
  44 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  45 {
  46         struct e1000_nvm_info *nvm = &hw->nvm;
  47         DEBUGFUNC("e1000_init_nvm_ops_generic");
  48
  49         /* Initialize function pointers */
  50         nvm->ops.init_params = e1000_null_ops_generic;
  51         nvm->ops.acquire = e1000_null_ops_generic;
  52         nvm->ops.read = e1000_null_read_nvm;
  53         nvm->ops.release = e1000_null_nvm_generic;
  54         nvm->ops.reload = e1000_reload_nvm_generic;
  55         nvm->ops.update = e1000_null_ops_generic;
  56         nvm->ops.valid_led_default = e1000_null_led_default;
  57         nvm->ops.validate = e1000_null_ops_generic;
  58         nvm->ops.write = e1000_null_write_nvm;
  59 }
  60
  61 /**
  62  *  e1000_null_nvm_read - No-op function, return 0
  63  *  @hw: pointer to the HW structure
  64  **/
  65 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
  66 {
  67         DEBUGFUNC("e1000_null_read_nvm");
  68         return E1000_SUCCESS;
  69 }
  70
  71 /**
  72  *  e1000_null_nvm_generic - No-op function, return void
  73  *  @hw: pointer to the HW structure
  74  **/
  75 void e1000_null_nvm_generic(struct e1000_hw *hw)
  76 {
  77         DEBUGFUNC("e1000_null_nvm_generic");
  78         return;
  79 }
  80
  81 /**
  82  *  e1000_null_led_default - No-op function, return 0
  83  *  @hw: pointer to the HW structure
  84  **/
  85 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
  86 {
  87         DEBUGFUNC("e1000_null_led_default");
  88         return E1000_SUCCESS;
  89 }
  90
  91 /**
  92  *  e1000_null_write_nvm - No-op function, return 0
  93  *  @hw: pointer to the HW structure
  94  **/
  95 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
  96 {
  97         DEBUGFUNC("e1000_null_write_nvm");
  98         return E1000_SUCCESS;
  99 }
 100
 101 /**
 102  *  e1000_raise_eec_clk - Raise EEPROM clock
 103  *  @hw: pointer to the HW structure
 104  *  @eecd: pointer to the EEPROM
 105  *
 106  *  Enable/Raise the EEPROM clock bit.
 107  **/
 108 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
 109 {
 110         *eecd = *eecd | E1000_EECD_SK;
 111         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 112         E1000_WRITE_FLUSH(hw);
 113         usec_delay(hw->nvm.delay_usec);
 114 }
 115
 116 /**
 117  *  e1000_lower_eec_clk - Lower EEPROM clock
 118  *  @hw: pointer to the HW structure
 119  *  @eecd: pointer to the EEPROM
 120  *
 121  *  Clear/Lower the EEPROM clock bit.
 122  **/
 123 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 124 {
 125         *eecd = *eecd & ~E1000_EECD_SK;
 126         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 127         E1000_WRITE_FLUSH(hw);
 128         usec_delay(hw->nvm.delay_usec);
 129 }
 130
 131 /**
 132  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 133  *  @hw: pointer to the HW structure
 134  *  @data: data to send to the EEPROM
 135  *  @count: number of bits to shift out
 136  *
 137  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 138  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 139  *  In order to do this, "data" must be broken down into bits.
 140  **/
 141 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 142 {
 143         struct e1000_nvm_info *nvm = &hw->nvm;
 144         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 145         u32 mask;
 146
 147         DEBUGFUNC("e1000_shift_out_eec_bits");
 148
 149         mask = 0x01 << (count - 1);
 150         if (nvm->type == e1000_nvm_eeprom_microwire)
 151                 eecd &= ~E1000_EECD_DO;
 152         else
 153         if (nvm->type == e1000_nvm_eeprom_spi)
 154                 eecd |= E1000_EECD_DO;
 155
 156         do {
 157                 eecd &= ~E1000_EECD_DI;
 158
 159                 if (data & mask)
 160                         eecd |= E1000_EECD_DI;
 161
 162                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 163                 E1000_WRITE_FLUSH(hw);
 164
 165                 usec_delay(nvm->delay_usec);
 166
 167                 e1000_raise_eec_clk(hw, &eecd);
 168                 e1000_lower_eec_clk(hw, &eecd);
 169
 170                 mask >>= 1;
 171         } while (mask);
 172
 173         eecd &= ~E1000_EECD_DI;
 174         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 175 }
 176
 177 /**
 178  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 179  *  @hw: pointer to the HW structure
 180  *  @count: number of bits to shift in
 181  *
 182  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 183  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 184  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 185  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 186  *  always be clear.
 187  **/
 188 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 189 {
 190         u32 eecd;
 191         u32 i;
 192         u16 data;
 193
 194         DEBUGFUNC("e1000_shift_in_eec_bits");
 195
 196         eecd = E1000_READ_REG(hw, E1000_EECD);
 197
 198         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 199         data = 0;
 200
 201         for (i = 0; i < count; i++) {
 202                 data <<= 1;
 203                 e1000_raise_eec_clk(hw, &eecd);
 204
 205                 eecd = E1000_READ_REG(hw, E1000_EECD);
 206
 207                 eecd &= ~E1000_EECD_DI;
 208                 if (eecd & E1000_EECD_DO)
 209                         data |= 1;
 210
 211                 e1000_lower_eec_clk(hw, &eecd);
 212         }
 213
 214         return data;
 215 }
 216
 217 /**
 218  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 219  *  @hw: pointer to the HW structure
 220  *  @ee_reg: EEPROM flag for polling
 221  *
 222  *  Polls the EEPROM status bit for either read or write completion based
 223  *  upon the value of 'ee_reg'.
 224  **/
 225 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 226 {
 227         u32 attempts = 100000;
 228         u32 i, reg = 0;
 229
 230         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 231
 232         for (i = 0; i < attempts; i++) {
 233                 if (ee_reg == E1000_NVM_POLL_READ)
 234                         reg = E1000_READ_REG(hw, E1000_EERD);
 235                 else
 236                         reg = E1000_READ_REG(hw, E1000_EEWR);
 237
 238                 if (reg & E1000_NVM_RW_REG_DONE)
 239                         return E1000_SUCCESS;
 240
 241                 usec_delay(5);
 242         }
 243
 244         return -E1000_ERR_NVM;
 245 }
 246
 247 /**
 248  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 249  *  @hw: pointer to the HW structure
 250  *
 251  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 252  *  Return successful if access grant bit set, else clear the request for
 253  *  EEPROM access and return -E1000_ERR_NVM (-1).
 254  **/
 255 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 256 {
 257         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 258         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 259
 260         DEBUGFUNC("e1000_acquire_nvm_generic");
 261
 262         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 263         eecd = E1000_READ_REG(hw, E1000_EECD);
 264
 265         while (timeout) {
 266                 if (eecd & E1000_EECD_GNT)
 267                         break;
 268                 usec_delay(5);
 269                 eecd = E1000_READ_REG(hw, E1000_EECD);
 270                 timeout--;
 271         }
 272
 273         if (!timeout) {
 274                 eecd &= ~E1000_EECD_REQ;
 275                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 276                 DEBUGOUT("Could not acquire NVM grant\n");
 277                 return -E1000_ERR_NVM;
 278         }
 279
 280         return E1000_SUCCESS;
 281 }
 282
 283 /**
 284  *  e1000_standby_nvm - Return EEPROM to standby state
 285  *  @hw: pointer to the HW structure
 286  *
 287  *  Return the EEPROM to a standby state.
 288  **/
 289 static void e1000_standby_nvm(struct e1000_hw *hw)
 290 {
 291         struct e1000_nvm_info *nvm = &hw->nvm;
 292         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 293
 294         DEBUGFUNC("e1000_standby_nvm");
 295
 296         if (nvm->type == e1000_nvm_eeprom_microwire) {
 297                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 298                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 299                 E1000_WRITE_FLUSH(hw);
 300                 usec_delay(nvm->delay_usec);
 301
 302                 e1000_raise_eec_clk(hw, &eecd);
 303
 304                 /* Select EEPROM */
 305                 eecd |= E1000_EECD_CS;
 306                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 307                 E1000_WRITE_FLUSH(hw);
 308                 usec_delay(nvm->delay_usec);
 309
 310                 e1000_lower_eec_clk(hw, &eecd);
 311         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 312                 /* Toggle CS to flush commands */
 313                 eecd |= E1000_EECD_CS;
 314                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 315                 E1000_WRITE_FLUSH(hw);
 316                 usec_delay(nvm->delay_usec);
 317                 eecd &= ~E1000_EECD_CS;
 318                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 319                 E1000_WRITE_FLUSH(hw);
 320                 usec_delay(nvm->delay_usec);
 321         }
 322 }
 323
 324 /**
 325  *  e1000_stop_nvm - Terminate EEPROM command
 326  *  @hw: pointer to the HW structure
 327  *
 328  *  Terminates the current command by inverting the EEPROM's chip select pin.
 329  **/
 330 void e1000_stop_nvm(struct e1000_hw *hw)
 331 {
 332         u32 eecd;
 333
 334         DEBUGFUNC("e1000_stop_nvm");
 335
 336         eecd = E1000_READ_REG(hw, E1000_EECD);
 337         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 338                 /* Pull CS high */
 339                 eecd |= E1000_EECD_CS;
 340                 e1000_lower_eec_clk(hw, &eecd);
 341         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 342                 /* CS on Microwire is active-high */
 343                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 344                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 345                 e1000_raise_eec_clk(hw, &eecd);
 346                 e1000_lower_eec_clk(hw, &eecd);
 347         }
 348 }
 349
 350 /**
 351  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 352  *  @hw: pointer to the HW structure
 353  *
 354  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 355  **/
 356 void e1000_release_nvm_generic(struct e1000_hw *hw)
 357 {
 358         u32 eecd;
 359
 360         DEBUGFUNC("e1000_release_nvm_generic");
 361
 362         e1000_stop_nvm(hw);
 363
 364         eecd = E1000_READ_REG(hw, E1000_EECD);
 365         eecd &= ~E1000_EECD_REQ;
 366         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 367 }
 368
 369 /**
 370  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 371  *  @hw: pointer to the HW structure
 372  *
 373  *  Setups the EEPROM for reading and writing.
 374  **/
 375 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 376 {
 377         struct e1000_nvm_info *nvm = &hw->nvm;
 378         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 379         u8 spi_stat_reg;
 380
 381         DEBUGFUNC("e1000_ready_nvm_eeprom");
 382
 383         if (nvm->type == e1000_nvm_eeprom_microwire) {
 384                 /* Clear SK and DI */
 385                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 386                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 387                 /* Set CS */
 388                 eecd |= E1000_EECD_CS;
 389                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 390         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 391                 u16 timeout = NVM_MAX_RETRY_SPI;
 392
 393                 /* Clear SK and CS */
 394                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 395                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 396                 E1000_WRITE_FLUSH(hw);
 397                 usec_delay(1);
 398
 399                 /*
 400                  * Read "Status Register" repeatedly until the LSB is cleared.
 401                  * The EEPROM will signal that the command has been completed
 402                  * by clearing bit 0 of the internal status register.  If it's
 403                  * not cleared within 'timeout', then error out.
 404                  */
 405                 while (timeout) {
 406                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 407                                                  hw->nvm.opcode_bits);
 408                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 409                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 410                                 break;
 411
 412                         usec_delay(5);
 413                         e1000_standby_nvm(hw);
 414                         timeout--;
 415                 }
 416
 417                 if (!timeout) {
 418                         DEBUGOUT("SPI NVM Status error\n");
 419                         return -E1000_ERR_NVM;
 420                 }
 421         }
 422
 423         return E1000_SUCCESS;
 424 }
 425
 426 /**
 427  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 428  *  @hw: pointer to the HW structure
 429  *  @offset: offset of word in the EEPROM to read
 430  *  @words: number of words to read
 431  *  @data: word read from the EEPROM
 432  *
 433  *  Reads a 16 bit word from the EEPROM.
 434  **/
 435 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 436 {
 437         struct e1000_nvm_info *nvm = &hw->nvm;
 438         u32 i = 0;
 439         s32 ret_val;
 440         u16 word_in;
 441         u8 read_opcode = NVM_READ_OPCODE_SPI;
 442
 443         DEBUGFUNC("e1000_read_nvm_spi");
 444
 445         /*
 446          * A check for invalid values:  offset too large, too many words,
 447          * and not enough words.
 448          */
 449         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 450             (words == 0)) {
 451                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 452                 return -E1000_ERR_NVM;
 453         }
 454
 455         ret_val = nvm->ops.acquire(hw);
 456         if (ret_val)
 457                 return ret_val;
 458
 459         ret_val = e1000_ready_nvm_eeprom(hw);
 460         if (ret_val)
 461                 goto release;
 462
 463         e1000_standby_nvm(hw);
 464
 465         if ((nvm->address_bits == 8) && (offset >= 128))
 466                 read_opcode |= NVM_A8_OPCODE_SPI;
 467
 468         /* Send the READ command (opcode + addr) */
 469         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 470         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 471
 472         /*
 473          * Read the data.  SPI NVMs increment the address with each byte
 474          * read and will roll over if reading beyond the end.  This allows
 475          * us to read the whole NVM from any offset
 476          */
 477         for (i = 0; i < words; i++) {
 478                 word_in = e1000_shift_in_eec_bits(hw, 16);
 479                 data[i] = (word_in >> 8) | (word_in << 8);
 480         }
 481
 482 release:
 483         nvm->ops.release(hw);
 484
 485         return ret_val;
 486 }
 487
 488 /**
 489  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 490  *  @hw: pointer to the HW structure
 491  *  @offset: offset of word in the EEPROM to read
 492  *  @words: number of words to read
 493  *  @data: word read from the EEPROM
 494  *
 495  *  Reads a 16 bit word from the EEPROM.
 496  **/
 497 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 498                              u16 *data)
 499 {
 500         struct e1000_nvm_info *nvm = &hw->nvm;
 501         u32 i = 0;
 502         s32 ret_val;
 503         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 504
 505         DEBUGFUNC("e1000_read_nvm_microwire");
 506
 507         /*
 508          * A check for invalid values:  offset too large, too many words,
 509          * and not enough words.
 510          */
 511         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 512             (words == 0)) {
 513                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 514                 return -E1000_ERR_NVM;
 515         }
 516
 517         ret_val = nvm->ops.acquire(hw);
 518         if (ret_val)
 519                 return ret_val;
 520
 521         ret_val = e1000_ready_nvm_eeprom(hw);
 522         if (ret_val)
 523                 goto release;
 524
 525         for (i = 0; i < words; i++) {
 526                 /* Send the READ command (opcode + addr) */
 527                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 528                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 529                                         nvm->address_bits);
 530
 531                 /*
 532                  * Read the data.  For microwire, each word requires the
 533                  * overhead of setup and tear-down.
 534                  */
 535                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 536                 e1000_standby_nvm(hw);
 537         }
 538
 539 release:
 540         nvm->ops.release(hw);
 541
 542         return ret_val;
 543 }
 544
 545 /**
 546  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 547  *  @hw: pointer to the HW structure
 548  *  @offset: offset of word in the EEPROM to read
 549  *  @words: number of words to read
 550  *  @data: word read from the EEPROM
 551  *
 552  *  Reads a 16 bit word from the EEPROM using the EERD register.
 553  **/
 554 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 555 {
 556         struct e1000_nvm_info *nvm = &hw->nvm;
 557         u32 i, eerd = 0;
 558         s32 ret_val = E1000_SUCCESS;
 559
 560         DEBUGFUNC("e1000_read_nvm_eerd");
 561
 562         /*
 563          * A check for invalid values:  offset too large, too many words,
 564          * too many words for the offset, and not enough words.
 565          */
 566         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 567             (words == 0)) {
 568                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 569                 return -E1000_ERR_NVM;
 570         }
 571
 572         for (i = 0; i < words; i++) {
 573                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 574                        E1000_NVM_RW_REG_START;
 575
 576                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 577                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 578                 if (ret_val)
 579                         break;
 580
 581                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 582                            E1000_NVM_RW_REG_DATA);
 583         }
 584
 585         return ret_val;
 586 }
 587
 588 /**
 589  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 590  *  @hw: pointer to the HW structure
 591  *  @offset: offset within the EEPROM to be written to
 592  *  @words: number of words to write
 593  *  @data: 16 bit word(s) to be written to the EEPROM
 594  *
 595  *  Writes data to EEPROM at offset using SPI interface.
 596  *
 597  *  If e1000_update_nvm_checksum is not called after this function , the
 598  *  EEPROM will most likely contain an invalid checksum.
 599  **/
 600 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 601 {
 602         struct e1000_nvm_info *nvm = &hw->nvm;
 603         s32 ret_val = -E1000_ERR_NVM;
 604         u16 widx = 0;
 605
 606         DEBUGFUNC("e1000_write_nvm_spi");
 607
 608         /*
 609          * A check for invalid values:  offset too large, too many words,
 610          * and not enough words.
 611          */
 612         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 613             (words == 0)) {
 614                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 615                 return -E1000_ERR_NVM;
 616         }
 617
 618         while (widx < words) {
 619                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 620
 621                 ret_val = nvm->ops.acquire(hw);
 622                 if (ret_val)
 623                         return ret_val;
 624
 625                 ret_val = e1000_ready_nvm_eeprom(hw);
 626                 if (ret_val) {
 627                         nvm->ops.release(hw);
 628                         return ret_val;
 629                 }
 630
 631                 e1000_standby_nvm(hw);
 632
 633                 /* Send the WRITE ENABLE command (8 bit opcode) */
 634                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 635                                          nvm->opcode_bits);
 636
 637                 e1000_standby_nvm(hw);
 638
 639                 /*
 640                  * Some SPI eeproms use the 8th address bit embedded in the
 641                  * opcode
 642                  */
 643                 if ((nvm->address_bits == 8) && (offset >= 128))
 644                         write_opcode |= NVM_A8_OPCODE_SPI;
 645
 646                 /* Send the Write command (8-bit opcode + addr) */
 647                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 648                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 649                                          nvm->address_bits);
 650
 651                 /* Loop to allow for up to whole page write of eeprom */
 652                 while (widx < words) {
 653                         u16 word_out = data[widx];
 654                         word_out = (word_out >> 8) | (word_out << 8);
 655                         e1000_shift_out_eec_bits(hw, word_out, 16);
 656                         widx++;
 657
 658                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 659                                 e1000_standby_nvm(hw);
 660                                 break;
 661                         }
 662                 }
 663                 msec_delay(10);
 664                 nvm->ops.release(hw);
 665         }
 666
 667         return ret_val;
 668 }
 669
 670 /**
 671  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 672  *  @hw: pointer to the HW structure
 673  *  @offset: offset within the EEPROM to be written to
 674  *  @words: number of words to write
 675  *  @data: 16 bit word(s) to be written to the EEPROM
 676  *
 677  *  Writes data to EEPROM at offset using microwire interface.
 678  *
 679  *  If e1000_update_nvm_checksum is not called after this function , the
 680  *  EEPROM will most likely contain an invalid checksum.
 681  **/
 682 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 683                               u16 *data)
 684 {
 685         struct e1000_nvm_info *nvm = &hw->nvm;
 686         s32  ret_val;
 687         u32 eecd;
 688         u16 words_written = 0;
 689         u16 widx = 0;
 690
 691         DEBUGFUNC("e1000_write_nvm_microwire");
 692
 693         /*
 694          * A check for invalid values:  offset too large, too many words,
 695          * and not enough words.
 696          */
 697         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 698             (words == 0)) {
 699                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 700                 return -E1000_ERR_NVM;
 701         }
 702
 703         ret_val = nvm->ops.acquire(hw);
 704         if (ret_val)
 705                 return ret_val;
 706
 707         ret_val = e1000_ready_nvm_eeprom(hw);
 708         if (ret_val)
 709                 goto release;
 710
 711         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 712                                  (u16)(nvm->opcode_bits + 2));
 713
 714         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 715
 716         e1000_standby_nvm(hw);
 717
 718         while (words_written < words) {
 719                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 720                                          nvm->opcode_bits);
 721
 722                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 723                                          nvm->address_bits);
 724
 725                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 726
 727                 e1000_standby_nvm(hw);
 728
 729                 for (widx = 0; widx < 200; widx++) {
 730                         eecd = E1000_READ_REG(hw, E1000_EECD);
 731                         if (eecd & E1000_EECD_DO)
 732                                 break;
 733                         usec_delay(50);
 734                 }
 735
 736                 if (widx == 200) {
 737                         DEBUGOUT("NVM Write did not complete\n");
 738                         ret_val = -E1000_ERR_NVM;
 739                         goto release;
 740                 }
 741
 742                 e1000_standby_nvm(hw);
 743
 744                 words_written++;
 745         }
 746
 747         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 748                                  (u16)(nvm->opcode_bits + 2));
 749
 750         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 751
 752 release:
 753         nvm->ops.release(hw);
 754
 755         return ret_val;
 756 }
 757
 758 /**
 759  *  e1000_read_pba_string_generic - Read device part number
 760  *  @hw: pointer to the HW structure
 761  *  @pba_num: pointer to device part number
 762  *  @pba_num_size: size of part number buffer
 763  *
 764  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 765  *  the value in pba_num.
 766  **/
 767 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 768                                   u32 pba_num_size)
 769 {
 770         s32 ret_val;
 771         u16 nvm_data;
 772         u16 pba_ptr;
 773         u16 offset;
 774         u16 length;
 775
 776         DEBUGFUNC("e1000_read_pba_string_generic");
 777
 778         if (pba_num == NULL) {
 779                 DEBUGOUT("PBA string buffer was null\n");
 780                 return -E1000_ERR_INVALID_ARGUMENT;
 781         }
 782
 783         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 784         if (ret_val) {
 785                 DEBUGOUT("NVM Read Error\n");
 786                 return ret_val;
 787         }
 788
 789         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 790         if (ret_val) {
 791                 DEBUGOUT("NVM Read Error\n");
 792                 return ret_val;
 793         }
 794
 795         /*
 796          * if nvm_data is not ptr guard the PBA must be in legacy format which
 797          * means pba_ptr is actually our second data word for the PBA number
 798          * and we can decode it into an ascii string
 799          */
 800         if (nvm_data != NVM_PBA_PTR_GUARD) {
 801                 DEBUGOUT("NVM PBA number is not stored as string\n");
 802
 803                 /* make sure callers buffer is big enough to store the PBA */
 804                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 805                         DEBUGOUT("PBA string buffer too small\n");
 806                         return E1000_ERR_NO_SPACE;
 807                 }
 808
 809                 /* extract hex string from data and pba_ptr */
 810                 pba_num[0] = (nvm_data >> 12) & 0xF;
 811                 pba_num[1] = (nvm_data >> 8) & 0xF;
 812                 pba_num[2] = (nvm_data >> 4) & 0xF;
 813                 pba_num[3] = nvm_data & 0xF;
 814                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 815                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 816                 pba_num[6] = '-';
 817                 pba_num[7] = 0;
 818                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 819                 pba_num[9] = pba_ptr & 0xF;
 820
 821                 /* put a null character on the end of our string */
 822                 pba_num[10] = '\0';
 823
 824                 /* switch all the data but the '-' to hex char */
 825                 for (offset = 0; offset < 10; offset++) {
 826                         if (pba_num[offset] < 0xA)
 827                                 pba_num[offset] += '0';
 828                         else if (pba_num[offset] < 0x10)
 829                                 pba_num[offset] += 'A' - 0xA;
 830                 }
 831
 832                 return E1000_SUCCESS;
 833         }
 834
 835         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 836         if (ret_val) {
 837                 DEBUGOUT("NVM Read Error\n");
 838                 return ret_val;
 839         }
 840
 841         if (length == 0xFFFF || length == 0) {
 842                 DEBUGOUT("NVM PBA number section invalid length\n");
 843                 return -E1000_ERR_NVM_PBA_SECTION;
 844         }
 845         /* check if pba_num buffer is big enough */
 846         if (pba_num_size < (((u32)length * 2) - 1)) {
 847                 DEBUGOUT("PBA string buffer too small\n");
 848                 return -E1000_ERR_NO_SPACE;
 849         }
 850
 851         /* trim pba length from start of string */
 852         pba_ptr++;
 853         length--;
 854
 855         for (offset = 0; offset < length; offset++) {
 856                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 857                 if (ret_val) {
 858                         DEBUGOUT("NVM Read Error\n");
 859                         return ret_val;
 860                 }
 861                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 862                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 863         }
 864         pba_num[offset * 2] = '\0';
 865
 866         return E1000_SUCCESS;
 867 }
 868
 869 /**
 870  *  e1000_read_pba_length_generic - Read device part number length
 871  *  @hw: pointer to the HW structure
 872  *  @pba_num_size: size of part number buffer
 873  *
 874  *  Reads the product board assembly (PBA) number length from the EEPROM and
 875  *  stores the value in pba_num_size.
 876  **/
 877 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 878 {
 879         s32 ret_val;
 880         u16 nvm_data;
 881         u16 pba_ptr;
 882         u16 length;
 883
 884         DEBUGFUNC("e1000_read_pba_length_generic");
 885
 886         if (pba_num_size == NULL) {
 887                 DEBUGOUT("PBA buffer size was null\n");
 888                 return -E1000_ERR_INVALID_ARGUMENT;
 889         }
 890
 891         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 892         if (ret_val) {
 893                 DEBUGOUT("NVM Read Error\n");
 894                 return ret_val;
 895         }
 896
 897         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 898         if (ret_val) {
 899                 DEBUGOUT("NVM Read Error\n");
 900                 return ret_val;
 901         }
 902
 903          /* if data is not ptr guard the PBA must be in legacy format */
 904         if (nvm_data != NVM_PBA_PTR_GUARD) {
 905                 *pba_num_size = E1000_PBANUM_LENGTH;
 906                 return E1000_SUCCESS;
 907         }
 908
 909         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 910         if (ret_val) {
 911                 DEBUGOUT("NVM Read Error\n");
 912                 return ret_val;
 913         }
 914
 915         if (length == 0xFFFF || length == 0) {
 916                 DEBUGOUT("NVM PBA number section invalid length\n");
 917                 return -E1000_ERR_NVM_PBA_SECTION;
 918         }
 919
 920         /*
 921          * Convert from length in u16 values to u8 chars, add 1 for NULL,
 922          * and subtract 2 because length field is included in length.
 923          */
 924         *pba_num_size = ((u32)length * 2) - 1;
 925
 926         return E1000_SUCCESS;
 927 }
 928
 929
 930 /**
 931  *  e1000_read_pba_raw
 932  *  @hw: pointer to the HW structure
 933  *  @eeprom_buf: optional pointer to EEPROM image
 934  *  @eeprom_buf_size: size of EEPROM image in words
 935  *  @max_pba_block_size: PBA block size limit
 936  *  @pba: pointer to output PBA structure
 937  *
 938  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 939  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 940  *
 941  **/
 942 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 943                        u32 eeprom_buf_size, u16 max_pba_block_size,
 944                        struct e1000_pba *pba)
 945 {
 946         s32 ret_val;
 947         u16 pba_block_size;
 948
 949         if (pba == NULL)
 950                 return -E1000_ERR_PARAM;
 951
 952         if (eeprom_buf == NULL) {
 953                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 954                                          &pba->word[0]);
 955                 if (ret_val)
 956                         return ret_val;
 957         } else {
 958                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
 959                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
 960                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
 961                 } else {
 962                         return -E1000_ERR_PARAM;
 963                 }
 964         }
 965
 966         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
 967                 if (pba->pba_block == NULL)
 968                         return -E1000_ERR_PARAM;
 969
 970                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
 971                                                    eeprom_buf_size,
 972                                                    &pba_block_size);
 973                 if (ret_val)
 974                         return ret_val;
 975
 976                 if (pba_block_size > max_pba_block_size)
 977                         return -E1000_ERR_PARAM;
 978
 979                 if (eeprom_buf == NULL) {
 980                         ret_val = e1000_read_nvm(hw, pba->word[1],
 981                                                  pba_block_size,
 982                                                  pba->pba_block);
 983                         if (ret_val)
 984                                 return ret_val;
 985                 } else {
 986                         if (eeprom_buf_size > (u32)(pba->word[1] +
 987                                               pba->pba_block[0])) {
 988                                 memcpy(pba->pba_block,
 989                                        &eeprom_buf[pba->word[1]],
 990                                        pba_block_size * sizeof(u16));
 991                         } else {
 992                                 return -E1000_ERR_PARAM;
 993                         }
 994                 }
 995         }
 996
 997         return E1000_SUCCESS;
 998 }
 999
1000 /**
1001  *  e1000_write_pba_raw
1002  *  @hw: pointer to the HW structure
1003  *  @eeprom_buf: optional pointer to EEPROM image
1004  *  @eeprom_buf_size: size of EEPROM image in words
1005  *  @pba: pointer to PBA structure
1006  *
1007  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1008  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1009  *
1010  **/
1011 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1012                         u32 eeprom_buf_size, struct e1000_pba *pba)
1013 {
1014         s32 ret_val;
1015
1016         if (pba == NULL)
1017                 return -E1000_ERR_PARAM;
1018
1019         if (eeprom_buf == NULL) {
1020                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1021                                           &pba->word[0]);
1022                 if (ret_val)
1023                         return ret_val;
1024         } else {
1025                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1026                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1027                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1028                 } else {
1029                         return -E1000_ERR_PARAM;
1030                 }
1031         }
1032
1033         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1034                 if (pba->pba_block == NULL)
1035                         return -E1000_ERR_PARAM;
1036
1037                 if (eeprom_buf == NULL) {
1038                         ret_val = e1000_write_nvm(hw, pba->word[1],
1039                                                   pba->pba_block[0],
1040                                                   pba->pba_block);
1041                         if (ret_val)
1042                                 return ret_val;
1043                 } else {
1044                         if (eeprom_buf_size > (u32)(pba->word[1] +
1045                                               pba->pba_block[0])) {
1046                                 memcpy(&eeprom_buf[pba->word[1]],
1047                                        pba->pba_block,
1048                                        pba->pba_block[0] * sizeof(u16));
1049                         } else {
1050                                 return -E1000_ERR_PARAM;
1051                         }
1052                 }
1053         }
1054
1055         return E1000_SUCCESS;
1056 }
1057
1058 /**
1059  *  e1000_get_pba_block_size
1060  *  @hw: pointer to the HW structure
1061  *  @eeprom_buf: optional pointer to EEPROM image
1062  *  @eeprom_buf_size: size of EEPROM image in words
1063  *  @pba_data_size: pointer to output variable
1064  *
1065  *  Returns the size of the PBA block in words. Function operates on EEPROM
1066  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1067  *  EEPROM device.
1068  *
1069  **/
1070 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1071                              u32 eeprom_buf_size, u16 *pba_block_size)
1072 {
1073         s32 ret_val;
1074         u16 pba_word[2];
1075         u16 length;
1076
1077         DEBUGFUNC("e1000_get_pba_block_size");
1078
1079         if (eeprom_buf == NULL) {
1080                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1081                 if (ret_val)
1082                         return ret_val;
1083         } else {
1084                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1085                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1086                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1087                 } else {
1088                         return -E1000_ERR_PARAM;
1089                 }
1090         }
1091
1092         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1093                 if (eeprom_buf == NULL) {
1094                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1095                                                  &length);
1096                         if (ret_val)
1097                                 return ret_val;
1098                 } else {
1099                         if (eeprom_buf_size > pba_word[1])
1100                                 length = eeprom_buf[pba_word[1] + 0];
1101                         else
1102                                 return -E1000_ERR_PARAM;
1103                 }
1104
1105                 if (length == 0xFFFF || length == 0)
1106                         return -E1000_ERR_NVM_PBA_SECTION;
1107         } else {
1108                 /* PBA number in legacy format, there is no PBA Block. */
1109                 length = 0;
1110         }
1111
1112         if (pba_block_size != NULL)
1113                 *pba_block_size = length;
1114
1115         return E1000_SUCCESS;
1116 }
1117
1118 /**
1119  *  e1000_read_mac_addr_generic - Read device MAC address
1120  *  @hw: pointer to the HW structure
1121  *
1122  *  Reads the device MAC address from the EEPROM and stores the value.
1123  *  Since devices with two ports use the same EEPROM, we increment the
1124  *  last bit in the MAC address for the second port.
1125  **/
1126 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1127 {
1128         u32 rar_high;
1129         u32 rar_low;
1130         u16 i;
1131
1132         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1133         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1134
1135         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1136                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1137
1138         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1139                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1140
1141         for (i = 0; i < ETH_ADDR_LEN; i++)
1142                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1143
1144         return E1000_SUCCESS;
1145 }
1146
1147 /**
1148  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1149  *  @hw: pointer to the HW structure
1150  *
1151  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1152  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1153  **/
1154 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1155 {
1156         s32 ret_val;
1157         u16 checksum = 0;
1158         u16 i, nvm_data;
1159
1160         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1161
1162         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1163                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1164                 if (ret_val) {
1165                         DEBUGOUT("NVM Read Error\n");
1166                         return ret_val;
1167                 }
1168                 checksum += nvm_data;
1169         }
1170
1171         if (checksum != (u16) NVM_SUM) {
1172                 DEBUGOUT("NVM Checksum Invalid\n");
1173                 return -E1000_ERR_NVM;
1174         }
1175
1176         return E1000_SUCCESS;
1177 }
1178
1179 /**
1180  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1181  *  @hw: pointer to the HW structure
1182  *
1183  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1184  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1185  *  value to the EEPROM.
1186  **/
1187 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1188 {
1189         s32 ret_val;
1190         u16 checksum = 0;
1191         u16 i, nvm_data;
1192
1193         DEBUGFUNC("e1000_update_nvm_checksum");
1194
1195         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1196                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1197                 if (ret_val) {
1198                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1199                         return ret_val;
1200                 }
1201                 checksum += nvm_data;
1202         }
1203         checksum = (u16) NVM_SUM - checksum;
1204         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1205         if (ret_val)
1206                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1207
1208         return ret_val;
1209 }
1210
1211 /**
1212  *  e1000_reload_nvm_generic - Reloads EEPROM
1213  *  @hw: pointer to the HW structure
1214  *
1215  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1216  *  extended control register.
1217  **/
1218 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1219 {
1220         u32 ctrl_ext;
1221
1222         DEBUGFUNC("e1000_reload_nvm_generic");
1223
1224         usec_delay(10);
1225         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1226         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1227         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1228         E1000_WRITE_FLUSH(hw);
1229 }
1230
1231 /**
1232  *  e1000_get_fw_version - Get firmware version information
1233  *  @hw: pointer to the HW structure
1234  *  @fw_vers: pointer to output version structure
1235  *
1236  *  unsupported/not present features return 0 in version structure
1237  **/
1238 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1239 {
1240         u16 eeprom_verh, eeprom_verl, fw_version;
1241         u16 comb_verh, comb_verl, comb_offset;
1242
1243         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1244
1245         /* this code only applies to certain mac types */
1246         switch (hw->mac.type) {
1247         case e1000_i211:
1248                 e1000_read_invm_version(hw, fw_vers);
1249                 return;
1250         case e1000_82575:
1251         case e1000_82576:
1252         case e1000_82580:
1253         case e1000_i350:
1254         case e1000_i210:
1255                 break;
1256         default:
1257                 return;
1258         }
1259
1260         /* basic eeprom version numbers */
1261         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1262         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
1263         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK);
1264
1265         /* etrack id */
1266         hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1267         hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1268         fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl;
1269
1270         switch (hw->mac.type) {
1271         case e1000_i210:
1272         case e1000_i350:
1273                 /* find combo image version */
1274                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1275                 if ((comb_offset != 0x0) &&
1276                     (comb_offset != NVM_VER_INVALID)) {
1277
1278                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1279                                          + 1), 1, &comb_verh);
1280                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1281                                          1, &comb_verl);
1282
1283                         /* get Option Rom version if it exists and is valid */
1284                         if ((comb_verh && comb_verl) &&
1285                             ((comb_verh != NVM_VER_INVALID) &&
1286                              (comb_verl != NVM_VER_INVALID))) {
1287
1288                                 fw_vers->or_valid = true;
1289                                 fw_vers->or_major =
1290                                         comb_verl >> NVM_COMB_VER_SHFT;
1291                                 fw_vers->or_build =
1292                                         (comb_verl << NVM_COMB_VER_SHFT)
1293                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1294                                 fw_vers->or_patch =
1295                                         comb_verh & NVM_COMB_VER_MASK;
1296                         }
1297                 }
1298                 break;
1299
1300         default:
1301                 break;
1302         }
1303         return;
1304 }
1305
1306