1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
39 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
40 * @hw: pointer to the HW structure
42 * Setups up the function pointers to no-op functions
44 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
46 struct e1000_nvm_info *nvm = &hw->nvm;
47 DEBUGFUNC("e1000_init_nvm_ops_generic");
49 /* Initialize function pointers */
50 nvm->ops.init_params = e1000_null_ops_generic;
51 nvm->ops.acquire = e1000_null_ops_generic;
52 nvm->ops.read = e1000_null_read_nvm;
53 nvm->ops.release = e1000_null_nvm_generic;
54 nvm->ops.reload = e1000_reload_nvm_generic;
55 nvm->ops.update = e1000_null_ops_generic;
56 nvm->ops.valid_led_default = e1000_null_led_default;
57 nvm->ops.validate = e1000_null_ops_generic;
58 nvm->ops.write = e1000_null_write_nvm;
62 * e1000_null_nvm_read - No-op function, return 0
63 * @hw: pointer to the HW structure
65 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
67 DEBUGFUNC("e1000_null_read_nvm");
72 * e1000_null_nvm_generic - No-op function, return void
73 * @hw: pointer to the HW structure
75 void e1000_null_nvm_generic(struct e1000_hw *hw)
77 DEBUGFUNC("e1000_null_nvm_generic");
82 * e1000_null_led_default - No-op function, return 0
83 * @hw: pointer to the HW structure
85 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
87 DEBUGFUNC("e1000_null_led_default");
92 * e1000_null_write_nvm - No-op function, return 0
93 * @hw: pointer to the HW structure
95 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
97 DEBUGFUNC("e1000_null_write_nvm");
102 * e1000_raise_eec_clk - Raise EEPROM clock
103 * @hw: pointer to the HW structure
104 * @eecd: pointer to the EEPROM
106 * Enable/Raise the EEPROM clock bit.
108 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
110 *eecd = *eecd | E1000_EECD_SK;
111 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
112 E1000_WRITE_FLUSH(hw);
113 usec_delay(hw->nvm.delay_usec);
117 * e1000_lower_eec_clk - Lower EEPROM clock
118 * @hw: pointer to the HW structure
119 * @eecd: pointer to the EEPROM
121 * Clear/Lower the EEPROM clock bit.
123 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
125 *eecd = *eecd & ~E1000_EECD_SK;
126 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
127 E1000_WRITE_FLUSH(hw);
128 usec_delay(hw->nvm.delay_usec);
132 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
133 * @hw: pointer to the HW structure
134 * @data: data to send to the EEPROM
135 * @count: number of bits to shift out
137 * We need to shift 'count' bits out to the EEPROM. So, the value in the
138 * "data" parameter will be shifted out to the EEPROM one bit at a time.
139 * In order to do this, "data" must be broken down into bits.
141 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
143 struct e1000_nvm_info *nvm = &hw->nvm;
144 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
147 DEBUGFUNC("e1000_shift_out_eec_bits");
149 mask = 0x01 << (count - 1);
150 if (nvm->type == e1000_nvm_eeprom_microwire)
151 eecd &= ~E1000_EECD_DO;
153 if (nvm->type == e1000_nvm_eeprom_spi)
154 eecd |= E1000_EECD_DO;
157 eecd &= ~E1000_EECD_DI;
160 eecd |= E1000_EECD_DI;
162 E1000_WRITE_REG(hw, E1000_EECD, eecd);
163 E1000_WRITE_FLUSH(hw);
165 usec_delay(nvm->delay_usec);
167 e1000_raise_eec_clk(hw, &eecd);
168 e1000_lower_eec_clk(hw, &eecd);
173 eecd &= ~E1000_EECD_DI;
174 E1000_WRITE_REG(hw, E1000_EECD, eecd);
178 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
179 * @hw: pointer to the HW structure
180 * @count: number of bits to shift in
182 * In order to read a register from the EEPROM, we need to shift 'count' bits
183 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
184 * the EEPROM (setting the SK bit), and then reading the value of the data out
185 * "DO" bit. During this "shifting in" process the data in "DI" bit should
188 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
194 DEBUGFUNC("e1000_shift_in_eec_bits");
196 eecd = E1000_READ_REG(hw, E1000_EECD);
198 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
201 for (i = 0; i < count; i++) {
203 e1000_raise_eec_clk(hw, &eecd);
205 eecd = E1000_READ_REG(hw, E1000_EECD);
207 eecd &= ~E1000_EECD_DI;
208 if (eecd & E1000_EECD_DO)
211 e1000_lower_eec_clk(hw, &eecd);
218 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
219 * @hw: pointer to the HW structure
220 * @ee_reg: EEPROM flag for polling
222 * Polls the EEPROM status bit for either read or write completion based
223 * upon the value of 'ee_reg'.
225 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
227 u32 attempts = 100000;
230 DEBUGFUNC("e1000_poll_eerd_eewr_done");
232 for (i = 0; i < attempts; i++) {
233 if (ee_reg == E1000_NVM_POLL_READ)
234 reg = E1000_READ_REG(hw, E1000_EERD);
236 reg = E1000_READ_REG(hw, E1000_EEWR);
238 if (reg & E1000_NVM_RW_REG_DONE)
239 return E1000_SUCCESS;
244 return -E1000_ERR_NVM;
248 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
249 * @hw: pointer to the HW structure
251 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
252 * Return successful if access grant bit set, else clear the request for
253 * EEPROM access and return -E1000_ERR_NVM (-1).
255 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
257 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
258 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
260 DEBUGFUNC("e1000_acquire_nvm_generic");
262 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
263 eecd = E1000_READ_REG(hw, E1000_EECD);
266 if (eecd & E1000_EECD_GNT)
269 eecd = E1000_READ_REG(hw, E1000_EECD);
274 eecd &= ~E1000_EECD_REQ;
275 E1000_WRITE_REG(hw, E1000_EECD, eecd);
276 DEBUGOUT("Could not acquire NVM grant\n");
277 return -E1000_ERR_NVM;
280 return E1000_SUCCESS;
284 * e1000_standby_nvm - Return EEPROM to standby state
285 * @hw: pointer to the HW structure
287 * Return the EEPROM to a standby state.
289 static void e1000_standby_nvm(struct e1000_hw *hw)
291 struct e1000_nvm_info *nvm = &hw->nvm;
292 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
294 DEBUGFUNC("e1000_standby_nvm");
296 if (nvm->type == e1000_nvm_eeprom_microwire) {
297 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
298 E1000_WRITE_REG(hw, E1000_EECD, eecd);
299 E1000_WRITE_FLUSH(hw);
300 usec_delay(nvm->delay_usec);
302 e1000_raise_eec_clk(hw, &eecd);
305 eecd |= E1000_EECD_CS;
306 E1000_WRITE_REG(hw, E1000_EECD, eecd);
307 E1000_WRITE_FLUSH(hw);
308 usec_delay(nvm->delay_usec);
310 e1000_lower_eec_clk(hw, &eecd);
311 } else if (nvm->type == e1000_nvm_eeprom_spi) {
312 /* Toggle CS to flush commands */
313 eecd |= E1000_EECD_CS;
314 E1000_WRITE_REG(hw, E1000_EECD, eecd);
315 E1000_WRITE_FLUSH(hw);
316 usec_delay(nvm->delay_usec);
317 eecd &= ~E1000_EECD_CS;
318 E1000_WRITE_REG(hw, E1000_EECD, eecd);
319 E1000_WRITE_FLUSH(hw);
320 usec_delay(nvm->delay_usec);
325 * e1000_stop_nvm - Terminate EEPROM command
326 * @hw: pointer to the HW structure
328 * Terminates the current command by inverting the EEPROM's chip select pin.
330 void e1000_stop_nvm(struct e1000_hw *hw)
334 DEBUGFUNC("e1000_stop_nvm");
336 eecd = E1000_READ_REG(hw, E1000_EECD);
337 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
339 eecd |= E1000_EECD_CS;
340 e1000_lower_eec_clk(hw, &eecd);
341 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
342 /* CS on Microwire is active-high */
343 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
344 E1000_WRITE_REG(hw, E1000_EECD, eecd);
345 e1000_raise_eec_clk(hw, &eecd);
346 e1000_lower_eec_clk(hw, &eecd);
351 * e1000_release_nvm_generic - Release exclusive access to EEPROM
352 * @hw: pointer to the HW structure
354 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
356 void e1000_release_nvm_generic(struct e1000_hw *hw)
360 DEBUGFUNC("e1000_release_nvm_generic");
364 eecd = E1000_READ_REG(hw, E1000_EECD);
365 eecd &= ~E1000_EECD_REQ;
366 E1000_WRITE_REG(hw, E1000_EECD, eecd);
370 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
371 * @hw: pointer to the HW structure
373 * Setups the EEPROM for reading and writing.
375 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
377 struct e1000_nvm_info *nvm = &hw->nvm;
378 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
381 DEBUGFUNC("e1000_ready_nvm_eeprom");
383 if (nvm->type == e1000_nvm_eeprom_microwire) {
384 /* Clear SK and DI */
385 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
386 E1000_WRITE_REG(hw, E1000_EECD, eecd);
388 eecd |= E1000_EECD_CS;
389 E1000_WRITE_REG(hw, E1000_EECD, eecd);
390 } else if (nvm->type == e1000_nvm_eeprom_spi) {
391 u16 timeout = NVM_MAX_RETRY_SPI;
393 /* Clear SK and CS */
394 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
395 E1000_WRITE_REG(hw, E1000_EECD, eecd);
396 E1000_WRITE_FLUSH(hw);
400 * Read "Status Register" repeatedly until the LSB is cleared.
401 * The EEPROM will signal that the command has been completed
402 * by clearing bit 0 of the internal status register. If it's
403 * not cleared within 'timeout', then error out.
406 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
407 hw->nvm.opcode_bits);
408 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
409 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
413 e1000_standby_nvm(hw);
418 DEBUGOUT("SPI NVM Status error\n");
419 return -E1000_ERR_NVM;
423 return E1000_SUCCESS;
427 * e1000_read_nvm_spi - Read EEPROM's using SPI
428 * @hw: pointer to the HW structure
429 * @offset: offset of word in the EEPROM to read
430 * @words: number of words to read
431 * @data: word read from the EEPROM
433 * Reads a 16 bit word from the EEPROM.
435 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
437 struct e1000_nvm_info *nvm = &hw->nvm;
441 u8 read_opcode = NVM_READ_OPCODE_SPI;
443 DEBUGFUNC("e1000_read_nvm_spi");
446 * A check for invalid values: offset too large, too many words,
447 * and not enough words.
449 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
451 DEBUGOUT("nvm parameter(s) out of bounds\n");
452 return -E1000_ERR_NVM;
455 ret_val = nvm->ops.acquire(hw);
459 ret_val = e1000_ready_nvm_eeprom(hw);
463 e1000_standby_nvm(hw);
465 if ((nvm->address_bits == 8) && (offset >= 128))
466 read_opcode |= NVM_A8_OPCODE_SPI;
468 /* Send the READ command (opcode + addr) */
469 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
470 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
473 * Read the data. SPI NVMs increment the address with each byte
474 * read and will roll over if reading beyond the end. This allows
475 * us to read the whole NVM from any offset
477 for (i = 0; i < words; i++) {
478 word_in = e1000_shift_in_eec_bits(hw, 16);
479 data[i] = (word_in >> 8) | (word_in << 8);
483 nvm->ops.release(hw);
489 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
490 * @hw: pointer to the HW structure
491 * @offset: offset of word in the EEPROM to read
492 * @words: number of words to read
493 * @data: word read from the EEPROM
495 * Reads a 16 bit word from the EEPROM.
497 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
500 struct e1000_nvm_info *nvm = &hw->nvm;
503 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
505 DEBUGFUNC("e1000_read_nvm_microwire");
508 * A check for invalid values: offset too large, too many words,
509 * and not enough words.
511 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
513 DEBUGOUT("nvm parameter(s) out of bounds\n");
514 return -E1000_ERR_NVM;
517 ret_val = nvm->ops.acquire(hw);
521 ret_val = e1000_ready_nvm_eeprom(hw);
525 for (i = 0; i < words; i++) {
526 /* Send the READ command (opcode + addr) */
527 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
528 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
532 * Read the data. For microwire, each word requires the
533 * overhead of setup and tear-down.
535 data[i] = e1000_shift_in_eec_bits(hw, 16);
536 e1000_standby_nvm(hw);
540 nvm->ops.release(hw);
546 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
547 * @hw: pointer to the HW structure
548 * @offset: offset of word in the EEPROM to read
549 * @words: number of words to read
550 * @data: word read from the EEPROM
552 * Reads a 16 bit word from the EEPROM using the EERD register.
554 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
556 struct e1000_nvm_info *nvm = &hw->nvm;
558 s32 ret_val = E1000_SUCCESS;
560 DEBUGFUNC("e1000_read_nvm_eerd");
563 * A check for invalid values: offset too large, too many words,
564 * too many words for the offset, and not enough words.
566 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
568 DEBUGOUT("nvm parameter(s) out of bounds\n");
569 return -E1000_ERR_NVM;
572 for (i = 0; i < words; i++) {
573 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
574 E1000_NVM_RW_REG_START;
576 E1000_WRITE_REG(hw, E1000_EERD, eerd);
577 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
581 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
582 E1000_NVM_RW_REG_DATA);
589 * e1000_write_nvm_spi - Write to EEPROM using SPI
590 * @hw: pointer to the HW structure
591 * @offset: offset within the EEPROM to be written to
592 * @words: number of words to write
593 * @data: 16 bit word(s) to be written to the EEPROM
595 * Writes data to EEPROM at offset using SPI interface.
597 * If e1000_update_nvm_checksum is not called after this function , the
598 * EEPROM will most likely contain an invalid checksum.
600 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
602 struct e1000_nvm_info *nvm = &hw->nvm;
603 s32 ret_val = -E1000_ERR_NVM;
606 DEBUGFUNC("e1000_write_nvm_spi");
609 * A check for invalid values: offset too large, too many words,
610 * and not enough words.
612 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
614 DEBUGOUT("nvm parameter(s) out of bounds\n");
615 return -E1000_ERR_NVM;
618 while (widx < words) {
619 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
621 ret_val = nvm->ops.acquire(hw);
625 ret_val = e1000_ready_nvm_eeprom(hw);
627 nvm->ops.release(hw);
631 e1000_standby_nvm(hw);
633 /* Send the WRITE ENABLE command (8 bit opcode) */
634 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
637 e1000_standby_nvm(hw);
640 * Some SPI eeproms use the 8th address bit embedded in the
643 if ((nvm->address_bits == 8) && (offset >= 128))
644 write_opcode |= NVM_A8_OPCODE_SPI;
646 /* Send the Write command (8-bit opcode + addr) */
647 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
648 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
651 /* Loop to allow for up to whole page write of eeprom */
652 while (widx < words) {
653 u16 word_out = data[widx];
654 word_out = (word_out >> 8) | (word_out << 8);
655 e1000_shift_out_eec_bits(hw, word_out, 16);
658 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
659 e1000_standby_nvm(hw);
664 nvm->ops.release(hw);
671 * e1000_write_nvm_microwire - Writes EEPROM using microwire
672 * @hw: pointer to the HW structure
673 * @offset: offset within the EEPROM to be written to
674 * @words: number of words to write
675 * @data: 16 bit word(s) to be written to the EEPROM
677 * Writes data to EEPROM at offset using microwire interface.
679 * If e1000_update_nvm_checksum is not called after this function , the
680 * EEPROM will most likely contain an invalid checksum.
682 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
685 struct e1000_nvm_info *nvm = &hw->nvm;
688 u16 words_written = 0;
691 DEBUGFUNC("e1000_write_nvm_microwire");
694 * A check for invalid values: offset too large, too many words,
695 * and not enough words.
697 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
699 DEBUGOUT("nvm parameter(s) out of bounds\n");
700 return -E1000_ERR_NVM;
703 ret_val = nvm->ops.acquire(hw);
707 ret_val = e1000_ready_nvm_eeprom(hw);
711 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
712 (u16)(nvm->opcode_bits + 2));
714 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
716 e1000_standby_nvm(hw);
718 while (words_written < words) {
719 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
722 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
725 e1000_shift_out_eec_bits(hw, data[words_written], 16);
727 e1000_standby_nvm(hw);
729 for (widx = 0; widx < 200; widx++) {
730 eecd = E1000_READ_REG(hw, E1000_EECD);
731 if (eecd & E1000_EECD_DO)
737 DEBUGOUT("NVM Write did not complete\n");
738 ret_val = -E1000_ERR_NVM;
742 e1000_standby_nvm(hw);
747 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
748 (u16)(nvm->opcode_bits + 2));
750 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
753 nvm->ops.release(hw);
759 * e1000_read_pba_string_generic - Read device part number
760 * @hw: pointer to the HW structure
761 * @pba_num: pointer to device part number
762 * @pba_num_size: size of part number buffer
764 * Reads the product board assembly (PBA) number from the EEPROM and stores
765 * the value in pba_num.
767 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
776 DEBUGFUNC("e1000_read_pba_string_generic");
778 if (pba_num == NULL) {
779 DEBUGOUT("PBA string buffer was null\n");
780 return -E1000_ERR_INVALID_ARGUMENT;
783 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
785 DEBUGOUT("NVM Read Error\n");
789 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
791 DEBUGOUT("NVM Read Error\n");
796 * if nvm_data is not ptr guard the PBA must be in legacy format which
797 * means pba_ptr is actually our second data word for the PBA number
798 * and we can decode it into an ascii string
800 if (nvm_data != NVM_PBA_PTR_GUARD) {
801 DEBUGOUT("NVM PBA number is not stored as string\n");
803 /* make sure callers buffer is big enough to store the PBA */
804 if (pba_num_size < E1000_PBANUM_LENGTH) {
805 DEBUGOUT("PBA string buffer too small\n");
806 return E1000_ERR_NO_SPACE;
809 /* extract hex string from data and pba_ptr */
810 pba_num[0] = (nvm_data >> 12) & 0xF;
811 pba_num[1] = (nvm_data >> 8) & 0xF;
812 pba_num[2] = (nvm_data >> 4) & 0xF;
813 pba_num[3] = nvm_data & 0xF;
814 pba_num[4] = (pba_ptr >> 12) & 0xF;
815 pba_num[5] = (pba_ptr >> 8) & 0xF;
818 pba_num[8] = (pba_ptr >> 4) & 0xF;
819 pba_num[9] = pba_ptr & 0xF;
821 /* put a null character on the end of our string */
824 /* switch all the data but the '-' to hex char */
825 for (offset = 0; offset < 10; offset++) {
826 if (pba_num[offset] < 0xA)
827 pba_num[offset] += '0';
828 else if (pba_num[offset] < 0x10)
829 pba_num[offset] += 'A' - 0xA;
832 return E1000_SUCCESS;
835 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
837 DEBUGOUT("NVM Read Error\n");
841 if (length == 0xFFFF || length == 0) {
842 DEBUGOUT("NVM PBA number section invalid length\n");
843 return -E1000_ERR_NVM_PBA_SECTION;
845 /* check if pba_num buffer is big enough */
846 if (pba_num_size < (((u32)length * 2) - 1)) {
847 DEBUGOUT("PBA string buffer too small\n");
848 return -E1000_ERR_NO_SPACE;
851 /* trim pba length from start of string */
855 for (offset = 0; offset < length; offset++) {
856 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
858 DEBUGOUT("NVM Read Error\n");
861 pba_num[offset * 2] = (u8)(nvm_data >> 8);
862 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
864 pba_num[offset * 2] = '\0';
866 return E1000_SUCCESS;
870 * e1000_read_pba_length_generic - Read device part number length
871 * @hw: pointer to the HW structure
872 * @pba_num_size: size of part number buffer
874 * Reads the product board assembly (PBA) number length from the EEPROM and
875 * stores the value in pba_num_size.
877 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
884 DEBUGFUNC("e1000_read_pba_length_generic");
886 if (pba_num_size == NULL) {
887 DEBUGOUT("PBA buffer size was null\n");
888 return -E1000_ERR_INVALID_ARGUMENT;
891 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
893 DEBUGOUT("NVM Read Error\n");
897 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
899 DEBUGOUT("NVM Read Error\n");
903 /* if data is not ptr guard the PBA must be in legacy format */
904 if (nvm_data != NVM_PBA_PTR_GUARD) {
905 *pba_num_size = E1000_PBANUM_LENGTH;
906 return E1000_SUCCESS;
909 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
911 DEBUGOUT("NVM Read Error\n");
915 if (length == 0xFFFF || length == 0) {
916 DEBUGOUT("NVM PBA number section invalid length\n");
917 return -E1000_ERR_NVM_PBA_SECTION;
921 * Convert from length in u16 values to u8 chars, add 1 for NULL,
922 * and subtract 2 because length field is included in length.
924 *pba_num_size = ((u32)length * 2) - 1;
926 return E1000_SUCCESS;
932 * @hw: pointer to the HW structure
933 * @eeprom_buf: optional pointer to EEPROM image
934 * @eeprom_buf_size: size of EEPROM image in words
935 * @max_pba_block_size: PBA block size limit
936 * @pba: pointer to output PBA structure
938 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
939 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
942 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
943 u32 eeprom_buf_size, u16 max_pba_block_size,
944 struct e1000_pba *pba)
950 return -E1000_ERR_PARAM;
952 if (eeprom_buf == NULL) {
953 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
958 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
959 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
960 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
962 return -E1000_ERR_PARAM;
966 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
967 if (pba->pba_block == NULL)
968 return -E1000_ERR_PARAM;
970 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
976 if (pba_block_size > max_pba_block_size)
977 return -E1000_ERR_PARAM;
979 if (eeprom_buf == NULL) {
980 ret_val = e1000_read_nvm(hw, pba->word[1],
986 if (eeprom_buf_size > (u32)(pba->word[1] +
987 pba->pba_block[0])) {
988 memcpy(pba->pba_block,
989 &eeprom_buf[pba->word[1]],
990 pba_block_size * sizeof(u16));
992 return -E1000_ERR_PARAM;
997 return E1000_SUCCESS;
1001 * e1000_write_pba_raw
1002 * @hw: pointer to the HW structure
1003 * @eeprom_buf: optional pointer to EEPROM image
1004 * @eeprom_buf_size: size of EEPROM image in words
1005 * @pba: pointer to PBA structure
1007 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
1008 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1011 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1012 u32 eeprom_buf_size, struct e1000_pba *pba)
1017 return -E1000_ERR_PARAM;
1019 if (eeprom_buf == NULL) {
1020 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1025 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1026 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1027 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1029 return -E1000_ERR_PARAM;
1033 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1034 if (pba->pba_block == NULL)
1035 return -E1000_ERR_PARAM;
1037 if (eeprom_buf == NULL) {
1038 ret_val = e1000_write_nvm(hw, pba->word[1],
1044 if (eeprom_buf_size > (u32)(pba->word[1] +
1045 pba->pba_block[0])) {
1046 memcpy(&eeprom_buf[pba->word[1]],
1048 pba->pba_block[0] * sizeof(u16));
1050 return -E1000_ERR_PARAM;
1055 return E1000_SUCCESS;
1059 * e1000_get_pba_block_size
1060 * @hw: pointer to the HW structure
1061 * @eeprom_buf: optional pointer to EEPROM image
1062 * @eeprom_buf_size: size of EEPROM image in words
1063 * @pba_data_size: pointer to output variable
1065 * Returns the size of the PBA block in words. Function operates on EEPROM
1066 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1070 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1071 u32 eeprom_buf_size, u16 *pba_block_size)
1077 DEBUGFUNC("e1000_get_pba_block_size");
1079 if (eeprom_buf == NULL) {
1080 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1084 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1085 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1086 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1088 return -E1000_ERR_PARAM;
1092 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1093 if (eeprom_buf == NULL) {
1094 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1099 if (eeprom_buf_size > pba_word[1])
1100 length = eeprom_buf[pba_word[1] + 0];
1102 return -E1000_ERR_PARAM;
1105 if (length == 0xFFFF || length == 0)
1106 return -E1000_ERR_NVM_PBA_SECTION;
1108 /* PBA number in legacy format, there is no PBA Block. */
1112 if (pba_block_size != NULL)
1113 *pba_block_size = length;
1115 return E1000_SUCCESS;
1119 * e1000_read_mac_addr_generic - Read device MAC address
1120 * @hw: pointer to the HW structure
1122 * Reads the device MAC address from the EEPROM and stores the value.
1123 * Since devices with two ports use the same EEPROM, we increment the
1124 * last bit in the MAC address for the second port.
1126 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1132 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1133 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1135 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1136 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1138 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1139 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1141 for (i = 0; i < ETH_ADDR_LEN; i++)
1142 hw->mac.addr[i] = hw->mac.perm_addr[i];
1144 return E1000_SUCCESS;
1148 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1149 * @hw: pointer to the HW structure
1151 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1152 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1154 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1160 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1162 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1163 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1165 DEBUGOUT("NVM Read Error\n");
1168 checksum += nvm_data;
1171 if (checksum != (u16) NVM_SUM) {
1172 DEBUGOUT("NVM Checksum Invalid\n");
1173 return -E1000_ERR_NVM;
1176 return E1000_SUCCESS;
1180 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1181 * @hw: pointer to the HW structure
1183 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1184 * up to the checksum. Then calculates the EEPROM checksum and writes the
1185 * value to the EEPROM.
1187 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1193 DEBUGFUNC("e1000_update_nvm_checksum");
1195 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1196 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1198 DEBUGOUT("NVM Read Error while updating checksum.\n");
1201 checksum += nvm_data;
1203 checksum = (u16) NVM_SUM - checksum;
1204 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1206 DEBUGOUT("NVM Write Error while updating checksum.\n");
1212 * e1000_reload_nvm_generic - Reloads EEPROM
1213 * @hw: pointer to the HW structure
1215 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1216 * extended control register.
1218 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1222 DEBUGFUNC("e1000_reload_nvm_generic");
1225 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1226 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1227 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1228 E1000_WRITE_FLUSH(hw);
1232 * e1000_get_fw_version - Get firmware version information
1233 * @hw: pointer to the HW structure
1234 * @fw_vers: pointer to output version structure
1236 * unsupported/not present features return 0 in version structure
1238 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1240 u16 eeprom_verh, eeprom_verl, fw_version;
1241 u16 comb_verh, comb_verl, comb_offset;
1243 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1245 /* this code only applies to certain mac types */
1246 switch (hw->mac.type) {
1248 e1000_read_invm_version(hw, fw_vers);
1260 /* basic eeprom version numbers */
1261 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1262 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
1263 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK);
1266 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1267 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1268 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl;
1270 switch (hw->mac.type) {
1273 /* find combo image version */
1274 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1275 if ((comb_offset != 0x0) &&
1276 (comb_offset != NVM_VER_INVALID)) {
1278 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1279 + 1), 1, &comb_verh);
1280 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1283 /* get Option Rom version if it exists and is valid */
1284 if ((comb_verh && comb_verl) &&
1285 ((comb_verh != NVM_VER_INVALID) &&
1286 (comb_verl != NVM_VER_INVALID))) {
1288 fw_vers->or_valid = true;
1290 comb_verl >> NVM_COMB_VER_SHFT;
1292 (comb_verl << NVM_COMB_VER_SHFT)
1293 | (comb_verh >> NVM_COMB_VER_SHFT);
1295 comb_verh & NVM_COMB_VER_MASK;