lib/librte_pmd_e1000/e1000/e1000_nvm.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "e1000_api.h"
  35
  36 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
  37
  38 /**
  39  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  40  *  @hw: pointer to the HW structure
  41  *
  42  *  Setups up the function pointers to no-op functions
  43  **/
  44 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  45 {
  46         struct e1000_nvm_info *nvm = &hw->nvm;
  47         DEBUGFUNC("e1000_init_nvm_ops_generic");
  48
  49         /* Initialize function pointers */
  50         nvm->ops.init_params = e1000_null_ops_generic;
  51         nvm->ops.acquire = e1000_null_ops_generic;
  52         nvm->ops.read = e1000_null_read_nvm;
  53         nvm->ops.release = e1000_null_nvm_generic;
  54         nvm->ops.reload = e1000_reload_nvm_generic;
  55         nvm->ops.update = e1000_null_ops_generic;
  56         nvm->ops.valid_led_default = e1000_null_led_default;
  57         nvm->ops.validate = e1000_null_ops_generic;
  58         nvm->ops.write = e1000_null_write_nvm;
  59 }
  60
  61 /**
  62  *  e1000_null_nvm_read - No-op function, return 0
  63  *  @hw: pointer to the HW structure
  64  **/
  65 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
  66                         u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
  67                         u16 E1000_UNUSEDARG *c)
  68 {
  69         DEBUGFUNC("e1000_null_read_nvm");
  70         UNREFERENCED_4PARAMETER(hw, a, b, c);
  71         return E1000_SUCCESS;
  72 }
  73
  74 /**
  75  *  e1000_null_nvm_generic - No-op function, return void
  76  *  @hw: pointer to the HW structure
  77  **/
  78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
  79 {
  80         DEBUGFUNC("e1000_null_nvm_generic");
  81         UNREFERENCED_1PARAMETER(hw);
  82         return;
  83 }
  84
  85 /**
  86  *  e1000_null_led_default - No-op function, return 0
  87  *  @hw: pointer to the HW structure
  88  **/
  89 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
  90                            u16 E1000_UNUSEDARG *data)
  91 {
  92         DEBUGFUNC("e1000_null_led_default");
  93         UNREFERENCED_2PARAMETER(hw, data);
  94         return E1000_SUCCESS;
  95 }
  96
  97 /**
  98  *  e1000_null_write_nvm - No-op function, return 0
  99  *  @hw: pointer to the HW structure
 100  **/
 101 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
 102                          u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
 103                          u16 E1000_UNUSEDARG *c)
 104 {
 105         DEBUGFUNC("e1000_null_write_nvm");
 106         UNREFERENCED_4PARAMETER(hw, a, b, c);
 107         return E1000_SUCCESS;
 108 }
 109
 110 /**
 111  *  e1000_raise_eec_clk - Raise EEPROM clock
 112  *  @hw: pointer to the HW structure
 113  *  @eecd: pointer to the EEPROM
 114  *
 115  *  Enable/Raise the EEPROM clock bit.
 116  **/
 117 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
 118 {
 119         *eecd = *eecd | E1000_EECD_SK;
 120         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 121         E1000_WRITE_FLUSH(hw);
 122         usec_delay(hw->nvm.delay_usec);
 123 }
 124
 125 /**
 126  *  e1000_lower_eec_clk - Lower EEPROM clock
 127  *  @hw: pointer to the HW structure
 128  *  @eecd: pointer to the EEPROM
 129  *
 130  *  Clear/Lower the EEPROM clock bit.
 131  **/
 132 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 133 {
 134         *eecd = *eecd & ~E1000_EECD_SK;
 135         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 136         E1000_WRITE_FLUSH(hw);
 137         usec_delay(hw->nvm.delay_usec);
 138 }
 139
 140 /**
 141  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 142  *  @hw: pointer to the HW structure
 143  *  @data: data to send to the EEPROM
 144  *  @count: number of bits to shift out
 145  *
 146  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 147  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 148  *  In order to do this, "data" must be broken down into bits.
 149  **/
 150 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 151 {
 152         struct e1000_nvm_info *nvm = &hw->nvm;
 153         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 154         u32 mask;
 155
 156         DEBUGFUNC("e1000_shift_out_eec_bits");
 157
 158         mask = 0x01 << (count - 1);
 159         if (nvm->type == e1000_nvm_eeprom_microwire)
 160                 eecd &= ~E1000_EECD_DO;
 161         else
 162         if (nvm->type == e1000_nvm_eeprom_spi)
 163                 eecd |= E1000_EECD_DO;
 164
 165         do {
 166                 eecd &= ~E1000_EECD_DI;
 167
 168                 if (data & mask)
 169                         eecd |= E1000_EECD_DI;
 170
 171                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 172                 E1000_WRITE_FLUSH(hw);
 173
 174                 usec_delay(nvm->delay_usec);
 175
 176                 e1000_raise_eec_clk(hw, &eecd);
 177                 e1000_lower_eec_clk(hw, &eecd);
 178
 179                 mask >>= 1;
 180         } while (mask);
 181
 182         eecd &= ~E1000_EECD_DI;
 183         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 184 }
 185
 186 /**
 187  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 188  *  @hw: pointer to the HW structure
 189  *  @count: number of bits to shift in
 190  *
 191  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 192  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 193  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 194  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 195  *  always be clear.
 196  **/
 197 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 198 {
 199         u32 eecd;
 200         u32 i;
 201         u16 data;
 202
 203         DEBUGFUNC("e1000_shift_in_eec_bits");
 204
 205         eecd = E1000_READ_REG(hw, E1000_EECD);
 206
 207         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 208         data = 0;
 209
 210         for (i = 0; i < count; i++) {
 211                 data <<= 1;
 212                 e1000_raise_eec_clk(hw, &eecd);
 213
 214                 eecd = E1000_READ_REG(hw, E1000_EECD);
 215
 216                 eecd &= ~E1000_EECD_DI;
 217                 if (eecd & E1000_EECD_DO)
 218                         data |= 1;
 219
 220                 e1000_lower_eec_clk(hw, &eecd);
 221         }
 222
 223         return data;
 224 }
 225
 226 /**
 227  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 228  *  @hw: pointer to the HW structure
 229  *  @ee_reg: EEPROM flag for polling
 230  *
 231  *  Polls the EEPROM status bit for either read or write completion based
 232  *  upon the value of 'ee_reg'.
 233  **/
 234 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 235 {
 236         u32 attempts = 100000;
 237         u32 i, reg = 0;
 238
 239         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 240
 241         for (i = 0; i < attempts; i++) {
 242                 if (ee_reg == E1000_NVM_POLL_READ)
 243                         reg = E1000_READ_REG(hw, E1000_EERD);
 244                 else
 245                         reg = E1000_READ_REG(hw, E1000_EEWR);
 246
 247                 if (reg & E1000_NVM_RW_REG_DONE)
 248                         return E1000_SUCCESS;
 249
 250                 usec_delay(5);
 251         }
 252
 253         return -E1000_ERR_NVM;
 254 }
 255
 256 /**
 257  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 258  *  @hw: pointer to the HW structure
 259  *
 260  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 261  *  Return successful if access grant bit set, else clear the request for
 262  *  EEPROM access and return -E1000_ERR_NVM (-1).
 263  **/
 264 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 265 {
 266         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 267         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 268
 269         DEBUGFUNC("e1000_acquire_nvm_generic");
 270
 271         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 272         eecd = E1000_READ_REG(hw, E1000_EECD);
 273
 274         while (timeout) {
 275                 if (eecd & E1000_EECD_GNT)
 276                         break;
 277                 usec_delay(5);
 278                 eecd = E1000_READ_REG(hw, E1000_EECD);
 279                 timeout--;
 280         }
 281
 282         if (!timeout) {
 283                 eecd &= ~E1000_EECD_REQ;
 284                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 285                 DEBUGOUT("Could not acquire NVM grant\n");
 286                 return -E1000_ERR_NVM;
 287         }
 288
 289         return E1000_SUCCESS;
 290 }
 291
 292 /**
 293  *  e1000_standby_nvm - Return EEPROM to standby state
 294  *  @hw: pointer to the HW structure
 295  *
 296  *  Return the EEPROM to a standby state.
 297  **/
 298 static void e1000_standby_nvm(struct e1000_hw *hw)
 299 {
 300         struct e1000_nvm_info *nvm = &hw->nvm;
 301         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 302
 303         DEBUGFUNC("e1000_standby_nvm");
 304
 305         if (nvm->type == e1000_nvm_eeprom_microwire) {
 306                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 307                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 308                 E1000_WRITE_FLUSH(hw);
 309                 usec_delay(nvm->delay_usec);
 310
 311                 e1000_raise_eec_clk(hw, &eecd);
 312
 313                 /* Select EEPROM */
 314                 eecd |= E1000_EECD_CS;
 315                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 316                 E1000_WRITE_FLUSH(hw);
 317                 usec_delay(nvm->delay_usec);
 318
 319                 e1000_lower_eec_clk(hw, &eecd);
 320         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 321                 /* Toggle CS to flush commands */
 322                 eecd |= E1000_EECD_CS;
 323                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 324                 E1000_WRITE_FLUSH(hw);
 325                 usec_delay(nvm->delay_usec);
 326                 eecd &= ~E1000_EECD_CS;
 327                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 328                 E1000_WRITE_FLUSH(hw);
 329                 usec_delay(nvm->delay_usec);
 330         }
 331 }
 332
 333 /**
 334  *  e1000_stop_nvm - Terminate EEPROM command
 335  *  @hw: pointer to the HW structure
 336  *
 337  *  Terminates the current command by inverting the EEPROM's chip select pin.
 338  **/
 339 void e1000_stop_nvm(struct e1000_hw *hw)
 340 {
 341         u32 eecd;
 342
 343         DEBUGFUNC("e1000_stop_nvm");
 344
 345         eecd = E1000_READ_REG(hw, E1000_EECD);
 346         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 347                 /* Pull CS high */
 348                 eecd |= E1000_EECD_CS;
 349                 e1000_lower_eec_clk(hw, &eecd);
 350         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 351                 /* CS on Microwire is active-high */
 352                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 353                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 354                 e1000_raise_eec_clk(hw, &eecd);
 355                 e1000_lower_eec_clk(hw, &eecd);
 356         }
 357 }
 358
 359 /**
 360  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 361  *  @hw: pointer to the HW structure
 362  *
 363  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 364  **/
 365 void e1000_release_nvm_generic(struct e1000_hw *hw)
 366 {
 367         u32 eecd;
 368
 369         DEBUGFUNC("e1000_release_nvm_generic");
 370
 371         e1000_stop_nvm(hw);
 372
 373         eecd = E1000_READ_REG(hw, E1000_EECD);
 374         eecd &= ~E1000_EECD_REQ;
 375         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 376 }
 377
 378 /**
 379  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 380  *  @hw: pointer to the HW structure
 381  *
 382  *  Setups the EEPROM for reading and writing.
 383  **/
 384 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 385 {
 386         struct e1000_nvm_info *nvm = &hw->nvm;
 387         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 388         u8 spi_stat_reg;
 389
 390         DEBUGFUNC("e1000_ready_nvm_eeprom");
 391
 392         if (nvm->type == e1000_nvm_eeprom_microwire) {
 393                 /* Clear SK and DI */
 394                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 395                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 396                 /* Set CS */
 397                 eecd |= E1000_EECD_CS;
 398                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 399         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 400                 u16 timeout = NVM_MAX_RETRY_SPI;
 401
 402                 /* Clear SK and CS */
 403                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 404                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 405                 E1000_WRITE_FLUSH(hw);
 406                 usec_delay(1);
 407
 408                 /* Read "Status Register" repeatedly until the LSB is cleared.
 409                  * The EEPROM will signal that the command has been completed
 410                  * by clearing bit 0 of the internal status register.  If it's
 411                  * not cleared within 'timeout', then error out.
 412                  */
 413                 while (timeout) {
 414                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 415                                                  hw->nvm.opcode_bits);
 416                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 417                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 418                                 break;
 419
 420                         usec_delay(5);
 421                         e1000_standby_nvm(hw);
 422                         timeout--;
 423                 }
 424
 425                 if (!timeout) {
 426                         DEBUGOUT("SPI NVM Status error\n");
 427                         return -E1000_ERR_NVM;
 428                 }
 429         }
 430
 431         return E1000_SUCCESS;
 432 }
 433
 434 /**
 435  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 436  *  @hw: pointer to the HW structure
 437  *  @offset: offset of word in the EEPROM to read
 438  *  @words: number of words to read
 439  *  @data: word read from the EEPROM
 440  *
 441  *  Reads a 16 bit word from the EEPROM.
 442  **/
 443 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 444 {
 445         struct e1000_nvm_info *nvm = &hw->nvm;
 446         u32 i = 0;
 447         s32 ret_val;
 448         u16 word_in;
 449         u8 read_opcode = NVM_READ_OPCODE_SPI;
 450
 451         DEBUGFUNC("e1000_read_nvm_spi");
 452
 453         /* A check for invalid values:  offset too large, too many words,
 454          * and not enough words.
 455          */
 456         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 457             (words == 0)) {
 458                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 459                 return -E1000_ERR_NVM;
 460         }
 461
 462         ret_val = nvm->ops.acquire(hw);
 463         if (ret_val)
 464                 return ret_val;
 465
 466         ret_val = e1000_ready_nvm_eeprom(hw);
 467         if (ret_val)
 468                 goto release;
 469
 470         e1000_standby_nvm(hw);
 471
 472         if ((nvm->address_bits == 8) && (offset >= 128))
 473                 read_opcode |= NVM_A8_OPCODE_SPI;
 474
 475         /* Send the READ command (opcode + addr) */
 476         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 477         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 478
 479         /* Read the data.  SPI NVMs increment the address with each byte
 480          * read and will roll over if reading beyond the end.  This allows
 481          * us to read the whole NVM from any offset
 482          */
 483         for (i = 0; i < words; i++) {
 484                 word_in = e1000_shift_in_eec_bits(hw, 16);
 485                 data[i] = (word_in >> 8) | (word_in << 8);
 486         }
 487
 488 release:
 489         nvm->ops.release(hw);
 490
 491         return ret_val;
 492 }
 493
 494 /**
 495  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 496  *  @hw: pointer to the HW structure
 497  *  @offset: offset of word in the EEPROM to read
 498  *  @words: number of words to read
 499  *  @data: word read from the EEPROM
 500  *
 501  *  Reads a 16 bit word from the EEPROM.
 502  **/
 503 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 504                              u16 *data)
 505 {
 506         struct e1000_nvm_info *nvm = &hw->nvm;
 507         u32 i = 0;
 508         s32 ret_val;
 509         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 510
 511         DEBUGFUNC("e1000_read_nvm_microwire");
 512
 513         /* A check for invalid values:  offset too large, too many words,
 514          * and not enough words.
 515          */
 516         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 517             (words == 0)) {
 518                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 519                 return -E1000_ERR_NVM;
 520         }
 521
 522         ret_val = nvm->ops.acquire(hw);
 523         if (ret_val)
 524                 return ret_val;
 525
 526         ret_val = e1000_ready_nvm_eeprom(hw);
 527         if (ret_val)
 528                 goto release;
 529
 530         for (i = 0; i < words; i++) {
 531                 /* Send the READ command (opcode + addr) */
 532                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 533                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 534                                         nvm->address_bits);
 535
 536                 /* Read the data.  For microwire, each word requires the
 537                  * overhead of setup and tear-down.
 538                  */
 539                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 540                 e1000_standby_nvm(hw);
 541         }
 542
 543 release:
 544         nvm->ops.release(hw);
 545
 546         return ret_val;
 547 }
 548
 549 /**
 550  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 551  *  @hw: pointer to the HW structure
 552  *  @offset: offset of word in the EEPROM to read
 553  *  @words: number of words to read
 554  *  @data: word read from the EEPROM
 555  *
 556  *  Reads a 16 bit word from the EEPROM using the EERD register.
 557  **/
 558 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 559 {
 560         struct e1000_nvm_info *nvm = &hw->nvm;
 561         u32 i, eerd = 0;
 562         s32 ret_val = E1000_SUCCESS;
 563
 564         DEBUGFUNC("e1000_read_nvm_eerd");
 565
 566         /* A check for invalid values:  offset too large, too many words,
 567          * too many words for the offset, and not enough words.
 568          */
 569         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 570             (words == 0)) {
 571                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 572                 return -E1000_ERR_NVM;
 573         }
 574
 575         for (i = 0; i < words; i++) {
 576                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 577                        E1000_NVM_RW_REG_START;
 578
 579                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 580                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 581                 if (ret_val)
 582                         break;
 583
 584                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 585                            E1000_NVM_RW_REG_DATA);
 586         }
 587
 588         return ret_val;
 589 }
 590
 591 /**
 592  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 593  *  @hw: pointer to the HW structure
 594  *  @offset: offset within the EEPROM to be written to
 595  *  @words: number of words to write
 596  *  @data: 16 bit word(s) to be written to the EEPROM
 597  *
 598  *  Writes data to EEPROM at offset using SPI interface.
 599  *
 600  *  If e1000_update_nvm_checksum is not called after this function , the
 601  *  EEPROM will most likely contain an invalid checksum.
 602  **/
 603 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 604 {
 605         struct e1000_nvm_info *nvm = &hw->nvm;
 606         s32 ret_val = -E1000_ERR_NVM;
 607         u16 widx = 0;
 608
 609         DEBUGFUNC("e1000_write_nvm_spi");
 610
 611         /* A check for invalid values:  offset too large, too many words,
 612          * and not enough words.
 613          */
 614         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 615             (words == 0)) {
 616                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 617                 return -E1000_ERR_NVM;
 618         }
 619
 620         while (widx < words) {
 621                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 622
 623                 ret_val = nvm->ops.acquire(hw);
 624                 if (ret_val)
 625                         return ret_val;
 626
 627                 ret_val = e1000_ready_nvm_eeprom(hw);
 628                 if (ret_val) {
 629                         nvm->ops.release(hw);
 630                         return ret_val;
 631                 }
 632
 633                 e1000_standby_nvm(hw);
 634
 635                 /* Send the WRITE ENABLE command (8 bit opcode) */
 636                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 637                                          nvm->opcode_bits);
 638
 639                 e1000_standby_nvm(hw);
 640
 641                 /* Some SPI eeproms use the 8th address bit embedded in the
 642                  * opcode
 643                  */
 644                 if ((nvm->address_bits == 8) && (offset >= 128))
 645                         write_opcode |= NVM_A8_OPCODE_SPI;
 646
 647                 /* Send the Write command (8-bit opcode + addr) */
 648                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 649                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 650                                          nvm->address_bits);
 651
 652                 /* Loop to allow for up to whole page write of eeprom */
 653                 while (widx < words) {
 654                         u16 word_out = data[widx];
 655                         word_out = (word_out >> 8) | (word_out << 8);
 656                         e1000_shift_out_eec_bits(hw, word_out, 16);
 657                         widx++;
 658
 659                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 660                                 e1000_standby_nvm(hw);
 661                                 break;
 662                         }
 663                 }
 664                 msec_delay(10);
 665                 nvm->ops.release(hw);
 666         }
 667
 668         return ret_val;
 669 }
 670
 671 /**
 672  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 673  *  @hw: pointer to the HW structure
 674  *  @offset: offset within the EEPROM to be written to
 675  *  @words: number of words to write
 676  *  @data: 16 bit word(s) to be written to the EEPROM
 677  *
 678  *  Writes data to EEPROM at offset using microwire interface.
 679  *
 680  *  If e1000_update_nvm_checksum is not called after this function , the
 681  *  EEPROM will most likely contain an invalid checksum.
 682  **/
 683 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 684                               u16 *data)
 685 {
 686         struct e1000_nvm_info *nvm = &hw->nvm;
 687         s32  ret_val;
 688         u32 eecd;
 689         u16 words_written = 0;
 690         u16 widx = 0;
 691
 692         DEBUGFUNC("e1000_write_nvm_microwire");
 693
 694         /* A check for invalid values:  offset too large, too many words,
 695          * and not enough words.
 696          */
 697         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 698             (words == 0)) {
 699                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 700                 return -E1000_ERR_NVM;
 701         }
 702
 703         ret_val = nvm->ops.acquire(hw);
 704         if (ret_val)
 705                 return ret_val;
 706
 707         ret_val = e1000_ready_nvm_eeprom(hw);
 708         if (ret_val)
 709                 goto release;
 710
 711         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 712                                  (u16)(nvm->opcode_bits + 2));
 713
 714         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 715
 716         e1000_standby_nvm(hw);
 717
 718         while (words_written < words) {
 719                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 720                                          nvm->opcode_bits);
 721
 722                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 723                                          nvm->address_bits);
 724
 725                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 726
 727                 e1000_standby_nvm(hw);
 728
 729                 for (widx = 0; widx < 200; widx++) {
 730                         eecd = E1000_READ_REG(hw, E1000_EECD);
 731                         if (eecd & E1000_EECD_DO)
 732                                 break;
 733                         usec_delay(50);
 734                 }
 735
 736                 if (widx == 200) {
 737                         DEBUGOUT("NVM Write did not complete\n");
 738                         ret_val = -E1000_ERR_NVM;
 739                         goto release;
 740                 }
 741
 742                 e1000_standby_nvm(hw);
 743
 744                 words_written++;
 745         }
 746
 747         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 748                                  (u16)(nvm->opcode_bits + 2));
 749
 750         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 751
 752 release:
 753         nvm->ops.release(hw);
 754
 755         return ret_val;
 756 }
 757
 758 /**
 759  *  e1000_read_pba_string_generic - Read device part number
 760  *  @hw: pointer to the HW structure
 761  *  @pba_num: pointer to device part number
 762  *  @pba_num_size: size of part number buffer
 763  *
 764  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 765  *  the value in pba_num.
 766  **/
 767 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 768                                   u32 pba_num_size)
 769 {
 770         s32 ret_val;
 771         u16 nvm_data;
 772         u16 pba_ptr;
 773         u16 offset;
 774         u16 length;
 775
 776         DEBUGFUNC("e1000_read_pba_string_generic");
 777
 778         if (pba_num == NULL) {
 779                 DEBUGOUT("PBA string buffer was null\n");
 780                 return -E1000_ERR_INVALID_ARGUMENT;
 781         }
 782
 783         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 784         if (ret_val) {
 785                 DEBUGOUT("NVM Read Error\n");
 786                 return ret_val;
 787         }
 788
 789         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 790         if (ret_val) {
 791                 DEBUGOUT("NVM Read Error\n");
 792                 return ret_val;
 793         }
 794
 795         /* if nvm_data is not ptr guard the PBA must be in legacy format which
 796          * means pba_ptr is actually our second data word for the PBA number
 797          * and we can decode it into an ascii string
 798          */
 799         if (nvm_data != NVM_PBA_PTR_GUARD) {
 800                 DEBUGOUT("NVM PBA number is not stored as string\n");
 801
 802                 /* make sure callers buffer is big enough to store the PBA */
 803                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 804                         DEBUGOUT("PBA string buffer too small\n");
 805                         return E1000_ERR_NO_SPACE;
 806                 }
 807
 808                 /* extract hex string from data and pba_ptr */
 809                 pba_num[0] = (nvm_data >> 12) & 0xF;
 810                 pba_num[1] = (nvm_data >> 8) & 0xF;
 811                 pba_num[2] = (nvm_data >> 4) & 0xF;
 812                 pba_num[3] = nvm_data & 0xF;
 813                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 814                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 815                 pba_num[6] = '-';
 816                 pba_num[7] = 0;
 817                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 818                 pba_num[9] = pba_ptr & 0xF;
 819
 820                 /* put a null character on the end of our string */
 821                 pba_num[10] = '\0';
 822
 823                 /* switch all the data but the '-' to hex char */
 824                 for (offset = 0; offset < 10; offset++) {
 825                         if (pba_num[offset] < 0xA)
 826                                 pba_num[offset] += '0';
 827                         else if (pba_num[offset] < 0x10)
 828                                 pba_num[offset] += 'A' - 0xA;
 829                 }
 830
 831                 return E1000_SUCCESS;
 832         }
 833
 834         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 835         if (ret_val) {
 836                 DEBUGOUT("NVM Read Error\n");
 837                 return ret_val;
 838         }
 839
 840         if (length == 0xFFFF || length == 0) {
 841                 DEBUGOUT("NVM PBA number section invalid length\n");
 842                 return -E1000_ERR_NVM_PBA_SECTION;
 843         }
 844         /* check if pba_num buffer is big enough */
 845         if (pba_num_size < (((u32)length * 2) - 1)) {
 846                 DEBUGOUT("PBA string buffer too small\n");
 847                 return -E1000_ERR_NO_SPACE;
 848         }
 849
 850         /* trim pba length from start of string */
 851         pba_ptr++;
 852         length--;
 853
 854         for (offset = 0; offset < length; offset++) {
 855                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 856                 if (ret_val) {
 857                         DEBUGOUT("NVM Read Error\n");
 858                         return ret_val;
 859                 }
 860                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 861                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 862         }
 863         pba_num[offset * 2] = '\0';
 864
 865         return E1000_SUCCESS;
 866 }
 867
 868 /**
 869  *  e1000_read_pba_length_generic - Read device part number length
 870  *  @hw: pointer to the HW structure
 871  *  @pba_num_size: size of part number buffer
 872  *
 873  *  Reads the product board assembly (PBA) number length from the EEPROM and
 874  *  stores the value in pba_num_size.
 875  **/
 876 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 877 {
 878         s32 ret_val;
 879         u16 nvm_data;
 880         u16 pba_ptr;
 881         u16 length;
 882
 883         DEBUGFUNC("e1000_read_pba_length_generic");
 884
 885         if (pba_num_size == NULL) {
 886                 DEBUGOUT("PBA buffer size was null\n");
 887                 return -E1000_ERR_INVALID_ARGUMENT;
 888         }
 889
 890         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 891         if (ret_val) {
 892                 DEBUGOUT("NVM Read Error\n");
 893                 return ret_val;
 894         }
 895
 896         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 897         if (ret_val) {
 898                 DEBUGOUT("NVM Read Error\n");
 899                 return ret_val;
 900         }
 901
 902          /* if data is not ptr guard the PBA must be in legacy format */
 903         if (nvm_data != NVM_PBA_PTR_GUARD) {
 904                 *pba_num_size = E1000_PBANUM_LENGTH;
 905                 return E1000_SUCCESS;
 906         }
 907
 908         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 909         if (ret_val) {
 910                 DEBUGOUT("NVM Read Error\n");
 911                 return ret_val;
 912         }
 913
 914         if (length == 0xFFFF || length == 0) {
 915                 DEBUGOUT("NVM PBA number section invalid length\n");
 916                 return -E1000_ERR_NVM_PBA_SECTION;
 917         }
 918
 919         /* Convert from length in u16 values to u8 chars, add 1 for NULL,
 920          * and subtract 2 because length field is included in length.
 921          */
 922         *pba_num_size = ((u32)length * 2) - 1;
 923
 924         return E1000_SUCCESS;
 925 }
 926
 927
 928 /**
 929  *  e1000_read_pba_raw
 930  *  @hw: pointer to the HW structure
 931  *  @eeprom_buf: optional pointer to EEPROM image
 932  *  @eeprom_buf_size: size of EEPROM image in words
 933  *  @max_pba_block_size: PBA block size limit
 934  *  @pba: pointer to output PBA structure
 935  *
 936  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 937  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 938  *
 939  **/
 940 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 941                        u32 eeprom_buf_size, u16 max_pba_block_size,
 942                        struct e1000_pba *pba)
 943 {
 944         s32 ret_val;
 945         u16 pba_block_size;
 946
 947         if (pba == NULL)
 948                 return -E1000_ERR_PARAM;
 949
 950         if (eeprom_buf == NULL) {
 951                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 952                                          &pba->word[0]);
 953                 if (ret_val)
 954                         return ret_val;
 955         } else {
 956                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
 957                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
 958                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
 959                 } else {
 960                         return -E1000_ERR_PARAM;
 961                 }
 962         }
 963
 964         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
 965                 if (pba->pba_block == NULL)
 966                         return -E1000_ERR_PARAM;
 967
 968                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
 969                                                    eeprom_buf_size,
 970                                                    &pba_block_size);
 971                 if (ret_val)
 972                         return ret_val;
 973
 974                 if (pba_block_size > max_pba_block_size)
 975                         return -E1000_ERR_PARAM;
 976
 977                 if (eeprom_buf == NULL) {
 978                         ret_val = e1000_read_nvm(hw, pba->word[1],
 979                                                  pba_block_size,
 980                                                  pba->pba_block);
 981                         if (ret_val)
 982                                 return ret_val;
 983                 } else {
 984                         if (eeprom_buf_size > (u32)(pba->word[1] +
 985                                               pba->pba_block[0])) {
 986                                 memcpy(pba->pba_block,
 987                                        &eeprom_buf[pba->word[1]],
 988                                        pba_block_size * sizeof(u16));
 989                         } else {
 990                                 return -E1000_ERR_PARAM;
 991                         }
 992                 }
 993         }
 994
 995         return E1000_SUCCESS;
 996 }
 997
 998 /**
 999  *  e1000_write_pba_raw
1000  *  @hw: pointer to the HW structure
1001  *  @eeprom_buf: optional pointer to EEPROM image
1002  *  @eeprom_buf_size: size of EEPROM image in words
1003  *  @pba: pointer to PBA structure
1004  *
1005  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1006  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1007  *
1008  **/
1009 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1010                         u32 eeprom_buf_size, struct e1000_pba *pba)
1011 {
1012         s32 ret_val;
1013
1014         if (pba == NULL)
1015                 return -E1000_ERR_PARAM;
1016
1017         if (eeprom_buf == NULL) {
1018                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1019                                           &pba->word[0]);
1020                 if (ret_val)
1021                         return ret_val;
1022         } else {
1023                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1024                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1025                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1026                 } else {
1027                         return -E1000_ERR_PARAM;
1028                 }
1029         }
1030
1031         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1032                 if (pba->pba_block == NULL)
1033                         return -E1000_ERR_PARAM;
1034
1035                 if (eeprom_buf == NULL) {
1036                         ret_val = e1000_write_nvm(hw, pba->word[1],
1037                                                   pba->pba_block[0],
1038                                                   pba->pba_block);
1039                         if (ret_val)
1040                                 return ret_val;
1041                 } else {
1042                         if (eeprom_buf_size > (u32)(pba->word[1] +
1043                                               pba->pba_block[0])) {
1044                                 memcpy(&eeprom_buf[pba->word[1]],
1045                                        pba->pba_block,
1046                                        pba->pba_block[0] * sizeof(u16));
1047                         } else {
1048                                 return -E1000_ERR_PARAM;
1049                         }
1050                 }
1051         }
1052
1053         return E1000_SUCCESS;
1054 }
1055
1056 /**
1057  *  e1000_get_pba_block_size
1058  *  @hw: pointer to the HW structure
1059  *  @eeprom_buf: optional pointer to EEPROM image
1060  *  @eeprom_buf_size: size of EEPROM image in words
1061  *  @pba_data_size: pointer to output variable
1062  *
1063  *  Returns the size of the PBA block in words. Function operates on EEPROM
1064  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1065  *  EEPROM device.
1066  *
1067  **/
1068 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1069                              u32 eeprom_buf_size, u16 *pba_block_size)
1070 {
1071         s32 ret_val;
1072         u16 pba_word[2];
1073         u16 length;
1074
1075         DEBUGFUNC("e1000_get_pba_block_size");
1076
1077         if (eeprom_buf == NULL) {
1078                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1079                 if (ret_val)
1080                         return ret_val;
1081         } else {
1082                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1083                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1084                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1085                 } else {
1086                         return -E1000_ERR_PARAM;
1087                 }
1088         }
1089
1090         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1091                 if (eeprom_buf == NULL) {
1092                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1093                                                  &length);
1094                         if (ret_val)
1095                                 return ret_val;
1096                 } else {
1097                         if (eeprom_buf_size > pba_word[1])
1098                                 length = eeprom_buf[pba_word[1] + 0];
1099                         else
1100                                 return -E1000_ERR_PARAM;
1101                 }
1102
1103                 if (length == 0xFFFF || length == 0)
1104                         return -E1000_ERR_NVM_PBA_SECTION;
1105         } else {
1106                 /* PBA number in legacy format, there is no PBA Block. */
1107                 length = 0;
1108         }
1109
1110         if (pba_block_size != NULL)
1111                 *pba_block_size = length;
1112
1113         return E1000_SUCCESS;
1114 }
1115
1116 /**
1117  *  e1000_read_mac_addr_generic - Read device MAC address
1118  *  @hw: pointer to the HW structure
1119  *
1120  *  Reads the device MAC address from the EEPROM and stores the value.
1121  *  Since devices with two ports use the same EEPROM, we increment the
1122  *  last bit in the MAC address for the second port.
1123  **/
1124 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1125 {
1126         u32 rar_high;
1127         u32 rar_low;
1128         u16 i;
1129
1130         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1131         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1132
1133         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1134                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1135
1136         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1137                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1138
1139         for (i = 0; i < ETH_ADDR_LEN; i++)
1140                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1141
1142         return E1000_SUCCESS;
1143 }
1144
1145 /**
1146  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1147  *  @hw: pointer to the HW structure
1148  *
1149  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1150  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1151  **/
1152 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1153 {
1154         s32 ret_val;
1155         u16 checksum = 0;
1156         u16 i, nvm_data;
1157
1158         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1159
1160         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1161                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1162                 if (ret_val) {
1163                         DEBUGOUT("NVM Read Error\n");
1164                         return ret_val;
1165                 }
1166                 checksum += nvm_data;
1167         }
1168
1169         if (checksum != (u16) NVM_SUM) {
1170                 DEBUGOUT("NVM Checksum Invalid\n");
1171                 return -E1000_ERR_NVM;
1172         }
1173
1174         return E1000_SUCCESS;
1175 }
1176
1177 /**
1178  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1179  *  @hw: pointer to the HW structure
1180  *
1181  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1182  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1183  *  value to the EEPROM.
1184  **/
1185 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1186 {
1187         s32 ret_val;
1188         u16 checksum = 0;
1189         u16 i, nvm_data;
1190
1191         DEBUGFUNC("e1000_update_nvm_checksum");
1192
1193         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1194                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1195                 if (ret_val) {
1196                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1197                         return ret_val;
1198                 }
1199                 checksum += nvm_data;
1200         }
1201         checksum = (u16) NVM_SUM - checksum;
1202         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1203         if (ret_val)
1204                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1205
1206         return ret_val;
1207 }
1208
1209 /**
1210  *  e1000_reload_nvm_generic - Reloads EEPROM
1211  *  @hw: pointer to the HW structure
1212  *
1213  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1214  *  extended control register.
1215  **/
1216 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1217 {
1218         u32 ctrl_ext;
1219
1220         DEBUGFUNC("e1000_reload_nvm_generic");
1221
1222         usec_delay(10);
1223         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1224         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1225         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1226         E1000_WRITE_FLUSH(hw);
1227 }
1228
1229 /**
1230  *  e1000_get_fw_version - Get firmware version information
1231  *  @hw: pointer to the HW structure
1232  *  @fw_vers: pointer to output version structure
1233  *
1234  *  unsupported/not present features return 0 in version structure
1235  **/
1236 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1237 {
1238         u16 eeprom_verh, eeprom_verl, fw_version;
1239         u16 comb_verh, comb_verl, comb_offset;
1240
1241         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1242
1243         /* this code only applies to certain mac types */
1244         switch (hw->mac.type) {
1245         case e1000_i211:
1246                 e1000_read_invm_version(hw, fw_vers);
1247                 return;
1248         case e1000_82575:
1249         case e1000_82576:
1250         case e1000_82580:
1251         case e1000_i350:
1252         case e1000_i210:
1253                 break;
1254         default:
1255                 return;
1256         }
1257
1258         /* basic eeprom version numbers */
1259         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1260         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
1261         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK);
1262
1263         /* etrack id */
1264         hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1265         hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1266         fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl;
1267
1268         switch (hw->mac.type) {
1269         case e1000_i210:
1270         case e1000_i350:
1271                 /* find combo image version */
1272                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1273                 if ((comb_offset != 0x0) &&
1274                     (comb_offset != NVM_VER_INVALID)) {
1275
1276                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1277                                          + 1), 1, &comb_verh);
1278                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1279                                          1, &comb_verl);
1280
1281                         /* get Option Rom version if it exists and is valid */
1282                         if ((comb_verh && comb_verl) &&
1283                             ((comb_verh != NVM_VER_INVALID) &&
1284                              (comb_verl != NVM_VER_INVALID))) {
1285
1286                                 fw_vers->or_valid = true;
1287                                 fw_vers->or_major =
1288                                         comb_verl >> NVM_COMB_VER_SHFT;
1289                                 fw_vers->or_build =
1290                                         (comb_verl << NVM_COMB_VER_SHFT)
1291                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1292                                 fw_vers->or_patch =
1293                                         comb_verh & NVM_COMB_VER_MASK;
1294                         }
1295                 }
1296                 break;
1297
1298         default:
1299                 break;
1300         }
1301         return;
1302 }
1303
1304