1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 static void e1000_stop_nvm(struct e1000_hw *hw);
37 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
41 * @hw: pointer to the HW structure
43 * Setups up the function pointers to no-op functions
45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
47 struct e1000_nvm_info *nvm = &hw->nvm;
48 DEBUGFUNC("e1000_init_nvm_ops_generic");
50 /* Initialize function pointers */
51 nvm->ops.init_params = e1000_null_ops_generic;
52 nvm->ops.acquire = e1000_null_ops_generic;
53 nvm->ops.read = e1000_null_read_nvm;
54 nvm->ops.release = e1000_null_nvm_generic;
55 nvm->ops.reload = e1000_reload_nvm_generic;
56 nvm->ops.update = e1000_null_ops_generic;
57 nvm->ops.valid_led_default = e1000_null_led_default;
58 nvm->ops.validate = e1000_null_ops_generic;
59 nvm->ops.write = e1000_null_write_nvm;
63 * e1000_null_nvm_read - No-op function, return 0
64 * @hw: pointer to the HW structure
66 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
68 DEBUGFUNC("e1000_null_read_nvm");
73 * e1000_null_nvm_generic - No-op function, return void
74 * @hw: pointer to the HW structure
76 void e1000_null_nvm_generic(struct e1000_hw *hw)
78 DEBUGFUNC("e1000_null_nvm_generic");
83 * e1000_null_led_default - No-op function, return 0
84 * @hw: pointer to the HW structure
86 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data)
88 DEBUGFUNC("e1000_null_led_default");
93 * e1000_null_write_nvm - No-op function, return 0
94 * @hw: pointer to the HW structure
96 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c)
98 DEBUGFUNC("e1000_null_write_nvm");
103 * e1000_raise_eec_clk - Raise EEPROM clock
104 * @hw: pointer to the HW structure
105 * @eecd: pointer to the EEPROM
107 * Enable/Raise the EEPROM clock bit.
109 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
111 *eecd = *eecd | E1000_EECD_SK;
112 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
113 E1000_WRITE_FLUSH(hw);
114 usec_delay(hw->nvm.delay_usec);
118 * e1000_lower_eec_clk - Lower EEPROM clock
119 * @hw: pointer to the HW structure
120 * @eecd: pointer to the EEPROM
122 * Clear/Lower the EEPROM clock bit.
124 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
126 *eecd = *eecd & ~E1000_EECD_SK;
127 E1000_WRITE_REG(hw, E1000_EECD, *eecd);
128 E1000_WRITE_FLUSH(hw);
129 usec_delay(hw->nvm.delay_usec);
133 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
134 * @hw: pointer to the HW structure
135 * @data: data to send to the EEPROM
136 * @count: number of bits to shift out
138 * We need to shift 'count' bits out to the EEPROM. So, the value in the
139 * "data" parameter will be shifted out to the EEPROM one bit at a time.
140 * In order to do this, "data" must be broken down into bits.
142 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
144 struct e1000_nvm_info *nvm = &hw->nvm;
145 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
148 DEBUGFUNC("e1000_shift_out_eec_bits");
150 mask = 0x01 << (count - 1);
151 if (nvm->type == e1000_nvm_eeprom_microwire)
152 eecd &= ~E1000_EECD_DO;
154 if (nvm->type == e1000_nvm_eeprom_spi)
155 eecd |= E1000_EECD_DO;
158 eecd &= ~E1000_EECD_DI;
161 eecd |= E1000_EECD_DI;
163 E1000_WRITE_REG(hw, E1000_EECD, eecd);
164 E1000_WRITE_FLUSH(hw);
166 usec_delay(nvm->delay_usec);
168 e1000_raise_eec_clk(hw, &eecd);
169 e1000_lower_eec_clk(hw, &eecd);
174 eecd &= ~E1000_EECD_DI;
175 E1000_WRITE_REG(hw, E1000_EECD, eecd);
179 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
180 * @hw: pointer to the HW structure
181 * @count: number of bits to shift in
183 * In order to read a register from the EEPROM, we need to shift 'count' bits
184 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
185 * the EEPROM (setting the SK bit), and then reading the value of the data out
186 * "DO" bit. During this "shifting in" process the data in "DI" bit should
189 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
195 DEBUGFUNC("e1000_shift_in_eec_bits");
197 eecd = E1000_READ_REG(hw, E1000_EECD);
199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
202 for (i = 0; i < count; i++) {
204 e1000_raise_eec_clk(hw, &eecd);
206 eecd = E1000_READ_REG(hw, E1000_EECD);
208 eecd &= ~E1000_EECD_DI;
209 if (eecd & E1000_EECD_DO)
212 e1000_lower_eec_clk(hw, &eecd);
219 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
220 * @hw: pointer to the HW structure
221 * @ee_reg: EEPROM flag for polling
223 * Polls the EEPROM status bit for either read or write completion based
224 * upon the value of 'ee_reg'.
226 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
228 u32 attempts = 100000;
230 s32 ret_val = -E1000_ERR_NVM;
232 DEBUGFUNC("e1000_poll_eerd_eewr_done");
234 for (i = 0; i < attempts; i++) {
235 if (ee_reg == E1000_NVM_POLL_READ)
236 reg = E1000_READ_REG(hw, E1000_EERD);
238 reg = E1000_READ_REG(hw, E1000_EEWR);
240 if (reg & E1000_NVM_RW_REG_DONE) {
241 ret_val = E1000_SUCCESS;
252 * e1000_acquire_nvm_generic - Generic request for access to EEPROM
253 * @hw: pointer to the HW structure
255 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
256 * Return successful if access grant bit set, else clear the request for
257 * EEPROM access and return -E1000_ERR_NVM (-1).
259 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
261 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
262 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
263 s32 ret_val = E1000_SUCCESS;
265 DEBUGFUNC("e1000_acquire_nvm_generic");
267 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
268 eecd = E1000_READ_REG(hw, E1000_EECD);
271 if (eecd & E1000_EECD_GNT)
274 eecd = E1000_READ_REG(hw, E1000_EECD);
279 eecd &= ~E1000_EECD_REQ;
280 E1000_WRITE_REG(hw, E1000_EECD, eecd);
281 DEBUGOUT("Could not acquire NVM grant\n");
282 ret_val = -E1000_ERR_NVM;
289 * e1000_standby_nvm - Return EEPROM to standby state
290 * @hw: pointer to the HW structure
292 * Return the EEPROM to a standby state.
294 static void e1000_standby_nvm(struct e1000_hw *hw)
296 struct e1000_nvm_info *nvm = &hw->nvm;
297 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
299 DEBUGFUNC("e1000_standby_nvm");
301 if (nvm->type == e1000_nvm_eeprom_microwire) {
302 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
303 E1000_WRITE_REG(hw, E1000_EECD, eecd);
304 E1000_WRITE_FLUSH(hw);
305 usec_delay(nvm->delay_usec);
307 e1000_raise_eec_clk(hw, &eecd);
310 eecd |= E1000_EECD_CS;
311 E1000_WRITE_REG(hw, E1000_EECD, eecd);
312 E1000_WRITE_FLUSH(hw);
313 usec_delay(nvm->delay_usec);
315 e1000_lower_eec_clk(hw, &eecd);
317 if (nvm->type == e1000_nvm_eeprom_spi) {
318 /* Toggle CS to flush commands */
319 eecd |= E1000_EECD_CS;
320 E1000_WRITE_REG(hw, E1000_EECD, eecd);
321 E1000_WRITE_FLUSH(hw);
322 usec_delay(nvm->delay_usec);
323 eecd &= ~E1000_EECD_CS;
324 E1000_WRITE_REG(hw, E1000_EECD, eecd);
325 E1000_WRITE_FLUSH(hw);
326 usec_delay(nvm->delay_usec);
331 * e1000_stop_nvm - Terminate EEPROM command
332 * @hw: pointer to the HW structure
334 * Terminates the current command by inverting the EEPROM's chip select pin.
336 static void e1000_stop_nvm(struct e1000_hw *hw)
340 DEBUGFUNC("e1000_stop_nvm");
342 eecd = E1000_READ_REG(hw, E1000_EECD);
343 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
345 eecd |= E1000_EECD_CS;
346 e1000_lower_eec_clk(hw, &eecd);
347 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
348 /* CS on Microwire is active-high */
349 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
350 E1000_WRITE_REG(hw, E1000_EECD, eecd);
351 e1000_raise_eec_clk(hw, &eecd);
352 e1000_lower_eec_clk(hw, &eecd);
357 * e1000_release_nvm_generic - Release exclusive access to EEPROM
358 * @hw: pointer to the HW structure
360 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
362 void e1000_release_nvm_generic(struct e1000_hw *hw)
366 DEBUGFUNC("e1000_release_nvm_generic");
370 eecd = E1000_READ_REG(hw, E1000_EECD);
371 eecd &= ~E1000_EECD_REQ;
372 E1000_WRITE_REG(hw, E1000_EECD, eecd);
376 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
377 * @hw: pointer to the HW structure
379 * Setups the EEPROM for reading and writing.
381 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
383 struct e1000_nvm_info *nvm = &hw->nvm;
384 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
385 s32 ret_val = E1000_SUCCESS;
388 DEBUGFUNC("e1000_ready_nvm_eeprom");
390 if (nvm->type == e1000_nvm_eeprom_microwire) {
391 /* Clear SK and DI */
392 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
393 E1000_WRITE_REG(hw, E1000_EECD, eecd);
395 eecd |= E1000_EECD_CS;
396 E1000_WRITE_REG(hw, E1000_EECD, eecd);
398 if (nvm->type == e1000_nvm_eeprom_spi) {
399 u16 timeout = NVM_MAX_RETRY_SPI;
401 /* Clear SK and CS */
402 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
403 E1000_WRITE_REG(hw, E1000_EECD, eecd);
407 * Read "Status Register" repeatedly until the LSB is cleared.
408 * The EEPROM will signal that the command has been completed
409 * by clearing bit 0 of the internal status register. If it's
410 * not cleared within 'timeout', then error out.
413 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
414 hw->nvm.opcode_bits);
415 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
416 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
420 e1000_standby_nvm(hw);
425 DEBUGOUT("SPI NVM Status error\n");
426 ret_val = -E1000_ERR_NVM;
436 * e1000_read_nvm_spi - Read EEPROM's using SPI
437 * @hw: pointer to the HW structure
438 * @offset: offset of word in the EEPROM to read
439 * @words: number of words to read
440 * @data: word read from the EEPROM
442 * Reads a 16 bit word from the EEPROM.
444 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
446 struct e1000_nvm_info *nvm = &hw->nvm;
450 u8 read_opcode = NVM_READ_OPCODE_SPI;
452 DEBUGFUNC("e1000_read_nvm_spi");
455 * A check for invalid values: offset too large, too many words,
456 * and not enough words.
458 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
460 DEBUGOUT("nvm parameter(s) out of bounds\n");
461 ret_val = -E1000_ERR_NVM;
465 ret_val = nvm->ops.acquire(hw);
469 ret_val = e1000_ready_nvm_eeprom(hw);
473 e1000_standby_nvm(hw);
475 if ((nvm->address_bits == 8) && (offset >= 128))
476 read_opcode |= NVM_A8_OPCODE_SPI;
478 /* Send the READ command (opcode + addr) */
479 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
480 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
483 * Read the data. SPI NVMs increment the address with each byte
484 * read and will roll over if reading beyond the end. This allows
485 * us to read the whole NVM from any offset
487 for (i = 0; i < words; i++) {
488 word_in = e1000_shift_in_eec_bits(hw, 16);
489 data[i] = (word_in >> 8) | (word_in << 8);
493 nvm->ops.release(hw);
500 * e1000_read_nvm_microwire - Reads EEPROM's using microwire
501 * @hw: pointer to the HW structure
502 * @offset: offset of word in the EEPROM to read
503 * @words: number of words to read
504 * @data: word read from the EEPROM
506 * Reads a 16 bit word from the EEPROM.
508 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
511 struct e1000_nvm_info *nvm = &hw->nvm;
514 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
516 DEBUGFUNC("e1000_read_nvm_microwire");
519 * A check for invalid values: offset too large, too many words,
520 * and not enough words.
522 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
524 DEBUGOUT("nvm parameter(s) out of bounds\n");
525 ret_val = -E1000_ERR_NVM;
529 ret_val = nvm->ops.acquire(hw);
533 ret_val = e1000_ready_nvm_eeprom(hw);
537 for (i = 0; i < words; i++) {
538 /* Send the READ command (opcode + addr) */
539 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
540 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
544 * Read the data. For microwire, each word requires the
545 * overhead of setup and tear-down.
547 data[i] = e1000_shift_in_eec_bits(hw, 16);
548 e1000_standby_nvm(hw);
552 nvm->ops.release(hw);
559 * e1000_read_nvm_eerd - Reads EEPROM using EERD register
560 * @hw: pointer to the HW structure
561 * @offset: offset of word in the EEPROM to read
562 * @words: number of words to read
563 * @data: word read from the EEPROM
565 * Reads a 16 bit word from the EEPROM using the EERD register.
567 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
569 struct e1000_nvm_info *nvm = &hw->nvm;
571 s32 ret_val = E1000_SUCCESS;
573 DEBUGFUNC("e1000_read_nvm_eerd");
576 * A check for invalid values: offset too large, too many words,
577 * too many words for the offset, and not enough words.
579 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
581 DEBUGOUT("nvm parameter(s) out of bounds\n");
582 ret_val = -E1000_ERR_NVM;
586 for (i = 0; i < words; i++) {
587 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
588 E1000_NVM_RW_REG_START;
590 E1000_WRITE_REG(hw, E1000_EERD, eerd);
591 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
595 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
596 E1000_NVM_RW_REG_DATA);
604 * e1000_write_nvm_spi - Write to EEPROM using SPI
605 * @hw: pointer to the HW structure
606 * @offset: offset within the EEPROM to be written to
607 * @words: number of words to write
608 * @data: 16 bit word(s) to be written to the EEPROM
610 * Writes data to EEPROM at offset using SPI interface.
612 * If e1000_update_nvm_checksum is not called after this function , the
613 * EEPROM will most likely contain an invalid checksum.
615 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
617 struct e1000_nvm_info *nvm = &hw->nvm;
621 DEBUGFUNC("e1000_write_nvm_spi");
624 * A check for invalid values: offset too large, too many words,
625 * and not enough words.
627 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
629 DEBUGOUT("nvm parameter(s) out of bounds\n");
630 ret_val = -E1000_ERR_NVM;
634 ret_val = nvm->ops.acquire(hw);
638 while (widx < words) {
639 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
641 ret_val = e1000_ready_nvm_eeprom(hw);
645 e1000_standby_nvm(hw);
647 /* Send the WRITE ENABLE command (8 bit opcode) */
648 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
651 e1000_standby_nvm(hw);
654 * Some SPI eeproms use the 8th address bit embedded in the
657 if ((nvm->address_bits == 8) && (offset >= 128))
658 write_opcode |= NVM_A8_OPCODE_SPI;
660 /* Send the Write command (8-bit opcode + addr) */
661 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
662 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
665 /* Loop to allow for up to whole page write of eeprom */
666 while (widx < words) {
667 u16 word_out = data[widx];
668 word_out = (word_out >> 8) | (word_out << 8);
669 e1000_shift_out_eec_bits(hw, word_out, 16);
672 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
673 e1000_standby_nvm(hw);
681 nvm->ops.release(hw);
688 * e1000_write_nvm_microwire - Writes EEPROM using microwire
689 * @hw: pointer to the HW structure
690 * @offset: offset within the EEPROM to be written to
691 * @words: number of words to write
692 * @data: 16 bit word(s) to be written to the EEPROM
694 * Writes data to EEPROM at offset using microwire interface.
696 * If e1000_update_nvm_checksum is not called after this function , the
697 * EEPROM will most likely contain an invalid checksum.
699 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
702 struct e1000_nvm_info *nvm = &hw->nvm;
705 u16 words_written = 0;
708 DEBUGFUNC("e1000_write_nvm_microwire");
711 * A check for invalid values: offset too large, too many words,
712 * and not enough words.
714 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
716 DEBUGOUT("nvm parameter(s) out of bounds\n");
717 ret_val = -E1000_ERR_NVM;
721 ret_val = nvm->ops.acquire(hw);
725 ret_val = e1000_ready_nvm_eeprom(hw);
729 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
730 (u16)(nvm->opcode_bits + 2));
732 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
734 e1000_standby_nvm(hw);
736 while (words_written < words) {
737 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
740 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
743 e1000_shift_out_eec_bits(hw, data[words_written], 16);
745 e1000_standby_nvm(hw);
747 for (widx = 0; widx < 200; widx++) {
748 eecd = E1000_READ_REG(hw, E1000_EECD);
749 if (eecd & E1000_EECD_DO)
755 DEBUGOUT("NVM Write did not complete\n");
756 ret_val = -E1000_ERR_NVM;
760 e1000_standby_nvm(hw);
765 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
766 (u16)(nvm->opcode_bits + 2));
768 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
771 nvm->ops.release(hw);
778 * e1000_read_pba_string_generic - Read device part number
779 * @hw: pointer to the HW structure
780 * @pba_num: pointer to device part number
781 * @pba_num_size: size of part number buffer
783 * Reads the product board assembly (PBA) number from the EEPROM and stores
784 * the value in pba_num.
786 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
795 DEBUGFUNC("e1000_read_pba_string_generic");
797 if (pba_num == NULL) {
798 DEBUGOUT("PBA string buffer was null\n");
799 ret_val = E1000_ERR_INVALID_ARGUMENT;
803 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
805 DEBUGOUT("NVM Read Error\n");
809 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
811 DEBUGOUT("NVM Read Error\n");
816 * if nvm_data is not ptr guard the PBA must be in legacy format which
817 * means pba_ptr is actually our second data word for the PBA number
818 * and we can decode it into an ascii string
820 if (nvm_data != NVM_PBA_PTR_GUARD) {
821 DEBUGOUT("NVM PBA number is not stored as string\n");
823 /* we will need 11 characters to store the PBA */
824 if (pba_num_size < 11) {
825 DEBUGOUT("PBA string buffer too small\n");
826 return E1000_ERR_NO_SPACE;
829 /* extract hex string from data and pba_ptr */
830 pba_num[0] = (nvm_data >> 12) & 0xF;
831 pba_num[1] = (nvm_data >> 8) & 0xF;
832 pba_num[2] = (nvm_data >> 4) & 0xF;
833 pba_num[3] = nvm_data & 0xF;
834 pba_num[4] = (pba_ptr >> 12) & 0xF;
835 pba_num[5] = (pba_ptr >> 8) & 0xF;
838 pba_num[8] = (pba_ptr >> 4) & 0xF;
839 pba_num[9] = pba_ptr & 0xF;
841 /* put a null character on the end of our string */
844 /* switch all the data but the '-' to hex char */
845 for (offset = 0; offset < 10; offset++) {
846 if (pba_num[offset] < 0xA)
847 pba_num[offset] += '0';
848 else if (pba_num[offset] < 0x10)
849 pba_num[offset] += 'A' - 0xA;
855 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
857 DEBUGOUT("NVM Read Error\n");
861 if (length == 0xFFFF || length == 0) {
862 DEBUGOUT("NVM PBA number section invalid length\n");
863 ret_val = E1000_ERR_NVM_PBA_SECTION;
866 /* check if pba_num buffer is big enough */
867 if (pba_num_size < (((u32)length * 2) - 1)) {
868 DEBUGOUT("PBA string buffer too small\n");
869 ret_val = E1000_ERR_NO_SPACE;
873 /* trim pba length from start of string */
877 for (offset = 0; offset < length; offset++) {
878 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
880 DEBUGOUT("NVM Read Error\n");
883 pba_num[offset * 2] = (u8)(nvm_data >> 8);
884 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
886 pba_num[offset * 2] = '\0';
893 * e1000_read_pba_length_generic - Read device part number length
894 * @hw: pointer to the HW structure
895 * @pba_num_size: size of part number buffer
897 * Reads the product board assembly (PBA) number length from the EEPROM and
898 * stores the value in pba_num_size.
900 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
907 DEBUGFUNC("e1000_read_pba_length_generic");
909 if (pba_num_size == NULL) {
910 DEBUGOUT("PBA buffer size was null\n");
911 ret_val = E1000_ERR_INVALID_ARGUMENT;
915 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
917 DEBUGOUT("NVM Read Error\n");
921 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
923 DEBUGOUT("NVM Read Error\n");
927 /* if data is not ptr guard the PBA must be in legacy format */
928 if (nvm_data != NVM_PBA_PTR_GUARD) {
933 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
935 DEBUGOUT("NVM Read Error\n");
939 if (length == 0xFFFF || length == 0) {
940 DEBUGOUT("NVM PBA number section invalid length\n");
941 ret_val = E1000_ERR_NVM_PBA_SECTION;
946 * Convert from length in u16 values to u8 chars, add 1 for NULL,
947 * and subtract 2 because length field is included in length.
949 *pba_num_size = ((u32)length * 2) - 1;
956 * e1000_read_mac_addr_generic - Read device MAC address
957 * @hw: pointer to the HW structure
959 * Reads the device MAC address from the EEPROM and stores the value.
960 * Since devices with two ports use the same EEPROM, we increment the
961 * last bit in the MAC address for the second port.
963 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
969 rar_high = E1000_READ_REG(hw, E1000_RAH(0));
970 rar_low = E1000_READ_REG(hw, E1000_RAL(0));
972 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
973 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
975 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
976 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
978 for (i = 0; i < ETH_ADDR_LEN; i++)
979 hw->mac.addr[i] = hw->mac.perm_addr[i];
981 return E1000_SUCCESS;
985 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
986 * @hw: pointer to the HW structure
988 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
989 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
991 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
993 s32 ret_val = E1000_SUCCESS;
997 DEBUGFUNC("e1000_validate_nvm_checksum_generic");
999 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1000 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1002 DEBUGOUT("NVM Read Error\n");
1005 checksum += nvm_data;
1008 if (checksum != (u16) NVM_SUM) {
1009 DEBUGOUT("NVM Checksum Invalid\n");
1010 ret_val = -E1000_ERR_NVM;
1019 * e1000_update_nvm_checksum_generic - Update EEPROM checksum
1020 * @hw: pointer to the HW structure
1022 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1023 * up to the checksum. Then calculates the EEPROM checksum and writes the
1024 * value to the EEPROM.
1026 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1032 DEBUGFUNC("e1000_update_nvm_checksum");
1034 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1035 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1037 DEBUGOUT("NVM Read Error while updating checksum.\n");
1040 checksum += nvm_data;
1042 checksum = (u16) NVM_SUM - checksum;
1043 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1045 DEBUGOUT("NVM Write Error while updating checksum.\n");
1052 * e1000_reload_nvm_generic - Reloads EEPROM
1053 * @hw: pointer to the HW structure
1055 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1056 * extended control register.
1058 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1062 DEBUGFUNC("e1000_reload_nvm_generic");
1065 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1066 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1067 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1068 E1000_WRITE_FLUSH(hw);