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3 Copyright (c) 2001-2014, Intel Corporation
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35 #ifndef _E1000_OSDEP_H_
36 #define _E1000_OSDEP_H_
42 #include <rte_common.h>
43 #include <rte_cycles.h>
45 #include <rte_debug.h>
47 #include "../e1000_logs.h"
49 #define DELAY(x) rte_delay_us(x)
50 #define usec_delay(x) DELAY(x)
51 #define usec_delay_irq(x) DELAY(x)
52 #define msec_delay(x) DELAY(1000*(x))
53 #define msec_delay_irq(x) DELAY(1000*(x))
55 #define DEBUGFUNC(F) DEBUGOUT(F "\n");
56 #define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)
57 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
58 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
59 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
60 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
61 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
63 #define UNREFERENCED_PARAMETER(_p)
64 #define UNREFERENCED_1PARAMETER(_p)
65 #define UNREFERENCED_2PARAMETER(_p, _q)
66 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
67 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
72 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
74 /* Mutex used in the shared code */
75 #define E1000_MUTEX uintptr_t
76 #define E1000_MUTEX_INIT(mutex) (*(mutex) = 0)
77 #define E1000_MUTEX_LOCK(mutex) (*(mutex) = 1)
78 #define E1000_MUTEX_UNLOCK(mutex) (*(mutex) = 0)
94 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
96 #define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
98 #define E1000_PCI_REG_WRITE(reg, value) do { \
99 E1000_PCI_REG((reg)) = (value); \
102 #define E1000_PCI_REG_ADDR(hw, reg) \
103 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
105 #define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \
106 E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
108 static inline uint32_t e1000_read_addr(volatile void* addr)
110 return E1000_PCI_REG(addr);
113 /* Necessary defines */
114 #define E1000_MRQC_ENABLE_MASK 0x00000007
115 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
116 #define E1000_ALL_FULL_DUPLEX ( \
117 ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
119 #define M88E1543_E_PHY_ID 0x01410EA0
123 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
124 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
126 /* Register READ/WRITE macros */
128 #define E1000_READ_REG(hw, reg) \
129 e1000_read_addr(E1000_PCI_REG_ADDR((hw), (reg)))
131 #define E1000_WRITE_REG(hw, reg, value) \
132 E1000_PCI_REG_WRITE(E1000_PCI_REG_ADDR((hw), (reg)), (value))
134 #define E1000_READ_REG_ARRAY(hw, reg, index) \
135 E1000_PCI_REG(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
137 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
138 E1000_PCI_REG_WRITE(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
140 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
141 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
143 #define E1000_ACCESS_PANIC(x, hw, reg, value) \
144 rte_panic("%s:%u\t" RTE_STR(x) "(%p, 0x%x, 0x%x)", \
145 __FILE__, __LINE__, (hw), (reg), (unsigned int)(value))
148 * To be able to do IO write, we need to map IO BAR
149 * (bar 2/4 depending on device).
150 * Right now mapping multiple BARs is not supported by DPDK.
151 * Fortunatelly we need it only for legacy hw support.
154 #define E1000_WRITE_REG_IO(hw, reg, value) \
155 E1000_WRITE_REG(hw, reg, value)
161 #define E1000_READ_FLASH_REG(hw, reg) \
162 (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG, hw, reg, 0), 0)
164 #define E1000_READ_FLASH_REG16(hw, reg) \
165 (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG16, hw, reg, 0), 0)
167 #define E1000_WRITE_FLASH_REG(hw, reg, value) \
168 E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG, hw, reg, value)
170 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \
171 E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG16, hw, reg, value)
173 #define STATIC static
176 #define ETH_ADDR_LEN 6
182 #endif /* _E1000_OSDEP_H_ */