1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
37 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table[] = {
40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
41 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
42 (sizeof(e1000_m88_cable_length_table) / \
43 sizeof(e1000_m88_cable_length_table[0]))
45 static const u16 e1000_igp_2_cable_length_table[] = {
46 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
47 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
48 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
49 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
50 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
51 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
52 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
54 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
55 (sizeof(e1000_igp_2_cable_length_table) / \
56 sizeof(e1000_igp_2_cable_length_table[0]))
59 * e1000_init_phy_ops_generic - Initialize PHY function pointers
60 * @hw: pointer to the HW structure
62 * Setups up the function pointers to no-op functions
64 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
66 struct e1000_phy_info *phy = &hw->phy;
67 DEBUGFUNC("e1000_init_phy_ops_generic");
69 /* Initialize function pointers */
70 phy->ops.init_params = e1000_null_ops_generic;
71 phy->ops.acquire = e1000_null_ops_generic;
72 phy->ops.check_polarity = e1000_null_ops_generic;
73 phy->ops.check_reset_block = e1000_null_ops_generic;
74 phy->ops.commit = e1000_null_ops_generic;
75 phy->ops.force_speed_duplex = e1000_null_ops_generic;
76 phy->ops.get_cfg_done = e1000_null_ops_generic;
77 phy->ops.get_cable_length = e1000_null_ops_generic;
78 phy->ops.get_info = e1000_null_ops_generic;
79 phy->ops.read_reg = e1000_null_read_reg;
80 phy->ops.read_reg_locked = e1000_null_read_reg;
81 phy->ops.release = e1000_null_phy_generic;
82 phy->ops.reset = e1000_null_ops_generic;
83 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
84 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
85 phy->ops.write_reg = e1000_null_write_reg;
86 phy->ops.write_reg_locked = e1000_null_write_reg;
87 phy->ops.power_up = e1000_null_phy_generic;
88 phy->ops.power_down = e1000_null_phy_generic;
92 * e1000_null_read_reg - No-op function, return 0
93 * @hw: pointer to the HW structure
95 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
97 DEBUGFUNC("e1000_null_read_reg");
102 * e1000_null_phy_generic - No-op function, return void
103 * @hw: pointer to the HW structure
105 void e1000_null_phy_generic(struct e1000_hw *hw)
107 DEBUGFUNC("e1000_null_phy_generic");
112 * e1000_null_lplu_state - No-op function, return 0
113 * @hw: pointer to the HW structure
115 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
117 DEBUGFUNC("e1000_null_lplu_state");
118 return E1000_SUCCESS;
122 * e1000_null_write_reg - No-op function, return 0
123 * @hw: pointer to the HW structure
125 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
127 DEBUGFUNC("e1000_null_write_reg");
128 return E1000_SUCCESS;
132 * e1000_check_reset_block_generic - Check if PHY reset is blocked
133 * @hw: pointer to the HW structure
135 * Read the PHY management control register and check whether a PHY reset
136 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
137 * return E1000_BLK_PHY_RESET (12).
139 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
143 DEBUGFUNC("e1000_check_reset_block");
145 manc = E1000_READ_REG(hw, E1000_MANC);
147 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
148 E1000_BLK_PHY_RESET : E1000_SUCCESS;
152 * e1000_get_phy_id - Retrieve the PHY ID and revision
153 * @hw: pointer to the HW structure
155 * Reads the PHY registers and stores the PHY ID and possibly the PHY
156 * revision in the hardware structure.
158 s32 e1000_get_phy_id(struct e1000_hw *hw)
160 struct e1000_phy_info *phy = &hw->phy;
161 s32 ret_val = E1000_SUCCESS;
164 DEBUGFUNC("e1000_get_phy_id");
166 if (!(phy->ops.read_reg))
169 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
173 phy->id = (u32)(phy_id << 16);
175 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
179 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
180 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
187 * e1000_phy_reset_dsp_generic - Reset PHY DSP
188 * @hw: pointer to the HW structure
190 * Reset the digital signal processor.
192 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
194 s32 ret_val = E1000_SUCCESS;
196 DEBUGFUNC("e1000_phy_reset_dsp_generic");
198 if (!(hw->phy.ops.write_reg))
201 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
205 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
212 * e1000_read_phy_reg_mdic - Read MDI control register
213 * @hw: pointer to the HW structure
214 * @offset: register offset to be read
215 * @data: pointer to the read data
217 * Reads the MDI control register in the PHY at offset and stores the
218 * information read to data.
220 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
222 struct e1000_phy_info *phy = &hw->phy;
224 s32 ret_val = E1000_SUCCESS;
226 DEBUGFUNC("e1000_read_phy_reg_mdic");
228 if (offset > MAX_PHY_REG_ADDRESS) {
229 DEBUGOUT1("PHY Address %d is out of range\n", offset);
230 return -E1000_ERR_PARAM;
234 * Set up Op-code, Phy Address, and register offset in the MDI
235 * Control register. The MAC will take care of interfacing with the
236 * PHY to retrieve the desired data.
238 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
239 (phy->addr << E1000_MDIC_PHY_SHIFT) |
240 (E1000_MDIC_OP_READ));
242 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
245 * Poll the ready bit to see if the MDI read completed
246 * Increasing the time out as testing showed failures with
249 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
251 mdic = E1000_READ_REG(hw, E1000_MDIC);
252 if (mdic & E1000_MDIC_READY)
255 if (!(mdic & E1000_MDIC_READY)) {
256 DEBUGOUT("MDI Read did not complete\n");
257 ret_val = -E1000_ERR_PHY;
260 if (mdic & E1000_MDIC_ERROR) {
261 DEBUGOUT("MDI Error\n");
262 ret_val = -E1000_ERR_PHY;
272 * e1000_write_phy_reg_mdic - Write MDI control register
273 * @hw: pointer to the HW structure
274 * @offset: register offset to write to
275 * @data: data to write to register at offset
277 * Writes data to MDI control register in the PHY at offset.
279 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
281 struct e1000_phy_info *phy = &hw->phy;
283 s32 ret_val = E1000_SUCCESS;
285 DEBUGFUNC("e1000_write_phy_reg_mdic");
287 if (offset > MAX_PHY_REG_ADDRESS) {
288 DEBUGOUT1("PHY Address %d is out of range\n", offset);
289 return -E1000_ERR_PARAM;
293 * Set up Op-code, Phy Address, and register offset in the MDI
294 * Control register. The MAC will take care of interfacing with the
295 * PHY to retrieve the desired data.
297 mdic = (((u32)data) |
298 (offset << E1000_MDIC_REG_SHIFT) |
299 (phy->addr << E1000_MDIC_PHY_SHIFT) |
300 (E1000_MDIC_OP_WRITE));
302 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
305 * Poll the ready bit to see if the MDI read completed
306 * Increasing the time out as testing showed failures with
309 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
311 mdic = E1000_READ_REG(hw, E1000_MDIC);
312 if (mdic & E1000_MDIC_READY)
315 if (!(mdic & E1000_MDIC_READY)) {
316 DEBUGOUT("MDI Write did not complete\n");
317 ret_val = -E1000_ERR_PHY;
320 if (mdic & E1000_MDIC_ERROR) {
321 DEBUGOUT("MDI Error\n");
322 ret_val = -E1000_ERR_PHY;
331 * e1000_read_phy_reg_i2c - Read PHY register using i2c
332 * @hw: pointer to the HW structure
333 * @offset: register offset to be read
334 * @data: pointer to the read data
336 * Reads the PHY register at offset using the i2c interface and stores the
337 * retrieved information in data.
339 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
341 struct e1000_phy_info *phy = &hw->phy;
344 DEBUGFUNC("e1000_read_phy_reg_i2c");
347 * Set up Op-code, Phy Address, and register address in the I2CCMD
348 * register. The MAC will take care of interfacing with the
349 * PHY to retrieve the desired data.
351 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
352 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
353 (E1000_I2CCMD_OPCODE_READ));
355 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
357 /* Poll the ready bit to see if the I2C read completed */
358 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
360 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
361 if (i2ccmd & E1000_I2CCMD_READY)
364 if (!(i2ccmd & E1000_I2CCMD_READY)) {
365 DEBUGOUT("I2CCMD Read did not complete\n");
366 return -E1000_ERR_PHY;
368 if (i2ccmd & E1000_I2CCMD_ERROR) {
369 DEBUGOUT("I2CCMD Error bit set\n");
370 return -E1000_ERR_PHY;
373 /* Need to byte-swap the 16-bit value. */
374 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
376 return E1000_SUCCESS;
380 * e1000_write_phy_reg_i2c - Write PHY register using i2c
381 * @hw: pointer to the HW structure
382 * @offset: register offset to write to
383 * @data: data to write at register offset
385 * Writes the data to PHY register at the offset using the i2c interface.
387 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
389 struct e1000_phy_info *phy = &hw->phy;
391 u16 phy_data_swapped;
393 DEBUGFUNC("e1000_write_phy_reg_i2c");
395 /* Swap the data bytes for the I2C interface */
396 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
399 * Set up Op-code, Phy Address, and register address in the I2CCMD
400 * register. The MAC will take care of interfacing with the
401 * PHY to retrieve the desired data.
403 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
404 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
405 E1000_I2CCMD_OPCODE_WRITE |
408 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
410 /* Poll the ready bit to see if the I2C read completed */
411 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
413 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
414 if (i2ccmd & E1000_I2CCMD_READY)
417 if (!(i2ccmd & E1000_I2CCMD_READY)) {
418 DEBUGOUT("I2CCMD Write did not complete\n");
419 return -E1000_ERR_PHY;
421 if (i2ccmd & E1000_I2CCMD_ERROR) {
422 DEBUGOUT("I2CCMD Error bit set\n");
423 return -E1000_ERR_PHY;
426 return E1000_SUCCESS;
430 * e1000_read_phy_reg_m88 - Read m88 PHY register
431 * @hw: pointer to the HW structure
432 * @offset: register offset to be read
433 * @data: pointer to the read data
435 * Acquires semaphore, if necessary, then reads the PHY register at offset
436 * and storing the retrieved information in data. Release any acquired
437 * semaphores before exiting.
439 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
441 s32 ret_val = E1000_SUCCESS;
443 DEBUGFUNC("e1000_read_phy_reg_m88");
445 if (!(hw->phy.ops.acquire))
448 ret_val = hw->phy.ops.acquire(hw);
452 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
455 hw->phy.ops.release(hw);
462 * e1000_write_phy_reg_m88 - Write m88 PHY register
463 * @hw: pointer to the HW structure
464 * @offset: register offset to write to
465 * @data: data to write at register offset
467 * Acquires semaphore, if necessary, then writes the data to PHY register
468 * at the offset. Release any acquired semaphores before exiting.
470 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
472 s32 ret_val = E1000_SUCCESS;
474 DEBUGFUNC("e1000_write_phy_reg_m88");
476 if (!(hw->phy.ops.acquire))
479 ret_val = hw->phy.ops.acquire(hw);
483 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
486 hw->phy.ops.release(hw);
493 * __e1000_read_phy_reg_igp - Read igp PHY register
494 * @hw: pointer to the HW structure
495 * @offset: register offset to be read
496 * @data: pointer to the read data
497 * @locked: semaphore has already been acquired or not
499 * Acquires semaphore, if necessary, then reads the PHY register at offset
500 * and stores the retrieved information in data. Release any acquired
501 * semaphores before exiting.
503 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
506 s32 ret_val = E1000_SUCCESS;
508 DEBUGFUNC("__e1000_read_phy_reg_igp");
511 if (!(hw->phy.ops.acquire))
514 ret_val = hw->phy.ops.acquire(hw);
519 if (offset > MAX_PHY_MULTI_PAGE_REG) {
520 ret_val = e1000_write_phy_reg_mdic(hw,
521 IGP01E1000_PHY_PAGE_SELECT,
527 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
532 hw->phy.ops.release(hw);
538 * e1000_read_phy_reg_igp - Read igp PHY register
539 * @hw: pointer to the HW structure
540 * @offset: register offset to be read
541 * @data: pointer to the read data
543 * Acquires semaphore then reads the PHY register at offset and stores the
544 * retrieved information in data.
545 * Release the acquired semaphore before exiting.
547 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
549 return __e1000_read_phy_reg_igp(hw, offset, data, false);
553 * e1000_read_phy_reg_igp_locked - Read igp PHY register
554 * @hw: pointer to the HW structure
555 * @offset: register offset to be read
556 * @data: pointer to the read data
558 * Reads the PHY register at offset and stores the retrieved information
559 * in data. Assumes semaphore already acquired.
561 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
563 return __e1000_read_phy_reg_igp(hw, offset, data, true);
567 * e1000_write_phy_reg_igp - Write igp PHY register
568 * @hw: pointer to the HW structure
569 * @offset: register offset to write to
570 * @data: data to write at register offset
571 * @locked: semaphore has already been acquired or not
573 * Acquires semaphore, if necessary, then writes the data to PHY register
574 * at the offset. Release any acquired semaphores before exiting.
576 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
579 s32 ret_val = E1000_SUCCESS;
581 DEBUGFUNC("e1000_write_phy_reg_igp");
584 if (!(hw->phy.ops.acquire))
587 ret_val = hw->phy.ops.acquire(hw);
592 if (offset > MAX_PHY_MULTI_PAGE_REG) {
593 ret_val = e1000_write_phy_reg_mdic(hw,
594 IGP01E1000_PHY_PAGE_SELECT,
600 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
605 hw->phy.ops.release(hw);
612 * e1000_write_phy_reg_igp - Write igp PHY register
613 * @hw: pointer to the HW structure
614 * @offset: register offset to write to
615 * @data: data to write at register offset
617 * Acquires semaphore then writes the data to PHY register
618 * at the offset. Release any acquired semaphores before exiting.
620 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
622 return __e1000_write_phy_reg_igp(hw, offset, data, false);
626 * e1000_write_phy_reg_igp_locked - Write igp PHY register
627 * @hw: pointer to the HW structure
628 * @offset: register offset to write to
629 * @data: data to write at register offset
631 * Writes the data to PHY register at the offset.
632 * Assumes semaphore already acquired.
634 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
636 return __e1000_write_phy_reg_igp(hw, offset, data, true);
640 * __e1000_read_kmrn_reg - Read kumeran register
641 * @hw: pointer to the HW structure
642 * @offset: register offset to be read
643 * @data: pointer to the read data
644 * @locked: semaphore has already been acquired or not
646 * Acquires semaphore, if necessary. Then reads the PHY register at offset
647 * using the kumeran interface. The information retrieved is stored in data.
648 * Release any acquired semaphores before exiting.
650 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
654 s32 ret_val = E1000_SUCCESS;
656 DEBUGFUNC("__e1000_read_kmrn_reg");
659 if (!(hw->phy.ops.acquire))
662 ret_val = hw->phy.ops.acquire(hw);
667 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
668 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
669 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
673 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
674 *data = (u16)kmrnctrlsta;
677 hw->phy.ops.release(hw);
684 * e1000_read_kmrn_reg_generic - Read kumeran register
685 * @hw: pointer to the HW structure
686 * @offset: register offset to be read
687 * @data: pointer to the read data
689 * Acquires semaphore then reads the PHY register at offset using the
690 * kumeran interface. The information retrieved is stored in data.
691 * Release the acquired semaphore before exiting.
693 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
695 return __e1000_read_kmrn_reg(hw, offset, data, false);
699 * e1000_read_kmrn_reg_locked - Read kumeran register
700 * @hw: pointer to the HW structure
701 * @offset: register offset to be read
702 * @data: pointer to the read data
704 * Reads the PHY register at offset using the kumeran interface. The
705 * information retrieved is stored in data.
706 * Assumes semaphore already acquired.
708 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
710 return __e1000_read_kmrn_reg(hw, offset, data, true);
714 * __e1000_write_kmrn_reg - Write kumeran register
715 * @hw: pointer to the HW structure
716 * @offset: register offset to write to
717 * @data: data to write at register offset
718 * @locked: semaphore has already been acquired or not
720 * Acquires semaphore, if necessary. Then write the data to PHY register
721 * at the offset using the kumeran interface. Release any acquired semaphores
724 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
728 s32 ret_val = E1000_SUCCESS;
730 DEBUGFUNC("e1000_write_kmrn_reg_generic");
733 if (!(hw->phy.ops.acquire))
736 ret_val = hw->phy.ops.acquire(hw);
741 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
742 E1000_KMRNCTRLSTA_OFFSET) | data;
743 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
748 hw->phy.ops.release(hw);
755 * e1000_write_kmrn_reg_generic - Write kumeran register
756 * @hw: pointer to the HW structure
757 * @offset: register offset to write to
758 * @data: data to write at register offset
760 * Acquires semaphore then writes the data to the PHY register at the offset
761 * using the kumeran interface. Release the acquired semaphore before exiting.
763 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
765 return __e1000_write_kmrn_reg(hw, offset, data, false);
769 * e1000_write_kmrn_reg_locked - Write kumeran register
770 * @hw: pointer to the HW structure
771 * @offset: register offset to write to
772 * @data: data to write at register offset
774 * Write the data to PHY register at the offset using the kumeran interface.
775 * Assumes semaphore already acquired.
777 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
779 return __e1000_write_kmrn_reg(hw, offset, data, true);
783 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
784 * @hw: pointer to the HW structure
786 * Sets up Carrier-sense on Transmit and downshift values.
788 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
793 DEBUGFUNC("e1000_copper_link_setup_82577");
795 if (hw->phy.reset_disable) {
796 ret_val = E1000_SUCCESS;
800 if (hw->phy.type == e1000_phy_82580) {
801 ret_val = hw->phy.ops.reset(hw);
803 DEBUGOUT("Error resetting the PHY.\n");
808 /* Enable CRS on Tx. This must be set for half-duplex operation. */
809 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
813 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
815 /* Enable downshift */
816 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
818 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
825 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
826 * @hw: pointer to the HW structure
828 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
829 * and downshift values are set also.
831 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
833 struct e1000_phy_info *phy = &hw->phy;
837 DEBUGFUNC("e1000_copper_link_setup_m88");
839 if (phy->reset_disable) {
840 ret_val = E1000_SUCCESS;
844 /* Enable CRS on Tx. This must be set for half-duplex operation. */
845 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
849 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
853 * MDI/MDI-X = 0 (default)
854 * 0 - Auto for all speeds
857 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
859 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
863 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
866 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
869 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
873 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
879 * disable_polarity_correction = 0 (default)
880 * Automatic Correction for Reversed Cable Polarity
884 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
885 if (phy->disable_polarity_correction == 1)
886 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
888 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
892 if (phy->revision < E1000_REVISION_4) {
894 * Force TX_CLK in the Extended PHY Specific Control Register
897 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
902 phy_data |= M88E1000_EPSCR_TX_CLK_25;
904 if ((phy->revision == E1000_REVISION_2) &&
905 (phy->id == M88E1111_I_PHY_ID)) {
906 /* 82573L PHY - set the downshift counter to 5x. */
907 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
908 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
910 /* Configure Master and Slave downshift values */
911 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
912 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
913 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
914 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
916 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
922 /* Commit the changes. */
923 ret_val = phy->ops.commit(hw);
925 DEBUGOUT("Error committing the PHY changes\n");
934 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
935 * @hw: pointer to the HW structure
937 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
938 * Also enables and sets the downshift parameters.
940 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
942 struct e1000_phy_info *phy = &hw->phy;
946 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
948 if (phy->reset_disable) {
949 ret_val = E1000_SUCCESS;
953 /* Enable CRS on Tx. This must be set for half-duplex operation. */
954 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
960 * MDI/MDI-X = 0 (default)
961 * 0 - Auto for all speeds
964 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
966 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
970 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
973 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
976 /* M88E1112 does not support this mode) */
977 if (phy->id != M88E1112_E_PHY_ID) {
978 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
983 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
989 * disable_polarity_correction = 0 (default)
990 * Automatic Correction for Reversed Cable Polarity
994 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
995 if (phy->disable_polarity_correction == 1)
996 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
998 /* Enable downshift and setting it to X6 */
999 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1000 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1001 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1003 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1007 /* Commit the changes. */
1008 ret_val = phy->ops.commit(hw);
1010 DEBUGOUT("Error committing the PHY changes\n");
1019 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1020 * @hw: pointer to the HW structure
1022 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1025 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1027 struct e1000_phy_info *phy = &hw->phy;
1031 DEBUGFUNC("e1000_copper_link_setup_igp");
1033 if (phy->reset_disable) {
1034 ret_val = E1000_SUCCESS;
1038 ret_val = hw->phy.ops.reset(hw);
1040 DEBUGOUT("Error resetting the PHY.\n");
1045 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1046 * timeout issues when LFS is enabled.
1050 /* disable lplu d0 during driver init */
1051 if (hw->phy.ops.set_d0_lplu_state) {
1052 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1054 DEBUGOUT("Error Disabling LPLU D0\n");
1058 /* Configure mdi-mdix settings */
1059 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1063 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1065 switch (phy->mdix) {
1067 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1070 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1074 data |= IGP01E1000_PSCR_AUTO_MDIX;
1077 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1081 /* set auto-master slave resolution settings */
1082 if (hw->mac.autoneg) {
1084 * when autonegotiation advertisement is only 1000Mbps then we
1085 * should disable SmartSpeed and enable Auto MasterSlave
1086 * resolution as hardware default.
1088 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1089 /* Disable SmartSpeed */
1090 ret_val = phy->ops.read_reg(hw,
1091 IGP01E1000_PHY_PORT_CONFIG,
1096 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1097 ret_val = phy->ops.write_reg(hw,
1098 IGP01E1000_PHY_PORT_CONFIG,
1103 /* Set auto Master/Slave resolution process */
1104 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1108 data &= ~CR_1000T_MS_ENABLE;
1109 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1114 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1118 /* load defaults for future use */
1119 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1120 ((data & CR_1000T_MS_VALUE) ?
1121 e1000_ms_force_master :
1122 e1000_ms_force_slave) :
1125 switch (phy->ms_type) {
1126 case e1000_ms_force_master:
1127 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1129 case e1000_ms_force_slave:
1130 data |= CR_1000T_MS_ENABLE;
1131 data &= ~(CR_1000T_MS_VALUE);
1134 data &= ~CR_1000T_MS_ENABLE;
1138 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1148 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1149 * @hw: pointer to the HW structure
1151 * Performs initial bounds checking on autoneg advertisement parameter, then
1152 * configure to advertise the full capability. Setup the PHY to autoneg
1153 * and restart the negotiation process between the link partner. If
1154 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1156 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1158 struct e1000_phy_info *phy = &hw->phy;
1162 DEBUGFUNC("e1000_copper_link_autoneg");
1165 * Perform some bounds checking on the autoneg advertisement
1168 phy->autoneg_advertised &= phy->autoneg_mask;
1171 * If autoneg_advertised is zero, we assume it was not defaulted
1172 * by the calling code so we set to advertise full capability.
1174 if (phy->autoneg_advertised == 0)
1175 phy->autoneg_advertised = phy->autoneg_mask;
1177 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1178 ret_val = e1000_phy_setup_autoneg(hw);
1180 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1183 DEBUGOUT("Restarting Auto-Neg\n");
1186 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1187 * the Auto Neg Restart bit in the PHY control register.
1189 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1193 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1194 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1199 * Does the user want to wait for Auto-Neg to complete here, or
1200 * check at a later time (for example, callback routine).
1202 if (phy->autoneg_wait_to_complete) {
1203 ret_val = hw->mac.ops.wait_autoneg(hw);
1205 DEBUGOUT("Error while waiting for "
1206 "autoneg to complete\n");
1211 hw->mac.get_link_status = TRUE;
1218 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1219 * @hw: pointer to the HW structure
1221 * Reads the MII auto-neg advertisement register and/or the 1000T control
1222 * register and if the PHY is already setup for auto-negotiation, then
1223 * return successful. Otherwise, setup advertisement and flow control to
1224 * the appropriate values for the wanted auto-negotiation.
1226 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1228 struct e1000_phy_info *phy = &hw->phy;
1230 u16 mii_autoneg_adv_reg;
1231 u16 mii_1000t_ctrl_reg = 0;
1233 DEBUGFUNC("e1000_phy_setup_autoneg");
1235 phy->autoneg_advertised &= phy->autoneg_mask;
1237 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1238 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1242 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1243 /* Read the MII 1000Base-T Control Register (Address 9). */
1244 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1245 &mii_1000t_ctrl_reg);
1251 * Need to parse both autoneg_advertised and fc and set up
1252 * the appropriate PHY registers. First we will parse for
1253 * autoneg_advertised software override. Since we can advertise
1254 * a plethora of combinations, we need to check each bit
1259 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1260 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1261 * the 1000Base-T Control Register (Address 9).
1263 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1264 NWAY_AR_100TX_HD_CAPS |
1265 NWAY_AR_10T_FD_CAPS |
1266 NWAY_AR_10T_HD_CAPS);
1267 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1269 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1271 /* Do we want to advertise 10 Mb Half Duplex? */
1272 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1273 DEBUGOUT("Advertise 10mb Half duplex\n");
1274 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1277 /* Do we want to advertise 10 Mb Full Duplex? */
1278 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1279 DEBUGOUT("Advertise 10mb Full duplex\n");
1280 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1283 /* Do we want to advertise 100 Mb Half Duplex? */
1284 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1285 DEBUGOUT("Advertise 100mb Half duplex\n");
1286 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1289 /* Do we want to advertise 100 Mb Full Duplex? */
1290 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1291 DEBUGOUT("Advertise 100mb Full duplex\n");
1292 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1295 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1296 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1297 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1299 /* Do we want to advertise 1000 Mb Full Duplex? */
1300 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1301 DEBUGOUT("Advertise 1000mb Full duplex\n");
1302 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1306 * Check for a software override of the flow control settings, and
1307 * setup the PHY advertisement registers accordingly. If
1308 * auto-negotiation is enabled, then software will have to set the
1309 * "PAUSE" bits to the correct value in the Auto-Negotiation
1310 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1313 * The possible values of the "fc" parameter are:
1314 * 0: Flow control is completely disabled
1315 * 1: Rx flow control is enabled (we can receive pause frames
1316 * but not send pause frames).
1317 * 2: Tx flow control is enabled (we can send pause frames
1318 * but we do not support receiving pause frames).
1319 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1320 * other: No software override. The flow control configuration
1321 * in the EEPROM is used.
1323 switch (hw->fc.current_mode) {
1326 * Flow control (Rx & Tx) is completely disabled by a
1327 * software over-ride.
1329 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1331 case e1000_fc_rx_pause:
1333 * Rx Flow control is enabled, and Tx Flow control is
1334 * disabled, by a software over-ride.
1336 * Since there really isn't a way to advertise that we are
1337 * capable of Rx Pause ONLY, we will advertise that we
1338 * support both symmetric and asymmetric Rx PAUSE. Later
1339 * (in e1000_config_fc_after_link_up) we will disable the
1340 * hw's ability to send PAUSE frames.
1342 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1344 case e1000_fc_tx_pause:
1346 * Tx Flow control is enabled, and Rx Flow control is
1347 * disabled, by a software over-ride.
1349 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1350 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1354 * Flow control (both Rx and Tx) is enabled by a software
1357 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1360 DEBUGOUT("Flow control param set incorrectly\n");
1361 ret_val = -E1000_ERR_CONFIG;
1365 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1369 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1371 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1372 ret_val = phy->ops.write_reg(hw,
1374 mii_1000t_ctrl_reg);
1384 * e1000_setup_copper_link_generic - Configure copper link settings
1385 * @hw: pointer to the HW structure
1387 * Calls the appropriate function to configure the link for auto-neg or forced
1388 * speed and duplex. Then we check for link, once link is established calls
1389 * to configure collision distance and flow control are called. If link is
1390 * not established, we return -E1000_ERR_PHY (-2).
1392 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1397 DEBUGFUNC("e1000_setup_copper_link_generic");
1399 if (hw->mac.autoneg) {
1401 * Setup autoneg and flow control advertisement and perform
1404 ret_val = e1000_copper_link_autoneg(hw);
1409 * PHY will be set to 10H, 10F, 100H or 100F
1410 * depending on user settings.
1412 DEBUGOUT("Forcing Speed and Duplex\n");
1413 ret_val = hw->phy.ops.force_speed_duplex(hw);
1415 DEBUGOUT("Error Forcing Speed and Duplex\n");
1421 * Check link status. Wait up to 100 microseconds for link to become
1424 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1430 DEBUGOUT("Valid link established!!!\n");
1431 e1000_config_collision_dist_generic(hw);
1432 ret_val = e1000_config_fc_after_link_up_generic(hw);
1434 DEBUGOUT("Unable to establish link!!!\n");
1442 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1443 * @hw: pointer to the HW structure
1445 * Calls the PHY setup function to force speed and duplex. Clears the
1446 * auto-crossover to force MDI manually. Waits for link and returns
1447 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1449 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1451 struct e1000_phy_info *phy = &hw->phy;
1456 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1458 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1462 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1464 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1469 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1470 * forced whenever speed and duplex are forced.
1472 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1476 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1477 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1479 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1483 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1487 if (phy->autoneg_wait_to_complete) {
1488 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1490 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1496 DEBUGOUT("Link taking longer than expected.\n");
1499 ret_val = e1000_phy_has_link_generic(hw,
1512 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1513 * @hw: pointer to the HW structure
1515 * Calls the PHY setup function to force speed and duplex. Clears the
1516 * auto-crossover to force MDI manually. Resets the PHY to commit the
1517 * changes. If time expires while waiting for link up, we reset the DSP.
1518 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1519 * successful completion, else return corresponding error code.
1521 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1523 struct e1000_phy_info *phy = &hw->phy;
1528 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1531 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1532 * forced whenever speed and duplex are forced.
1534 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1538 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1539 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1543 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1545 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1549 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1551 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1555 /* Reset the phy to commit changes. */
1556 ret_val = hw->phy.ops.commit(hw);
1560 if (phy->autoneg_wait_to_complete) {
1561 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1563 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1569 if (hw->phy.type != e1000_phy_m88 ||
1570 hw->phy.id == I347AT4_E_PHY_ID ||
1571 hw->phy.id == M88E1340M_E_PHY_ID ||
1572 hw->phy.id == M88E1112_E_PHY_ID) {
1573 DEBUGOUT("Link taking longer than expected.\n");
1576 * We didn't get link.
1577 * Reset the DSP and cross our fingers.
1579 ret_val = phy->ops.write_reg(hw,
1580 M88E1000_PHY_PAGE_SELECT,
1584 ret_val = e1000_phy_reset_dsp_generic(hw);
1591 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1597 if (hw->phy.type != e1000_phy_m88 ||
1598 hw->phy.id == I347AT4_E_PHY_ID ||
1599 hw->phy.id == M88E1340M_E_PHY_ID ||
1600 hw->phy.id == M88E1112_E_PHY_ID)
1603 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1608 * Resetting the phy means we need to re-force TX_CLK in the
1609 * Extended PHY Specific Control Register to 25MHz clock from
1610 * the reset value of 2.5MHz.
1612 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1613 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1618 * In addition, we must re-enable CRS on Tx for both half and full
1621 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1625 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1626 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1633 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1634 * @hw: pointer to the HW structure
1636 * Forces the speed and duplex settings of the PHY.
1637 * This is a function pointer entry point only called by
1638 * PHY setup routines.
1640 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1642 struct e1000_phy_info *phy = &hw->phy;
1647 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1649 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1653 e1000_phy_force_speed_duplex_setup(hw, &data);
1655 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1659 /* Disable MDI-X support for 10/100 */
1660 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1664 data &= ~IFE_PMC_AUTO_MDIX;
1665 data &= ~IFE_PMC_FORCE_MDIX;
1667 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1671 DEBUGOUT1("IFE PMC: %X\n", data);
1675 if (phy->autoneg_wait_to_complete) {
1676 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1678 ret_val = e1000_phy_has_link_generic(hw,
1686 DEBUGOUT("Link taking longer than expected.\n");
1689 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1698 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1699 * @hw: pointer to the HW structure
1700 * @phy_ctrl: pointer to current value of PHY_CONTROL
1702 * Forces speed and duplex on the PHY by doing the following: disable flow
1703 * control, force speed/duplex on the MAC, disable auto speed detection,
1704 * disable auto-negotiation, configure duplex, configure speed, configure
1705 * the collision distance, write configuration to CTRL register. The
1706 * caller must write to the PHY_CONTROL register for these settings to
1709 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1711 struct e1000_mac_info *mac = &hw->mac;
1714 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1716 /* Turn off flow control when forcing speed/duplex */
1717 hw->fc.current_mode = e1000_fc_none;
1719 /* Force speed/duplex on the mac */
1720 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1721 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1722 ctrl &= ~E1000_CTRL_SPD_SEL;
1724 /* Disable Auto Speed Detection */
1725 ctrl &= ~E1000_CTRL_ASDE;
1727 /* Disable autoneg on the phy */
1728 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1730 /* Forcing Full or Half Duplex? */
1731 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1732 ctrl &= ~E1000_CTRL_FD;
1733 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1734 DEBUGOUT("Half Duplex\n");
1736 ctrl |= E1000_CTRL_FD;
1737 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1738 DEBUGOUT("Full Duplex\n");
1741 /* Forcing 10mb or 100mb? */
1742 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1743 ctrl |= E1000_CTRL_SPD_100;
1744 *phy_ctrl |= MII_CR_SPEED_100;
1745 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1746 DEBUGOUT("Forcing 100mb\n");
1748 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1749 *phy_ctrl |= MII_CR_SPEED_10;
1750 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1751 DEBUGOUT("Forcing 10mb\n");
1754 e1000_config_collision_dist_generic(hw);
1756 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1760 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1761 * @hw: pointer to the HW structure
1762 * @active: boolean used to enable/disable lplu
1764 * Success returns 0, Failure returns 1
1766 * The low power link up (lplu) state is set to the power management level D3
1767 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1768 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1769 * is used during Dx states where the power conservation is most important.
1770 * During driver activity, SmartSpeed should be enabled so performance is
1773 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1775 struct e1000_phy_info *phy = &hw->phy;
1776 s32 ret_val = E1000_SUCCESS;
1779 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1781 if (!(hw->phy.ops.read_reg))
1784 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1789 data &= ~IGP02E1000_PM_D3_LPLU;
1790 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1795 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1796 * during Dx states where the power conservation is most
1797 * important. During driver activity we should enable
1798 * SmartSpeed, so performance is maintained.
1800 if (phy->smart_speed == e1000_smart_speed_on) {
1801 ret_val = phy->ops.read_reg(hw,
1802 IGP01E1000_PHY_PORT_CONFIG,
1807 data |= IGP01E1000_PSCFR_SMART_SPEED;
1808 ret_val = phy->ops.write_reg(hw,
1809 IGP01E1000_PHY_PORT_CONFIG,
1813 } else if (phy->smart_speed == e1000_smart_speed_off) {
1814 ret_val = phy->ops.read_reg(hw,
1815 IGP01E1000_PHY_PORT_CONFIG,
1820 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1821 ret_val = phy->ops.write_reg(hw,
1822 IGP01E1000_PHY_PORT_CONFIG,
1827 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1828 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1829 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1830 data |= IGP02E1000_PM_D3_LPLU;
1831 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1836 /* When LPLU is enabled, we should disable SmartSpeed */
1837 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1842 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1843 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1852 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1853 * @hw: pointer to the HW structure
1855 * Success returns 0, Failure returns 1
1857 * A downshift is detected by querying the PHY link health.
1859 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1861 struct e1000_phy_info *phy = &hw->phy;
1863 u16 phy_data, offset, mask;
1865 DEBUGFUNC("e1000_check_downshift_generic");
1867 switch (phy->type) {
1869 case e1000_phy_gg82563:
1870 offset = M88E1000_PHY_SPEC_STATUS;
1871 mask = M88E1000_PSSR_DOWNSHIFT;
1873 case e1000_phy_igp_2:
1874 case e1000_phy_igp_3:
1875 offset = IGP01E1000_PHY_LINK_HEALTH;
1876 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1879 /* speed downshift not supported */
1880 phy->speed_downgraded = false;
1881 ret_val = E1000_SUCCESS;
1885 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1888 phy->speed_downgraded = !!(phy_data & mask);
1895 * e1000_check_polarity_m88 - Checks the polarity.
1896 * @hw: pointer to the HW structure
1898 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1900 * Polarity is determined based on the PHY specific status register.
1902 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1904 struct e1000_phy_info *phy = &hw->phy;
1908 DEBUGFUNC("e1000_check_polarity_m88");
1910 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1913 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1914 ? e1000_rev_polarity_reversed
1915 : e1000_rev_polarity_normal;
1921 * e1000_check_polarity_igp - Checks the polarity.
1922 * @hw: pointer to the HW structure
1924 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1926 * Polarity is determined based on the PHY port status register, and the
1927 * current speed (since there is no polarity at 100Mbps).
1929 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1931 struct e1000_phy_info *phy = &hw->phy;
1933 u16 data, offset, mask;
1935 DEBUGFUNC("e1000_check_polarity_igp");
1938 * Polarity is determined based on the speed of
1941 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1945 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1946 IGP01E1000_PSSR_SPEED_1000MBPS) {
1947 offset = IGP01E1000_PHY_PCS_INIT_REG;
1948 mask = IGP01E1000_PHY_POLARITY_MASK;
1951 * This really only applies to 10Mbps since
1952 * there is no polarity for 100Mbps (always 0).
1954 offset = IGP01E1000_PHY_PORT_STATUS;
1955 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1958 ret_val = phy->ops.read_reg(hw, offset, &data);
1961 phy->cable_polarity = (data & mask)
1962 ? e1000_rev_polarity_reversed
1963 : e1000_rev_polarity_normal;
1970 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1971 * @hw: pointer to the HW structure
1973 * Polarity is determined on the polarity reversal feature being enabled.
1975 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1977 struct e1000_phy_info *phy = &hw->phy;
1979 u16 phy_data, offset, mask;
1981 DEBUGFUNC("e1000_check_polarity_ife");
1984 * Polarity is determined based on the reversal feature being enabled.
1986 if (phy->polarity_correction) {
1987 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1988 mask = IFE_PESC_POLARITY_REVERSED;
1990 offset = IFE_PHY_SPECIAL_CONTROL;
1991 mask = IFE_PSC_FORCE_POLARITY;
1994 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1997 phy->cable_polarity = (phy_data & mask)
1998 ? e1000_rev_polarity_reversed
1999 : e1000_rev_polarity_normal;
2005 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2006 * @hw: pointer to the HW structure
2008 * Waits for auto-negotiation to complete or for the auto-negotiation time
2009 * limit to expire, which ever happens first.
2011 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2013 s32 ret_val = E1000_SUCCESS;
2016 DEBUGFUNC("e1000_wait_autoneg_generic");
2018 if (!hw->phy.ops.read_reg)
2019 return E1000_SUCCESS;
2021 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2022 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2023 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2026 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2029 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2035 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2042 * e1000_phy_has_link_generic - Polls PHY for link
2043 * @hw: pointer to the HW structure
2044 * @iterations: number of times to poll for link
2045 * @usec_interval: delay between polling attempts
2046 * @success: pointer to whether polling was successful or not
2048 * Polls the PHY status register for link, 'iterations' number of times.
2050 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2051 u32 usec_interval, bool *success)
2053 s32 ret_val = E1000_SUCCESS;
2056 DEBUGFUNC("e1000_phy_has_link_generic");
2058 if (!hw->phy.ops.read_reg)
2059 return E1000_SUCCESS;
2061 for (i = 0; i < iterations; i++) {
2063 * Some PHYs require the PHY_STATUS register to be read
2064 * twice due to the link bit being sticky. No harm doing
2065 * it across the board.
2067 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2070 * If the first read fails, another entity may have
2071 * ownership of the resources, wait and try again to
2072 * see if they have relinquished the resources yet.
2074 usec_delay(usec_interval);
2075 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2078 if (phy_status & MII_SR_LINK_STATUS)
2080 if (usec_interval >= 1000)
2081 msec_delay_irq(usec_interval/1000);
2083 usec_delay(usec_interval);
2086 *success = (i < iterations);
2092 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2093 * @hw: pointer to the HW structure
2095 * Reads the PHY specific status register to retrieve the cable length
2096 * information. The cable length is determined by averaging the minimum and
2097 * maximum values to get the "average" cable length. The m88 PHY has four
2098 * possible cable length values, which are:
2099 * Register Value Cable Length
2103 * 3 110 - 140 meters
2106 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2108 struct e1000_phy_info *phy = &hw->phy;
2110 u16 phy_data, index;
2112 DEBUGFUNC("e1000_get_cable_length_m88");
2114 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2118 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2119 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2120 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2121 ret_val = -E1000_ERR_PHY;
2125 phy->min_cable_length = e1000_m88_cable_length_table[index];
2126 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2128 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2134 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2136 struct e1000_phy_info *phy = &hw->phy;
2138 u16 phy_data, phy_data2, index, default_page, is_cm;
2140 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2142 switch (hw->phy.id) {
2143 case M88E1340M_E_PHY_ID:
2144 case I347AT4_E_PHY_ID:
2145 /* Remember the original page select and set it to 7 */
2146 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2151 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2155 /* Get cable length from PHY Cable Diagnostics Control Reg */
2156 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2161 /* Check if the unit of cable length is meters or cm */
2162 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2166 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2168 /* Populate the phy structure with cable length in meters */
2169 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2170 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2171 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2173 /* Reset the page select to its original value */
2174 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2180 case M88E1112_E_PHY_ID:
2181 /* Remember the original page select and set it to 5 */
2182 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2187 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2191 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2196 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2197 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2198 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2199 ret_val = -E1000_ERR_PHY;
2203 phy->min_cable_length = e1000_m88_cable_length_table[index];
2204 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2206 phy->cable_length = (phy->min_cable_length +
2207 phy->max_cable_length) / 2;
2209 /* Reset the page select to its original value */
2210 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2217 ret_val = -E1000_ERR_PHY;
2226 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2227 * @hw: pointer to the HW structure
2229 * The automatic gain control (agc) normalizes the amplitude of the
2230 * received signal, adjusting for the attenuation produced by the
2231 * cable. By reading the AGC registers, which represent the
2232 * combination of coarse and fine gain value, the value can be put
2233 * into a lookup table to obtain the approximate cable length
2236 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2238 struct e1000_phy_info *phy = &hw->phy;
2239 s32 ret_val = E1000_SUCCESS;
2240 u16 phy_data, i, agc_value = 0;
2241 u16 cur_agc_index, max_agc_index = 0;
2242 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2243 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2244 IGP02E1000_PHY_AGC_A,
2245 IGP02E1000_PHY_AGC_B,
2246 IGP02E1000_PHY_AGC_C,
2247 IGP02E1000_PHY_AGC_D
2250 DEBUGFUNC("e1000_get_cable_length_igp_2");
2252 /* Read the AGC registers for all channels */
2253 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2254 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2259 * Getting bits 15:9, which represent the combination of
2260 * coarse and fine gain values. The result is a number
2261 * that can be put into the lookup table to obtain the
2262 * approximate cable length.
2264 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2265 IGP02E1000_AGC_LENGTH_MASK;
2267 /* Array index bound check. */
2268 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2269 (cur_agc_index == 0)) {
2270 ret_val = -E1000_ERR_PHY;
2274 /* Remove min & max AGC values from calculation. */
2275 if (e1000_igp_2_cable_length_table[min_agc_index] >
2276 e1000_igp_2_cable_length_table[cur_agc_index])
2277 min_agc_index = cur_agc_index;
2278 if (e1000_igp_2_cable_length_table[max_agc_index] <
2279 e1000_igp_2_cable_length_table[cur_agc_index])
2280 max_agc_index = cur_agc_index;
2282 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2285 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2286 e1000_igp_2_cable_length_table[max_agc_index]);
2287 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2289 /* Calculate cable length with the error range of +/- 10 meters. */
2290 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2291 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2292 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2294 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2301 * e1000_get_phy_info_m88 - Retrieve PHY information
2302 * @hw: pointer to the HW structure
2304 * Valid for only copper links. Read the PHY status register (sticky read)
2305 * to verify that link is up. Read the PHY special control register to
2306 * determine the polarity and 10base-T extended distance. Read the PHY
2307 * special status register to determine MDI/MDIx and current speed. If
2308 * speed is 1000, then determine cable length, local and remote receiver.
2310 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2312 struct e1000_phy_info *phy = &hw->phy;
2317 DEBUGFUNC("e1000_get_phy_info_m88");
2319 if (phy->media_type != e1000_media_type_copper) {
2320 DEBUGOUT("Phy info is only valid for copper media\n");
2321 ret_val = -E1000_ERR_CONFIG;
2325 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2330 DEBUGOUT("Phy info is only valid if link is up\n");
2331 ret_val = -E1000_ERR_CONFIG;
2335 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2339 phy->polarity_correction = !!(phy_data &
2340 M88E1000_PSCR_POLARITY_REVERSAL);
2342 ret_val = e1000_check_polarity_m88(hw);
2346 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2350 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2352 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2353 ret_val = hw->phy.ops.get_cable_length(hw);
2357 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2361 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2362 ? e1000_1000t_rx_status_ok
2363 : e1000_1000t_rx_status_not_ok;
2365 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2366 ? e1000_1000t_rx_status_ok
2367 : e1000_1000t_rx_status_not_ok;
2369 /* Set values to "undefined" */
2370 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2371 phy->local_rx = e1000_1000t_rx_status_undefined;
2372 phy->remote_rx = e1000_1000t_rx_status_undefined;
2380 * e1000_get_phy_info_igp - Retrieve igp PHY information
2381 * @hw: pointer to the HW structure
2383 * Read PHY status to determine if link is up. If link is up, then
2384 * set/determine 10base-T extended distance and polarity correction. Read
2385 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2386 * determine on the cable length, local and remote receiver.
2388 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2390 struct e1000_phy_info *phy = &hw->phy;
2395 DEBUGFUNC("e1000_get_phy_info_igp");
2397 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2402 DEBUGOUT("Phy info is only valid if link is up\n");
2403 ret_val = -E1000_ERR_CONFIG;
2407 phy->polarity_correction = true;
2409 ret_val = e1000_check_polarity_igp(hw);
2413 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2417 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2419 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2420 IGP01E1000_PSSR_SPEED_1000MBPS) {
2421 ret_val = phy->ops.get_cable_length(hw);
2425 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2429 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2430 ? e1000_1000t_rx_status_ok
2431 : e1000_1000t_rx_status_not_ok;
2433 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2434 ? e1000_1000t_rx_status_ok
2435 : e1000_1000t_rx_status_not_ok;
2437 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2438 phy->local_rx = e1000_1000t_rx_status_undefined;
2439 phy->remote_rx = e1000_1000t_rx_status_undefined;
2447 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2448 * @hw: pointer to the HW structure
2450 * Populates "phy" structure with various feature states.
2452 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2454 struct e1000_phy_info *phy = &hw->phy;
2459 DEBUGFUNC("e1000_get_phy_info_ife");
2461 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2466 DEBUGOUT("Phy info is only valid if link is up\n");
2467 ret_val = -E1000_ERR_CONFIG;
2471 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2474 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2477 if (phy->polarity_correction) {
2478 ret_val = e1000_check_polarity_ife(hw);
2482 /* Polarity is forced */
2483 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2484 ? e1000_rev_polarity_reversed
2485 : e1000_rev_polarity_normal;
2488 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2492 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2494 /* The following parameters are undefined for 10/100 operation. */
2495 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2496 phy->local_rx = e1000_1000t_rx_status_undefined;
2497 phy->remote_rx = e1000_1000t_rx_status_undefined;
2504 * e1000_phy_sw_reset_generic - PHY software reset
2505 * @hw: pointer to the HW structure
2507 * Does a software reset of the PHY by reading the PHY control register and
2508 * setting/write the control register reset bit to the PHY.
2510 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2512 s32 ret_val = E1000_SUCCESS;
2515 DEBUGFUNC("e1000_phy_sw_reset_generic");
2517 if (!(hw->phy.ops.read_reg))
2520 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2524 phy_ctrl |= MII_CR_RESET;
2525 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2536 * e1000_phy_hw_reset_generic - PHY hardware reset
2537 * @hw: pointer to the HW structure
2539 * Verify the reset block is not blocking us from resetting. Acquire
2540 * semaphore (if necessary) and read/set/write the device control reset
2541 * bit in the PHY. Wait the appropriate delay time for the device to
2542 * reset and release the semaphore (if necessary).
2544 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2546 struct e1000_phy_info *phy = &hw->phy;
2547 s32 ret_val = E1000_SUCCESS;
2550 DEBUGFUNC("e1000_phy_hw_reset_generic");
2552 ret_val = phy->ops.check_reset_block(hw);
2554 ret_val = E1000_SUCCESS;
2558 ret_val = phy->ops.acquire(hw);
2562 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2563 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2564 E1000_WRITE_FLUSH(hw);
2566 usec_delay(phy->reset_delay_us);
2568 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2569 E1000_WRITE_FLUSH(hw);
2573 phy->ops.release(hw);
2575 ret_val = phy->ops.get_cfg_done(hw);
2582 * e1000_get_cfg_done_generic - Generic configuration done
2583 * @hw: pointer to the HW structure
2585 * Generic function to wait 10 milli-seconds for configuration to complete
2586 * and return success.
2588 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2590 DEBUGFUNC("e1000_get_cfg_done_generic");
2594 return E1000_SUCCESS;
2598 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2599 * @hw: pointer to the HW structure
2601 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2603 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2605 DEBUGOUT("Running IGP 3 PHY init script\n");
2607 /* PHY init IGP 3 */
2608 /* Enable rise/fall, 10-mode work in class-A */
2609 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2610 /* Remove all caps from Replica path filter */
2611 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2612 /* Bias trimming for ADC, AFE and Driver (Default) */
2613 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2614 /* Increase Hybrid poly bias */
2615 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2616 /* Add 4% to Tx amplitude in Gig mode */
2617 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2618 /* Disable trimming (TTT) */
2619 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2620 /* Poly DC correction to 94.6% + 2% for all channels */
2621 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2622 /* ABS DC correction to 95.9% */
2623 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2624 /* BG temp curve trim */
2625 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2626 /* Increasing ADC OPAMP stage 1 currents to max */
2627 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2628 /* Force 1000 ( required for enabling PHY regs configuration) */
2629 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2630 /* Set upd_freq to 6 */
2631 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2633 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2634 /* Disable adaptive fixed FFE (Default) */
2635 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2636 /* Enable FFE hysteresis */
2637 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2638 /* Fixed FFE for short cable lengths */
2639 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2640 /* Fixed FFE for medium cable lengths */
2641 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2642 /* Fixed FFE for long cable lengths */
2643 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2644 /* Enable Adaptive Clip Threshold */
2645 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2646 /* AHT reset limit to 1 */
2647 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2648 /* Set AHT master delay to 127 msec */
2649 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2650 /* Set scan bits for AHT */
2651 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2652 /* Set AHT Preset bits */
2653 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2654 /* Change integ_factor of channel A to 3 */
2655 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2656 /* Change prop_factor of channels BCD to 8 */
2657 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2658 /* Change cg_icount + enable integbp for channels BCD */
2659 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2661 * Change cg_icount + enable integbp + change prop_factor_master
2662 * to 8 for channel A
2664 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2665 /* Disable AHT in Slave mode on channel A */
2666 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2668 * Enable LPLU and disable AN to 1000 in non-D0a states,
2671 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2672 /* Enable restart AN on an1000_dis change */
2673 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2674 /* Enable wh_fifo read clock in 10/100 modes */
2675 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2676 /* Restart AN, Speed selection is 1000 */
2677 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2679 return E1000_SUCCESS;
2683 * e1000_get_phy_type_from_id - Get PHY type from id
2684 * @phy_id: phy_id read from the phy
2686 * Returns the phy type from the id.
2688 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2690 enum e1000_phy_type phy_type = e1000_phy_unknown;
2693 case M88E1000_I_PHY_ID:
2694 case M88E1000_E_PHY_ID:
2695 case M88E1111_I_PHY_ID:
2696 case M88E1011_I_PHY_ID:
2697 case I347AT4_E_PHY_ID:
2698 case M88E1112_E_PHY_ID:
2699 case M88E1340M_E_PHY_ID:
2700 phy_type = e1000_phy_m88;
2702 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2703 phy_type = e1000_phy_igp_2;
2705 case GG82563_E_PHY_ID:
2706 phy_type = e1000_phy_gg82563;
2708 case IGP03E1000_E_PHY_ID:
2709 phy_type = e1000_phy_igp_3;
2712 case IFE_PLUS_E_PHY_ID:
2713 case IFE_C_E_PHY_ID:
2714 phy_type = e1000_phy_ife;
2716 case I82580_I_PHY_ID:
2717 phy_type = e1000_phy_82580;
2720 phy_type = e1000_phy_unknown;
2727 * e1000_determine_phy_address - Determines PHY address.
2728 * @hw: pointer to the HW structure
2730 * This uses a trial and error method to loop through possible PHY
2731 * addresses. It tests each by reading the PHY ID registers and
2732 * checking for a match.
2734 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2736 s32 ret_val = -E1000_ERR_PHY_TYPE;
2739 enum e1000_phy_type phy_type = e1000_phy_unknown;
2741 hw->phy.id = phy_type;
2743 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2744 hw->phy.addr = phy_addr;
2748 e1000_get_phy_id(hw);
2749 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2752 * If phy_type is valid, break - we found our
2755 if (phy_type != e1000_phy_unknown) {
2756 ret_val = E1000_SUCCESS;
2769 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2770 * @hw: pointer to the HW structure
2772 * In the case of a PHY power down to save power, or to turn off link during a
2773 * driver unload, or wake on lan is not enabled, restore the link to previous
2776 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2780 /* The PHY will retain its settings across a power down/up cycle */
2781 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2782 mii_reg &= ~MII_CR_POWER_DOWN;
2783 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2787 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2788 * @hw: pointer to the HW structure
2790 * In the case of a PHY power down to save power, or to turn off link during a
2791 * driver unload, or wake on lan is not enabled, restore the link to previous
2794 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2798 /* The PHY will retain its settings across a power down/up cycle */
2799 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2800 mii_reg |= MII_CR_POWER_DOWN;
2801 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2806 * e1000_check_polarity_82577 - Checks the polarity.
2807 * @hw: pointer to the HW structure
2809 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2811 * Polarity is determined based on the PHY specific status register.
2813 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2815 struct e1000_phy_info *phy = &hw->phy;
2819 DEBUGFUNC("e1000_check_polarity_82577");
2821 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2824 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
2825 ? e1000_rev_polarity_reversed
2826 : e1000_rev_polarity_normal;
2832 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2833 * @hw: pointer to the HW structure
2835 * Calls the PHY setup function to force speed and duplex.
2837 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2839 struct e1000_phy_info *phy = &hw->phy;
2844 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
2846 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2850 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
2852 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2858 if (phy->autoneg_wait_to_complete) {
2859 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
2861 ret_val = e1000_phy_has_link_generic(hw,
2869 DEBUGOUT("Link taking longer than expected.\n");
2872 ret_val = e1000_phy_has_link_generic(hw,
2885 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2886 * @hw: pointer to the HW structure
2888 * Read PHY status to determine if link is up. If link is up, then
2889 * set/determine 10base-T extended distance and polarity correction. Read
2890 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2891 * determine on the cable length, local and remote receiver.
2893 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
2895 struct e1000_phy_info *phy = &hw->phy;
2900 DEBUGFUNC("e1000_get_phy_info_82577");
2902 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2907 DEBUGOUT("Phy info is only valid if link is up\n");
2908 ret_val = -E1000_ERR_CONFIG;
2912 phy->polarity_correction = TRUE;
2914 ret_val = e1000_check_polarity_82577(hw);
2918 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2922 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
2924 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
2925 I82577_PHY_STATUS2_SPEED_1000MBPS) {
2926 ret_val = hw->phy.ops.get_cable_length(hw);
2930 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2934 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2935 ? e1000_1000t_rx_status_ok
2936 : e1000_1000t_rx_status_not_ok;
2938 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2939 ? e1000_1000t_rx_status_ok
2940 : e1000_1000t_rx_status_not_ok;
2942 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2943 phy->local_rx = e1000_1000t_rx_status_undefined;
2944 phy->remote_rx = e1000_1000t_rx_status_undefined;
2952 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2953 * @hw: pointer to the HW structure
2955 * Reads the diagnostic status register and verifies result is valid before
2956 * placing it in the phy_cable_length field.
2958 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
2960 struct e1000_phy_info *phy = &hw->phy;
2962 u16 phy_data, length;
2964 DEBUGFUNC("e1000_get_cable_length_82577");
2966 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
2970 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
2971 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
2973 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2974 ret_val = -E1000_ERR_PHY;
2976 phy->cable_length = length;