1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
37 u16 *data, bool read, bool page_set);
38 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
39 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read);
42 /* Cable length tables */
43 static const u16 e1000_m88_cable_length_table[] = {
44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
46 (sizeof(e1000_m88_cable_length_table) / \
47 sizeof(e1000_m88_cable_length_table[0]))
49 static const u16 e1000_igp_2_cable_length_table[] = {
50 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
51 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
52 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
53 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
54 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
55 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
56 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
58 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
59 (sizeof(e1000_igp_2_cable_length_table) / \
60 sizeof(e1000_igp_2_cable_length_table[0]))
63 * e1000_init_phy_ops_generic - Initialize PHY function pointers
64 * @hw: pointer to the HW structure
66 * Setups up the function pointers to no-op functions
68 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
70 struct e1000_phy_info *phy = &hw->phy;
71 DEBUGFUNC("e1000_init_phy_ops_generic");
73 /* Initialize function pointers */
74 phy->ops.init_params = e1000_null_ops_generic;
75 phy->ops.acquire = e1000_null_ops_generic;
76 phy->ops.check_polarity = e1000_null_ops_generic;
77 phy->ops.check_reset_block = e1000_null_ops_generic;
78 phy->ops.commit = e1000_null_ops_generic;
79 phy->ops.force_speed_duplex = e1000_null_ops_generic;
80 phy->ops.get_cfg_done = e1000_null_ops_generic;
81 phy->ops.get_cable_length = e1000_null_ops_generic;
82 phy->ops.get_info = e1000_null_ops_generic;
83 phy->ops.set_page = e1000_null_set_page;
84 phy->ops.read_reg = e1000_null_read_reg;
85 phy->ops.read_reg_locked = e1000_null_read_reg;
86 phy->ops.read_reg_page = e1000_null_read_reg;
87 phy->ops.release = e1000_null_phy_generic;
88 phy->ops.reset = e1000_null_ops_generic;
89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
91 phy->ops.write_reg = e1000_null_write_reg;
92 phy->ops.write_reg_locked = e1000_null_write_reg;
93 phy->ops.write_reg_page = e1000_null_write_reg;
94 phy->ops.power_up = e1000_null_phy_generic;
95 phy->ops.power_down = e1000_null_phy_generic;
96 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
97 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
98 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
102 * e1000_null_set_page - No-op function, return 0
103 * @hw: pointer to the HW structure
105 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
106 u16 E1000_UNUSEDARG data)
108 DEBUGFUNC("e1000_null_set_page");
109 UNREFERENCED_2PARAMETER(hw, data);
110 return E1000_SUCCESS;
114 * e1000_null_read_reg - No-op function, return 0
115 * @hw: pointer to the HW structure
117 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
118 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
120 DEBUGFUNC("e1000_null_read_reg");
121 UNREFERENCED_3PARAMETER(hw, offset, data);
122 return E1000_SUCCESS;
126 * e1000_null_phy_generic - No-op function, return void
127 * @hw: pointer to the HW structure
129 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
131 DEBUGFUNC("e1000_null_phy_generic");
132 UNREFERENCED_1PARAMETER(hw);
137 * e1000_null_lplu_state - No-op function, return 0
138 * @hw: pointer to the HW structure
140 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
141 bool E1000_UNUSEDARG active)
143 DEBUGFUNC("e1000_null_lplu_state");
144 UNREFERENCED_2PARAMETER(hw, active);
145 return E1000_SUCCESS;
149 * e1000_null_write_reg - No-op function, return 0
150 * @hw: pointer to the HW structure
152 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
153 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
155 DEBUGFUNC("e1000_null_write_reg");
156 UNREFERENCED_3PARAMETER(hw, offset, data);
157 return E1000_SUCCESS;
161 * e1000_read_i2c_byte_null - No-op function, return 0
162 * @hw: pointer to hardware structure
163 * @byte_offset: byte offset to write
164 * @dev_addr: device address
165 * @data: data value read
168 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
169 u8 E1000_UNUSEDARG byte_offset,
170 u8 E1000_UNUSEDARG dev_addr,
171 u8 E1000_UNUSEDARG *data)
173 DEBUGFUNC("e1000_read_i2c_byte_null");
174 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
175 return E1000_SUCCESS;
179 * e1000_write_i2c_byte_null - No-op function, return 0
180 * @hw: pointer to hardware structure
181 * @byte_offset: byte offset to write
182 * @dev_addr: device address
183 * @data: data value to write
186 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
187 u8 E1000_UNUSEDARG byte_offset,
188 u8 E1000_UNUSEDARG dev_addr,
189 u8 E1000_UNUSEDARG data)
191 DEBUGFUNC("e1000_write_i2c_byte_null");
192 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
193 return E1000_SUCCESS;
197 * e1000_check_reset_block_generic - Check if PHY reset is blocked
198 * @hw: pointer to the HW structure
200 * Read the PHY management control register and check whether a PHY reset
201 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
202 * return E1000_BLK_PHY_RESET (12).
204 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
208 DEBUGFUNC("e1000_check_reset_block");
210 manc = E1000_READ_REG(hw, E1000_MANC);
212 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
213 E1000_BLK_PHY_RESET : E1000_SUCCESS;
217 * e1000_get_phy_id - Retrieve the PHY ID and revision
218 * @hw: pointer to the HW structure
220 * Reads the PHY registers and stores the PHY ID and possibly the PHY
221 * revision in the hardware structure.
223 s32 e1000_get_phy_id(struct e1000_hw *hw)
225 struct e1000_phy_info *phy = &hw->phy;
226 s32 ret_val = E1000_SUCCESS;
230 DEBUGFUNC("e1000_get_phy_id");
232 if (!phy->ops.read_reg)
233 return E1000_SUCCESS;
235 while (retry_count < 2) {
236 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
240 phy->id = (u32)(phy_id << 16);
242 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
246 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
247 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
249 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
250 return E1000_SUCCESS;
255 return E1000_SUCCESS;
259 * e1000_phy_reset_dsp_generic - Reset PHY DSP
260 * @hw: pointer to the HW structure
262 * Reset the digital signal processor.
264 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
268 DEBUGFUNC("e1000_phy_reset_dsp_generic");
270 if (!hw->phy.ops.write_reg)
271 return E1000_SUCCESS;
273 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
277 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
281 * e1000_read_phy_reg_mdic - Read MDI control register
282 * @hw: pointer to the HW structure
283 * @offset: register offset to be read
284 * @data: pointer to the read data
286 * Reads the MDI control register in the PHY at offset and stores the
287 * information read to data.
289 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
291 struct e1000_phy_info *phy = &hw->phy;
294 DEBUGFUNC("e1000_read_phy_reg_mdic");
296 if (offset > MAX_PHY_REG_ADDRESS) {
297 DEBUGOUT1("PHY Address %d is out of range\n", offset);
298 return -E1000_ERR_PARAM;
301 /* Set up Op-code, Phy Address, and register offset in the MDI
302 * Control register. The MAC will take care of interfacing with the
303 * PHY to retrieve the desired data.
305 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
306 (phy->addr << E1000_MDIC_PHY_SHIFT) |
307 (E1000_MDIC_OP_READ));
309 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
311 /* Poll the ready bit to see if the MDI read completed
312 * Increasing the time out as testing showed failures with
315 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
317 mdic = E1000_READ_REG(hw, E1000_MDIC);
318 if (mdic & E1000_MDIC_READY)
321 if (!(mdic & E1000_MDIC_READY)) {
322 DEBUGOUT("MDI Read did not complete\n");
323 return -E1000_ERR_PHY;
325 if (mdic & E1000_MDIC_ERROR) {
326 DEBUGOUT("MDI Error\n");
327 return -E1000_ERR_PHY;
331 /* Allow some time after each MDIC transaction to avoid
332 * reading duplicate data in the next MDIC transaction.
334 if (hw->mac.type == e1000_pch2lan)
337 return E1000_SUCCESS;
341 * e1000_write_phy_reg_mdic - Write MDI control register
342 * @hw: pointer to the HW structure
343 * @offset: register offset to write to
344 * @data: data to write to register at offset
346 * Writes data to MDI control register in the PHY at offset.
348 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
350 struct e1000_phy_info *phy = &hw->phy;
353 DEBUGFUNC("e1000_write_phy_reg_mdic");
355 if (offset > MAX_PHY_REG_ADDRESS) {
356 DEBUGOUT1("PHY Address %d is out of range\n", offset);
357 return -E1000_ERR_PARAM;
360 /* Set up Op-code, Phy Address, and register offset in the MDI
361 * Control register. The MAC will take care of interfacing with the
362 * PHY to retrieve the desired data.
364 mdic = (((u32)data) |
365 (offset << E1000_MDIC_REG_SHIFT) |
366 (phy->addr << E1000_MDIC_PHY_SHIFT) |
367 (E1000_MDIC_OP_WRITE));
369 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
371 /* Poll the ready bit to see if the MDI read completed
372 * Increasing the time out as testing showed failures with
375 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
377 mdic = E1000_READ_REG(hw, E1000_MDIC);
378 if (mdic & E1000_MDIC_READY)
381 if (!(mdic & E1000_MDIC_READY)) {
382 DEBUGOUT("MDI Write did not complete\n");
383 return -E1000_ERR_PHY;
385 if (mdic & E1000_MDIC_ERROR) {
386 DEBUGOUT("MDI Error\n");
387 return -E1000_ERR_PHY;
390 /* Allow some time after each MDIC transaction to avoid
391 * reading duplicate data in the next MDIC transaction.
393 if (hw->mac.type == e1000_pch2lan)
396 return E1000_SUCCESS;
400 * e1000_read_phy_reg_i2c - Read PHY register using i2c
401 * @hw: pointer to the HW structure
402 * @offset: register offset to be read
403 * @data: pointer to the read data
405 * Reads the PHY register at offset using the i2c interface and stores the
406 * retrieved information in data.
408 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
410 struct e1000_phy_info *phy = &hw->phy;
413 DEBUGFUNC("e1000_read_phy_reg_i2c");
415 /* Set up Op-code, Phy Address, and register address in the I2CCMD
416 * register. The MAC will take care of interfacing with the
417 * PHY to retrieve the desired data.
419 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
420 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
421 (E1000_I2CCMD_OPCODE_READ));
423 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
425 /* Poll the ready bit to see if the I2C read completed */
426 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
428 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
429 if (i2ccmd & E1000_I2CCMD_READY)
432 if (!(i2ccmd & E1000_I2CCMD_READY)) {
433 DEBUGOUT("I2CCMD Read did not complete\n");
434 return -E1000_ERR_PHY;
436 if (i2ccmd & E1000_I2CCMD_ERROR) {
437 DEBUGOUT("I2CCMD Error bit set\n");
438 return -E1000_ERR_PHY;
441 /* Need to byte-swap the 16-bit value. */
442 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
444 return E1000_SUCCESS;
448 * e1000_write_phy_reg_i2c - Write PHY register using i2c
449 * @hw: pointer to the HW structure
450 * @offset: register offset to write to
451 * @data: data to write at register offset
453 * Writes the data to PHY register at the offset using the i2c interface.
455 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
457 struct e1000_phy_info *phy = &hw->phy;
459 u16 phy_data_swapped;
461 DEBUGFUNC("e1000_write_phy_reg_i2c");
463 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
464 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
465 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
467 return -E1000_ERR_CONFIG;
470 /* Swap the data bytes for the I2C interface */
471 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
473 /* Set up Op-code, Phy Address, and register address in the I2CCMD
474 * register. The MAC will take care of interfacing with the
475 * PHY to retrieve the desired data.
477 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
478 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
479 E1000_I2CCMD_OPCODE_WRITE |
482 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
484 /* Poll the ready bit to see if the I2C read completed */
485 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
487 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
488 if (i2ccmd & E1000_I2CCMD_READY)
491 if (!(i2ccmd & E1000_I2CCMD_READY)) {
492 DEBUGOUT("I2CCMD Write did not complete\n");
493 return -E1000_ERR_PHY;
495 if (i2ccmd & E1000_I2CCMD_ERROR) {
496 DEBUGOUT("I2CCMD Error bit set\n");
497 return -E1000_ERR_PHY;
500 return E1000_SUCCESS;
504 * e1000_read_sfp_data_byte - Reads SFP module data.
505 * @hw: pointer to the HW structure
506 * @offset: byte location offset to be read
507 * @data: read data buffer pointer
509 * Reads one byte from SFP module data stored
510 * in SFP resided EEPROM memory or SFP diagnostic area.
511 * Function should be called with
512 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
513 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
516 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
522 DEBUGFUNC("e1000_read_sfp_data_byte");
524 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
525 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
526 return -E1000_ERR_PHY;
529 /* Set up Op-code, EEPROM Address,in the I2CCMD
530 * register. The MAC will take care of interfacing with the
531 * EEPROM to retrieve the desired data.
533 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
534 E1000_I2CCMD_OPCODE_READ);
536 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
538 /* Poll the ready bit to see if the I2C read completed */
539 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
541 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
542 if (data_local & E1000_I2CCMD_READY)
545 if (!(data_local & E1000_I2CCMD_READY)) {
546 DEBUGOUT("I2CCMD Read did not complete\n");
547 return -E1000_ERR_PHY;
549 if (data_local & E1000_I2CCMD_ERROR) {
550 DEBUGOUT("I2CCMD Error bit set\n");
551 return -E1000_ERR_PHY;
553 *data = (u8) data_local & 0xFF;
555 return E1000_SUCCESS;
559 * e1000_write_sfp_data_byte - Writes SFP module data.
560 * @hw: pointer to the HW structure
561 * @offset: byte location offset to write to
562 * @data: data to write
564 * Writes one byte to SFP module data stored
565 * in SFP resided EEPROM memory or SFP diagnostic area.
566 * Function should be called with
567 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
568 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
571 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
577 DEBUGFUNC("e1000_write_sfp_data_byte");
579 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
580 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
581 return -E1000_ERR_PHY;
583 /* The programming interface is 16 bits wide
584 * so we need to read the whole word first
585 * then update appropriate byte lane and write
586 * the updated word back.
588 /* Set up Op-code, EEPROM Address,in the I2CCMD
589 * register. The MAC will take care of interfacing
590 * with an EEPROM to write the data given.
592 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
593 E1000_I2CCMD_OPCODE_READ);
594 /* Set a command to read single word */
595 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
596 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
598 /* Poll the ready bit to see if lastly
599 * launched I2C operation completed
601 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
602 if (i2ccmd & E1000_I2CCMD_READY) {
603 /* Check if this is READ or WRITE phase */
604 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
605 E1000_I2CCMD_OPCODE_READ) {
606 /* Write the selected byte
607 * lane and update whole word
609 data_local = i2ccmd & 0xFF00;
612 E1000_I2CCMD_REG_ADDR_SHIFT) |
613 E1000_I2CCMD_OPCODE_WRITE | data_local);
614 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
620 if (!(i2ccmd & E1000_I2CCMD_READY)) {
621 DEBUGOUT("I2CCMD Write did not complete\n");
622 return -E1000_ERR_PHY;
624 if (i2ccmd & E1000_I2CCMD_ERROR) {
625 DEBUGOUT("I2CCMD Error bit set\n");
626 return -E1000_ERR_PHY;
628 return E1000_SUCCESS;
632 * e1000_read_phy_reg_m88 - Read m88 PHY register
633 * @hw: pointer to the HW structure
634 * @offset: register offset to be read
635 * @data: pointer to the read data
637 * Acquires semaphore, if necessary, then reads the PHY register at offset
638 * and storing the retrieved information in data. Release any acquired
639 * semaphores before exiting.
641 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
645 DEBUGFUNC("e1000_read_phy_reg_m88");
647 if (!hw->phy.ops.acquire)
648 return E1000_SUCCESS;
650 ret_val = hw->phy.ops.acquire(hw);
654 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
657 hw->phy.ops.release(hw);
663 * e1000_write_phy_reg_m88 - Write m88 PHY register
664 * @hw: pointer to the HW structure
665 * @offset: register offset to write to
666 * @data: data to write at register offset
668 * Acquires semaphore, if necessary, then writes the data to PHY register
669 * at the offset. Release any acquired semaphores before exiting.
671 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
675 DEBUGFUNC("e1000_write_phy_reg_m88");
677 if (!hw->phy.ops.acquire)
678 return E1000_SUCCESS;
680 ret_val = hw->phy.ops.acquire(hw);
684 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
687 hw->phy.ops.release(hw);
693 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
694 * @hw: pointer to the HW structure
695 * @page: page to set (shifted left when necessary)
697 * Sets PHY page required for PHY register access. Assumes semaphore is
698 * already acquired. Note, this function sets phy.addr to 1 so the caller
699 * must set it appropriately (if necessary) after this function returns.
701 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
703 DEBUGFUNC("e1000_set_page_igp");
705 DEBUGOUT1("Setting page 0x%x\n", page);
709 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
713 * __e1000_read_phy_reg_igp - Read igp PHY register
714 * @hw: pointer to the HW structure
715 * @offset: register offset to be read
716 * @data: pointer to the read data
717 * @locked: semaphore has already been acquired or not
719 * Acquires semaphore, if necessary, then reads the PHY register at offset
720 * and stores the retrieved information in data. Release any acquired
721 * semaphores before exiting.
723 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
726 s32 ret_val = E1000_SUCCESS;
728 DEBUGFUNC("__e1000_read_phy_reg_igp");
731 if (!hw->phy.ops.acquire)
732 return E1000_SUCCESS;
734 ret_val = hw->phy.ops.acquire(hw);
739 if (offset > MAX_PHY_MULTI_PAGE_REG)
740 ret_val = e1000_write_phy_reg_mdic(hw,
741 IGP01E1000_PHY_PAGE_SELECT,
744 ret_val = e1000_read_phy_reg_mdic(hw,
745 MAX_PHY_REG_ADDRESS & offset,
748 hw->phy.ops.release(hw);
754 * e1000_read_phy_reg_igp - Read igp PHY register
755 * @hw: pointer to the HW structure
756 * @offset: register offset to be read
757 * @data: pointer to the read data
759 * Acquires semaphore then reads the PHY register at offset and stores the
760 * retrieved information in data.
761 * Release the acquired semaphore before exiting.
763 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
765 return __e1000_read_phy_reg_igp(hw, offset, data, false);
769 * e1000_read_phy_reg_igp_locked - Read igp PHY register
770 * @hw: pointer to the HW structure
771 * @offset: register offset to be read
772 * @data: pointer to the read data
774 * Reads the PHY register at offset and stores the retrieved information
775 * in data. Assumes semaphore already acquired.
777 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
779 return __e1000_read_phy_reg_igp(hw, offset, data, true);
783 * e1000_write_phy_reg_igp - Write igp PHY register
784 * @hw: pointer to the HW structure
785 * @offset: register offset to write to
786 * @data: data to write at register offset
787 * @locked: semaphore has already been acquired or not
789 * Acquires semaphore, if necessary, then writes the data to PHY register
790 * at the offset. Release any acquired semaphores before exiting.
792 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
795 s32 ret_val = E1000_SUCCESS;
797 DEBUGFUNC("e1000_write_phy_reg_igp");
800 if (!hw->phy.ops.acquire)
801 return E1000_SUCCESS;
803 ret_val = hw->phy.ops.acquire(hw);
808 if (offset > MAX_PHY_MULTI_PAGE_REG)
809 ret_val = e1000_write_phy_reg_mdic(hw,
810 IGP01E1000_PHY_PAGE_SELECT,
813 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
817 hw->phy.ops.release(hw);
823 * e1000_write_phy_reg_igp - Write igp PHY register
824 * @hw: pointer to the HW structure
825 * @offset: register offset to write to
826 * @data: data to write at register offset
828 * Acquires semaphore then writes the data to PHY register
829 * at the offset. Release any acquired semaphores before exiting.
831 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
833 return __e1000_write_phy_reg_igp(hw, offset, data, false);
837 * e1000_write_phy_reg_igp_locked - Write igp PHY register
838 * @hw: pointer to the HW structure
839 * @offset: register offset to write to
840 * @data: data to write at register offset
842 * Writes the data to PHY register at the offset.
843 * Assumes semaphore already acquired.
845 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
847 return __e1000_write_phy_reg_igp(hw, offset, data, true);
851 * __e1000_read_kmrn_reg - Read kumeran register
852 * @hw: pointer to the HW structure
853 * @offset: register offset to be read
854 * @data: pointer to the read data
855 * @locked: semaphore has already been acquired or not
857 * Acquires semaphore, if necessary. Then reads the PHY register at offset
858 * using the kumeran interface. The information retrieved is stored in data.
859 * Release any acquired semaphores before exiting.
861 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
866 DEBUGFUNC("__e1000_read_kmrn_reg");
869 s32 ret_val = E1000_SUCCESS;
871 if (!hw->phy.ops.acquire)
872 return E1000_SUCCESS;
874 ret_val = hw->phy.ops.acquire(hw);
879 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
880 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
881 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
882 E1000_WRITE_FLUSH(hw);
886 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
887 *data = (u16)kmrnctrlsta;
890 hw->phy.ops.release(hw);
892 return E1000_SUCCESS;
896 * e1000_read_kmrn_reg_generic - Read kumeran register
897 * @hw: pointer to the HW structure
898 * @offset: register offset to be read
899 * @data: pointer to the read data
901 * Acquires semaphore then reads the PHY register at offset using the
902 * kumeran interface. The information retrieved is stored in data.
903 * Release the acquired semaphore before exiting.
905 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
907 return __e1000_read_kmrn_reg(hw, offset, data, false);
911 * e1000_read_kmrn_reg_locked - Read kumeran register
912 * @hw: pointer to the HW structure
913 * @offset: register offset to be read
914 * @data: pointer to the read data
916 * Reads the PHY register at offset using the kumeran interface. The
917 * information retrieved is stored in data.
918 * Assumes semaphore already acquired.
920 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
922 return __e1000_read_kmrn_reg(hw, offset, data, true);
926 * __e1000_write_kmrn_reg - Write kumeran register
927 * @hw: pointer to the HW structure
928 * @offset: register offset to write to
929 * @data: data to write at register offset
930 * @locked: semaphore has already been acquired or not
932 * Acquires semaphore, if necessary. Then write the data to PHY register
933 * at the offset using the kumeran interface. Release any acquired semaphores
936 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
941 DEBUGFUNC("e1000_write_kmrn_reg_generic");
944 s32 ret_val = E1000_SUCCESS;
946 if (!hw->phy.ops.acquire)
947 return E1000_SUCCESS;
949 ret_val = hw->phy.ops.acquire(hw);
954 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
955 E1000_KMRNCTRLSTA_OFFSET) | data;
956 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
957 E1000_WRITE_FLUSH(hw);
962 hw->phy.ops.release(hw);
964 return E1000_SUCCESS;
968 * e1000_write_kmrn_reg_generic - Write kumeran register
969 * @hw: pointer to the HW structure
970 * @offset: register offset to write to
971 * @data: data to write at register offset
973 * Acquires semaphore then writes the data to the PHY register at the offset
974 * using the kumeran interface. Release the acquired semaphore before exiting.
976 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
978 return __e1000_write_kmrn_reg(hw, offset, data, false);
982 * e1000_write_kmrn_reg_locked - Write kumeran register
983 * @hw: pointer to the HW structure
984 * @offset: register offset to write to
985 * @data: data to write at register offset
987 * Write the data to PHY register at the offset using the kumeran interface.
988 * Assumes semaphore already acquired.
990 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
992 return __e1000_write_kmrn_reg(hw, offset, data, true);
996 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
997 * @hw: pointer to the HW structure
999 * Sets up Master/slave mode
1001 STATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1006 /* Resolve Master/Slave mode */
1007 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1011 /* load defaults for future use */
1012 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1013 ((phy_data & CR_1000T_MS_VALUE) ?
1014 e1000_ms_force_master :
1015 e1000_ms_force_slave) : e1000_ms_auto;
1017 switch (hw->phy.ms_type) {
1018 case e1000_ms_force_master:
1019 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1021 case e1000_ms_force_slave:
1022 phy_data |= CR_1000T_MS_ENABLE;
1023 phy_data &= ~(CR_1000T_MS_VALUE);
1026 phy_data &= ~CR_1000T_MS_ENABLE;
1032 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1036 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1037 * @hw: pointer to the HW structure
1039 * Sets up Carrier-sense on Transmit and downshift values.
1041 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1046 DEBUGFUNC("e1000_copper_link_setup_82577");
1048 if (hw->phy.type == e1000_phy_82580) {
1049 ret_val = hw->phy.ops.reset(hw);
1051 DEBUGOUT("Error resetting the PHY.\n");
1056 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1057 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1061 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1063 /* Enable downshift */
1064 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1066 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1070 /* Set MDI/MDIX mode */
1071 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1074 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1076 * 0 - Auto (default)
1080 switch (hw->phy.mdix) {
1084 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1088 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1091 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1095 return e1000_set_master_slave_mode(hw);
1099 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1100 * @hw: pointer to the HW structure
1102 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1103 * and downshift values are set also.
1105 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1107 struct e1000_phy_info *phy = &hw->phy;
1111 DEBUGFUNC("e1000_copper_link_setup_m88");
1114 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1115 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1119 /* For BM PHY this bit is downshift enable */
1120 if (phy->type != e1000_phy_bm)
1121 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1124 * MDI/MDI-X = 0 (default)
1125 * 0 - Auto for all speeds
1128 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1130 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1132 switch (phy->mdix) {
1134 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1137 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1140 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1144 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1149 * disable_polarity_correction = 0 (default)
1150 * Automatic Correction for Reversed Cable Polarity
1154 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1155 if (phy->disable_polarity_correction)
1156 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1158 /* Enable downshift on BM (disabled by default) */
1159 if (phy->type == e1000_phy_bm) {
1160 /* For 82574/82583, first disable then enable downshift */
1161 if (phy->id == BME1000_E_PHY_ID_R2) {
1162 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1163 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1167 /* Commit the changes. */
1168 ret_val = phy->ops.commit(hw);
1170 DEBUGOUT("Error committing the PHY changes\n");
1175 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1182 if ((phy->type == e1000_phy_m88) &&
1183 (phy->revision < E1000_REVISION_4) &&
1184 (phy->id != BME1000_E_PHY_ID_R2)) {
1185 /* Force TX_CLK in the Extended PHY Specific Control Register
1188 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1193 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1195 if ((phy->revision == E1000_REVISION_2) &&
1196 (phy->id == M88E1111_I_PHY_ID)) {
1197 /* 82573L PHY - set the downshift counter to 5x. */
1198 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1199 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1201 /* Configure Master and Slave downshift values */
1202 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1203 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1204 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1205 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1207 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1213 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1214 /* Set PHY page 0, register 29 to 0x0003 */
1215 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1219 /* Set PHY page 0, register 30 to 0x0000 */
1220 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1225 /* Commit the changes. */
1226 ret_val = phy->ops.commit(hw);
1228 DEBUGOUT("Error committing the PHY changes\n");
1232 if (phy->type == e1000_phy_82578) {
1233 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1238 /* 82578 PHY - set the downshift count to 1x. */
1239 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1240 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1241 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1247 if (phy->type == e1000_phy_i210) {
1248 ret_val = e1000_set_master_slave_mode(hw);
1253 return E1000_SUCCESS;
1257 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1258 * @hw: pointer to the HW structure
1260 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1261 * Also enables and sets the downshift parameters.
1263 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1265 struct e1000_phy_info *phy = &hw->phy;
1269 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1272 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1273 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1278 * MDI/MDI-X = 0 (default)
1279 * 0 - Auto for all speeds
1282 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1284 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1286 switch (phy->mdix) {
1288 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1291 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1294 /* M88E1112 does not support this mode) */
1295 if (phy->id != M88E1112_E_PHY_ID) {
1296 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1301 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1306 * disable_polarity_correction = 0 (default)
1307 * Automatic Correction for Reversed Cable Polarity
1311 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1312 if (phy->disable_polarity_correction)
1313 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1315 /* Enable downshift and setting it to X6 */
1316 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1317 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1318 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1320 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1324 /* Commit the changes. */
1325 ret_val = phy->ops.commit(hw);
1327 DEBUGOUT("Error committing the PHY changes\n");
1331 return E1000_SUCCESS;
1335 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1336 * @hw: pointer to the HW structure
1338 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1341 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1343 struct e1000_phy_info *phy = &hw->phy;
1347 DEBUGFUNC("e1000_copper_link_setup_igp");
1350 ret_val = hw->phy.ops.reset(hw);
1352 DEBUGOUT("Error resetting the PHY.\n");
1356 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1357 * timeout issues when LFS is enabled.
1361 /* The NVM settings will configure LPLU in D3 for
1364 if (phy->type == e1000_phy_igp) {
1365 /* disable lplu d3 during driver init */
1366 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1368 DEBUGOUT("Error Disabling LPLU D3\n");
1373 /* disable lplu d0 during driver init */
1374 if (hw->phy.ops.set_d0_lplu_state) {
1375 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1377 DEBUGOUT("Error Disabling LPLU D0\n");
1381 /* Configure mdi-mdix settings */
1382 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1386 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1388 switch (phy->mdix) {
1390 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1393 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1397 data |= IGP01E1000_PSCR_AUTO_MDIX;
1400 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1404 /* set auto-master slave resolution settings */
1405 if (hw->mac.autoneg) {
1406 /* when autonegotiation advertisement is only 1000Mbps then we
1407 * should disable SmartSpeed and enable Auto MasterSlave
1408 * resolution as hardware default.
1410 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1411 /* Disable SmartSpeed */
1412 ret_val = phy->ops.read_reg(hw,
1413 IGP01E1000_PHY_PORT_CONFIG,
1418 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1419 ret_val = phy->ops.write_reg(hw,
1420 IGP01E1000_PHY_PORT_CONFIG,
1425 /* Set auto Master/Slave resolution process */
1426 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1430 data &= ~CR_1000T_MS_ENABLE;
1431 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1436 ret_val = e1000_set_master_slave_mode(hw);
1443 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1444 * @hw: pointer to the HW structure
1446 * Reads the MII auto-neg advertisement register and/or the 1000T control
1447 * register and if the PHY is already setup for auto-negotiation, then
1448 * return successful. Otherwise, setup advertisement and flow control to
1449 * the appropriate values for the wanted auto-negotiation.
1451 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1453 struct e1000_phy_info *phy = &hw->phy;
1455 u16 mii_autoneg_adv_reg;
1456 u16 mii_1000t_ctrl_reg = 0;
1458 DEBUGFUNC("e1000_phy_setup_autoneg");
1460 phy->autoneg_advertised &= phy->autoneg_mask;
1462 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1463 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1467 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1468 /* Read the MII 1000Base-T Control Register (Address 9). */
1469 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1470 &mii_1000t_ctrl_reg);
1475 /* Need to parse both autoneg_advertised and fc and set up
1476 * the appropriate PHY registers. First we will parse for
1477 * autoneg_advertised software override. Since we can advertise
1478 * a plethora of combinations, we need to check each bit
1482 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1483 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1484 * the 1000Base-T Control Register (Address 9).
1486 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1487 NWAY_AR_100TX_HD_CAPS |
1488 NWAY_AR_10T_FD_CAPS |
1489 NWAY_AR_10T_HD_CAPS);
1490 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1492 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1494 /* Do we want to advertise 10 Mb Half Duplex? */
1495 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1496 DEBUGOUT("Advertise 10mb Half duplex\n");
1497 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1500 /* Do we want to advertise 10 Mb Full Duplex? */
1501 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1502 DEBUGOUT("Advertise 10mb Full duplex\n");
1503 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1506 /* Do we want to advertise 100 Mb Half Duplex? */
1507 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1508 DEBUGOUT("Advertise 100mb Half duplex\n");
1509 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1512 /* Do we want to advertise 100 Mb Full Duplex? */
1513 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1514 DEBUGOUT("Advertise 100mb Full duplex\n");
1515 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1518 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1519 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1520 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1522 /* Do we want to advertise 1000 Mb Full Duplex? */
1523 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1524 DEBUGOUT("Advertise 1000mb Full duplex\n");
1525 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1528 /* Check for a software override of the flow control settings, and
1529 * setup the PHY advertisement registers accordingly. If
1530 * auto-negotiation is enabled, then software will have to set the
1531 * "PAUSE" bits to the correct value in the Auto-Negotiation
1532 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1535 * The possible values of the "fc" parameter are:
1536 * 0: Flow control is completely disabled
1537 * 1: Rx flow control is enabled (we can receive pause frames
1538 * but not send pause frames).
1539 * 2: Tx flow control is enabled (we can send pause frames
1540 * but we do not support receiving pause frames).
1541 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1542 * other: No software override. The flow control configuration
1543 * in the EEPROM is used.
1545 switch (hw->fc.current_mode) {
1547 /* Flow control (Rx & Tx) is completely disabled by a
1548 * software over-ride.
1550 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1552 case e1000_fc_rx_pause:
1553 /* Rx Flow control is enabled, and Tx Flow control is
1554 * disabled, by a software over-ride.
1556 * Since there really isn't a way to advertise that we are
1557 * capable of Rx Pause ONLY, we will advertise that we
1558 * support both symmetric and asymmetric Rx PAUSE. Later
1559 * (in e1000_config_fc_after_link_up) we will disable the
1560 * hw's ability to send PAUSE frames.
1562 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1564 case e1000_fc_tx_pause:
1565 /* Tx Flow control is enabled, and Rx Flow control is
1566 * disabled, by a software over-ride.
1568 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1569 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1572 /* Flow control (both Rx and Tx) is enabled by a software
1575 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1578 DEBUGOUT("Flow control param set incorrectly\n");
1579 return -E1000_ERR_CONFIG;
1582 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1586 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1588 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1589 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1590 mii_1000t_ctrl_reg);
1596 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1597 * @hw: pointer to the HW structure
1599 * Performs initial bounds checking on autoneg advertisement parameter, then
1600 * configure to advertise the full capability. Setup the PHY to autoneg
1601 * and restart the negotiation process between the link partner. If
1602 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1604 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1606 struct e1000_phy_info *phy = &hw->phy;
1610 DEBUGFUNC("e1000_copper_link_autoneg");
1612 /* Perform some bounds checking on the autoneg advertisement
1615 phy->autoneg_advertised &= phy->autoneg_mask;
1617 /* If autoneg_advertised is zero, we assume it was not defaulted
1618 * by the calling code so we set to advertise full capability.
1620 if (!phy->autoneg_advertised)
1621 phy->autoneg_advertised = phy->autoneg_mask;
1623 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1624 ret_val = e1000_phy_setup_autoneg(hw);
1626 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1629 DEBUGOUT("Restarting Auto-Neg\n");
1631 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1632 * the Auto Neg Restart bit in the PHY control register.
1634 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1638 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1639 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1643 /* Does the user want to wait for Auto-Neg to complete here, or
1644 * check at a later time (for example, callback routine).
1646 if (phy->autoneg_wait_to_complete) {
1647 ret_val = hw->mac.ops.wait_autoneg(hw);
1649 DEBUGOUT("Error while waiting for autoneg to complete\n");
1654 hw->mac.get_link_status = true;
1660 * e1000_setup_copper_link_generic - Configure copper link settings
1661 * @hw: pointer to the HW structure
1663 * Calls the appropriate function to configure the link for auto-neg or forced
1664 * speed and duplex. Then we check for link, once link is established calls
1665 * to configure collision distance and flow control are called. If link is
1666 * not established, we return -E1000_ERR_PHY (-2).
1668 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1673 DEBUGFUNC("e1000_setup_copper_link_generic");
1675 if (hw->mac.autoneg) {
1676 /* Setup autoneg and flow control advertisement and perform
1679 ret_val = e1000_copper_link_autoneg(hw);
1683 /* PHY will be set to 10H, 10F, 100H or 100F
1684 * depending on user settings.
1686 DEBUGOUT("Forcing Speed and Duplex\n");
1687 ret_val = hw->phy.ops.force_speed_duplex(hw);
1689 DEBUGOUT("Error Forcing Speed and Duplex\n");
1694 /* Check link status. Wait up to 100 microseconds for link to become
1697 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1703 DEBUGOUT("Valid link established!!!\n");
1704 hw->mac.ops.config_collision_dist(hw);
1705 ret_val = e1000_config_fc_after_link_up_generic(hw);
1707 DEBUGOUT("Unable to establish link!!!\n");
1714 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1715 * @hw: pointer to the HW structure
1717 * Calls the PHY setup function to force speed and duplex. Clears the
1718 * auto-crossover to force MDI manually. Waits for link and returns
1719 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1721 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1723 struct e1000_phy_info *phy = &hw->phy;
1728 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1730 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1734 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1736 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1740 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1741 * forced whenever speed and duplex are forced.
1743 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1747 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1748 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1750 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1754 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1758 if (phy->autoneg_wait_to_complete) {
1759 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1761 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1767 DEBUGOUT("Link taking longer than expected.\n");
1770 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1778 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1779 * @hw: pointer to the HW structure
1781 * Calls the PHY setup function to force speed and duplex. Clears the
1782 * auto-crossover to force MDI manually. Resets the PHY to commit the
1783 * changes. If time expires while waiting for link up, we reset the DSP.
1784 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1785 * successful completion, else return corresponding error code.
1787 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1789 struct e1000_phy_info *phy = &hw->phy;
1794 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1796 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1797 if (phy->type != e1000_phy_i210) {
1798 /* Clear Auto-Crossover to force MDI manually. M88E1000
1799 * requires MDI forced whenever speed and duplex are forced.
1801 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1806 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1807 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1813 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1815 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1819 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1821 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1825 /* Reset the phy to commit changes. */
1826 ret_val = hw->phy.ops.commit(hw);
1830 if (phy->autoneg_wait_to_complete) {
1831 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1833 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1839 bool reset_dsp = true;
1841 switch (hw->phy.id) {
1842 case I347AT4_E_PHY_ID:
1843 case M88E1340M_E_PHY_ID:
1844 case M88E1112_E_PHY_ID:
1849 if (hw->phy.type != e1000_phy_m88)
1855 DEBUGOUT("Link taking longer than expected.\n");
1857 /* We didn't get link.
1858 * Reset the DSP and cross our fingers.
1860 ret_val = phy->ops.write_reg(hw,
1861 M88E1000_PHY_PAGE_SELECT,
1865 ret_val = e1000_phy_reset_dsp_generic(hw);
1872 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1878 if (hw->phy.type != e1000_phy_m88)
1879 return E1000_SUCCESS;
1881 if (hw->phy.id == I347AT4_E_PHY_ID ||
1882 hw->phy.id == M88E1340M_E_PHY_ID ||
1883 hw->phy.id == M88E1112_E_PHY_ID)
1884 return E1000_SUCCESS;
1885 if (hw->phy.id == I210_I_PHY_ID)
1886 return E1000_SUCCESS;
1887 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1891 /* Resetting the phy means we need to re-force TX_CLK in the
1892 * Extended PHY Specific Control Register to 25MHz clock from
1893 * the reset value of 2.5MHz.
1895 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1896 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1900 /* In addition, we must re-enable CRS on Tx for both half and full
1903 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1907 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1908 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1914 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1915 * @hw: pointer to the HW structure
1917 * Forces the speed and duplex settings of the PHY.
1918 * This is a function pointer entry point only called by
1919 * PHY setup routines.
1921 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1923 struct e1000_phy_info *phy = &hw->phy;
1928 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1930 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1934 e1000_phy_force_speed_duplex_setup(hw, &data);
1936 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1940 /* Disable MDI-X support for 10/100 */
1941 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1945 data &= ~IFE_PMC_AUTO_MDIX;
1946 data &= ~IFE_PMC_FORCE_MDIX;
1948 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1952 DEBUGOUT1("IFE PMC: %X\n", data);
1956 if (phy->autoneg_wait_to_complete) {
1957 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1959 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1965 DEBUGOUT("Link taking longer than expected.\n");
1968 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1974 return E1000_SUCCESS;
1978 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1979 * @hw: pointer to the HW structure
1980 * @phy_ctrl: pointer to current value of PHY_CONTROL
1982 * Forces speed and duplex on the PHY by doing the following: disable flow
1983 * control, force speed/duplex on the MAC, disable auto speed detection,
1984 * disable auto-negotiation, configure duplex, configure speed, configure
1985 * the collision distance, write configuration to CTRL register. The
1986 * caller must write to the PHY_CONTROL register for these settings to
1989 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1991 struct e1000_mac_info *mac = &hw->mac;
1994 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1996 /* Turn off flow control when forcing speed/duplex */
1997 hw->fc.current_mode = e1000_fc_none;
1999 /* Force speed/duplex on the mac */
2000 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2001 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2002 ctrl &= ~E1000_CTRL_SPD_SEL;
2004 /* Disable Auto Speed Detection */
2005 ctrl &= ~E1000_CTRL_ASDE;
2007 /* Disable autoneg on the phy */
2008 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2010 /* Forcing Full or Half Duplex? */
2011 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2012 ctrl &= ~E1000_CTRL_FD;
2013 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2014 DEBUGOUT("Half Duplex\n");
2016 ctrl |= E1000_CTRL_FD;
2017 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2018 DEBUGOUT("Full Duplex\n");
2021 /* Forcing 10mb or 100mb? */
2022 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2023 ctrl |= E1000_CTRL_SPD_100;
2024 *phy_ctrl |= MII_CR_SPEED_100;
2025 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2026 DEBUGOUT("Forcing 100mb\n");
2028 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2029 *phy_ctrl |= MII_CR_SPEED_10;
2030 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2031 DEBUGOUT("Forcing 10mb\n");
2034 hw->mac.ops.config_collision_dist(hw);
2036 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2040 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2041 * @hw: pointer to the HW structure
2042 * @active: boolean used to enable/disable lplu
2044 * Success returns 0, Failure returns 1
2046 * The low power link up (lplu) state is set to the power management level D3
2047 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2048 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2049 * is used during Dx states where the power conservation is most important.
2050 * During driver activity, SmartSpeed should be enabled so performance is
2053 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2055 struct e1000_phy_info *phy = &hw->phy;
2059 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2061 if (!hw->phy.ops.read_reg)
2062 return E1000_SUCCESS;
2064 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2069 data &= ~IGP02E1000_PM_D3_LPLU;
2070 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2074 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2075 * during Dx states where the power conservation is most
2076 * important. During driver activity we should enable
2077 * SmartSpeed, so performance is maintained.
2079 if (phy->smart_speed == e1000_smart_speed_on) {
2080 ret_val = phy->ops.read_reg(hw,
2081 IGP01E1000_PHY_PORT_CONFIG,
2086 data |= IGP01E1000_PSCFR_SMART_SPEED;
2087 ret_val = phy->ops.write_reg(hw,
2088 IGP01E1000_PHY_PORT_CONFIG,
2092 } else if (phy->smart_speed == e1000_smart_speed_off) {
2093 ret_val = phy->ops.read_reg(hw,
2094 IGP01E1000_PHY_PORT_CONFIG,
2099 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2100 ret_val = phy->ops.write_reg(hw,
2101 IGP01E1000_PHY_PORT_CONFIG,
2106 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2107 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2108 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2109 data |= IGP02E1000_PM_D3_LPLU;
2110 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2115 /* When LPLU is enabled, we should disable SmartSpeed */
2116 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2121 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2122 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2130 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2131 * @hw: pointer to the HW structure
2133 * Success returns 0, Failure returns 1
2135 * A downshift is detected by querying the PHY link health.
2137 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2139 struct e1000_phy_info *phy = &hw->phy;
2141 u16 phy_data, offset, mask;
2143 DEBUGFUNC("e1000_check_downshift_generic");
2145 switch (phy->type) {
2146 case e1000_phy_i210:
2148 case e1000_phy_gg82563:
2150 case e1000_phy_82578:
2151 offset = M88E1000_PHY_SPEC_STATUS;
2152 mask = M88E1000_PSSR_DOWNSHIFT;
2155 case e1000_phy_igp_2:
2156 case e1000_phy_igp_3:
2157 offset = IGP01E1000_PHY_LINK_HEALTH;
2158 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2161 /* speed downshift not supported */
2162 phy->speed_downgraded = false;
2163 return E1000_SUCCESS;
2166 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2169 phy->speed_downgraded = !!(phy_data & mask);
2175 * e1000_check_polarity_m88 - Checks the polarity.
2176 * @hw: pointer to the HW structure
2178 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2180 * Polarity is determined based on the PHY specific status register.
2182 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2184 struct e1000_phy_info *phy = &hw->phy;
2188 DEBUGFUNC("e1000_check_polarity_m88");
2190 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2193 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2194 ? e1000_rev_polarity_reversed
2195 : e1000_rev_polarity_normal);
2201 * e1000_check_polarity_igp - Checks the polarity.
2202 * @hw: pointer to the HW structure
2204 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2206 * Polarity is determined based on the PHY port status register, and the
2207 * current speed (since there is no polarity at 100Mbps).
2209 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2211 struct e1000_phy_info *phy = &hw->phy;
2213 u16 data, offset, mask;
2215 DEBUGFUNC("e1000_check_polarity_igp");
2217 /* Polarity is determined based on the speed of
2220 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2224 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2225 IGP01E1000_PSSR_SPEED_1000MBPS) {
2226 offset = IGP01E1000_PHY_PCS_INIT_REG;
2227 mask = IGP01E1000_PHY_POLARITY_MASK;
2229 /* This really only applies to 10Mbps since
2230 * there is no polarity for 100Mbps (always 0).
2232 offset = IGP01E1000_PHY_PORT_STATUS;
2233 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2236 ret_val = phy->ops.read_reg(hw, offset, &data);
2239 phy->cable_polarity = ((data & mask)
2240 ? e1000_rev_polarity_reversed
2241 : e1000_rev_polarity_normal);
2247 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2248 * @hw: pointer to the HW structure
2250 * Polarity is determined on the polarity reversal feature being enabled.
2252 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2254 struct e1000_phy_info *phy = &hw->phy;
2256 u16 phy_data, offset, mask;
2258 DEBUGFUNC("e1000_check_polarity_ife");
2260 /* Polarity is determined based on the reversal feature being enabled.
2262 if (phy->polarity_correction) {
2263 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2264 mask = IFE_PESC_POLARITY_REVERSED;
2266 offset = IFE_PHY_SPECIAL_CONTROL;
2267 mask = IFE_PSC_FORCE_POLARITY;
2270 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2273 phy->cable_polarity = ((phy_data & mask)
2274 ? e1000_rev_polarity_reversed
2275 : e1000_rev_polarity_normal);
2281 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2282 * @hw: pointer to the HW structure
2284 * Waits for auto-negotiation to complete or for the auto-negotiation time
2285 * limit to expire, which ever happens first.
2287 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2289 s32 ret_val = E1000_SUCCESS;
2292 DEBUGFUNC("e1000_wait_autoneg_generic");
2294 if (!hw->phy.ops.read_reg)
2295 return E1000_SUCCESS;
2297 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2298 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2299 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2302 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2305 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2310 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2317 * e1000_phy_has_link_generic - Polls PHY for link
2318 * @hw: pointer to the HW structure
2319 * @iterations: number of times to poll for link
2320 * @usec_interval: delay between polling attempts
2321 * @success: pointer to whether polling was successful or not
2323 * Polls the PHY status register for link, 'iterations' number of times.
2325 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2326 u32 usec_interval, bool *success)
2328 s32 ret_val = E1000_SUCCESS;
2331 DEBUGFUNC("e1000_phy_has_link_generic");
2333 if (!hw->phy.ops.read_reg)
2334 return E1000_SUCCESS;
2336 for (i = 0; i < iterations; i++) {
2337 /* Some PHYs require the PHY_STATUS register to be read
2338 * twice due to the link bit being sticky. No harm doing
2339 * it across the board.
2341 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2343 /* If the first read fails, another entity may have
2344 * ownership of the resources, wait and try again to
2345 * see if they have relinquished the resources yet.
2347 usec_delay(usec_interval);
2348 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2351 if (phy_status & MII_SR_LINK_STATUS)
2353 if (usec_interval >= 1000)
2354 msec_delay_irq(usec_interval/1000);
2356 usec_delay(usec_interval);
2359 *success = (i < iterations);
2365 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2366 * @hw: pointer to the HW structure
2368 * Reads the PHY specific status register to retrieve the cable length
2369 * information. The cable length is determined by averaging the minimum and
2370 * maximum values to get the "average" cable length. The m88 PHY has four
2371 * possible cable length values, which are:
2372 * Register Value Cable Length
2376 * 3 110 - 140 meters
2379 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2381 struct e1000_phy_info *phy = &hw->phy;
2383 u16 phy_data, index;
2385 DEBUGFUNC("e1000_get_cable_length_m88");
2387 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2391 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2392 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2394 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2395 return -E1000_ERR_PHY;
2397 phy->min_cable_length = e1000_m88_cable_length_table[index];
2398 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2400 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2402 return E1000_SUCCESS;
2405 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2407 struct e1000_phy_info *phy = &hw->phy;
2409 u16 phy_data, phy_data2, index, default_page, is_cm;
2411 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2413 switch (hw->phy.id) {
2415 /* Get cable length from PHY Cable Diagnostics Control Reg */
2416 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2417 (I347AT4_PCDL + phy->addr),
2422 /* Check if the unit of cable length is meters or cm */
2423 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2424 I347AT4_PCDC, &phy_data2);
2428 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2430 /* Populate the phy structure with cable length in meters */
2431 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2432 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2433 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2435 case M88E1340M_E_PHY_ID:
2436 case I347AT4_E_PHY_ID:
2437 /* Remember the original page select and set it to 7 */
2438 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2443 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2447 /* Get cable length from PHY Cable Diagnostics Control Reg */
2448 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2453 /* Check if the unit of cable length is meters or cm */
2454 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2458 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2460 /* Populate the phy structure with cable length in meters */
2461 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2462 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2463 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2465 /* Reset the page select to its original value */
2466 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2472 case M88E1112_E_PHY_ID:
2473 /* Remember the original page select and set it to 5 */
2474 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2479 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2483 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2488 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2489 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2491 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2492 return -E1000_ERR_PHY;
2494 phy->min_cable_length = e1000_m88_cable_length_table[index];
2495 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2497 phy->cable_length = (phy->min_cable_length +
2498 phy->max_cable_length) / 2;
2500 /* Reset the page select to its original value */
2501 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2508 return -E1000_ERR_PHY;
2515 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2516 * @hw: pointer to the HW structure
2518 * The automatic gain control (agc) normalizes the amplitude of the
2519 * received signal, adjusting for the attenuation produced by the
2520 * cable. By reading the AGC registers, which represent the
2521 * combination of coarse and fine gain value, the value can be put
2522 * into a lookup table to obtain the approximate cable length
2525 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2527 struct e1000_phy_info *phy = &hw->phy;
2529 u16 phy_data, i, agc_value = 0;
2530 u16 cur_agc_index, max_agc_index = 0;
2531 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2532 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2533 IGP02E1000_PHY_AGC_A,
2534 IGP02E1000_PHY_AGC_B,
2535 IGP02E1000_PHY_AGC_C,
2536 IGP02E1000_PHY_AGC_D
2539 DEBUGFUNC("e1000_get_cable_length_igp_2");
2541 /* Read the AGC registers for all channels */
2542 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2543 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2547 /* Getting bits 15:9, which represent the combination of
2548 * coarse and fine gain values. The result is a number
2549 * that can be put into the lookup table to obtain the
2550 * approximate cable length.
2552 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2553 IGP02E1000_AGC_LENGTH_MASK);
2555 /* Array index bound check. */
2556 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2557 (cur_agc_index == 0))
2558 return -E1000_ERR_PHY;
2560 /* Remove min & max AGC values from calculation. */
2561 if (e1000_igp_2_cable_length_table[min_agc_index] >
2562 e1000_igp_2_cable_length_table[cur_agc_index])
2563 min_agc_index = cur_agc_index;
2564 if (e1000_igp_2_cable_length_table[max_agc_index] <
2565 e1000_igp_2_cable_length_table[cur_agc_index])
2566 max_agc_index = cur_agc_index;
2568 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2571 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2572 e1000_igp_2_cable_length_table[max_agc_index]);
2573 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2575 /* Calculate cable length with the error range of +/- 10 meters. */
2576 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2577 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2578 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2580 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2582 return E1000_SUCCESS;
2586 * e1000_get_phy_info_m88 - Retrieve PHY information
2587 * @hw: pointer to the HW structure
2589 * Valid for only copper links. Read the PHY status register (sticky read)
2590 * to verify that link is up. Read the PHY special control register to
2591 * determine the polarity and 10base-T extended distance. Read the PHY
2592 * special status register to determine MDI/MDIx and current speed. If
2593 * speed is 1000, then determine cable length, local and remote receiver.
2595 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2597 struct e1000_phy_info *phy = &hw->phy;
2602 DEBUGFUNC("e1000_get_phy_info_m88");
2604 if (phy->media_type != e1000_media_type_copper) {
2605 DEBUGOUT("Phy info is only valid for copper media\n");
2606 return -E1000_ERR_CONFIG;
2609 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2614 DEBUGOUT("Phy info is only valid if link is up\n");
2615 return -E1000_ERR_CONFIG;
2618 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2622 phy->polarity_correction = !!(phy_data &
2623 M88E1000_PSCR_POLARITY_REVERSAL);
2625 ret_val = e1000_check_polarity_m88(hw);
2629 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2633 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2635 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2636 ret_val = hw->phy.ops.get_cable_length(hw);
2640 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2644 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2645 ? e1000_1000t_rx_status_ok
2646 : e1000_1000t_rx_status_not_ok;
2648 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2649 ? e1000_1000t_rx_status_ok
2650 : e1000_1000t_rx_status_not_ok;
2652 /* Set values to "undefined" */
2653 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2654 phy->local_rx = e1000_1000t_rx_status_undefined;
2655 phy->remote_rx = e1000_1000t_rx_status_undefined;
2662 * e1000_get_phy_info_igp - Retrieve igp PHY information
2663 * @hw: pointer to the HW structure
2665 * Read PHY status to determine if link is up. If link is up, then
2666 * set/determine 10base-T extended distance and polarity correction. Read
2667 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2668 * determine on the cable length, local and remote receiver.
2670 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2672 struct e1000_phy_info *phy = &hw->phy;
2677 DEBUGFUNC("e1000_get_phy_info_igp");
2679 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2684 DEBUGOUT("Phy info is only valid if link is up\n");
2685 return -E1000_ERR_CONFIG;
2688 phy->polarity_correction = true;
2690 ret_val = e1000_check_polarity_igp(hw);
2694 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2698 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2700 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2701 IGP01E1000_PSSR_SPEED_1000MBPS) {
2702 ret_val = phy->ops.get_cable_length(hw);
2706 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2710 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2711 ? e1000_1000t_rx_status_ok
2712 : e1000_1000t_rx_status_not_ok;
2714 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2715 ? e1000_1000t_rx_status_ok
2716 : e1000_1000t_rx_status_not_ok;
2718 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2719 phy->local_rx = e1000_1000t_rx_status_undefined;
2720 phy->remote_rx = e1000_1000t_rx_status_undefined;
2727 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2728 * @hw: pointer to the HW structure
2730 * Populates "phy" structure with various feature states.
2732 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2734 struct e1000_phy_info *phy = &hw->phy;
2739 DEBUGFUNC("e1000_get_phy_info_ife");
2741 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2746 DEBUGOUT("Phy info is only valid if link is up\n");
2747 return -E1000_ERR_CONFIG;
2750 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2753 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2755 if (phy->polarity_correction) {
2756 ret_val = e1000_check_polarity_ife(hw);
2760 /* Polarity is forced */
2761 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2762 ? e1000_rev_polarity_reversed
2763 : e1000_rev_polarity_normal);
2766 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2770 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2772 /* The following parameters are undefined for 10/100 operation. */
2773 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2774 phy->local_rx = e1000_1000t_rx_status_undefined;
2775 phy->remote_rx = e1000_1000t_rx_status_undefined;
2777 return E1000_SUCCESS;
2781 * e1000_phy_sw_reset_generic - PHY software reset
2782 * @hw: pointer to the HW structure
2784 * Does a software reset of the PHY by reading the PHY control register and
2785 * setting/write the control register reset bit to the PHY.
2787 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2792 DEBUGFUNC("e1000_phy_sw_reset_generic");
2794 if (!hw->phy.ops.read_reg)
2795 return E1000_SUCCESS;
2797 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2801 phy_ctrl |= MII_CR_RESET;
2802 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2812 * e1000_phy_hw_reset_generic - PHY hardware reset
2813 * @hw: pointer to the HW structure
2815 * Verify the reset block is not blocking us from resetting. Acquire
2816 * semaphore (if necessary) and read/set/write the device control reset
2817 * bit in the PHY. Wait the appropriate delay time for the device to
2818 * reset and release the semaphore (if necessary).
2820 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2822 struct e1000_phy_info *phy = &hw->phy;
2826 DEBUGFUNC("e1000_phy_hw_reset_generic");
2828 if (phy->ops.check_reset_block) {
2829 ret_val = phy->ops.check_reset_block(hw);
2831 return E1000_SUCCESS;
2834 ret_val = phy->ops.acquire(hw);
2838 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2839 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2840 E1000_WRITE_FLUSH(hw);
2842 usec_delay(phy->reset_delay_us);
2844 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2845 E1000_WRITE_FLUSH(hw);
2849 phy->ops.release(hw);
2851 return phy->ops.get_cfg_done(hw);
2855 * e1000_get_cfg_done_generic - Generic configuration done
2856 * @hw: pointer to the HW structure
2858 * Generic function to wait 10 milli-seconds for configuration to complete
2859 * and return success.
2861 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2863 DEBUGFUNC("e1000_get_cfg_done_generic");
2864 UNREFERENCED_1PARAMETER(hw);
2868 return E1000_SUCCESS;
2872 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2873 * @hw: pointer to the HW structure
2875 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2877 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2879 DEBUGOUT("Running IGP 3 PHY init script\n");
2881 /* PHY init IGP 3 */
2882 /* Enable rise/fall, 10-mode work in class-A */
2883 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2884 /* Remove all caps from Replica path filter */
2885 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2886 /* Bias trimming for ADC, AFE and Driver (Default) */
2887 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2888 /* Increase Hybrid poly bias */
2889 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2890 /* Add 4% to Tx amplitude in Gig mode */
2891 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2892 /* Disable trimming (TTT) */
2893 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2894 /* Poly DC correction to 94.6% + 2% for all channels */
2895 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2896 /* ABS DC correction to 95.9% */
2897 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2898 /* BG temp curve trim */
2899 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2900 /* Increasing ADC OPAMP stage 1 currents to max */
2901 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2902 /* Force 1000 ( required for enabling PHY regs configuration) */
2903 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2904 /* Set upd_freq to 6 */
2905 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2907 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2908 /* Disable adaptive fixed FFE (Default) */
2909 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2910 /* Enable FFE hysteresis */
2911 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2912 /* Fixed FFE for short cable lengths */
2913 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2914 /* Fixed FFE for medium cable lengths */
2915 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2916 /* Fixed FFE for long cable lengths */
2917 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2918 /* Enable Adaptive Clip Threshold */
2919 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2920 /* AHT reset limit to 1 */
2921 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2922 /* Set AHT master delay to 127 msec */
2923 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2924 /* Set scan bits for AHT */
2925 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2926 /* Set AHT Preset bits */
2927 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2928 /* Change integ_factor of channel A to 3 */
2929 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2930 /* Change prop_factor of channels BCD to 8 */
2931 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2932 /* Change cg_icount + enable integbp for channels BCD */
2933 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2934 /* Change cg_icount + enable integbp + change prop_factor_master
2935 * to 8 for channel A
2937 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2938 /* Disable AHT in Slave mode on channel A */
2939 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2940 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2943 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2944 /* Enable restart AN on an1000_dis change */
2945 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2946 /* Enable wh_fifo read clock in 10/100 modes */
2947 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2948 /* Restart AN, Speed selection is 1000 */
2949 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2951 return E1000_SUCCESS;
2955 * e1000_get_phy_type_from_id - Get PHY type from id
2956 * @phy_id: phy_id read from the phy
2958 * Returns the phy type from the id.
2960 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2962 enum e1000_phy_type phy_type = e1000_phy_unknown;
2965 case M88E1000_I_PHY_ID:
2966 case M88E1000_E_PHY_ID:
2967 case M88E1111_I_PHY_ID:
2968 case M88E1011_I_PHY_ID:
2969 case I347AT4_E_PHY_ID:
2970 case M88E1112_E_PHY_ID:
2971 case M88E1340M_E_PHY_ID:
2972 phy_type = e1000_phy_m88;
2974 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2975 phy_type = e1000_phy_igp_2;
2977 case GG82563_E_PHY_ID:
2978 phy_type = e1000_phy_gg82563;
2980 case IGP03E1000_E_PHY_ID:
2981 phy_type = e1000_phy_igp_3;
2984 case IFE_PLUS_E_PHY_ID:
2985 case IFE_C_E_PHY_ID:
2986 phy_type = e1000_phy_ife;
2988 case BME1000_E_PHY_ID:
2989 case BME1000_E_PHY_ID_R2:
2990 phy_type = e1000_phy_bm;
2992 case I82578_E_PHY_ID:
2993 phy_type = e1000_phy_82578;
2995 case I82577_E_PHY_ID:
2996 phy_type = e1000_phy_82577;
2998 case I82579_E_PHY_ID:
2999 phy_type = e1000_phy_82579;
3002 phy_type = e1000_phy_i217;
3004 case I82580_I_PHY_ID:
3005 phy_type = e1000_phy_82580;
3008 phy_type = e1000_phy_i210;
3011 phy_type = e1000_phy_unknown;
3018 * e1000_determine_phy_address - Determines PHY address.
3019 * @hw: pointer to the HW structure
3021 * This uses a trial and error method to loop through possible PHY
3022 * addresses. It tests each by reading the PHY ID registers and
3023 * checking for a match.
3025 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3029 enum e1000_phy_type phy_type = e1000_phy_unknown;
3031 hw->phy.id = phy_type;
3033 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3034 hw->phy.addr = phy_addr;
3038 e1000_get_phy_id(hw);
3039 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3041 /* If phy_type is valid, break - we found our
3044 if (phy_type != e1000_phy_unknown)
3045 return E1000_SUCCESS;
3052 return -E1000_ERR_PHY_TYPE;
3056 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3057 * @page: page to access
3059 * Returns the phy address for the page requested.
3061 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3065 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3072 * e1000_write_phy_reg_bm - Write BM PHY register
3073 * @hw: pointer to the HW structure
3074 * @offset: register offset to write to
3075 * @data: data to write at register offset
3077 * Acquires semaphore, if necessary, then writes the data to PHY register
3078 * at the offset. Release any acquired semaphores before exiting.
3080 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3083 u32 page = offset >> IGP_PAGE_SHIFT;
3085 DEBUGFUNC("e1000_write_phy_reg_bm");
3087 ret_val = hw->phy.ops.acquire(hw);
3091 /* Page 800 works differently than the rest so it has its own func */
3092 if (page == BM_WUC_PAGE) {
3093 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3098 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3100 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3101 u32 page_shift, page_select;
3103 /* Page select is register 31 for phy address 1 and 22 for
3104 * phy address 2 and 3. Page select is shifted only for
3107 if (hw->phy.addr == 1) {
3108 page_shift = IGP_PAGE_SHIFT;
3109 page_select = IGP01E1000_PHY_PAGE_SELECT;
3112 page_select = BM_PHY_PAGE_SELECT;
3115 /* Page is shifted left, PHY expects (page x 32) */
3116 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3117 (page << page_shift));
3122 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3126 hw->phy.ops.release(hw);
3131 * e1000_read_phy_reg_bm - Read BM PHY register
3132 * @hw: pointer to the HW structure
3133 * @offset: register offset to be read
3134 * @data: pointer to the read data
3136 * Acquires semaphore, if necessary, then reads the PHY register at offset
3137 * and storing the retrieved information in data. Release any acquired
3138 * semaphores before exiting.
3140 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3143 u32 page = offset >> IGP_PAGE_SHIFT;
3145 DEBUGFUNC("e1000_read_phy_reg_bm");
3147 ret_val = hw->phy.ops.acquire(hw);
3151 /* Page 800 works differently than the rest so it has its own func */
3152 if (page == BM_WUC_PAGE) {
3153 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3158 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3160 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3161 u32 page_shift, page_select;
3163 /* Page select is register 31 for phy address 1 and 22 for
3164 * phy address 2 and 3. Page select is shifted only for
3167 if (hw->phy.addr == 1) {
3168 page_shift = IGP_PAGE_SHIFT;
3169 page_select = IGP01E1000_PHY_PAGE_SELECT;
3172 page_select = BM_PHY_PAGE_SELECT;
3175 /* Page is shifted left, PHY expects (page x 32) */
3176 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3177 (page << page_shift));
3182 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3185 hw->phy.ops.release(hw);
3190 * e1000_read_phy_reg_bm2 - Read BM PHY register
3191 * @hw: pointer to the HW structure
3192 * @offset: register offset to be read
3193 * @data: pointer to the read data
3195 * Acquires semaphore, if necessary, then reads the PHY register at offset
3196 * and storing the retrieved information in data. Release any acquired
3197 * semaphores before exiting.
3199 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3202 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3204 DEBUGFUNC("e1000_read_phy_reg_bm2");
3206 ret_val = hw->phy.ops.acquire(hw);
3210 /* Page 800 works differently than the rest so it has its own func */
3211 if (page == BM_WUC_PAGE) {
3212 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3219 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3220 /* Page is shifted left, PHY expects (page x 32) */
3221 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3228 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3231 hw->phy.ops.release(hw);
3236 * e1000_write_phy_reg_bm2 - Write BM PHY register
3237 * @hw: pointer to the HW structure
3238 * @offset: register offset to write to
3239 * @data: data to write at register offset
3241 * Acquires semaphore, if necessary, then writes the data to PHY register
3242 * at the offset. Release any acquired semaphores before exiting.
3244 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3247 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3249 DEBUGFUNC("e1000_write_phy_reg_bm2");
3251 ret_val = hw->phy.ops.acquire(hw);
3255 /* Page 800 works differently than the rest so it has its own func */
3256 if (page == BM_WUC_PAGE) {
3257 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3264 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3265 /* Page is shifted left, PHY expects (page x 32) */
3266 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3273 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3277 hw->phy.ops.release(hw);
3282 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3283 * @hw: pointer to the HW structure
3284 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3286 * Assumes semaphore already acquired and phy_reg points to a valid memory
3287 * address to store contents of the BM_WUC_ENABLE_REG register.
3289 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3294 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3297 return -E1000_ERR_PARAM;
3299 /* All page select, port ctrl and wakeup registers use phy address 1 */
3302 /* Select Port Control Registers page */
3303 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3305 DEBUGOUT("Could not set Port Control page\n");
3309 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3311 DEBUGOUT2("Could not read PHY register %d.%d\n",
3312 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3316 /* Enable both PHY wakeup mode and Wakeup register page writes.
3317 * Prevent a power state change by disabling ME and Host PHY wakeup.
3320 temp |= BM_WUC_ENABLE_BIT;
3321 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3323 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3325 DEBUGOUT2("Could not write PHY register %d.%d\n",
3326 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3330 /* Select Host Wakeup Registers page - caller now able to write
3331 * registers on the Wakeup registers page
3333 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3337 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3338 * @hw: pointer to the HW structure
3339 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3341 * Restore BM_WUC_ENABLE_REG to its original value.
3343 * Assumes semaphore already acquired and *phy_reg is the contents of the
3344 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3347 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3351 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3354 return -E1000_ERR_PARAM;
3356 /* Select Port Control Registers page */
3357 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3359 DEBUGOUT("Could not set Port Control page\n");
3363 /* Restore 769.17 to its original value */
3364 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3366 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3367 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3373 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3374 * @hw: pointer to the HW structure
3375 * @offset: register offset to be read or written
3376 * @data: pointer to the data to read or write
3377 * @read: determines if operation is read or write
3378 * @page_set: BM_WUC_PAGE already set and access enabled
3380 * Read the PHY register at offset and store the retrieved information in
3381 * data, or write data to PHY register at offset. Note the procedure to
3382 * access the PHY wakeup registers is different than reading the other PHY
3383 * registers. It works as such:
3384 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3385 * 2) Set page to 800 for host (801 if we were manageability)
3386 * 3) Write the address using the address opcode (0x11)
3387 * 4) Read or write the data using the data opcode (0x12)
3388 * 5) Restore 769.17.2 to its original value
3390 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3391 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3393 * Assumes semaphore is already acquired. When page_set==true, assumes
3394 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3395 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3397 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3398 u16 *data, bool read, bool page_set)
3401 u16 reg = BM_PHY_REG_NUM(offset);
3402 u16 page = BM_PHY_REG_PAGE(offset);
3405 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3407 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3408 if ((hw->mac.type == e1000_pchlan) &&
3409 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3410 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3414 /* Enable access to PHY wakeup registers */
3415 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3417 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3422 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3424 /* Write the Wakeup register page offset value using opcode 0x11 */
3425 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3427 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3432 /* Read the Wakeup register page value using opcode 0x12 */
3433 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3436 /* Write the Wakeup register page value using opcode 0x12 */
3437 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3442 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3447 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3453 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3454 * @hw: pointer to the HW structure
3456 * In the case of a PHY power down to save power, or to turn off link during a
3457 * driver unload, or wake on lan is not enabled, restore the link to previous
3460 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3465 /* The PHY will retain its settings across a power down/up cycle */
3466 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3467 mii_reg &= ~MII_CR_POWER_DOWN;
3468 if (hw->phy.type == e1000_phy_i210) {
3469 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3470 power_reg &= ~GS40G_CS_POWER_DOWN;
3471 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3473 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3477 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3478 * @hw: pointer to the HW structure
3480 * In the case of a PHY power down to save power, or to turn off link during a
3481 * driver unload, or wake on lan is not enabled, restore the link to previous
3484 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3489 /* The PHY will retain its settings across a power down/up cycle */
3490 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3491 mii_reg |= MII_CR_POWER_DOWN;
3492 /* i210 Phy requires an additional bit for power up/down */
3493 if (hw->phy.type == e1000_phy_i210) {
3494 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3495 power_reg |= GS40G_CS_POWER_DOWN;
3496 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3498 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3503 * __e1000_read_phy_reg_hv - Read HV PHY register
3504 * @hw: pointer to the HW structure
3505 * @offset: register offset to be read
3506 * @data: pointer to the read data
3507 * @locked: semaphore has already been acquired or not
3509 * Acquires semaphore, if necessary, then reads the PHY register at offset
3510 * and stores the retrieved information in data. Release any acquired
3511 * semaphore before exiting.
3513 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3514 bool locked, bool page_set)
3517 u16 page = BM_PHY_REG_PAGE(offset);
3518 u16 reg = BM_PHY_REG_NUM(offset);
3519 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3521 DEBUGFUNC("__e1000_read_phy_reg_hv");
3524 ret_val = hw->phy.ops.acquire(hw);
3529 /* Page 800 works differently than the rest so it has its own func */
3530 if (page == BM_WUC_PAGE) {
3531 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3536 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3537 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3543 if (page == HV_INTC_FC_PAGE_START)
3546 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3547 /* Page is shifted left, PHY expects (page x 32) */
3548 ret_val = e1000_set_page_igp(hw,
3549 (page << IGP_PAGE_SHIFT));
3551 hw->phy.addr = phy_addr;
3558 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3559 page << IGP_PAGE_SHIFT, reg);
3561 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3565 hw->phy.ops.release(hw);
3571 * e1000_read_phy_reg_hv - Read HV PHY register
3572 * @hw: pointer to the HW structure
3573 * @offset: register offset to be read
3574 * @data: pointer to the read data
3576 * Acquires semaphore then reads the PHY register at offset and stores
3577 * the retrieved information in data. Release the acquired semaphore
3580 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3582 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3586 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3587 * @hw: pointer to the HW structure
3588 * @offset: register offset to be read
3589 * @data: pointer to the read data
3591 * Reads the PHY register at offset and stores the retrieved information
3592 * in data. Assumes semaphore already acquired.
3594 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3596 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3600 * e1000_read_phy_reg_page_hv - Read HV PHY register
3601 * @hw: pointer to the HW structure
3602 * @offset: register offset to write to
3603 * @data: data to write at register offset
3605 * Reads the PHY register at offset and stores the retrieved information
3606 * in data. Assumes semaphore already acquired and page already set.
3608 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3610 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3614 * __e1000_write_phy_reg_hv - Write HV PHY register
3615 * @hw: pointer to the HW structure
3616 * @offset: register offset to write to
3617 * @data: data to write at register offset
3618 * @locked: semaphore has already been acquired or not
3620 * Acquires semaphore, if necessary, then writes the data to PHY register
3621 * at the offset. Release any acquired semaphores before exiting.
3623 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3624 bool locked, bool page_set)
3627 u16 page = BM_PHY_REG_PAGE(offset);
3628 u16 reg = BM_PHY_REG_NUM(offset);
3629 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3631 DEBUGFUNC("__e1000_write_phy_reg_hv");
3634 ret_val = hw->phy.ops.acquire(hw);
3639 /* Page 800 works differently than the rest so it has its own func */
3640 if (page == BM_WUC_PAGE) {
3641 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3646 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3647 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3653 if (page == HV_INTC_FC_PAGE_START)
3656 /* Workaround MDIO accesses being disabled after entering IEEE
3657 * Power Down (when bit 11 of the PHY Control register is set)
3659 if ((hw->phy.type == e1000_phy_82578) &&
3660 (hw->phy.revision >= 1) &&
3661 (hw->phy.addr == 2) &&
3662 !(MAX_PHY_REG_ADDRESS & reg) &&
3663 (data & (1 << 11))) {
3665 ret_val = e1000_access_phy_debug_regs_hv(hw,
3672 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3673 /* Page is shifted left, PHY expects (page x 32) */
3674 ret_val = e1000_set_page_igp(hw,
3675 (page << IGP_PAGE_SHIFT));
3677 hw->phy.addr = phy_addr;
3684 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3685 page << IGP_PAGE_SHIFT, reg);
3687 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3692 hw->phy.ops.release(hw);
3698 * e1000_write_phy_reg_hv - Write HV PHY register
3699 * @hw: pointer to the HW structure
3700 * @offset: register offset to write to
3701 * @data: data to write at register offset
3703 * Acquires semaphore then writes the data to PHY register at the offset.
3704 * Release the acquired semaphores before exiting.
3706 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3708 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3712 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3713 * @hw: pointer to the HW structure
3714 * @offset: register offset to write to
3715 * @data: data to write at register offset
3717 * Writes the data to PHY register at the offset. Assumes semaphore
3720 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3722 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3726 * e1000_write_phy_reg_page_hv - Write HV PHY register
3727 * @hw: pointer to the HW structure
3728 * @offset: register offset to write to
3729 * @data: data to write at register offset
3731 * Writes the data to PHY register at the offset. Assumes semaphore
3732 * already acquired and page already set.
3734 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3736 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3740 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3741 * @page: page to be accessed
3743 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page)
3747 if (page >= HV_INTC_FC_PAGE_START)
3754 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3755 * @hw: pointer to the HW structure
3756 * @offset: register offset to be read or written
3757 * @data: pointer to the data to be read or written
3758 * @read: determines if operation is read or write
3760 * Reads the PHY register at offset and stores the retreived information
3761 * in data. Assumes semaphore already acquired. Note that the procedure
3762 * to access these regs uses the address port and data port to read/write.
3763 * These accesses done with PHY address 2 and without using pages.
3765 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3766 u16 *data, bool read)
3772 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3774 /* This takes care of the difference with desktop vs mobile phy */
3775 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3776 I82578_ADDR_REG : I82577_ADDR_REG);
3777 data_reg = addr_reg + 1;
3779 /* All operations in this function are phy address 2 */
3782 /* masking with 0x3F to remove the page from offset */
3783 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3785 DEBUGOUT("Could not write the Address Offset port register\n");
3789 /* Read or write the data value next */
3791 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3793 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3796 DEBUGOUT("Could not access the Data port register\n");
3802 * e1000_link_stall_workaround_hv - Si workaround
3803 * @hw: pointer to the HW structure
3805 * This function works around a Si bug where the link partner can get
3806 * a link up indication before the PHY does. If small packets are sent
3807 * by the link partner they can be placed in the packet buffer without
3808 * being properly accounted for by the PHY and will stall preventing
3809 * further packets from being received. The workaround is to clear the
3810 * packet buffer after the PHY detects link up.
3812 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3814 s32 ret_val = E1000_SUCCESS;
3817 DEBUGFUNC("e1000_link_stall_workaround_hv");
3819 if (hw->phy.type != e1000_phy_82578)
3820 return E1000_SUCCESS;
3822 /* Do not apply workaround if in PHY loopback bit 14 set */
3823 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3824 if (data & PHY_CONTROL_LB)
3825 return E1000_SUCCESS;
3827 /* check if link is up and at 1Gbps */
3828 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3832 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3833 BM_CS_STATUS_SPEED_MASK);
3835 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3836 BM_CS_STATUS_SPEED_1000))
3837 return E1000_SUCCESS;
3841 /* flush the packets in the fifo buffer */
3842 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3843 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3844 HV_MUX_DATA_CTRL_FORCE_SPEED));
3848 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3849 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3853 * e1000_check_polarity_82577 - Checks the polarity.
3854 * @hw: pointer to the HW structure
3856 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3858 * Polarity is determined based on the PHY specific status register.
3860 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3862 struct e1000_phy_info *phy = &hw->phy;
3866 DEBUGFUNC("e1000_check_polarity_82577");
3868 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3871 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3872 ? e1000_rev_polarity_reversed
3873 : e1000_rev_polarity_normal);
3879 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3880 * @hw: pointer to the HW structure
3882 * Calls the PHY setup function to force speed and duplex.
3884 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3886 struct e1000_phy_info *phy = &hw->phy;
3891 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3893 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3897 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3899 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3905 if (phy->autoneg_wait_to_complete) {
3906 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3908 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3914 DEBUGOUT("Link taking longer than expected.\n");
3917 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3925 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3926 * @hw: pointer to the HW structure
3928 * Read PHY status to determine if link is up. If link is up, then
3929 * set/determine 10base-T extended distance and polarity correction. Read
3930 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3931 * determine on the cable length, local and remote receiver.
3933 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3935 struct e1000_phy_info *phy = &hw->phy;
3940 DEBUGFUNC("e1000_get_phy_info_82577");
3942 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3947 DEBUGOUT("Phy info is only valid if link is up\n");
3948 return -E1000_ERR_CONFIG;
3951 phy->polarity_correction = true;
3953 ret_val = e1000_check_polarity_82577(hw);
3957 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3961 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3963 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3964 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3965 ret_val = hw->phy.ops.get_cable_length(hw);
3969 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3973 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3974 ? e1000_1000t_rx_status_ok
3975 : e1000_1000t_rx_status_not_ok;
3977 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3978 ? e1000_1000t_rx_status_ok
3979 : e1000_1000t_rx_status_not_ok;
3981 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3982 phy->local_rx = e1000_1000t_rx_status_undefined;
3983 phy->remote_rx = e1000_1000t_rx_status_undefined;
3986 return E1000_SUCCESS;
3990 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3991 * @hw: pointer to the HW structure
3993 * Reads the diagnostic status register and verifies result is valid before
3994 * placing it in the phy_cable_length field.
3996 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3998 struct e1000_phy_info *phy = &hw->phy;
4000 u16 phy_data, length;
4002 DEBUGFUNC("e1000_get_cable_length_82577");
4004 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4008 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4009 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4011 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4012 ret_val = -E1000_ERR_PHY;
4014 phy->cable_length = length;
4016 return E1000_SUCCESS;
4020 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4021 * @hw: pointer to the HW structure
4022 * @offset: register offset to write to
4023 * @data: data to write at register offset
4025 * Acquires semaphore, if necessary, then writes the data to PHY register
4026 * at the offset. Release any acquired semaphores before exiting.
4028 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4031 u16 page = offset >> GS40G_PAGE_SHIFT;
4033 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4035 offset = offset & GS40G_OFFSET_MASK;
4036 ret_val = hw->phy.ops.acquire(hw);
4040 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4043 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4046 hw->phy.ops.release(hw);
4051 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4052 * @hw: pointer to the HW structure
4053 * @offset: lower half is register offset to read to
4054 * upper half is page to use.
4055 * @data: data to read at register offset
4057 * Acquires semaphore, if necessary, then reads the data in the PHY register
4058 * at the offset. Release any acquired semaphores before exiting.
4060 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4063 u16 page = offset >> GS40G_PAGE_SHIFT;
4065 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4067 offset = offset & GS40G_OFFSET_MASK;
4068 ret_val = hw->phy.ops.acquire(hw);
4072 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4075 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4078 hw->phy.ops.release(hw);