1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "e1000_api.h"
36 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
37 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
38 u16 *data, bool read, bool page_set);
39 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
40 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
41 u16 *data, bool read);
43 /* Cable length tables */
44 static const u16 e1000_m88_cable_length_table[] = {
45 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
46 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47 (sizeof(e1000_m88_cable_length_table) / \
48 sizeof(e1000_m88_cable_length_table[0]))
50 static const u16 e1000_igp_2_cable_length_table[] = {
51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 (sizeof(e1000_igp_2_cable_length_table) / \
61 sizeof(e1000_igp_2_cable_length_table[0]))
64 * e1000_init_phy_ops_generic - Initialize PHY function pointers
65 * @hw: pointer to the HW structure
67 * Setups up the function pointers to no-op functions
69 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
71 struct e1000_phy_info *phy = &hw->phy;
72 DEBUGFUNC("e1000_init_phy_ops_generic");
74 /* Initialize function pointers */
75 phy->ops.init_params = e1000_null_ops_generic;
76 phy->ops.acquire = e1000_null_ops_generic;
77 phy->ops.check_polarity = e1000_null_ops_generic;
78 phy->ops.check_reset_block = e1000_null_ops_generic;
79 phy->ops.commit = e1000_null_ops_generic;
80 phy->ops.force_speed_duplex = e1000_null_ops_generic;
81 phy->ops.get_cfg_done = e1000_null_ops_generic;
82 phy->ops.get_cable_length = e1000_null_ops_generic;
83 phy->ops.get_info = e1000_null_ops_generic;
84 phy->ops.set_page = e1000_null_set_page;
85 phy->ops.read_reg = e1000_null_read_reg;
86 phy->ops.read_reg_locked = e1000_null_read_reg;
87 phy->ops.read_reg_page = e1000_null_read_reg;
88 phy->ops.release = e1000_null_phy_generic;
89 phy->ops.reset = e1000_null_ops_generic;
90 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
91 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
92 phy->ops.write_reg = e1000_null_write_reg;
93 phy->ops.write_reg_locked = e1000_null_write_reg;
94 phy->ops.write_reg_page = e1000_null_write_reg;
95 phy->ops.power_up = e1000_null_phy_generic;
96 phy->ops.power_down = e1000_null_phy_generic;
97 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
98 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
99 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
103 * e1000_null_set_page - No-op function, return 0
104 * @hw: pointer to the HW structure
106 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
108 DEBUGFUNC("e1000_null_set_page");
109 return E1000_SUCCESS;
113 * e1000_null_read_reg - No-op function, return 0
114 * @hw: pointer to the HW structure
116 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
118 DEBUGFUNC("e1000_null_read_reg");
119 return E1000_SUCCESS;
123 * e1000_null_phy_generic - No-op function, return void
124 * @hw: pointer to the HW structure
126 void e1000_null_phy_generic(struct e1000_hw *hw)
128 DEBUGFUNC("e1000_null_phy_generic");
133 * e1000_null_lplu_state - No-op function, return 0
134 * @hw: pointer to the HW structure
136 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
138 DEBUGFUNC("e1000_null_lplu_state");
139 return E1000_SUCCESS;
143 * e1000_null_write_reg - No-op function, return 0
144 * @hw: pointer to the HW structure
146 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
148 DEBUGFUNC("e1000_null_write_reg");
149 return E1000_SUCCESS;
153 * e1000_read_i2c_byte_null - No-op function, return 0
154 * @hw: pointer to hardware structure
155 * @byte_offset: byte offset to write
156 * @dev_addr: device address
157 * @data: data value read
160 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
161 u8 dev_addr, u8 *data)
163 DEBUGFUNC("e1000_read_i2c_byte_null");
164 return E1000_SUCCESS;
168 * e1000_write_i2c_byte_null - No-op function, return 0
169 * @hw: pointer to hardware structure
170 * @byte_offset: byte offset to write
171 * @dev_addr: device address
172 * @data: data value to write
175 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
176 u8 dev_addr, u8 data)
178 DEBUGFUNC("e1000_write_i2c_byte_null");
179 return E1000_SUCCESS;
183 * e1000_check_reset_block_generic - Check if PHY reset is blocked
184 * @hw: pointer to the HW structure
186 * Read the PHY management control register and check whether a PHY reset
187 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
188 * return E1000_BLK_PHY_RESET (12).
190 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
194 DEBUGFUNC("e1000_check_reset_block");
196 manc = E1000_READ_REG(hw, E1000_MANC);
198 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
199 E1000_BLK_PHY_RESET : E1000_SUCCESS;
203 * e1000_get_phy_id - Retrieve the PHY ID and revision
204 * @hw: pointer to the HW structure
206 * Reads the PHY registers and stores the PHY ID and possibly the PHY
207 * revision in the hardware structure.
209 s32 e1000_get_phy_id(struct e1000_hw *hw)
211 struct e1000_phy_info *phy = &hw->phy;
212 s32 ret_val = E1000_SUCCESS;
216 DEBUGFUNC("e1000_get_phy_id");
218 if (!phy->ops.read_reg)
219 return E1000_SUCCESS;
221 while (retry_count < 2) {
222 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
226 phy->id = (u32)(phy_id << 16);
228 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
232 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
233 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
235 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
236 return E1000_SUCCESS;
241 return E1000_SUCCESS;
245 * e1000_phy_reset_dsp_generic - Reset PHY DSP
246 * @hw: pointer to the HW structure
248 * Reset the digital signal processor.
250 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
254 DEBUGFUNC("e1000_phy_reset_dsp_generic");
256 if (!hw->phy.ops.write_reg)
257 return E1000_SUCCESS;
259 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
263 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
267 * e1000_read_phy_reg_mdic - Read MDI control register
268 * @hw: pointer to the HW structure
269 * @offset: register offset to be read
270 * @data: pointer to the read data
272 * Reads the MDI control register in the PHY at offset and stores the
273 * information read to data.
275 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
277 struct e1000_phy_info *phy = &hw->phy;
280 DEBUGFUNC("e1000_read_phy_reg_mdic");
282 if (offset > MAX_PHY_REG_ADDRESS) {
283 DEBUGOUT1("PHY Address %d is out of range\n", offset);
284 return -E1000_ERR_PARAM;
288 * Set up Op-code, Phy Address, and register offset in the MDI
289 * Control register. The MAC will take care of interfacing with the
290 * PHY to retrieve the desired data.
292 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
293 (phy->addr << E1000_MDIC_PHY_SHIFT) |
294 (E1000_MDIC_OP_READ));
296 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
299 * Poll the ready bit to see if the MDI read completed
300 * Increasing the time out as testing showed failures with
303 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
305 mdic = E1000_READ_REG(hw, E1000_MDIC);
306 if (mdic & E1000_MDIC_READY)
309 if (!(mdic & E1000_MDIC_READY)) {
310 DEBUGOUT("MDI Read did not complete\n");
311 return -E1000_ERR_PHY;
313 if (mdic & E1000_MDIC_ERROR) {
314 DEBUGOUT("MDI Error\n");
315 return -E1000_ERR_PHY;
320 * Allow some time after each MDIC transaction to avoid
321 * reading duplicate data in the next MDIC transaction.
323 if (hw->mac.type == e1000_pch2lan)
326 return E1000_SUCCESS;
330 * e1000_write_phy_reg_mdic - Write MDI control register
331 * @hw: pointer to the HW structure
332 * @offset: register offset to write to
333 * @data: data to write to register at offset
335 * Writes data to MDI control register in the PHY at offset.
337 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
339 struct e1000_phy_info *phy = &hw->phy;
342 DEBUGFUNC("e1000_write_phy_reg_mdic");
344 if (offset > MAX_PHY_REG_ADDRESS) {
345 DEBUGOUT1("PHY Address %d is out of range\n", offset);
346 return -E1000_ERR_PARAM;
350 * Set up Op-code, Phy Address, and register offset in the MDI
351 * Control register. The MAC will take care of interfacing with the
352 * PHY to retrieve the desired data.
354 mdic = (((u32)data) |
355 (offset << E1000_MDIC_REG_SHIFT) |
356 (phy->addr << E1000_MDIC_PHY_SHIFT) |
357 (E1000_MDIC_OP_WRITE));
359 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
362 * Poll the ready bit to see if the MDI read completed
363 * Increasing the time out as testing showed failures with
366 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
368 mdic = E1000_READ_REG(hw, E1000_MDIC);
369 if (mdic & E1000_MDIC_READY)
372 if (!(mdic & E1000_MDIC_READY)) {
373 DEBUGOUT("MDI Write did not complete\n");
374 return -E1000_ERR_PHY;
376 if (mdic & E1000_MDIC_ERROR) {
377 DEBUGOUT("MDI Error\n");
378 return -E1000_ERR_PHY;
382 * Allow some time after each MDIC transaction to avoid
383 * reading duplicate data in the next MDIC transaction.
385 if (hw->mac.type == e1000_pch2lan)
388 return E1000_SUCCESS;
392 * e1000_read_phy_reg_i2c - Read PHY register using i2c
393 * @hw: pointer to the HW structure
394 * @offset: register offset to be read
395 * @data: pointer to the read data
397 * Reads the PHY register at offset using the i2c interface and stores the
398 * retrieved information in data.
400 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
402 struct e1000_phy_info *phy = &hw->phy;
405 DEBUGFUNC("e1000_read_phy_reg_i2c");
408 * Set up Op-code, Phy Address, and register address in the I2CCMD
409 * register. The MAC will take care of interfacing with the
410 * PHY to retrieve the desired data.
412 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
413 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
414 (E1000_I2CCMD_OPCODE_READ));
416 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
418 /* Poll the ready bit to see if the I2C read completed */
419 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
421 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
422 if (i2ccmd & E1000_I2CCMD_READY)
425 if (!(i2ccmd & E1000_I2CCMD_READY)) {
426 DEBUGOUT("I2CCMD Read did not complete\n");
427 return -E1000_ERR_PHY;
429 if (i2ccmd & E1000_I2CCMD_ERROR) {
430 DEBUGOUT("I2CCMD Error bit set\n");
431 return -E1000_ERR_PHY;
434 /* Need to byte-swap the 16-bit value. */
435 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
437 return E1000_SUCCESS;
441 * e1000_write_phy_reg_i2c - Write PHY register using i2c
442 * @hw: pointer to the HW structure
443 * @offset: register offset to write to
444 * @data: data to write at register offset
446 * Writes the data to PHY register at the offset using the i2c interface.
448 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
450 struct e1000_phy_info *phy = &hw->phy;
452 u16 phy_data_swapped;
454 DEBUGFUNC("e1000_write_phy_reg_i2c");
456 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
457 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
458 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
460 return -E1000_ERR_CONFIG;
463 /* Swap the data bytes for the I2C interface */
464 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
467 * Set up Op-code, Phy Address, and register address in the I2CCMD
468 * register. The MAC will take care of interfacing with the
469 * PHY to retrieve the desired data.
471 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
472 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
473 E1000_I2CCMD_OPCODE_WRITE |
476 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
478 /* Poll the ready bit to see if the I2C read completed */
479 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
481 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
482 if (i2ccmd & E1000_I2CCMD_READY)
485 if (!(i2ccmd & E1000_I2CCMD_READY)) {
486 DEBUGOUT("I2CCMD Write did not complete\n");
487 return -E1000_ERR_PHY;
489 if (i2ccmd & E1000_I2CCMD_ERROR) {
490 DEBUGOUT("I2CCMD Error bit set\n");
491 return -E1000_ERR_PHY;
494 return E1000_SUCCESS;
498 * e1000_read_sfp_data_byte - Reads SFP module data.
499 * @hw: pointer to the HW structure
500 * @offset: byte location offset to be read
501 * @data: read data buffer pointer
503 * Reads one byte from SFP module data stored
504 * in SFP resided EEPROM memory or SFP diagnostic area.
505 * Function should be called with
506 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
507 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
510 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
516 DEBUGFUNC("e1000_read_sfp_data_byte");
518 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
519 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
520 return -E1000_ERR_PHY;
524 * Set up Op-code, EEPROM Address,in the I2CCMD
525 * register. The MAC will take care of interfacing with the
526 * EEPROM to retrieve the desired data.
528 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
529 E1000_I2CCMD_OPCODE_READ);
531 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
533 /* Poll the ready bit to see if the I2C read completed */
534 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
536 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
537 if (data_local & E1000_I2CCMD_READY)
540 if (!(data_local & E1000_I2CCMD_READY)) {
541 DEBUGOUT("I2CCMD Read did not complete\n");
542 return -E1000_ERR_PHY;
544 if (data_local & E1000_I2CCMD_ERROR) {
545 DEBUGOUT("I2CCMD Error bit set\n");
546 return -E1000_ERR_PHY;
548 *data = (u8) data_local & 0xFF;
550 return E1000_SUCCESS;
554 * e1000_write_sfp_data_byte - Writes SFP module data.
555 * @hw: pointer to the HW structure
556 * @offset: byte location offset to write to
557 * @data: data to write
559 * Writes one byte to SFP module data stored
560 * in SFP resided EEPROM memory or SFP diagnostic area.
561 * Function should be called with
562 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
563 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
566 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
572 DEBUGFUNC("e1000_write_sfp_data_byte");
574 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
575 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
576 return -E1000_ERR_PHY;
579 * The programming interface is 16 bits wide
580 * so we need to read the whole word first
581 * then update appropriate byte lane and write
582 * the updated word back.
585 * Set up Op-code, EEPROM Address,in the I2CCMD
586 * register. The MAC will take care of interfacing
587 * with an EEPROM to write the data given.
589 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
590 E1000_I2CCMD_OPCODE_READ);
591 /* Set a command to read single word */
592 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
593 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
596 * Poll the ready bit to see if lastly
597 * launched I2C operation completed
599 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
600 if (i2ccmd & E1000_I2CCMD_READY) {
601 /* Check if this is READ or WRITE phase */
602 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
603 E1000_I2CCMD_OPCODE_READ) {
605 * Write the selected byte
606 * lane and update whole word
608 data_local = i2ccmd & 0xFF00;
611 E1000_I2CCMD_REG_ADDR_SHIFT) |
612 E1000_I2CCMD_OPCODE_WRITE | data_local);
613 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
619 if (!(i2ccmd & E1000_I2CCMD_READY)) {
620 DEBUGOUT("I2CCMD Write did not complete\n");
621 return -E1000_ERR_PHY;
623 if (i2ccmd & E1000_I2CCMD_ERROR) {
624 DEBUGOUT("I2CCMD Error bit set\n");
625 return -E1000_ERR_PHY;
627 return E1000_SUCCESS;
631 * e1000_read_phy_reg_m88 - Read m88 PHY register
632 * @hw: pointer to the HW structure
633 * @offset: register offset to be read
634 * @data: pointer to the read data
636 * Acquires semaphore, if necessary, then reads the PHY register at offset
637 * and storing the retrieved information in data. Release any acquired
638 * semaphores before exiting.
640 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
644 DEBUGFUNC("e1000_read_phy_reg_m88");
646 if (!hw->phy.ops.acquire)
647 return E1000_SUCCESS;
649 ret_val = hw->phy.ops.acquire(hw);
653 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
656 hw->phy.ops.release(hw);
662 * e1000_write_phy_reg_m88 - Write m88 PHY register
663 * @hw: pointer to the HW structure
664 * @offset: register offset to write to
665 * @data: data to write at register offset
667 * Acquires semaphore, if necessary, then writes the data to PHY register
668 * at the offset. Release any acquired semaphores before exiting.
670 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
674 DEBUGFUNC("e1000_write_phy_reg_m88");
676 if (!hw->phy.ops.acquire)
677 return E1000_SUCCESS;
679 ret_val = hw->phy.ops.acquire(hw);
683 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
686 hw->phy.ops.release(hw);
692 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
693 * @hw: pointer to the HW structure
694 * @page: page to set (shifted left when necessary)
696 * Sets PHY page required for PHY register access. Assumes semaphore is
697 * already acquired. Note, this function sets phy.addr to 1 so the caller
698 * must set it appropriately (if necessary) after this function returns.
700 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
702 DEBUGFUNC("e1000_set_page_igp");
704 DEBUGOUT1("Setting page 0x%x\n", page);
708 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
712 * __e1000_read_phy_reg_igp - Read igp PHY register
713 * @hw: pointer to the HW structure
714 * @offset: register offset to be read
715 * @data: pointer to the read data
716 * @locked: semaphore has already been acquired or not
718 * Acquires semaphore, if necessary, then reads the PHY register at offset
719 * and stores the retrieved information in data. Release any acquired
720 * semaphores before exiting.
722 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
725 s32 ret_val = E1000_SUCCESS;
727 DEBUGFUNC("__e1000_read_phy_reg_igp");
730 if (!hw->phy.ops.acquire)
731 return E1000_SUCCESS;
733 ret_val = hw->phy.ops.acquire(hw);
738 if (offset > MAX_PHY_MULTI_PAGE_REG)
739 ret_val = e1000_write_phy_reg_mdic(hw,
740 IGP01E1000_PHY_PAGE_SELECT,
743 ret_val = e1000_read_phy_reg_mdic(hw,
744 MAX_PHY_REG_ADDRESS & offset,
747 hw->phy.ops.release(hw);
753 * e1000_read_phy_reg_igp - Read igp PHY register
754 * @hw: pointer to the HW structure
755 * @offset: register offset to be read
756 * @data: pointer to the read data
758 * Acquires semaphore then reads the PHY register at offset and stores the
759 * retrieved information in data.
760 * Release the acquired semaphore before exiting.
762 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
764 return __e1000_read_phy_reg_igp(hw, offset, data, false);
768 * e1000_read_phy_reg_igp_locked - Read igp PHY register
769 * @hw: pointer to the HW structure
770 * @offset: register offset to be read
771 * @data: pointer to the read data
773 * Reads the PHY register at offset and stores the retrieved information
774 * in data. Assumes semaphore already acquired.
776 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
778 return __e1000_read_phy_reg_igp(hw, offset, data, true);
782 * e1000_write_phy_reg_igp - Write igp PHY register
783 * @hw: pointer to the HW structure
784 * @offset: register offset to write to
785 * @data: data to write at register offset
786 * @locked: semaphore has already been acquired or not
788 * Acquires semaphore, if necessary, then writes the data to PHY register
789 * at the offset. Release any acquired semaphores before exiting.
791 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
794 s32 ret_val = E1000_SUCCESS;
796 DEBUGFUNC("e1000_write_phy_reg_igp");
799 if (!hw->phy.ops.acquire)
800 return E1000_SUCCESS;
802 ret_val = hw->phy.ops.acquire(hw);
807 if (offset > MAX_PHY_MULTI_PAGE_REG)
808 ret_val = e1000_write_phy_reg_mdic(hw,
809 IGP01E1000_PHY_PAGE_SELECT,
812 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
816 hw->phy.ops.release(hw);
822 * e1000_write_phy_reg_igp - Write igp PHY register
823 * @hw: pointer to the HW structure
824 * @offset: register offset to write to
825 * @data: data to write at register offset
827 * Acquires semaphore then writes the data to PHY register
828 * at the offset. Release any acquired semaphores before exiting.
830 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
832 return __e1000_write_phy_reg_igp(hw, offset, data, false);
836 * e1000_write_phy_reg_igp_locked - Write igp PHY register
837 * @hw: pointer to the HW structure
838 * @offset: register offset to write to
839 * @data: data to write at register offset
841 * Writes the data to PHY register at the offset.
842 * Assumes semaphore already acquired.
844 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
846 return __e1000_write_phy_reg_igp(hw, offset, data, true);
850 * __e1000_read_kmrn_reg - Read kumeran register
851 * @hw: pointer to the HW structure
852 * @offset: register offset to be read
853 * @data: pointer to the read data
854 * @locked: semaphore has already been acquired or not
856 * Acquires semaphore, if necessary. Then reads the PHY register at offset
857 * using the kumeran interface. The information retrieved is stored in data.
858 * Release any acquired semaphores before exiting.
860 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
865 DEBUGFUNC("__e1000_read_kmrn_reg");
868 s32 ret_val = E1000_SUCCESS;
870 if (!hw->phy.ops.acquire)
871 return E1000_SUCCESS;
873 ret_val = hw->phy.ops.acquire(hw);
878 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
879 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
880 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
881 E1000_WRITE_FLUSH(hw);
885 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
886 *data = (u16)kmrnctrlsta;
889 hw->phy.ops.release(hw);
891 return E1000_SUCCESS;
895 * e1000_read_kmrn_reg_generic - Read kumeran register
896 * @hw: pointer to the HW structure
897 * @offset: register offset to be read
898 * @data: pointer to the read data
900 * Acquires semaphore then reads the PHY register at offset using the
901 * kumeran interface. The information retrieved is stored in data.
902 * Release the acquired semaphore before exiting.
904 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
906 return __e1000_read_kmrn_reg(hw, offset, data, false);
910 * e1000_read_kmrn_reg_locked - Read kumeran register
911 * @hw: pointer to the HW structure
912 * @offset: register offset to be read
913 * @data: pointer to the read data
915 * Reads the PHY register at offset using the kumeran interface. The
916 * information retrieved is stored in data.
917 * Assumes semaphore already acquired.
919 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
921 return __e1000_read_kmrn_reg(hw, offset, data, true);
925 * __e1000_write_kmrn_reg - Write kumeran register
926 * @hw: pointer to the HW structure
927 * @offset: register offset to write to
928 * @data: data to write at register offset
929 * @locked: semaphore has already been acquired or not
931 * Acquires semaphore, if necessary. Then write the data to PHY register
932 * at the offset using the kumeran interface. Release any acquired semaphores
935 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
940 DEBUGFUNC("e1000_write_kmrn_reg_generic");
943 s32 ret_val = E1000_SUCCESS;
945 if (!hw->phy.ops.acquire)
946 return E1000_SUCCESS;
948 ret_val = hw->phy.ops.acquire(hw);
953 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
954 E1000_KMRNCTRLSTA_OFFSET) | data;
955 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
956 E1000_WRITE_FLUSH(hw);
961 hw->phy.ops.release(hw);
963 return E1000_SUCCESS;
967 * e1000_write_kmrn_reg_generic - Write kumeran register
968 * @hw: pointer to the HW structure
969 * @offset: register offset to write to
970 * @data: data to write at register offset
972 * Acquires semaphore then writes the data to the PHY register at the offset
973 * using the kumeran interface. Release the acquired semaphore before exiting.
975 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
977 return __e1000_write_kmrn_reg(hw, offset, data, false);
981 * e1000_write_kmrn_reg_locked - Write kumeran register
982 * @hw: pointer to the HW structure
983 * @offset: register offset to write to
984 * @data: data to write at register offset
986 * Write the data to PHY register at the offset using the kumeran interface.
987 * Assumes semaphore already acquired.
989 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
991 return __e1000_write_kmrn_reg(hw, offset, data, true);
995 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
996 * @hw: pointer to the HW structure
998 * Sets up Master/slave mode
1000 STATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1005 /* Resolve Master/Slave mode */
1006 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1010 /* load defaults for future use */
1011 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1012 ((phy_data & CR_1000T_MS_VALUE) ?
1013 e1000_ms_force_master :
1014 e1000_ms_force_slave) : e1000_ms_auto;
1016 switch (hw->phy.ms_type) {
1017 case e1000_ms_force_master:
1018 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1020 case e1000_ms_force_slave:
1021 phy_data |= CR_1000T_MS_ENABLE;
1022 phy_data &= ~(CR_1000T_MS_VALUE);
1025 phy_data &= ~CR_1000T_MS_ENABLE;
1031 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1035 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1036 * @hw: pointer to the HW structure
1038 * Sets up Carrier-sense on Transmit and downshift values.
1040 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1045 DEBUGFUNC("e1000_copper_link_setup_82577");
1047 if (hw->phy.type == e1000_phy_82580) {
1048 ret_val = hw->phy.ops.reset(hw);
1050 DEBUGOUT("Error resetting the PHY.\n");
1055 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1056 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1060 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1062 /* Enable downshift */
1063 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1065 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1069 /* Set MDI/MDIX mode */
1070 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1073 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1076 * 0 - Auto (default)
1080 switch (hw->phy.mdix) {
1084 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1088 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1091 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1095 return e1000_set_master_slave_mode(hw);
1099 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1100 * @hw: pointer to the HW structure
1102 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1103 * and downshift values are set also.
1105 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1107 struct e1000_phy_info *phy = &hw->phy;
1111 DEBUGFUNC("e1000_copper_link_setup_m88");
1114 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1115 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1119 /* For BM PHY this bit is downshift enable */
1120 if (phy->type != e1000_phy_bm)
1121 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1125 * MDI/MDI-X = 0 (default)
1126 * 0 - Auto for all speeds
1129 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1131 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1133 switch (phy->mdix) {
1135 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1138 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1141 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1145 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1151 * disable_polarity_correction = 0 (default)
1152 * Automatic Correction for Reversed Cable Polarity
1156 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1157 if (phy->disable_polarity_correction)
1158 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1160 /* Enable downshift on BM (disabled by default) */
1161 if (phy->type == e1000_phy_bm) {
1162 /* For 82574/82583, first disable then enable downshift */
1163 if (phy->id == BME1000_E_PHY_ID_R2) {
1164 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1165 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1169 /* Commit the changes. */
1170 ret_val = phy->ops.commit(hw);
1172 DEBUGOUT("Error committing the PHY changes\n");
1177 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1180 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1184 if ((phy->type == e1000_phy_m88) &&
1185 (phy->revision < E1000_REVISION_4) &&
1186 (phy->id != BME1000_E_PHY_ID_R2)) {
1188 * Force TX_CLK in the Extended PHY Specific Control Register
1191 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1196 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1198 if ((phy->revision == E1000_REVISION_2) &&
1199 (phy->id == M88E1111_I_PHY_ID)) {
1200 /* 82573L PHY - set the downshift counter to 5x. */
1201 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1202 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1204 /* Configure Master and Slave downshift values */
1205 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1206 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1207 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1208 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1210 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1216 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1217 /* Set PHY page 0, register 29 to 0x0003 */
1218 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1222 /* Set PHY page 0, register 30 to 0x0000 */
1223 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1228 /* Commit the changes. */
1229 ret_val = phy->ops.commit(hw);
1231 DEBUGOUT("Error committing the PHY changes\n");
1235 if (phy->type == e1000_phy_82578) {
1236 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1241 /* 82578 PHY - set the downshift count to 1x. */
1242 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1243 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1244 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1250 if (phy->type == e1000_phy_i210) {
1251 ret_val = e1000_set_master_slave_mode(hw);
1256 return E1000_SUCCESS;
1260 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1261 * @hw: pointer to the HW structure
1263 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1264 * Also enables and sets the downshift parameters.
1266 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1268 struct e1000_phy_info *phy = &hw->phy;
1272 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1275 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1276 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1282 * MDI/MDI-X = 0 (default)
1283 * 0 - Auto for all speeds
1286 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1288 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1290 switch (phy->mdix) {
1292 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1295 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1298 /* M88E1112 does not support this mode) */
1299 if (phy->id != M88E1112_E_PHY_ID) {
1300 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1305 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1311 * disable_polarity_correction = 0 (default)
1312 * Automatic Correction for Reversed Cable Polarity
1316 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1317 if (phy->disable_polarity_correction)
1318 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1320 /* Enable downshift and setting it to X6 */
1321 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1322 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1323 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1325 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1329 /* Commit the changes. */
1330 ret_val = phy->ops.commit(hw);
1332 DEBUGOUT("Error committing the PHY changes\n");
1336 return E1000_SUCCESS;
1340 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1341 * @hw: pointer to the HW structure
1343 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1346 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1348 struct e1000_phy_info *phy = &hw->phy;
1352 DEBUGFUNC("e1000_copper_link_setup_igp");
1355 ret_val = hw->phy.ops.reset(hw);
1357 DEBUGOUT("Error resetting the PHY.\n");
1362 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1363 * timeout issues when LFS is enabled.
1368 * The NVM settings will configure LPLU in D3 for
1371 if (phy->type == e1000_phy_igp) {
1372 /* disable lplu d3 during driver init */
1373 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1375 DEBUGOUT("Error Disabling LPLU D3\n");
1380 /* disable lplu d0 during driver init */
1381 if (hw->phy.ops.set_d0_lplu_state) {
1382 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1384 DEBUGOUT("Error Disabling LPLU D0\n");
1388 /* Configure mdi-mdix settings */
1389 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1393 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1395 switch (phy->mdix) {
1397 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1400 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1404 data |= IGP01E1000_PSCR_AUTO_MDIX;
1407 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1411 /* set auto-master slave resolution settings */
1412 if (hw->mac.autoneg) {
1414 * when autonegotiation advertisement is only 1000Mbps then we
1415 * should disable SmartSpeed and enable Auto MasterSlave
1416 * resolution as hardware default.
1418 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1419 /* Disable SmartSpeed */
1420 ret_val = phy->ops.read_reg(hw,
1421 IGP01E1000_PHY_PORT_CONFIG,
1426 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1427 ret_val = phy->ops.write_reg(hw,
1428 IGP01E1000_PHY_PORT_CONFIG,
1433 /* Set auto Master/Slave resolution process */
1434 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1438 data &= ~CR_1000T_MS_ENABLE;
1439 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1444 ret_val = e1000_set_master_slave_mode(hw);
1451 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1452 * @hw: pointer to the HW structure
1454 * Reads the MII auto-neg advertisement register and/or the 1000T control
1455 * register and if the PHY is already setup for auto-negotiation, then
1456 * return successful. Otherwise, setup advertisement and flow control to
1457 * the appropriate values for the wanted auto-negotiation.
1459 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1461 struct e1000_phy_info *phy = &hw->phy;
1463 u16 mii_autoneg_adv_reg;
1464 u16 mii_1000t_ctrl_reg = 0;
1466 DEBUGFUNC("e1000_phy_setup_autoneg");
1468 phy->autoneg_advertised &= phy->autoneg_mask;
1470 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1471 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1475 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1476 /* Read the MII 1000Base-T Control Register (Address 9). */
1477 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1478 &mii_1000t_ctrl_reg);
1484 * Need to parse both autoneg_advertised and fc and set up
1485 * the appropriate PHY registers. First we will parse for
1486 * autoneg_advertised software override. Since we can advertise
1487 * a plethora of combinations, we need to check each bit
1492 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1493 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1494 * the 1000Base-T Control Register (Address 9).
1496 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1497 NWAY_AR_100TX_HD_CAPS |
1498 NWAY_AR_10T_FD_CAPS |
1499 NWAY_AR_10T_HD_CAPS);
1500 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1502 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1504 /* Do we want to advertise 10 Mb Half Duplex? */
1505 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1506 DEBUGOUT("Advertise 10mb Half duplex\n");
1507 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1510 /* Do we want to advertise 10 Mb Full Duplex? */
1511 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1512 DEBUGOUT("Advertise 10mb Full duplex\n");
1513 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1516 /* Do we want to advertise 100 Mb Half Duplex? */
1517 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1518 DEBUGOUT("Advertise 100mb Half duplex\n");
1519 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1522 /* Do we want to advertise 100 Mb Full Duplex? */
1523 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1524 DEBUGOUT("Advertise 100mb Full duplex\n");
1525 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1528 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1529 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1530 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1532 /* Do we want to advertise 1000 Mb Full Duplex? */
1533 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1534 DEBUGOUT("Advertise 1000mb Full duplex\n");
1535 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1539 * Check for a software override of the flow control settings, and
1540 * setup the PHY advertisement registers accordingly. If
1541 * auto-negotiation is enabled, then software will have to set the
1542 * "PAUSE" bits to the correct value in the Auto-Negotiation
1543 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1546 * The possible values of the "fc" parameter are:
1547 * 0: Flow control is completely disabled
1548 * 1: Rx flow control is enabled (we can receive pause frames
1549 * but not send pause frames).
1550 * 2: Tx flow control is enabled (we can send pause frames
1551 * but we do not support receiving pause frames).
1552 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1553 * other: No software override. The flow control configuration
1554 * in the EEPROM is used.
1556 switch (hw->fc.current_mode) {
1559 * Flow control (Rx & Tx) is completely disabled by a
1560 * software over-ride.
1562 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1564 case e1000_fc_rx_pause:
1566 * Rx Flow control is enabled, and Tx Flow control is
1567 * disabled, by a software over-ride.
1569 * Since there really isn't a way to advertise that we are
1570 * capable of Rx Pause ONLY, we will advertise that we
1571 * support both symmetric and asymmetric Rx PAUSE. Later
1572 * (in e1000_config_fc_after_link_up) we will disable the
1573 * hw's ability to send PAUSE frames.
1575 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1577 case e1000_fc_tx_pause:
1579 * Tx Flow control is enabled, and Rx Flow control is
1580 * disabled, by a software over-ride.
1582 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1583 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1587 * Flow control (both Rx and Tx) is enabled by a software
1590 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1593 DEBUGOUT("Flow control param set incorrectly\n");
1594 return -E1000_ERR_CONFIG;
1597 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1601 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1603 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1604 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1605 mii_1000t_ctrl_reg);
1611 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1612 * @hw: pointer to the HW structure
1614 * Performs initial bounds checking on autoneg advertisement parameter, then
1615 * configure to advertise the full capability. Setup the PHY to autoneg
1616 * and restart the negotiation process between the link partner. If
1617 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1619 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1621 struct e1000_phy_info *phy = &hw->phy;
1625 DEBUGFUNC("e1000_copper_link_autoneg");
1628 * Perform some bounds checking on the autoneg advertisement
1631 phy->autoneg_advertised &= phy->autoneg_mask;
1634 * If autoneg_advertised is zero, we assume it was not defaulted
1635 * by the calling code so we set to advertise full capability.
1637 if (!phy->autoneg_advertised)
1638 phy->autoneg_advertised = phy->autoneg_mask;
1640 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1641 ret_val = e1000_phy_setup_autoneg(hw);
1643 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1646 DEBUGOUT("Restarting Auto-Neg\n");
1649 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1650 * the Auto Neg Restart bit in the PHY control register.
1652 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1656 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1657 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1662 * Does the user want to wait for Auto-Neg to complete here, or
1663 * check at a later time (for example, callback routine).
1665 if (phy->autoneg_wait_to_complete) {
1666 ret_val = hw->mac.ops.wait_autoneg(hw);
1668 DEBUGOUT("Error while waiting for autoneg to complete\n");
1673 hw->mac.get_link_status = true;
1679 * e1000_setup_copper_link_generic - Configure copper link settings
1680 * @hw: pointer to the HW structure
1682 * Calls the appropriate function to configure the link for auto-neg or forced
1683 * speed and duplex. Then we check for link, once link is established calls
1684 * to configure collision distance and flow control are called. If link is
1685 * not established, we return -E1000_ERR_PHY (-2).
1687 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1692 DEBUGFUNC("e1000_setup_copper_link_generic");
1694 if (hw->mac.autoneg) {
1696 * Setup autoneg and flow control advertisement and perform
1699 ret_val = e1000_copper_link_autoneg(hw);
1704 * PHY will be set to 10H, 10F, 100H or 100F
1705 * depending on user settings.
1707 DEBUGOUT("Forcing Speed and Duplex\n");
1708 ret_val = hw->phy.ops.force_speed_duplex(hw);
1710 DEBUGOUT("Error Forcing Speed and Duplex\n");
1716 * Check link status. Wait up to 100 microseconds for link to become
1719 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1725 DEBUGOUT("Valid link established!!!\n");
1726 hw->mac.ops.config_collision_dist(hw);
1727 ret_val = e1000_config_fc_after_link_up_generic(hw);
1729 DEBUGOUT("Unable to establish link!!!\n");
1736 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1737 * @hw: pointer to the HW structure
1739 * Calls the PHY setup function to force speed and duplex. Clears the
1740 * auto-crossover to force MDI manually. Waits for link and returns
1741 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1743 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1745 struct e1000_phy_info *phy = &hw->phy;
1750 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1752 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1756 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1758 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1763 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1764 * forced whenever speed and duplex are forced.
1766 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1770 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1771 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1773 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1777 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1781 if (phy->autoneg_wait_to_complete) {
1782 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1784 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1790 DEBUGOUT("Link taking longer than expected.\n");
1793 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1801 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1802 * @hw: pointer to the HW structure
1804 * Calls the PHY setup function to force speed and duplex. Clears the
1805 * auto-crossover to force MDI manually. Resets the PHY to commit the
1806 * changes. If time expires while waiting for link up, we reset the DSP.
1807 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1808 * successful completion, else return corresponding error code.
1810 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1812 struct e1000_phy_info *phy = &hw->phy;
1817 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1819 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1820 if (phy->type != e1000_phy_i210) {
1822 * Clear Auto-Crossover to force MDI manually. M88E1000
1823 * requires MDI forced whenever speed and duplex are forced.
1825 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1830 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1831 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1837 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1839 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1843 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1845 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1849 /* Reset the phy to commit changes. */
1850 ret_val = hw->phy.ops.commit(hw);
1854 if (phy->autoneg_wait_to_complete) {
1855 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1857 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1863 bool reset_dsp = true;
1865 switch (hw->phy.id) {
1866 case I347AT4_E_PHY_ID:
1867 case M88E1340M_E_PHY_ID:
1868 case M88E1112_E_PHY_ID:
1873 if (hw->phy.type != e1000_phy_m88)
1879 DEBUGOUT("Link taking longer than expected.\n");
1882 * We didn't get link.
1883 * Reset the DSP and cross our fingers.
1885 ret_val = phy->ops.write_reg(hw,
1886 M88E1000_PHY_PAGE_SELECT,
1890 ret_val = e1000_phy_reset_dsp_generic(hw);
1897 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1903 if (hw->phy.type != e1000_phy_m88)
1904 return E1000_SUCCESS;
1906 if (hw->phy.id == I347AT4_E_PHY_ID ||
1907 hw->phy.id == M88E1340M_E_PHY_ID ||
1908 hw->phy.id == M88E1112_E_PHY_ID)
1909 return E1000_SUCCESS;
1910 if (hw->phy.id == I210_I_PHY_ID)
1911 return E1000_SUCCESS;
1912 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1917 * Resetting the phy means we need to re-force TX_CLK in the
1918 * Extended PHY Specific Control Register to 25MHz clock from
1919 * the reset value of 2.5MHz.
1921 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1922 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1927 * In addition, we must re-enable CRS on Tx for both half and full
1930 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1934 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1935 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1941 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1942 * @hw: pointer to the HW structure
1944 * Forces the speed and duplex settings of the PHY.
1945 * This is a function pointer entry point only called by
1946 * PHY setup routines.
1948 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1950 struct e1000_phy_info *phy = &hw->phy;
1955 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1957 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1961 e1000_phy_force_speed_duplex_setup(hw, &data);
1963 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1967 /* Disable MDI-X support for 10/100 */
1968 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1972 data &= ~IFE_PMC_AUTO_MDIX;
1973 data &= ~IFE_PMC_FORCE_MDIX;
1975 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1979 DEBUGOUT1("IFE PMC: %X\n", data);
1983 if (phy->autoneg_wait_to_complete) {
1984 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1986 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1992 DEBUGOUT("Link taking longer than expected.\n");
1995 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2001 return E1000_SUCCESS;
2005 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2006 * @hw: pointer to the HW structure
2007 * @phy_ctrl: pointer to current value of PHY_CONTROL
2009 * Forces speed and duplex on the PHY by doing the following: disable flow
2010 * control, force speed/duplex on the MAC, disable auto speed detection,
2011 * disable auto-negotiation, configure duplex, configure speed, configure
2012 * the collision distance, write configuration to CTRL register. The
2013 * caller must write to the PHY_CONTROL register for these settings to
2016 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2018 struct e1000_mac_info *mac = &hw->mac;
2021 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2023 /* Turn off flow control when forcing speed/duplex */
2024 hw->fc.current_mode = e1000_fc_none;
2026 /* Force speed/duplex on the mac */
2027 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2028 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2029 ctrl &= ~E1000_CTRL_SPD_SEL;
2031 /* Disable Auto Speed Detection */
2032 ctrl &= ~E1000_CTRL_ASDE;
2034 /* Disable autoneg on the phy */
2035 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2037 /* Forcing Full or Half Duplex? */
2038 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2039 ctrl &= ~E1000_CTRL_FD;
2040 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2041 DEBUGOUT("Half Duplex\n");
2043 ctrl |= E1000_CTRL_FD;
2044 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2045 DEBUGOUT("Full Duplex\n");
2048 /* Forcing 10mb or 100mb? */
2049 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2050 ctrl |= E1000_CTRL_SPD_100;
2051 *phy_ctrl |= MII_CR_SPEED_100;
2052 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2053 DEBUGOUT("Forcing 100mb\n");
2055 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2056 *phy_ctrl |= MII_CR_SPEED_10;
2057 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2058 DEBUGOUT("Forcing 10mb\n");
2061 hw->mac.ops.config_collision_dist(hw);
2063 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2067 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2068 * @hw: pointer to the HW structure
2069 * @active: boolean used to enable/disable lplu
2071 * Success returns 0, Failure returns 1
2073 * The low power link up (lplu) state is set to the power management level D3
2074 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2075 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2076 * is used during Dx states where the power conservation is most important.
2077 * During driver activity, SmartSpeed should be enabled so performance is
2080 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2082 struct e1000_phy_info *phy = &hw->phy;
2086 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2088 if (!hw->phy.ops.read_reg)
2089 return E1000_SUCCESS;
2091 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2096 data &= ~IGP02E1000_PM_D3_LPLU;
2097 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2102 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2103 * during Dx states where the power conservation is most
2104 * important. During driver activity we should enable
2105 * SmartSpeed, so performance is maintained.
2107 if (phy->smart_speed == e1000_smart_speed_on) {
2108 ret_val = phy->ops.read_reg(hw,
2109 IGP01E1000_PHY_PORT_CONFIG,
2114 data |= IGP01E1000_PSCFR_SMART_SPEED;
2115 ret_val = phy->ops.write_reg(hw,
2116 IGP01E1000_PHY_PORT_CONFIG,
2120 } else if (phy->smart_speed == e1000_smart_speed_off) {
2121 ret_val = phy->ops.read_reg(hw,
2122 IGP01E1000_PHY_PORT_CONFIG,
2127 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2128 ret_val = phy->ops.write_reg(hw,
2129 IGP01E1000_PHY_PORT_CONFIG,
2134 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2135 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2136 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2137 data |= IGP02E1000_PM_D3_LPLU;
2138 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2143 /* When LPLU is enabled, we should disable SmartSpeed */
2144 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2149 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2150 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2158 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2159 * @hw: pointer to the HW structure
2161 * Success returns 0, Failure returns 1
2163 * A downshift is detected by querying the PHY link health.
2165 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2167 struct e1000_phy_info *phy = &hw->phy;
2169 u16 phy_data, offset, mask;
2171 DEBUGFUNC("e1000_check_downshift_generic");
2173 switch (phy->type) {
2174 case e1000_phy_i210:
2176 case e1000_phy_gg82563:
2178 case e1000_phy_82578:
2179 offset = M88E1000_PHY_SPEC_STATUS;
2180 mask = M88E1000_PSSR_DOWNSHIFT;
2183 case e1000_phy_igp_2:
2184 case e1000_phy_igp_3:
2185 offset = IGP01E1000_PHY_LINK_HEALTH;
2186 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2189 /* speed downshift not supported */
2190 phy->speed_downgraded = false;
2191 return E1000_SUCCESS;
2194 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2197 phy->speed_downgraded = !!(phy_data & mask);
2203 * e1000_check_polarity_m88 - Checks the polarity.
2204 * @hw: pointer to the HW structure
2206 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2208 * Polarity is determined based on the PHY specific status register.
2210 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2212 struct e1000_phy_info *phy = &hw->phy;
2216 DEBUGFUNC("e1000_check_polarity_m88");
2218 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2221 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
2222 ? e1000_rev_polarity_reversed
2223 : e1000_rev_polarity_normal;
2229 * e1000_check_polarity_igp - Checks the polarity.
2230 * @hw: pointer to the HW structure
2232 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2234 * Polarity is determined based on the PHY port status register, and the
2235 * current speed (since there is no polarity at 100Mbps).
2237 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2239 struct e1000_phy_info *phy = &hw->phy;
2241 u16 data, offset, mask;
2243 DEBUGFUNC("e1000_check_polarity_igp");
2246 * Polarity is determined based on the speed of
2249 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2253 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2254 IGP01E1000_PSSR_SPEED_1000MBPS) {
2255 offset = IGP01E1000_PHY_PCS_INIT_REG;
2256 mask = IGP01E1000_PHY_POLARITY_MASK;
2259 * This really only applies to 10Mbps since
2260 * there is no polarity for 100Mbps (always 0).
2262 offset = IGP01E1000_PHY_PORT_STATUS;
2263 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2266 ret_val = phy->ops.read_reg(hw, offset, &data);
2269 phy->cable_polarity = (data & mask)
2270 ? e1000_rev_polarity_reversed
2271 : e1000_rev_polarity_normal;
2277 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2278 * @hw: pointer to the HW structure
2280 * Polarity is determined on the polarity reversal feature being enabled.
2282 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2284 struct e1000_phy_info *phy = &hw->phy;
2286 u16 phy_data, offset, mask;
2288 DEBUGFUNC("e1000_check_polarity_ife");
2291 * Polarity is determined based on the reversal feature being enabled.
2293 if (phy->polarity_correction) {
2294 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2295 mask = IFE_PESC_POLARITY_REVERSED;
2297 offset = IFE_PHY_SPECIAL_CONTROL;
2298 mask = IFE_PSC_FORCE_POLARITY;
2301 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2304 phy->cable_polarity = (phy_data & mask)
2305 ? e1000_rev_polarity_reversed
2306 : e1000_rev_polarity_normal;
2312 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2313 * @hw: pointer to the HW structure
2315 * Waits for auto-negotiation to complete or for the auto-negotiation time
2316 * limit to expire, which ever happens first.
2318 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2320 s32 ret_val = E1000_SUCCESS;
2323 DEBUGFUNC("e1000_wait_autoneg_generic");
2325 if (!hw->phy.ops.read_reg)
2326 return E1000_SUCCESS;
2328 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2329 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2330 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2333 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2336 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2342 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2349 * e1000_phy_has_link_generic - Polls PHY for link
2350 * @hw: pointer to the HW structure
2351 * @iterations: number of times to poll for link
2352 * @usec_interval: delay between polling attempts
2353 * @success: pointer to whether polling was successful or not
2355 * Polls the PHY status register for link, 'iterations' number of times.
2357 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2358 u32 usec_interval, bool *success)
2360 s32 ret_val = E1000_SUCCESS;
2363 DEBUGFUNC("e1000_phy_has_link_generic");
2365 if (!hw->phy.ops.read_reg)
2366 return E1000_SUCCESS;
2368 for (i = 0; i < iterations; i++) {
2370 * Some PHYs require the PHY_STATUS register to be read
2371 * twice due to the link bit being sticky. No harm doing
2372 * it across the board.
2374 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2377 * If the first read fails, another entity may have
2378 * ownership of the resources, wait and try again to
2379 * see if they have relinquished the resources yet.
2381 usec_delay(usec_interval);
2382 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2385 if (phy_status & MII_SR_LINK_STATUS)
2387 if (usec_interval >= 1000)
2388 msec_delay_irq(usec_interval/1000);
2390 usec_delay(usec_interval);
2393 *success = (i < iterations);
2399 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2400 * @hw: pointer to the HW structure
2402 * Reads the PHY specific status register to retrieve the cable length
2403 * information. The cable length is determined by averaging the minimum and
2404 * maximum values to get the "average" cable length. The m88 PHY has four
2405 * possible cable length values, which are:
2406 * Register Value Cable Length
2410 * 3 110 - 140 meters
2413 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2415 struct e1000_phy_info *phy = &hw->phy;
2417 u16 phy_data, index;
2419 DEBUGFUNC("e1000_get_cable_length_m88");
2421 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2425 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2426 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2428 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2429 return -E1000_ERR_PHY;
2431 phy->min_cable_length = e1000_m88_cable_length_table[index];
2432 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2434 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2436 return E1000_SUCCESS;
2439 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2441 struct e1000_phy_info *phy = &hw->phy;
2443 u16 phy_data, phy_data2, index, default_page, is_cm;
2445 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2447 switch (hw->phy.id) {
2449 /* Get cable length from PHY Cable Diagnostics Control Reg */
2450 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2451 (I347AT4_PCDL + phy->addr),
2456 /* Check if the unit of cable length is meters or cm */
2457 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2458 I347AT4_PCDC, &phy_data2);
2462 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2464 /* Populate the phy structure with cable length in meters */
2465 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2466 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2467 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2469 case M88E1340M_E_PHY_ID:
2470 case I347AT4_E_PHY_ID:
2471 /* Remember the original page select and set it to 7 */
2472 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2477 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2481 /* Get cable length from PHY Cable Diagnostics Control Reg */
2482 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2487 /* Check if the unit of cable length is meters or cm */
2488 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2492 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2494 /* Populate the phy structure with cable length in meters */
2495 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2496 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2497 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2499 /* Reset the page select to its original value */
2500 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2506 case M88E1112_E_PHY_ID:
2507 /* Remember the original page select and set it to 5 */
2508 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2513 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2517 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2522 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2523 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2525 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2526 return -E1000_ERR_PHY;
2528 phy->min_cable_length = e1000_m88_cable_length_table[index];
2529 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2531 phy->cable_length = (phy->min_cable_length +
2532 phy->max_cable_length) / 2;
2534 /* Reset the page select to its original value */
2535 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2542 return -E1000_ERR_PHY;
2549 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2550 * @hw: pointer to the HW structure
2552 * The automatic gain control (agc) normalizes the amplitude of the
2553 * received signal, adjusting for the attenuation produced by the
2554 * cable. By reading the AGC registers, which represent the
2555 * combination of coarse and fine gain value, the value can be put
2556 * into a lookup table to obtain the approximate cable length
2559 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2561 struct e1000_phy_info *phy = &hw->phy;
2563 u16 phy_data, i, agc_value = 0;
2564 u16 cur_agc_index, max_agc_index = 0;
2565 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2566 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2567 IGP02E1000_PHY_AGC_A,
2568 IGP02E1000_PHY_AGC_B,
2569 IGP02E1000_PHY_AGC_C,
2570 IGP02E1000_PHY_AGC_D
2573 DEBUGFUNC("e1000_get_cable_length_igp_2");
2575 /* Read the AGC registers for all channels */
2576 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2577 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2582 * Getting bits 15:9, which represent the combination of
2583 * coarse and fine gain values. The result is a number
2584 * that can be put into the lookup table to obtain the
2585 * approximate cable length.
2587 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2588 IGP02E1000_AGC_LENGTH_MASK;
2590 /* Array index bound check. */
2591 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2592 (cur_agc_index == 0))
2593 return -E1000_ERR_PHY;
2595 /* Remove min & max AGC values from calculation. */
2596 if (e1000_igp_2_cable_length_table[min_agc_index] >
2597 e1000_igp_2_cable_length_table[cur_agc_index])
2598 min_agc_index = cur_agc_index;
2599 if (e1000_igp_2_cable_length_table[max_agc_index] <
2600 e1000_igp_2_cable_length_table[cur_agc_index])
2601 max_agc_index = cur_agc_index;
2603 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2606 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2607 e1000_igp_2_cable_length_table[max_agc_index]);
2608 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2610 /* Calculate cable length with the error range of +/- 10 meters. */
2611 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2612 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2613 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2615 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2617 return E1000_SUCCESS;
2621 * e1000_get_phy_info_m88 - Retrieve PHY information
2622 * @hw: pointer to the HW structure
2624 * Valid for only copper links. Read the PHY status register (sticky read)
2625 * to verify that link is up. Read the PHY special control register to
2626 * determine the polarity and 10base-T extended distance. Read the PHY
2627 * special status register to determine MDI/MDIx and current speed. If
2628 * speed is 1000, then determine cable length, local and remote receiver.
2630 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2632 struct e1000_phy_info *phy = &hw->phy;
2637 DEBUGFUNC("e1000_get_phy_info_m88");
2639 if (phy->media_type != e1000_media_type_copper) {
2640 DEBUGOUT("Phy info is only valid for copper media\n");
2641 return -E1000_ERR_CONFIG;
2644 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2649 DEBUGOUT("Phy info is only valid if link is up\n");
2650 return -E1000_ERR_CONFIG;
2653 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2657 phy->polarity_correction = !!(phy_data &
2658 M88E1000_PSCR_POLARITY_REVERSAL);
2660 ret_val = e1000_check_polarity_m88(hw);
2664 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2668 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2670 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2671 ret_val = hw->phy.ops.get_cable_length(hw);
2675 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2679 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2680 ? e1000_1000t_rx_status_ok
2681 : e1000_1000t_rx_status_not_ok;
2683 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2684 ? e1000_1000t_rx_status_ok
2685 : e1000_1000t_rx_status_not_ok;
2687 /* Set values to "undefined" */
2688 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2689 phy->local_rx = e1000_1000t_rx_status_undefined;
2690 phy->remote_rx = e1000_1000t_rx_status_undefined;
2697 * e1000_get_phy_info_igp - Retrieve igp PHY information
2698 * @hw: pointer to the HW structure
2700 * Read PHY status to determine if link is up. If link is up, then
2701 * set/determine 10base-T extended distance and polarity correction. Read
2702 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2703 * determine on the cable length, local and remote receiver.
2705 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2707 struct e1000_phy_info *phy = &hw->phy;
2712 DEBUGFUNC("e1000_get_phy_info_igp");
2714 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2719 DEBUGOUT("Phy info is only valid if link is up\n");
2720 return -E1000_ERR_CONFIG;
2723 phy->polarity_correction = true;
2725 ret_val = e1000_check_polarity_igp(hw);
2729 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2733 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2735 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2736 IGP01E1000_PSSR_SPEED_1000MBPS) {
2737 ret_val = phy->ops.get_cable_length(hw);
2741 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2745 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2746 ? e1000_1000t_rx_status_ok
2747 : e1000_1000t_rx_status_not_ok;
2749 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2750 ? e1000_1000t_rx_status_ok
2751 : e1000_1000t_rx_status_not_ok;
2753 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2754 phy->local_rx = e1000_1000t_rx_status_undefined;
2755 phy->remote_rx = e1000_1000t_rx_status_undefined;
2762 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2763 * @hw: pointer to the HW structure
2765 * Populates "phy" structure with various feature states.
2767 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2769 struct e1000_phy_info *phy = &hw->phy;
2774 DEBUGFUNC("e1000_get_phy_info_ife");
2776 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2781 DEBUGOUT("Phy info is only valid if link is up\n");
2782 return -E1000_ERR_CONFIG;
2785 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2788 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2790 if (phy->polarity_correction) {
2791 ret_val = e1000_check_polarity_ife(hw);
2795 /* Polarity is forced */
2796 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2797 ? e1000_rev_polarity_reversed
2798 : e1000_rev_polarity_normal;
2801 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2805 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2807 /* The following parameters are undefined for 10/100 operation. */
2808 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2809 phy->local_rx = e1000_1000t_rx_status_undefined;
2810 phy->remote_rx = e1000_1000t_rx_status_undefined;
2812 return E1000_SUCCESS;
2816 * e1000_phy_sw_reset_generic - PHY software reset
2817 * @hw: pointer to the HW structure
2819 * Does a software reset of the PHY by reading the PHY control register and
2820 * setting/write the control register reset bit to the PHY.
2822 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2827 DEBUGFUNC("e1000_phy_sw_reset_generic");
2829 if (!hw->phy.ops.read_reg)
2830 return E1000_SUCCESS;
2832 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2836 phy_ctrl |= MII_CR_RESET;
2837 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2847 * e1000_phy_hw_reset_generic - PHY hardware reset
2848 * @hw: pointer to the HW structure
2850 * Verify the reset block is not blocking us from resetting. Acquire
2851 * semaphore (if necessary) and read/set/write the device control reset
2852 * bit in the PHY. Wait the appropriate delay time for the device to
2853 * reset and release the semaphore (if necessary).
2855 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2857 struct e1000_phy_info *phy = &hw->phy;
2861 DEBUGFUNC("e1000_phy_hw_reset_generic");
2863 if (phy->ops.check_reset_block) {
2864 ret_val = phy->ops.check_reset_block(hw);
2866 return E1000_SUCCESS;
2869 ret_val = phy->ops.acquire(hw);
2873 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2874 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2875 E1000_WRITE_FLUSH(hw);
2877 usec_delay(phy->reset_delay_us);
2879 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2880 E1000_WRITE_FLUSH(hw);
2884 phy->ops.release(hw);
2886 return phy->ops.get_cfg_done(hw);
2890 * e1000_get_cfg_done_generic - Generic configuration done
2891 * @hw: pointer to the HW structure
2893 * Generic function to wait 10 milli-seconds for configuration to complete
2894 * and return success.
2896 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2898 DEBUGFUNC("e1000_get_cfg_done_generic");
2902 return E1000_SUCCESS;
2906 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2907 * @hw: pointer to the HW structure
2909 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2911 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2913 DEBUGOUT("Running IGP 3 PHY init script\n");
2915 /* PHY init IGP 3 */
2916 /* Enable rise/fall, 10-mode work in class-A */
2917 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2918 /* Remove all caps from Replica path filter */
2919 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2920 /* Bias trimming for ADC, AFE and Driver (Default) */
2921 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2922 /* Increase Hybrid poly bias */
2923 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2924 /* Add 4% to Tx amplitude in Gig mode */
2925 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2926 /* Disable trimming (TTT) */
2927 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2928 /* Poly DC correction to 94.6% + 2% for all channels */
2929 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2930 /* ABS DC correction to 95.9% */
2931 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2932 /* BG temp curve trim */
2933 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2934 /* Increasing ADC OPAMP stage 1 currents to max */
2935 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2936 /* Force 1000 ( required for enabling PHY regs configuration) */
2937 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2938 /* Set upd_freq to 6 */
2939 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2941 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2942 /* Disable adaptive fixed FFE (Default) */
2943 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2944 /* Enable FFE hysteresis */
2945 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2946 /* Fixed FFE for short cable lengths */
2947 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2948 /* Fixed FFE for medium cable lengths */
2949 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2950 /* Fixed FFE for long cable lengths */
2951 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2952 /* Enable Adaptive Clip Threshold */
2953 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2954 /* AHT reset limit to 1 */
2955 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2956 /* Set AHT master delay to 127 msec */
2957 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2958 /* Set scan bits for AHT */
2959 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2960 /* Set AHT Preset bits */
2961 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2962 /* Change integ_factor of channel A to 3 */
2963 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2964 /* Change prop_factor of channels BCD to 8 */
2965 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2966 /* Change cg_icount + enable integbp for channels BCD */
2967 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2969 * Change cg_icount + enable integbp + change prop_factor_master
2970 * to 8 for channel A
2972 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2973 /* Disable AHT in Slave mode on channel A */
2974 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2976 * Enable LPLU and disable AN to 1000 in non-D0a states,
2979 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2980 /* Enable restart AN on an1000_dis change */
2981 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2982 /* Enable wh_fifo read clock in 10/100 modes */
2983 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2984 /* Restart AN, Speed selection is 1000 */
2985 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2987 return E1000_SUCCESS;
2991 * e1000_get_phy_type_from_id - Get PHY type from id
2992 * @phy_id: phy_id read from the phy
2994 * Returns the phy type from the id.
2996 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2998 enum e1000_phy_type phy_type = e1000_phy_unknown;
3001 case M88E1000_I_PHY_ID:
3002 case M88E1000_E_PHY_ID:
3003 case M88E1111_I_PHY_ID:
3004 case M88E1011_I_PHY_ID:
3005 case I347AT4_E_PHY_ID:
3006 case M88E1112_E_PHY_ID:
3007 case M88E1340M_E_PHY_ID:
3008 phy_type = e1000_phy_m88;
3010 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3011 phy_type = e1000_phy_igp_2;
3013 case GG82563_E_PHY_ID:
3014 phy_type = e1000_phy_gg82563;
3016 case IGP03E1000_E_PHY_ID:
3017 phy_type = e1000_phy_igp_3;
3020 case IFE_PLUS_E_PHY_ID:
3021 case IFE_C_E_PHY_ID:
3022 phy_type = e1000_phy_ife;
3024 case BME1000_E_PHY_ID:
3025 case BME1000_E_PHY_ID_R2:
3026 phy_type = e1000_phy_bm;
3028 case I82578_E_PHY_ID:
3029 phy_type = e1000_phy_82578;
3031 case I82577_E_PHY_ID:
3032 phy_type = e1000_phy_82577;
3034 case I82579_E_PHY_ID:
3035 phy_type = e1000_phy_82579;
3038 phy_type = e1000_phy_i217;
3040 case I82580_I_PHY_ID:
3041 phy_type = e1000_phy_82580;
3044 phy_type = e1000_phy_i210;
3047 phy_type = e1000_phy_unknown;
3054 * e1000_determine_phy_address - Determines PHY address.
3055 * @hw: pointer to the HW structure
3057 * This uses a trial and error method to loop through possible PHY
3058 * addresses. It tests each by reading the PHY ID registers and
3059 * checking for a match.
3061 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3065 enum e1000_phy_type phy_type = e1000_phy_unknown;
3067 hw->phy.id = phy_type;
3069 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3070 hw->phy.addr = phy_addr;
3074 e1000_get_phy_id(hw);
3075 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3078 * If phy_type is valid, break - we found our
3081 if (phy_type != e1000_phy_unknown)
3082 return E1000_SUCCESS;
3089 return -E1000_ERR_PHY_TYPE;
3093 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3094 * @page: page to access
3096 * Returns the phy address for the page requested.
3098 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3102 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3109 * e1000_write_phy_reg_bm - Write BM PHY register
3110 * @hw: pointer to the HW structure
3111 * @offset: register offset to write to
3112 * @data: data to write at register offset
3114 * Acquires semaphore, if necessary, then writes the data to PHY register
3115 * at the offset. Release any acquired semaphores before exiting.
3117 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3120 u32 page = offset >> IGP_PAGE_SHIFT;
3122 DEBUGFUNC("e1000_write_phy_reg_bm");
3124 ret_val = hw->phy.ops.acquire(hw);
3128 /* Page 800 works differently than the rest so it has its own func */
3129 if (page == BM_WUC_PAGE) {
3130 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3135 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3137 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3138 u32 page_shift, page_select;
3141 * Page select is register 31 for phy address 1 and 22 for
3142 * phy address 2 and 3. Page select is shifted only for
3145 if (hw->phy.addr == 1) {
3146 page_shift = IGP_PAGE_SHIFT;
3147 page_select = IGP01E1000_PHY_PAGE_SELECT;
3150 page_select = BM_PHY_PAGE_SELECT;
3153 /* Page is shifted left, PHY expects (page x 32) */
3154 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3155 (page << page_shift));
3160 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3164 hw->phy.ops.release(hw);
3169 * e1000_read_phy_reg_bm - Read BM PHY register
3170 * @hw: pointer to the HW structure
3171 * @offset: register offset to be read
3172 * @data: pointer to the read data
3174 * Acquires semaphore, if necessary, then reads the PHY register at offset
3175 * and storing the retrieved information in data. Release any acquired
3176 * semaphores before exiting.
3178 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3181 u32 page = offset >> IGP_PAGE_SHIFT;
3183 DEBUGFUNC("e1000_read_phy_reg_bm");
3185 ret_val = hw->phy.ops.acquire(hw);
3189 /* Page 800 works differently than the rest so it has its own func */
3190 if (page == BM_WUC_PAGE) {
3191 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3196 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3198 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3199 u32 page_shift, page_select;
3202 * Page select is register 31 for phy address 1 and 22 for
3203 * phy address 2 and 3. Page select is shifted only for
3206 if (hw->phy.addr == 1) {
3207 page_shift = IGP_PAGE_SHIFT;
3208 page_select = IGP01E1000_PHY_PAGE_SELECT;
3211 page_select = BM_PHY_PAGE_SELECT;
3214 /* Page is shifted left, PHY expects (page x 32) */
3215 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3216 (page << page_shift));
3221 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3224 hw->phy.ops.release(hw);
3229 * e1000_read_phy_reg_bm2 - Read BM PHY register
3230 * @hw: pointer to the HW structure
3231 * @offset: register offset to be read
3232 * @data: pointer to the read data
3234 * Acquires semaphore, if necessary, then reads the PHY register at offset
3235 * and storing the retrieved information in data. Release any acquired
3236 * semaphores before exiting.
3238 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3241 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3243 DEBUGFUNC("e1000_read_phy_reg_bm2");
3245 ret_val = hw->phy.ops.acquire(hw);
3249 /* Page 800 works differently than the rest so it has its own func */
3250 if (page == BM_WUC_PAGE) {
3251 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3258 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3260 /* Page is shifted left, PHY expects (page x 32) */
3261 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3268 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3271 hw->phy.ops.release(hw);
3276 * e1000_write_phy_reg_bm2 - Write BM PHY register
3277 * @hw: pointer to the HW structure
3278 * @offset: register offset to write to
3279 * @data: data to write at register offset
3281 * Acquires semaphore, if necessary, then writes the data to PHY register
3282 * at the offset. Release any acquired semaphores before exiting.
3284 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3287 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3289 DEBUGFUNC("e1000_write_phy_reg_bm2");
3291 ret_val = hw->phy.ops.acquire(hw);
3295 /* Page 800 works differently than the rest so it has its own func */
3296 if (page == BM_WUC_PAGE) {
3297 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3304 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3305 /* Page is shifted left, PHY expects (page x 32) */
3306 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3313 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3317 hw->phy.ops.release(hw);
3322 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3323 * @hw: pointer to the HW structure
3324 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3326 * Assumes semaphore already acquired and phy_reg points to a valid memory
3327 * address to store contents of the BM_WUC_ENABLE_REG register.
3329 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3334 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3337 return -E1000_ERR_PARAM;
3339 /* All page select, port ctrl and wakeup registers use phy address 1 */
3342 /* Select Port Control Registers page */
3343 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3345 DEBUGOUT("Could not set Port Control page\n");
3349 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3351 DEBUGOUT2("Could not read PHY register %d.%d\n",
3352 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3357 * Enable both PHY wakeup mode and Wakeup register page writes.
3358 * Prevent a power state change by disabling ME and Host PHY wakeup.
3361 temp |= BM_WUC_ENABLE_BIT;
3362 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3364 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3366 DEBUGOUT2("Could not write PHY register %d.%d\n",
3367 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3372 * Select Host Wakeup Registers page - caller now able to write
3373 * registers on the Wakeup registers page
3375 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3379 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3380 * @hw: pointer to the HW structure
3381 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3383 * Restore BM_WUC_ENABLE_REG to its original value.
3385 * Assumes semaphore already acquired and *phy_reg is the contents of the
3386 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3389 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3391 s32 ret_val = E1000_SUCCESS;
3393 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3396 return -E1000_ERR_PARAM;
3398 /* Select Port Control Registers page */
3399 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3401 DEBUGOUT("Could not set Port Control page\n");
3405 /* Restore 769.17 to its original value */
3406 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3408 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3409 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3415 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3416 * @hw: pointer to the HW structure
3417 * @offset: register offset to be read or written
3418 * @data: pointer to the data to read or write
3419 * @read: determines if operation is read or write
3420 * @page_set: BM_WUC_PAGE already set and access enabled
3422 * Read the PHY register at offset and store the retrieved information in
3423 * data, or write data to PHY register at offset. Note the procedure to
3424 * access the PHY wakeup registers is different than reading the other PHY
3425 * registers. It works as such:
3426 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3427 * 2) Set page to 800 for host (801 if we were manageability)
3428 * 3) Write the address using the address opcode (0x11)
3429 * 4) Read or write the data using the data opcode (0x12)
3430 * 5) Restore 769.17.2 to its original value
3432 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3433 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3435 * Assumes semaphore is already acquired. When page_set==true, assumes
3436 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3437 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3439 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3440 u16 *data, bool read, bool page_set)
3443 u16 reg = BM_PHY_REG_NUM(offset);
3444 u16 page = BM_PHY_REG_PAGE(offset);
3447 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3449 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3450 if ((hw->mac.type == e1000_pchlan) &&
3451 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3452 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3456 /* Enable access to PHY wakeup registers */
3457 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3459 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3464 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3466 /* Write the Wakeup register page offset value using opcode 0x11 */
3467 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3469 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3474 /* Read the Wakeup register page value using opcode 0x12 */
3475 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3478 /* Write the Wakeup register page value using opcode 0x12 */
3479 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3484 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3489 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3495 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3496 * @hw: pointer to the HW structure
3498 * In the case of a PHY power down to save power, or to turn off link during a
3499 * driver unload, or wake on lan is not enabled, restore the link to previous
3502 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3507 /* The PHY will retain its settings across a power down/up cycle */
3508 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3509 mii_reg &= ~MII_CR_POWER_DOWN;
3510 if (hw->phy.type == e1000_phy_i210) {
3511 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3512 power_reg &= ~GS40G_CS_POWER_DOWN;
3513 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3515 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3519 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3520 * @hw: pointer to the HW structure
3522 * In the case of a PHY power down to save power, or to turn off link during a
3523 * driver unload, or wake on lan is not enabled, restore the link to previous
3526 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3531 /* The PHY will retain its settings across a power down/up cycle */
3532 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3533 mii_reg |= MII_CR_POWER_DOWN;
3534 /* i210 Phy requires an additional bit for power up/down */
3535 if (hw->phy.type == e1000_phy_i210) {
3536 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3537 power_reg |= GS40G_CS_POWER_DOWN;
3538 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3540 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3545 * __e1000_read_phy_reg_hv - Read HV PHY register
3546 * @hw: pointer to the HW structure
3547 * @offset: register offset to be read
3548 * @data: pointer to the read data
3549 * @locked: semaphore has already been acquired or not
3551 * Acquires semaphore, if necessary, then reads the PHY register at offset
3552 * and stores the retrieved information in data. Release any acquired
3553 * semaphore before exiting.
3555 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3556 bool locked, bool page_set)
3559 u16 page = BM_PHY_REG_PAGE(offset);
3560 u16 reg = BM_PHY_REG_NUM(offset);
3561 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3563 DEBUGFUNC("__e1000_read_phy_reg_hv");
3566 ret_val = hw->phy.ops.acquire(hw);
3571 /* Page 800 works differently than the rest so it has its own func */
3572 if (page == BM_WUC_PAGE) {
3573 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3578 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3579 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3585 if (page == HV_INTC_FC_PAGE_START)
3588 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3589 /* Page is shifted left, PHY expects (page x 32) */
3590 ret_val = e1000_set_page_igp(hw,
3591 (page << IGP_PAGE_SHIFT));
3593 hw->phy.addr = phy_addr;
3600 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3601 page << IGP_PAGE_SHIFT, reg);
3603 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3607 hw->phy.ops.release(hw);
3613 * e1000_read_phy_reg_hv - Read HV PHY register
3614 * @hw: pointer to the HW structure
3615 * @offset: register offset to be read
3616 * @data: pointer to the read data
3618 * Acquires semaphore then reads the PHY register at offset and stores
3619 * the retrieved information in data. Release the acquired semaphore
3622 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3624 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3628 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3629 * @hw: pointer to the HW structure
3630 * @offset: register offset to be read
3631 * @data: pointer to the read data
3633 * Reads the PHY register at offset and stores the retrieved information
3634 * in data. Assumes semaphore already acquired.
3636 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3638 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3642 * e1000_read_phy_reg_page_hv - Read HV PHY register
3643 * @hw: pointer to the HW structure
3644 * @offset: register offset to write to
3645 * @data: data to write at register offset
3647 * Reads the PHY register at offset and stores the retrieved information
3648 * in data. Assumes semaphore already acquired and page already set.
3650 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3652 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3656 * __e1000_write_phy_reg_hv - Write HV PHY register
3657 * @hw: pointer to the HW structure
3658 * @offset: register offset to write to
3659 * @data: data to write at register offset
3660 * @locked: semaphore has already been acquired or not
3662 * Acquires semaphore, if necessary, then writes the data to PHY register
3663 * at the offset. Release any acquired semaphores before exiting.
3665 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3666 bool locked, bool page_set)
3669 u16 page = BM_PHY_REG_PAGE(offset);
3670 u16 reg = BM_PHY_REG_NUM(offset);
3671 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3673 DEBUGFUNC("__e1000_write_phy_reg_hv");
3676 ret_val = hw->phy.ops.acquire(hw);
3681 /* Page 800 works differently than the rest so it has its own func */
3682 if (page == BM_WUC_PAGE) {
3683 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3688 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3689 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3695 if (page == HV_INTC_FC_PAGE_START)
3699 * Workaround MDIO accesses being disabled after entering IEEE
3700 * Power Down (when bit 11 of the PHY Control register is set)
3702 if ((hw->phy.type == e1000_phy_82578) &&
3703 (hw->phy.revision >= 1) &&
3704 (hw->phy.addr == 2) &&
3705 !(MAX_PHY_REG_ADDRESS & reg) &&
3706 (data & (1 << 11))) {
3708 ret_val = e1000_access_phy_debug_regs_hv(hw,
3715 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3716 /* Page is shifted left, PHY expects (page x 32) */
3717 ret_val = e1000_set_page_igp(hw,
3718 (page << IGP_PAGE_SHIFT));
3720 hw->phy.addr = phy_addr;
3727 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3728 page << IGP_PAGE_SHIFT, reg);
3730 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3735 hw->phy.ops.release(hw);
3741 * e1000_write_phy_reg_hv - Write HV PHY register
3742 * @hw: pointer to the HW structure
3743 * @offset: register offset to write to
3744 * @data: data to write at register offset
3746 * Acquires semaphore then writes the data to PHY register at the offset.
3747 * Release the acquired semaphores before exiting.
3749 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3751 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3755 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3756 * @hw: pointer to the HW structure
3757 * @offset: register offset to write to
3758 * @data: data to write at register offset
3760 * Writes the data to PHY register at the offset. Assumes semaphore
3763 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3765 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3769 * e1000_write_phy_reg_page_hv - Write HV PHY register
3770 * @hw: pointer to the HW structure
3771 * @offset: register offset to write to
3772 * @data: data to write at register offset
3774 * Writes the data to PHY register at the offset. Assumes semaphore
3775 * already acquired and page already set.
3777 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3779 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3783 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3784 * @page: page to be accessed
3786 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page)
3790 if (page >= HV_INTC_FC_PAGE_START)
3797 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3798 * @hw: pointer to the HW structure
3799 * @offset: register offset to be read or written
3800 * @data: pointer to the data to be read or written
3801 * @read: determines if operation is read or write
3803 * Reads the PHY register at offset and stores the retreived information
3804 * in data. Assumes semaphore already acquired. Note that the procedure
3805 * to access these regs uses the address port and data port to read/write.
3806 * These accesses done with PHY address 2 and without using pages.
3808 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3809 u16 *data, bool read)
3815 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3817 /* This takes care of the difference with desktop vs mobile phy */
3818 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3819 I82578_ADDR_REG : I82577_ADDR_REG;
3820 data_reg = addr_reg + 1;
3822 /* All operations in this function are phy address 2 */
3825 /* masking with 0x3F to remove the page from offset */
3826 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3828 DEBUGOUT("Could not write the Address Offset port register\n");
3832 /* Read or write the data value next */
3834 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3836 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3839 DEBUGOUT("Could not access the Data port register\n");
3845 * e1000_link_stall_workaround_hv - Si workaround
3846 * @hw: pointer to the HW structure
3848 * This function works around a Si bug where the link partner can get
3849 * a link up indication before the PHY does. If small packets are sent
3850 * by the link partner they can be placed in the packet buffer without
3851 * being properly accounted for by the PHY and will stall preventing
3852 * further packets from being received. The workaround is to clear the
3853 * packet buffer after the PHY detects link up.
3855 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3857 s32 ret_val = E1000_SUCCESS;
3860 DEBUGFUNC("e1000_link_stall_workaround_hv");
3862 if (hw->phy.type != e1000_phy_82578)
3863 return E1000_SUCCESS;
3865 /* Do not apply workaround if in PHY loopback bit 14 set */
3866 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3867 if (data & PHY_CONTROL_LB)
3868 return E1000_SUCCESS;
3870 /* check if link is up and at 1Gbps */
3871 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3875 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3876 BM_CS_STATUS_SPEED_MASK;
3878 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3879 BM_CS_STATUS_SPEED_1000))
3880 return E1000_SUCCESS;
3884 /* flush the packets in the fifo buffer */
3885 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3886 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3887 HV_MUX_DATA_CTRL_FORCE_SPEED);
3891 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3892 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3896 * e1000_check_polarity_82577 - Checks the polarity.
3897 * @hw: pointer to the HW structure
3899 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3901 * Polarity is determined based on the PHY specific status register.
3903 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3905 struct e1000_phy_info *phy = &hw->phy;
3909 DEBUGFUNC("e1000_check_polarity_82577");
3911 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3914 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3915 ? e1000_rev_polarity_reversed
3916 : e1000_rev_polarity_normal;
3922 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3923 * @hw: pointer to the HW structure
3925 * Calls the PHY setup function to force speed and duplex.
3927 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3929 struct e1000_phy_info *phy = &hw->phy;
3934 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3936 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3940 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3942 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3948 if (phy->autoneg_wait_to_complete) {
3949 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3951 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3957 DEBUGOUT("Link taking longer than expected.\n");
3960 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3968 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3969 * @hw: pointer to the HW structure
3971 * Read PHY status to determine if link is up. If link is up, then
3972 * set/determine 10base-T extended distance and polarity correction. Read
3973 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3974 * determine on the cable length, local and remote receiver.
3976 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3978 struct e1000_phy_info *phy = &hw->phy;
3983 DEBUGFUNC("e1000_get_phy_info_82577");
3985 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3990 DEBUGOUT("Phy info is only valid if link is up\n");
3991 return -E1000_ERR_CONFIG;
3994 phy->polarity_correction = true;
3996 ret_val = e1000_check_polarity_82577(hw);
4000 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
4004 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
4006 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
4007 I82577_PHY_STATUS2_SPEED_1000MBPS) {
4008 ret_val = hw->phy.ops.get_cable_length(hw);
4012 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4016 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4017 ? e1000_1000t_rx_status_ok
4018 : e1000_1000t_rx_status_not_ok;
4020 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4021 ? e1000_1000t_rx_status_ok
4022 : e1000_1000t_rx_status_not_ok;
4024 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4025 phy->local_rx = e1000_1000t_rx_status_undefined;
4026 phy->remote_rx = e1000_1000t_rx_status_undefined;
4029 return E1000_SUCCESS;
4033 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4034 * @hw: pointer to the HW structure
4036 * Reads the diagnostic status register and verifies result is valid before
4037 * placing it in the phy_cable_length field.
4039 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4041 struct e1000_phy_info *phy = &hw->phy;
4043 u16 phy_data, length;
4045 DEBUGFUNC("e1000_get_cable_length_82577");
4047 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4051 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4052 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
4054 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4055 ret_val = -E1000_ERR_PHY;
4057 phy->cable_length = length;
4059 return E1000_SUCCESS;
4063 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4064 * @hw: pointer to the HW structure
4065 * @offset: register offset to write to
4066 * @data: data to write at register offset
4068 * Acquires semaphore, if necessary, then writes the data to PHY register
4069 * at the offset. Release any acquired semaphores before exiting.
4071 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4074 u16 page = offset >> GS40G_PAGE_SHIFT;
4076 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4078 offset = offset & GS40G_OFFSET_MASK;
4079 ret_val = hw->phy.ops.acquire(hw);
4083 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4086 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4089 hw->phy.ops.release(hw);
4094 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4095 * @hw: pointer to the HW structure
4096 * @offset: lower half is register offset to read to
4097 * upper half is page to use.
4098 * @data: data to read at register offset
4100 * Acquires semaphore, if necessary, then reads the data in the PHY register
4101 * at the offset. Release any acquired semaphores before exiting.
4103 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4106 u16 page = offset >> GS40G_PAGE_SHIFT;
4108 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4110 offset = offset & GS40G_OFFSET_MASK;
4111 ret_val = hw->phy.ops.acquire(hw);
4115 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4118 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4121 hw->phy.ops.release(hw);