1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
37 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table[] = {
40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
41 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
42 (sizeof(e1000_m88_cable_length_table) / \
43 sizeof(e1000_m88_cable_length_table[0]))
45 static const u16 e1000_igp_2_cable_length_table[] = {
46 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
47 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
48 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
49 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
50 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
51 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
52 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
54 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
55 (sizeof(e1000_igp_2_cable_length_table) / \
56 sizeof(e1000_igp_2_cable_length_table[0]))
59 * e1000_init_phy_ops_generic - Initialize PHY function pointers
60 * @hw: pointer to the HW structure
62 * Setups up the function pointers to no-op functions
64 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
66 struct e1000_phy_info *phy = &hw->phy;
67 DEBUGFUNC("e1000_init_phy_ops_generic");
69 /* Initialize function pointers */
70 phy->ops.init_params = e1000_null_ops_generic;
71 phy->ops.acquire = e1000_null_ops_generic;
72 phy->ops.check_polarity = e1000_null_ops_generic;
73 phy->ops.check_reset_block = e1000_null_ops_generic;
74 phy->ops.commit = e1000_null_ops_generic;
75 phy->ops.force_speed_duplex = e1000_null_ops_generic;
76 phy->ops.get_cfg_done = e1000_null_ops_generic;
77 phy->ops.get_cable_length = e1000_null_ops_generic;
78 phy->ops.get_info = e1000_null_ops_generic;
79 phy->ops.read_reg = e1000_null_read_reg;
80 phy->ops.read_reg_locked = e1000_null_read_reg;
81 phy->ops.release = e1000_null_phy_generic;
82 phy->ops.reset = e1000_null_ops_generic;
83 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
84 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
85 phy->ops.write_reg = e1000_null_write_reg;
86 phy->ops.write_reg_locked = e1000_null_write_reg;
87 phy->ops.power_up = e1000_null_phy_generic;
88 phy->ops.power_down = e1000_null_phy_generic;
92 * e1000_null_read_reg - No-op function, return 0
93 * @hw: pointer to the HW structure
95 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
97 DEBUGFUNC("e1000_null_read_reg");
102 * e1000_null_phy_generic - No-op function, return void
103 * @hw: pointer to the HW structure
105 void e1000_null_phy_generic(struct e1000_hw *hw)
107 DEBUGFUNC("e1000_null_phy_generic");
112 * e1000_null_lplu_state - No-op function, return 0
113 * @hw: pointer to the HW structure
115 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
117 DEBUGFUNC("e1000_null_lplu_state");
118 return E1000_SUCCESS;
122 * e1000_null_write_reg - No-op function, return 0
123 * @hw: pointer to the HW structure
125 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
127 DEBUGFUNC("e1000_null_write_reg");
128 return E1000_SUCCESS;
132 * e1000_check_reset_block_generic - Check if PHY reset is blocked
133 * @hw: pointer to the HW structure
135 * Read the PHY management control register and check whether a PHY reset
136 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
137 * return E1000_BLK_PHY_RESET (12).
139 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
143 DEBUGFUNC("e1000_check_reset_block");
145 manc = E1000_READ_REG(hw, E1000_MANC);
147 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
148 E1000_BLK_PHY_RESET : E1000_SUCCESS;
152 * e1000_get_phy_id - Retrieve the PHY ID and revision
153 * @hw: pointer to the HW structure
155 * Reads the PHY registers and stores the PHY ID and possibly the PHY
156 * revision in the hardware structure.
158 s32 e1000_get_phy_id(struct e1000_hw *hw)
160 struct e1000_phy_info *phy = &hw->phy;
161 s32 ret_val = E1000_SUCCESS;
164 DEBUGFUNC("e1000_get_phy_id");
166 if (!(phy->ops.read_reg))
169 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
173 phy->id = (u32)(phy_id << 16);
175 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
179 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
180 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
187 * e1000_phy_reset_dsp_generic - Reset PHY DSP
188 * @hw: pointer to the HW structure
190 * Reset the digital signal processor.
192 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
194 s32 ret_val = E1000_SUCCESS;
196 DEBUGFUNC("e1000_phy_reset_dsp_generic");
198 if (!(hw->phy.ops.write_reg))
201 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
205 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
212 * e1000_read_phy_reg_mdic - Read MDI control register
213 * @hw: pointer to the HW structure
214 * @offset: register offset to be read
215 * @data: pointer to the read data
217 * Reads the MDI control register in the PHY at offset and stores the
218 * information read to data.
220 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
222 struct e1000_phy_info *phy = &hw->phy;
224 s32 ret_val = E1000_SUCCESS;
226 DEBUGFUNC("e1000_read_phy_reg_mdic");
228 if (offset > MAX_PHY_REG_ADDRESS) {
229 DEBUGOUT1("PHY Address %d is out of range\n", offset);
230 return -E1000_ERR_PARAM;
234 * Set up Op-code, Phy Address, and register offset in the MDI
235 * Control register. The MAC will take care of interfacing with the
236 * PHY to retrieve the desired data.
238 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
239 (phy->addr << E1000_MDIC_PHY_SHIFT) |
240 (E1000_MDIC_OP_READ));
242 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
245 * Poll the ready bit to see if the MDI read completed
246 * Increasing the time out as testing showed failures with
249 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
251 mdic = E1000_READ_REG(hw, E1000_MDIC);
252 if (mdic & E1000_MDIC_READY)
255 if (!(mdic & E1000_MDIC_READY)) {
256 DEBUGOUT("MDI Read did not complete\n");
257 ret_val = -E1000_ERR_PHY;
260 if (mdic & E1000_MDIC_ERROR) {
261 DEBUGOUT("MDI Error\n");
262 ret_val = -E1000_ERR_PHY;
272 * e1000_write_phy_reg_mdic - Write MDI control register
273 * @hw: pointer to the HW structure
274 * @offset: register offset to write to
275 * @data: data to write to register at offset
277 * Writes data to MDI control register in the PHY at offset.
279 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
281 struct e1000_phy_info *phy = &hw->phy;
283 s32 ret_val = E1000_SUCCESS;
285 DEBUGFUNC("e1000_write_phy_reg_mdic");
287 if (offset > MAX_PHY_REG_ADDRESS) {
288 DEBUGOUT1("PHY Address %d is out of range\n", offset);
289 return -E1000_ERR_PARAM;
293 * Set up Op-code, Phy Address, and register offset in the MDI
294 * Control register. The MAC will take care of interfacing with the
295 * PHY to retrieve the desired data.
297 mdic = (((u32)data) |
298 (offset << E1000_MDIC_REG_SHIFT) |
299 (phy->addr << E1000_MDIC_PHY_SHIFT) |
300 (E1000_MDIC_OP_WRITE));
302 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
305 * Poll the ready bit to see if the MDI read completed
306 * Increasing the time out as testing showed failures with
309 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
311 mdic = E1000_READ_REG(hw, E1000_MDIC);
312 if (mdic & E1000_MDIC_READY)
315 if (!(mdic & E1000_MDIC_READY)) {
316 DEBUGOUT("MDI Write did not complete\n");
317 ret_val = -E1000_ERR_PHY;
320 if (mdic & E1000_MDIC_ERROR) {
321 DEBUGOUT("MDI Error\n");
322 ret_val = -E1000_ERR_PHY;
331 * e1000_read_phy_reg_i2c - Read PHY register using i2c
332 * @hw: pointer to the HW structure
333 * @offset: register offset to be read
334 * @data: pointer to the read data
336 * Reads the PHY register at offset using the i2c interface and stores the
337 * retrieved information in data.
339 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
341 struct e1000_phy_info *phy = &hw->phy;
344 DEBUGFUNC("e1000_read_phy_reg_i2c");
347 * Set up Op-code, Phy Address, and register address in the I2CCMD
348 * register. The MAC will take care of interfacing with the
349 * PHY to retrieve the desired data.
351 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
352 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
353 (E1000_I2CCMD_OPCODE_READ));
355 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
357 /* Poll the ready bit to see if the I2C read completed */
358 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
360 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
361 if (i2ccmd & E1000_I2CCMD_READY)
364 if (!(i2ccmd & E1000_I2CCMD_READY)) {
365 DEBUGOUT("I2CCMD Read did not complete\n");
366 return -E1000_ERR_PHY;
368 if (i2ccmd & E1000_I2CCMD_ERROR) {
369 DEBUGOUT("I2CCMD Error bit set\n");
370 return -E1000_ERR_PHY;
373 /* Need to byte-swap the 16-bit value. */
374 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
376 return E1000_SUCCESS;
380 * e1000_write_phy_reg_i2c - Write PHY register using i2c
381 * @hw: pointer to the HW structure
382 * @offset: register offset to write to
383 * @data: data to write at register offset
385 * Writes the data to PHY register at the offset using the i2c interface.
387 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
389 struct e1000_phy_info *phy = &hw->phy;
391 u16 phy_data_swapped;
393 DEBUGFUNC("e1000_write_phy_reg_i2c");
395 /* Swap the data bytes for the I2C interface */
396 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
399 * Set up Op-code, Phy Address, and register address in the I2CCMD
400 * register. The MAC will take care of interfacing with the
401 * PHY to retrieve the desired data.
403 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
404 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
405 E1000_I2CCMD_OPCODE_WRITE |
408 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
410 /* Poll the ready bit to see if the I2C read completed */
411 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
413 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
414 if (i2ccmd & E1000_I2CCMD_READY)
417 if (!(i2ccmd & E1000_I2CCMD_READY)) {
418 DEBUGOUT("I2CCMD Write did not complete\n");
419 return -E1000_ERR_PHY;
421 if (i2ccmd & E1000_I2CCMD_ERROR) {
422 DEBUGOUT("I2CCMD Error bit set\n");
423 return -E1000_ERR_PHY;
426 return E1000_SUCCESS;
430 * e1000_read_phy_reg_m88 - Read m88 PHY register
431 * @hw: pointer to the HW structure
432 * @offset: register offset to be read
433 * @data: pointer to the read data
435 * Acquires semaphore, if necessary, then reads the PHY register at offset
436 * and storing the retrieved information in data. Release any acquired
437 * semaphores before exiting.
439 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
441 s32 ret_val = E1000_SUCCESS;
443 DEBUGFUNC("e1000_read_phy_reg_m88");
445 if (!(hw->phy.ops.acquire))
448 ret_val = hw->phy.ops.acquire(hw);
452 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
455 hw->phy.ops.release(hw);
462 * e1000_write_phy_reg_m88 - Write m88 PHY register
463 * @hw: pointer to the HW structure
464 * @offset: register offset to write to
465 * @data: data to write at register offset
467 * Acquires semaphore, if necessary, then writes the data to PHY register
468 * at the offset. Release any acquired semaphores before exiting.
470 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
472 s32 ret_val = E1000_SUCCESS;
474 DEBUGFUNC("e1000_write_phy_reg_m88");
476 if (!(hw->phy.ops.acquire))
479 ret_val = hw->phy.ops.acquire(hw);
483 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
486 hw->phy.ops.release(hw);
493 * __e1000_read_phy_reg_igp - Read igp PHY register
494 * @hw: pointer to the HW structure
495 * @offset: register offset to be read
496 * @data: pointer to the read data
497 * @locked: semaphore has already been acquired or not
499 * Acquires semaphore, if necessary, then reads the PHY register at offset
500 * and stores the retrieved information in data. Release any acquired
501 * semaphores before exiting.
503 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
506 s32 ret_val = E1000_SUCCESS;
508 DEBUGFUNC("__e1000_read_phy_reg_igp");
511 if (!(hw->phy.ops.acquire))
514 ret_val = hw->phy.ops.acquire(hw);
519 if (offset > MAX_PHY_MULTI_PAGE_REG) {
520 ret_val = e1000_write_phy_reg_mdic(hw,
521 IGP01E1000_PHY_PAGE_SELECT,
527 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
532 hw->phy.ops.release(hw);
538 * e1000_read_phy_reg_igp - Read igp PHY register
539 * @hw: pointer to the HW structure
540 * @offset: register offset to be read
541 * @data: pointer to the read data
543 * Acquires semaphore then reads the PHY register at offset and stores the
544 * retrieved information in data.
545 * Release the acquired semaphore before exiting.
547 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
549 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
553 * e1000_read_phy_reg_igp_locked - Read igp PHY register
554 * @hw: pointer to the HW structure
555 * @offset: register offset to be read
556 * @data: pointer to the read data
558 * Reads the PHY register at offset and stores the retrieved information
559 * in data. Assumes semaphore already acquired.
561 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
563 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
567 * e1000_write_phy_reg_igp - Write igp PHY register
568 * @hw: pointer to the HW structure
569 * @offset: register offset to write to
570 * @data: data to write at register offset
571 * @locked: semaphore has already been acquired or not
573 * Acquires semaphore, if necessary, then writes the data to PHY register
574 * at the offset. Release any acquired semaphores before exiting.
576 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
579 s32 ret_val = E1000_SUCCESS;
581 DEBUGFUNC("e1000_write_phy_reg_igp");
584 if (!(hw->phy.ops.acquire))
587 ret_val = hw->phy.ops.acquire(hw);
592 if (offset > MAX_PHY_MULTI_PAGE_REG) {
593 ret_val = e1000_write_phy_reg_mdic(hw,
594 IGP01E1000_PHY_PAGE_SELECT,
600 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
605 hw->phy.ops.release(hw);
612 * e1000_write_phy_reg_igp - Write igp PHY register
613 * @hw: pointer to the HW structure
614 * @offset: register offset to write to
615 * @data: data to write at register offset
617 * Acquires semaphore then writes the data to PHY register
618 * at the offset. Release any acquired semaphores before exiting.
620 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
622 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
626 * e1000_write_phy_reg_igp_locked - Write igp PHY register
627 * @hw: pointer to the HW structure
628 * @offset: register offset to write to
629 * @data: data to write at register offset
631 * Writes the data to PHY register at the offset.
632 * Assumes semaphore already acquired.
634 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
636 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
640 * __e1000_read_kmrn_reg - Read kumeran register
641 * @hw: pointer to the HW structure
642 * @offset: register offset to be read
643 * @data: pointer to the read data
644 * @locked: semaphore has already been acquired or not
646 * Acquires semaphore, if necessary. Then reads the PHY register at offset
647 * using the kumeran interface. The information retrieved is stored in data.
648 * Release any acquired semaphores before exiting.
650 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
654 s32 ret_val = E1000_SUCCESS;
656 DEBUGFUNC("__e1000_read_kmrn_reg");
659 if (!(hw->phy.ops.acquire))
662 ret_val = hw->phy.ops.acquire(hw);
667 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
668 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
669 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
673 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
674 *data = (u16)kmrnctrlsta;
677 hw->phy.ops.release(hw);
684 * e1000_read_kmrn_reg_generic - Read kumeran register
685 * @hw: pointer to the HW structure
686 * @offset: register offset to be read
687 * @data: pointer to the read data
689 * Acquires semaphore then reads the PHY register at offset using the
690 * kumeran interface. The information retrieved is stored in data.
691 * Release the acquired semaphore before exiting.
693 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
695 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
699 * e1000_read_kmrn_reg_locked - Read kumeran register
700 * @hw: pointer to the HW structure
701 * @offset: register offset to be read
702 * @data: pointer to the read data
704 * Reads the PHY register at offset using the kumeran interface. The
705 * information retrieved is stored in data.
706 * Assumes semaphore already acquired.
708 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
710 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
714 * __e1000_write_kmrn_reg - Write kumeran register
715 * @hw: pointer to the HW structure
716 * @offset: register offset to write to
717 * @data: data to write at register offset
718 * @locked: semaphore has already been acquired or not
720 * Acquires semaphore, if necessary. Then write the data to PHY register
721 * at the offset using the kumeran interface. Release any acquired semaphores
724 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
728 s32 ret_val = E1000_SUCCESS;
730 DEBUGFUNC("e1000_write_kmrn_reg_generic");
733 if (!(hw->phy.ops.acquire))
736 ret_val = hw->phy.ops.acquire(hw);
741 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
742 E1000_KMRNCTRLSTA_OFFSET) | data;
743 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
748 hw->phy.ops.release(hw);
755 * e1000_write_kmrn_reg_generic - Write kumeran register
756 * @hw: pointer to the HW structure
757 * @offset: register offset to write to
758 * @data: data to write at register offset
760 * Acquires semaphore then writes the data to the PHY register at the offset
761 * using the kumeran interface. Release the acquired semaphore before exiting.
763 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
765 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
769 * e1000_write_kmrn_reg_locked - Write kumeran register
770 * @hw: pointer to the HW structure
771 * @offset: register offset to write to
772 * @data: data to write at register offset
774 * Write the data to PHY register at the offset using the kumeran interface.
775 * Assumes semaphore already acquired.
777 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
779 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
783 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
784 * @hw: pointer to the HW structure
786 * Sets up Carrier-sense on Transmit and downshift values.
788 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
793 DEBUGFUNC("e1000_copper_link_setup_82577");
795 if (hw->phy.reset_disable) {
796 ret_val = E1000_SUCCESS;
800 if (hw->phy.type == e1000_phy_82580) {
801 ret_val = hw->phy.ops.reset(hw);
803 DEBUGOUT("Error resetting the PHY.\n");
808 /* Enable CRS on Tx. This must be set for half-duplex operation. */
809 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
813 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
815 /* Enable downshift */
816 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
818 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
825 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
826 * @hw: pointer to the HW structure
828 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
829 * and downshift values are set also.
831 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
833 struct e1000_phy_info *phy = &hw->phy;
837 DEBUGFUNC("e1000_copper_link_setup_m88");
839 if (phy->reset_disable) {
840 ret_val = E1000_SUCCESS;
844 /* Enable CRS on Tx. This must be set for half-duplex operation. */
845 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
849 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
853 * MDI/MDI-X = 0 (default)
854 * 0 - Auto for all speeds
857 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
859 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
863 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
866 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
869 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
873 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
879 * disable_polarity_correction = 0 (default)
880 * Automatic Correction for Reversed Cable Polarity
884 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
885 if (phy->disable_polarity_correction == 1)
886 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
888 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
892 if (phy->revision < E1000_REVISION_4) {
894 * Force TX_CLK in the Extended PHY Specific Control Register
897 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
902 phy_data |= M88E1000_EPSCR_TX_CLK_25;
904 if ((phy->revision == E1000_REVISION_2) &&
905 (phy->id == M88E1111_I_PHY_ID)) {
906 /* 82573L PHY - set the downshift counter to 5x. */
907 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
908 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
910 /* Configure Master and Slave downshift values */
911 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
912 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
913 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
914 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
916 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
922 /* Commit the changes. */
923 ret_val = phy->ops.commit(hw);
925 DEBUGOUT("Error committing the PHY changes\n");
934 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
935 * @hw: pointer to the HW structure
937 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
938 * Also enables and sets the downshift parameters.
940 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
942 struct e1000_phy_info *phy = &hw->phy;
946 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
948 if (phy->reset_disable) {
949 ret_val = E1000_SUCCESS;
953 /* Enable CRS on Tx. This must be set for half-duplex operation. */
954 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
960 * MDI/MDI-X = 0 (default)
961 * 0 - Auto for all speeds
964 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
966 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
970 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
973 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
976 /* M88E1112 does not support this mode) */
977 if (phy->id != M88E1112_E_PHY_ID) {
978 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
983 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
989 * disable_polarity_correction = 0 (default)
990 * Automatic Correction for Reversed Cable Polarity
994 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
995 if (phy->disable_polarity_correction == 1)
996 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
998 /* Enable downshift and setting it to X6 */
999 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1000 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1001 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1003 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1007 /* Commit the changes. */
1008 ret_val = phy->ops.commit(hw);
1010 DEBUGOUT("Error committing the PHY changes\n");
1019 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1020 * @hw: pointer to the HW structure
1022 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1025 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1027 struct e1000_phy_info *phy = &hw->phy;
1031 DEBUGFUNC("e1000_copper_link_setup_igp");
1033 if (phy->reset_disable) {
1034 ret_val = E1000_SUCCESS;
1038 ret_val = hw->phy.ops.reset(hw);
1040 DEBUGOUT("Error resetting the PHY.\n");
1045 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1046 * timeout issues when LFS is enabled.
1050 /* disable lplu d0 during driver init */
1051 if (hw->phy.ops.set_d0_lplu_state) {
1052 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1054 DEBUGOUT("Error Disabling LPLU D0\n");
1058 /* Configure mdi-mdix settings */
1059 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1063 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1065 switch (phy->mdix) {
1067 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1070 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1074 data |= IGP01E1000_PSCR_AUTO_MDIX;
1077 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1081 /* set auto-master slave resolution settings */
1082 if (hw->mac.autoneg) {
1084 * when autonegotiation advertisement is only 1000Mbps then we
1085 * should disable SmartSpeed and enable Auto MasterSlave
1086 * resolution as hardware default.
1088 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1089 /* Disable SmartSpeed */
1090 ret_val = phy->ops.read_reg(hw,
1091 IGP01E1000_PHY_PORT_CONFIG,
1096 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1097 ret_val = phy->ops.write_reg(hw,
1098 IGP01E1000_PHY_PORT_CONFIG,
1103 /* Set auto Master/Slave resolution process */
1104 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1108 data &= ~CR_1000T_MS_ENABLE;
1109 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1114 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1118 /* load defaults for future use */
1119 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1120 ((data & CR_1000T_MS_VALUE) ?
1121 e1000_ms_force_master :
1122 e1000_ms_force_slave) :
1125 switch (phy->ms_type) {
1126 case e1000_ms_force_master:
1127 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1129 case e1000_ms_force_slave:
1130 data |= CR_1000T_MS_ENABLE;
1131 data &= ~(CR_1000T_MS_VALUE);
1134 data &= ~CR_1000T_MS_ENABLE;
1138 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1148 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1149 * @hw: pointer to the HW structure
1151 * Performs initial bounds checking on autoneg advertisement parameter, then
1152 * configure to advertise the full capability. Setup the PHY to autoneg
1153 * and restart the negotiation process between the link partner. If
1154 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1156 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1158 struct e1000_phy_info *phy = &hw->phy;
1162 DEBUGFUNC("e1000_copper_link_autoneg");
1165 * Perform some bounds checking on the autoneg advertisement
1168 phy->autoneg_advertised &= phy->autoneg_mask;
1171 * If autoneg_advertised is zero, we assume it was not defaulted
1172 * by the calling code so we set to advertise full capability.
1174 if (phy->autoneg_advertised == 0)
1175 phy->autoneg_advertised = phy->autoneg_mask;
1177 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1178 ret_val = e1000_phy_setup_autoneg(hw);
1180 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1183 DEBUGOUT("Restarting Auto-Neg\n");
1186 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1187 * the Auto Neg Restart bit in the PHY control register.
1189 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1193 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1194 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1199 * Does the user want to wait for Auto-Neg to complete here, or
1200 * check at a later time (for example, callback routine).
1202 if (phy->autoneg_wait_to_complete) {
1203 ret_val = hw->mac.ops.wait_autoneg(hw);
1205 DEBUGOUT("Error while waiting for "
1206 "autoneg to complete\n");
1211 hw->mac.get_link_status = TRUE;
1218 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1219 * @hw: pointer to the HW structure
1221 * Reads the MII auto-neg advertisement register and/or the 1000T control
1222 * register and if the PHY is already setup for auto-negotiation, then
1223 * return successful. Otherwise, setup advertisement and flow control to
1224 * the appropriate values for the wanted auto-negotiation.
1226 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1228 struct e1000_phy_info *phy = &hw->phy;
1230 u16 mii_autoneg_adv_reg;
1231 u16 mii_1000t_ctrl_reg = 0;
1233 DEBUGFUNC("e1000_phy_setup_autoneg");
1235 phy->autoneg_advertised &= phy->autoneg_mask;
1237 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1238 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1242 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1243 /* Read the MII 1000Base-T Control Register (Address 9). */
1244 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1245 &mii_1000t_ctrl_reg);
1251 * Need to parse both autoneg_advertised and fc and set up
1252 * the appropriate PHY registers. First we will parse for
1253 * autoneg_advertised software override. Since we can advertise
1254 * a plethora of combinations, we need to check each bit
1259 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1260 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1261 * the 1000Base-T Control Register (Address 9).
1263 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1264 NWAY_AR_100TX_HD_CAPS |
1265 NWAY_AR_10T_FD_CAPS |
1266 NWAY_AR_10T_HD_CAPS);
1267 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1269 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1271 /* Do we want to advertise 10 Mb Half Duplex? */
1272 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1273 DEBUGOUT("Advertise 10mb Half duplex\n");
1274 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1277 /* Do we want to advertise 10 Mb Full Duplex? */
1278 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1279 DEBUGOUT("Advertise 10mb Full duplex\n");
1280 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1283 /* Do we want to advertise 100 Mb Half Duplex? */
1284 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1285 DEBUGOUT("Advertise 100mb Half duplex\n");
1286 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1289 /* Do we want to advertise 100 Mb Full Duplex? */
1290 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1291 DEBUGOUT("Advertise 100mb Full duplex\n");
1292 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1295 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1296 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1297 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1299 /* Do we want to advertise 1000 Mb Full Duplex? */
1300 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1301 DEBUGOUT("Advertise 1000mb Full duplex\n");
1302 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1306 * Check for a software override of the flow control settings, and
1307 * setup the PHY advertisement registers accordingly. If
1308 * auto-negotiation is enabled, then software will have to set the
1309 * "PAUSE" bits to the correct value in the Auto-Negotiation
1310 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1313 * The possible values of the "fc" parameter are:
1314 * 0: Flow control is completely disabled
1315 * 1: Rx flow control is enabled (we can receive pause frames
1316 * but not send pause frames).
1317 * 2: Tx flow control is enabled (we can send pause frames
1318 * but we do not support receiving pause frames).
1319 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1320 * other: No software override. The flow control configuration
1321 * in the EEPROM is used.
1323 switch (hw->fc.current_mode) {
1326 * Flow control (Rx & Tx) is completely disabled by a
1327 * software over-ride.
1329 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1331 case e1000_fc_rx_pause:
1333 * Rx Flow control is enabled, and Tx Flow control is
1334 * disabled, by a software over-ride.
1336 * Since there really isn't a way to advertise that we are
1337 * capable of Rx Pause ONLY, we will advertise that we
1338 * support both symmetric and asymmetric Rx PAUSE. Later
1339 * (in e1000_config_fc_after_link_up) we will disable the
1340 * hw's ability to send PAUSE frames.
1342 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1344 case e1000_fc_tx_pause:
1346 * Tx Flow control is enabled, and Rx Flow control is
1347 * disabled, by a software over-ride.
1349 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1350 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1354 * Flow control (both Rx and Tx) is enabled by a software
1357 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1360 DEBUGOUT("Flow control param set incorrectly\n");
1361 ret_val = -E1000_ERR_CONFIG;
1365 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1369 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1371 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1372 ret_val = phy->ops.write_reg(hw,
1374 mii_1000t_ctrl_reg);
1384 * e1000_setup_copper_link_generic - Configure copper link settings
1385 * @hw: pointer to the HW structure
1387 * Calls the appropriate function to configure the link for auto-neg or forced
1388 * speed and duplex. Then we check for link, once link is established calls
1389 * to configure collision distance and flow control are called. If link is
1390 * not established, we return -E1000_ERR_PHY (-2).
1392 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1397 DEBUGFUNC("e1000_setup_copper_link_generic");
1399 if (hw->mac.autoneg) {
1401 * Setup autoneg and flow control advertisement and perform
1404 ret_val = e1000_copper_link_autoneg(hw);
1409 * PHY will be set to 10H, 10F, 100H or 100F
1410 * depending on user settings.
1412 DEBUGOUT("Forcing Speed and Duplex\n");
1413 ret_val = hw->phy.ops.force_speed_duplex(hw);
1415 DEBUGOUT("Error Forcing Speed and Duplex\n");
1421 * Check link status. Wait up to 100 microseconds for link to become
1424 ret_val = e1000_phy_has_link_generic(hw,
1425 COPPER_LINK_UP_LIMIT,
1432 DEBUGOUT("Valid link established!!!\n");
1433 e1000_config_collision_dist_generic(hw);
1434 ret_val = e1000_config_fc_after_link_up_generic(hw);
1436 DEBUGOUT("Unable to establish link!!!\n");
1444 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1445 * @hw: pointer to the HW structure
1447 * Calls the PHY setup function to force speed and duplex. Clears the
1448 * auto-crossover to force MDI manually. Waits for link and returns
1449 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1451 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1453 struct e1000_phy_info *phy = &hw->phy;
1458 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1460 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1464 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1466 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1471 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1472 * forced whenever speed and duplex are forced.
1474 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1478 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1479 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1481 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1485 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1489 if (phy->autoneg_wait_to_complete) {
1490 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1492 ret_val = e1000_phy_has_link_generic(hw,
1500 DEBUGOUT("Link taking longer than expected.\n");
1503 ret_val = e1000_phy_has_link_generic(hw,
1516 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1517 * @hw: pointer to the HW structure
1519 * Calls the PHY setup function to force speed and duplex. Clears the
1520 * auto-crossover to force MDI manually. Resets the PHY to commit the
1521 * changes. If time expires while waiting for link up, we reset the DSP.
1522 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1523 * successful completion, else return corresponding error code.
1525 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1527 struct e1000_phy_info *phy = &hw->phy;
1532 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1535 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1536 * forced whenever speed and duplex are forced.
1538 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1542 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1543 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1547 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1549 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1553 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1555 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1559 /* Reset the phy to commit changes. */
1560 ret_val = hw->phy.ops.commit(hw);
1564 if (phy->autoneg_wait_to_complete) {
1565 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1567 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1573 if (hw->phy.type != e1000_phy_m88 ||
1574 hw->phy.id == I347AT4_E_PHY_ID ||
1575 hw->phy.id == M88E1340M_E_PHY_ID ||
1576 hw->phy.id == M88E1112_E_PHY_ID) {
1577 DEBUGOUT("Link taking longer than expected.\n");
1580 * We didn't get link.
1581 * Reset the DSP and cross our fingers.
1583 ret_val = phy->ops.write_reg(hw,
1584 M88E1000_PHY_PAGE_SELECT,
1588 ret_val = e1000_phy_reset_dsp_generic(hw);
1595 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1601 if (hw->phy.type != e1000_phy_m88 ||
1602 hw->phy.id == I347AT4_E_PHY_ID ||
1603 hw->phy.id == M88E1340M_E_PHY_ID ||
1604 hw->phy.id == M88E1112_E_PHY_ID)
1607 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1612 * Resetting the phy means we need to re-force TX_CLK in the
1613 * Extended PHY Specific Control Register to 25MHz clock from
1614 * the reset value of 2.5MHz.
1616 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1617 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1622 * In addition, we must re-enable CRS on Tx for both half and full
1625 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1629 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1630 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1637 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1638 * @hw: pointer to the HW structure
1640 * Forces the speed and duplex settings of the PHY.
1641 * This is a function pointer entry point only called by
1642 * PHY setup routines.
1644 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1646 struct e1000_phy_info *phy = &hw->phy;
1651 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1653 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1657 e1000_phy_force_speed_duplex_setup(hw, &data);
1659 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1663 /* Disable MDI-X support for 10/100 */
1664 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1668 data &= ~IFE_PMC_AUTO_MDIX;
1669 data &= ~IFE_PMC_FORCE_MDIX;
1671 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1675 DEBUGOUT1("IFE PMC: %X\n", data);
1679 if (phy->autoneg_wait_to_complete) {
1680 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1682 ret_val = e1000_phy_has_link_generic(hw,
1690 DEBUGOUT("Link taking longer than expected.\n");
1693 ret_val = e1000_phy_has_link_generic(hw,
1706 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1707 * @hw: pointer to the HW structure
1708 * @phy_ctrl: pointer to current value of PHY_CONTROL
1710 * Forces speed and duplex on the PHY by doing the following: disable flow
1711 * control, force speed/duplex on the MAC, disable auto speed detection,
1712 * disable auto-negotiation, configure duplex, configure speed, configure
1713 * the collision distance, write configuration to CTRL register. The
1714 * caller must write to the PHY_CONTROL register for these settings to
1717 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1719 struct e1000_mac_info *mac = &hw->mac;
1722 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1724 /* Turn off flow control when forcing speed/duplex */
1725 hw->fc.current_mode = e1000_fc_none;
1727 /* Force speed/duplex on the mac */
1728 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1729 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1730 ctrl &= ~E1000_CTRL_SPD_SEL;
1732 /* Disable Auto Speed Detection */
1733 ctrl &= ~E1000_CTRL_ASDE;
1735 /* Disable autoneg on the phy */
1736 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1738 /* Forcing Full or Half Duplex? */
1739 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1740 ctrl &= ~E1000_CTRL_FD;
1741 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1742 DEBUGOUT("Half Duplex\n");
1744 ctrl |= E1000_CTRL_FD;
1745 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1746 DEBUGOUT("Full Duplex\n");
1749 /* Forcing 10mb or 100mb? */
1750 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1751 ctrl |= E1000_CTRL_SPD_100;
1752 *phy_ctrl |= MII_CR_SPEED_100;
1753 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1754 DEBUGOUT("Forcing 100mb\n");
1756 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1757 *phy_ctrl |= MII_CR_SPEED_10;
1758 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1759 DEBUGOUT("Forcing 10mb\n");
1762 e1000_config_collision_dist_generic(hw);
1764 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1768 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1769 * @hw: pointer to the HW structure
1770 * @active: boolean used to enable/disable lplu
1772 * Success returns 0, Failure returns 1
1774 * The low power link up (lplu) state is set to the power management level D3
1775 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
1776 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1777 * is used during Dx states where the power conservation is most important.
1778 * During driver activity, SmartSpeed should be enabled so performance is
1781 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1783 struct e1000_phy_info *phy = &hw->phy;
1784 s32 ret_val = E1000_SUCCESS;
1787 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1789 if (!(hw->phy.ops.read_reg))
1792 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1797 data &= ~IGP02E1000_PM_D3_LPLU;
1798 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1803 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1804 * during Dx states where the power conservation is most
1805 * important. During driver activity we should enable
1806 * SmartSpeed, so performance is maintained.
1808 if (phy->smart_speed == e1000_smart_speed_on) {
1809 ret_val = phy->ops.read_reg(hw,
1810 IGP01E1000_PHY_PORT_CONFIG,
1815 data |= IGP01E1000_PSCFR_SMART_SPEED;
1816 ret_val = phy->ops.write_reg(hw,
1817 IGP01E1000_PHY_PORT_CONFIG,
1821 } else if (phy->smart_speed == e1000_smart_speed_off) {
1822 ret_val = phy->ops.read_reg(hw,
1823 IGP01E1000_PHY_PORT_CONFIG,
1828 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1829 ret_val = phy->ops.write_reg(hw,
1830 IGP01E1000_PHY_PORT_CONFIG,
1835 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1836 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1837 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1838 data |= IGP02E1000_PM_D3_LPLU;
1839 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1844 /* When LPLU is enabled, we should disable SmartSpeed */
1845 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1850 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1851 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1860 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1861 * @hw: pointer to the HW structure
1863 * Success returns 0, Failure returns 1
1865 * A downshift is detected by querying the PHY link health.
1867 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1869 struct e1000_phy_info *phy = &hw->phy;
1871 u16 phy_data, offset, mask;
1873 DEBUGFUNC("e1000_check_downshift_generic");
1875 switch (phy->type) {
1877 case e1000_phy_gg82563:
1878 offset = M88E1000_PHY_SPEC_STATUS;
1879 mask = M88E1000_PSSR_DOWNSHIFT;
1881 case e1000_phy_igp_2:
1882 case e1000_phy_igp_3:
1883 offset = IGP01E1000_PHY_LINK_HEALTH;
1884 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1887 /* speed downshift not supported */
1888 phy->speed_downgraded = FALSE;
1889 ret_val = E1000_SUCCESS;
1893 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1896 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1903 * e1000_check_polarity_m88 - Checks the polarity.
1904 * @hw: pointer to the HW structure
1906 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1908 * Polarity is determined based on the PHY specific status register.
1910 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1912 struct e1000_phy_info *phy = &hw->phy;
1916 DEBUGFUNC("e1000_check_polarity_m88");
1918 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1921 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1922 ? e1000_rev_polarity_reversed
1923 : e1000_rev_polarity_normal;
1929 * e1000_check_polarity_igp - Checks the polarity.
1930 * @hw: pointer to the HW structure
1932 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1934 * Polarity is determined based on the PHY port status register, and the
1935 * current speed (since there is no polarity at 100Mbps).
1937 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1939 struct e1000_phy_info *phy = &hw->phy;
1941 u16 data, offset, mask;
1943 DEBUGFUNC("e1000_check_polarity_igp");
1946 * Polarity is determined based on the speed of
1949 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1953 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1954 IGP01E1000_PSSR_SPEED_1000MBPS) {
1955 offset = IGP01E1000_PHY_PCS_INIT_REG;
1956 mask = IGP01E1000_PHY_POLARITY_MASK;
1959 * This really only applies to 10Mbps since
1960 * there is no polarity for 100Mbps (always 0).
1962 offset = IGP01E1000_PHY_PORT_STATUS;
1963 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1966 ret_val = phy->ops.read_reg(hw, offset, &data);
1969 phy->cable_polarity = (data & mask)
1970 ? e1000_rev_polarity_reversed
1971 : e1000_rev_polarity_normal;
1978 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1979 * @hw: pointer to the HW structure
1981 * Polarity is determined on the polarity reversal feature being enabled.
1983 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1985 struct e1000_phy_info *phy = &hw->phy;
1987 u16 phy_data, offset, mask;
1989 DEBUGFUNC("e1000_check_polarity_ife");
1992 * Polarity is determined based on the reversal feature being enabled.
1994 if (phy->polarity_correction) {
1995 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1996 mask = IFE_PESC_POLARITY_REVERSED;
1998 offset = IFE_PHY_SPECIAL_CONTROL;
1999 mask = IFE_PSC_FORCE_POLARITY;
2002 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2005 phy->cable_polarity = (phy_data & mask)
2006 ? e1000_rev_polarity_reversed
2007 : e1000_rev_polarity_normal;
2013 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2014 * @hw: pointer to the HW structure
2016 * Waits for auto-negotiation to complete or for the auto-negotiation time
2017 * limit to expire, which ever happens first.
2019 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2021 s32 ret_val = E1000_SUCCESS;
2024 DEBUGFUNC("e1000_wait_autoneg_generic");
2026 if (!(hw->phy.ops.read_reg))
2027 return E1000_SUCCESS;
2029 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2030 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2031 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2034 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2037 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2043 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2050 * e1000_phy_has_link_generic - Polls PHY for link
2051 * @hw: pointer to the HW structure
2052 * @iterations: number of times to poll for link
2053 * @usec_interval: delay between polling attempts
2054 * @success: pointer to whether polling was successful or not
2056 * Polls the PHY status register for link, 'iterations' number of times.
2058 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2059 u32 usec_interval, bool *success)
2061 s32 ret_val = E1000_SUCCESS;
2064 DEBUGFUNC("e1000_phy_has_link_generic");
2066 if (!(hw->phy.ops.read_reg))
2067 return E1000_SUCCESS;
2069 for (i = 0; i < iterations; i++) {
2071 * Some PHYs require the PHY_STATUS register to be read
2072 * twice due to the link bit being sticky. No harm doing
2073 * it across the board.
2075 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2078 * If the first read fails, another entity may have
2079 * ownership of the resources, wait and try again to
2080 * see if they have relinquished the resources yet.
2082 usec_delay(usec_interval);
2083 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2086 if (phy_status & MII_SR_LINK_STATUS)
2088 if (usec_interval >= 1000)
2089 msec_delay_irq(usec_interval/1000);
2091 usec_delay(usec_interval);
2094 *success = (i < iterations) ? TRUE : FALSE;
2100 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2101 * @hw: pointer to the HW structure
2103 * Reads the PHY specific status register to retrieve the cable length
2104 * information. The cable length is determined by averaging the minimum and
2105 * maximum values to get the "average" cable length. The m88 PHY has four
2106 * possible cable length values, which are:
2107 * Register Value Cable Length
2111 * 3 110 - 140 meters
2114 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2116 struct e1000_phy_info *phy = &hw->phy;
2118 u16 phy_data, index;
2120 DEBUGFUNC("e1000_get_cable_length_m88");
2122 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2126 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2127 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2128 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2129 ret_val = -E1000_ERR_PHY;
2133 phy->min_cable_length = e1000_m88_cable_length_table[index];
2134 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2136 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2142 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2144 struct e1000_phy_info *phy = &hw->phy;
2146 u16 phy_data, phy_data2, index, default_page, is_cm;
2148 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2150 switch (hw->phy.id) {
2151 case M88E1340M_E_PHY_ID:
2152 case I347AT4_E_PHY_ID:
2153 /* Remember the original page select and set it to 7 */
2154 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2159 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2163 /* Get cable length from PHY Cable Diagnostics Control Reg */
2164 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2169 /* Check if the unit of cable length is meters or cm */
2170 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2174 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2176 /* Populate the phy structure with cable length in meters */
2177 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2178 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2179 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2181 /* Reset the page selec to its original value */
2182 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2187 case M88E1112_E_PHY_ID:
2188 /* Remember the original page select and set it to 5 */
2189 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2194 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2198 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2203 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2204 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2205 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2206 ret_val = -E1000_ERR_PHY;
2210 phy->min_cable_length = e1000_m88_cable_length_table[index];
2211 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2213 phy->cable_length = (phy->min_cable_length +
2214 phy->max_cable_length) / 2;
2216 /* Reset the page select to its original value */
2217 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2224 ret_val = -E1000_ERR_PHY;
2233 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2234 * @hw: pointer to the HW structure
2236 * The automatic gain control (agc) normalizes the amplitude of the
2237 * received signal, adjusting for the attenuation produced by the
2238 * cable. By reading the AGC registers, which represent the
2239 * combination of coarse and fine gain value, the value can be put
2240 * into a lookup table to obtain the approximate cable length
2243 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2245 struct e1000_phy_info *phy = &hw->phy;
2246 s32 ret_val = E1000_SUCCESS;
2247 u16 phy_data, i, agc_value = 0;
2248 u16 cur_agc_index, max_agc_index = 0;
2249 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2250 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2251 IGP02E1000_PHY_AGC_A,
2252 IGP02E1000_PHY_AGC_B,
2253 IGP02E1000_PHY_AGC_C,
2254 IGP02E1000_PHY_AGC_D
2257 DEBUGFUNC("e1000_get_cable_length_igp_2");
2259 /* Read the AGC registers for all channels */
2260 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2261 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2266 * Getting bits 15:9, which represent the combination of
2267 * coarse and fine gain values. The result is a number
2268 * that can be put into the lookup table to obtain the
2269 * approximate cable length.
2271 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2272 IGP02E1000_AGC_LENGTH_MASK;
2274 /* Array index bound check. */
2275 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2276 (cur_agc_index == 0)) {
2277 ret_val = -E1000_ERR_PHY;
2281 /* Remove min & max AGC values from calculation. */
2282 if (e1000_igp_2_cable_length_table[min_agc_index] >
2283 e1000_igp_2_cable_length_table[cur_agc_index])
2284 min_agc_index = cur_agc_index;
2285 if (e1000_igp_2_cable_length_table[max_agc_index] <
2286 e1000_igp_2_cable_length_table[cur_agc_index])
2287 max_agc_index = cur_agc_index;
2289 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2292 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2293 e1000_igp_2_cable_length_table[max_agc_index]);
2294 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2296 /* Calculate cable length with the error range of +/- 10 meters. */
2297 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2298 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2299 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2301 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2308 * e1000_get_phy_info_m88 - Retrieve PHY information
2309 * @hw: pointer to the HW structure
2311 * Valid for only copper links. Read the PHY status register (sticky read)
2312 * to verify that link is up. Read the PHY special control register to
2313 * determine the polarity and 10base-T extended distance. Read the PHY
2314 * special status register to determine MDI/MDIx and current speed. If
2315 * speed is 1000, then determine cable length, local and remote receiver.
2317 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2319 struct e1000_phy_info *phy = &hw->phy;
2324 DEBUGFUNC("e1000_get_phy_info_m88");
2326 if (phy->media_type != e1000_media_type_copper) {
2327 DEBUGOUT("Phy info is only valid for copper media\n");
2328 ret_val = -E1000_ERR_CONFIG;
2332 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2337 DEBUGOUT("Phy info is only valid if link is up\n");
2338 ret_val = -E1000_ERR_CONFIG;
2342 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2346 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2349 ret_val = e1000_check_polarity_m88(hw);
2353 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2357 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2359 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2360 ret_val = hw->phy.ops.get_cable_length(hw);
2364 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2368 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2369 ? e1000_1000t_rx_status_ok
2370 : e1000_1000t_rx_status_not_ok;
2372 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2373 ? e1000_1000t_rx_status_ok
2374 : e1000_1000t_rx_status_not_ok;
2376 /* Set values to "undefined" */
2377 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2378 phy->local_rx = e1000_1000t_rx_status_undefined;
2379 phy->remote_rx = e1000_1000t_rx_status_undefined;
2387 * e1000_get_phy_info_igp - Retrieve igp PHY information
2388 * @hw: pointer to the HW structure
2390 * Read PHY status to determine if link is up. If link is up, then
2391 * set/determine 10base-T extended distance and polarity correction. Read
2392 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2393 * determine on the cable length, local and remote receiver.
2395 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2397 struct e1000_phy_info *phy = &hw->phy;
2402 DEBUGFUNC("e1000_get_phy_info_igp");
2404 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2409 DEBUGOUT("Phy info is only valid if link is up\n");
2410 ret_val = -E1000_ERR_CONFIG;
2414 phy->polarity_correction = TRUE;
2416 ret_val = e1000_check_polarity_igp(hw);
2420 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2424 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2426 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2427 IGP01E1000_PSSR_SPEED_1000MBPS) {
2428 ret_val = phy->ops.get_cable_length(hw);
2432 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2436 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2437 ? e1000_1000t_rx_status_ok
2438 : e1000_1000t_rx_status_not_ok;
2440 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2441 ? e1000_1000t_rx_status_ok
2442 : e1000_1000t_rx_status_not_ok;
2444 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2445 phy->local_rx = e1000_1000t_rx_status_undefined;
2446 phy->remote_rx = e1000_1000t_rx_status_undefined;
2454 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2455 * @hw: pointer to the HW structure
2457 * Populates "phy" structure with various feature states.
2459 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2461 struct e1000_phy_info *phy = &hw->phy;
2466 DEBUGFUNC("e1000_get_phy_info_ife");
2468 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2473 DEBUGOUT("Phy info is only valid if link is up\n");
2474 ret_val = -E1000_ERR_CONFIG;
2478 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2481 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2484 if (phy->polarity_correction) {
2485 ret_val = e1000_check_polarity_ife(hw);
2489 /* Polarity is forced */
2490 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2491 ? e1000_rev_polarity_reversed
2492 : e1000_rev_polarity_normal;
2495 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2499 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2501 /* The following parameters are undefined for 10/100 operation. */
2502 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2503 phy->local_rx = e1000_1000t_rx_status_undefined;
2504 phy->remote_rx = e1000_1000t_rx_status_undefined;
2511 * e1000_phy_sw_reset_generic - PHY software reset
2512 * @hw: pointer to the HW structure
2514 * Does a software reset of the PHY by reading the PHY control register and
2515 * setting/write the control register reset bit to the PHY.
2517 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2519 s32 ret_val = E1000_SUCCESS;
2522 DEBUGFUNC("e1000_phy_sw_reset_generic");
2524 if (!(hw->phy.ops.read_reg))
2527 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2531 phy_ctrl |= MII_CR_RESET;
2532 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2543 * e1000_phy_hw_reset_generic - PHY hardware reset
2544 * @hw: pointer to the HW structure
2546 * Verify the reset block is not blocking us from resetting. Acquire
2547 * semaphore (if necessary) and read/set/write the device control reset
2548 * bit in the PHY. Wait the appropriate delay time for the device to
2549 * reset and release the semaphore (if necessary).
2551 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2553 struct e1000_phy_info *phy = &hw->phy;
2554 s32 ret_val = E1000_SUCCESS;
2557 DEBUGFUNC("e1000_phy_hw_reset_generic");
2559 ret_val = phy->ops.check_reset_block(hw);
2561 ret_val = E1000_SUCCESS;
2565 ret_val = phy->ops.acquire(hw);
2569 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2570 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2571 E1000_WRITE_FLUSH(hw);
2573 usec_delay(phy->reset_delay_us);
2575 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2576 E1000_WRITE_FLUSH(hw);
2580 phy->ops.release(hw);
2582 ret_val = phy->ops.get_cfg_done(hw);
2589 * e1000_get_cfg_done_generic - Generic configuration done
2590 * @hw: pointer to the HW structure
2592 * Generic function to wait 10 milli-seconds for configuration to complete
2593 * and return success.
2595 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2597 DEBUGFUNC("e1000_get_cfg_done_generic");
2601 return E1000_SUCCESS;
2605 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2606 * @hw: pointer to the HW structure
2608 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2610 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2612 DEBUGOUT("Running IGP 3 PHY init script\n");
2614 /* PHY init IGP 3 */
2615 /* Enable rise/fall, 10-mode work in class-A */
2616 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2617 /* Remove all caps from Replica path filter */
2618 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2619 /* Bias trimming for ADC, AFE and Driver (Default) */
2620 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2621 /* Increase Hybrid poly bias */
2622 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2623 /* Add 4% to Tx amplitude in Gig mode */
2624 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2625 /* Disable trimming (TTT) */
2626 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2627 /* Poly DC correction to 94.6% + 2% for all channels */
2628 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2629 /* ABS DC correction to 95.9% */
2630 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2631 /* BG temp curve trim */
2632 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2633 /* Increasing ADC OPAMP stage 1 currents to max */
2634 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2635 /* Force 1000 ( required for enabling PHY regs configuration) */
2636 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2637 /* Set upd_freq to 6 */
2638 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2640 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2641 /* Disable adaptive fixed FFE (Default) */
2642 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2643 /* Enable FFE hysteresis */
2644 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2645 /* Fixed FFE for short cable lengths */
2646 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2647 /* Fixed FFE for medium cable lengths */
2648 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2649 /* Fixed FFE for long cable lengths */
2650 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2651 /* Enable Adaptive Clip Threshold */
2652 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2653 /* AHT reset limit to 1 */
2654 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2655 /* Set AHT master delay to 127 msec */
2656 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2657 /* Set scan bits for AHT */
2658 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2659 /* Set AHT Preset bits */
2660 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2661 /* Change integ_factor of channel A to 3 */
2662 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2663 /* Change prop_factor of channels BCD to 8 */
2664 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2665 /* Change cg_icount + enable integbp for channels BCD */
2666 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2668 * Change cg_icount + enable integbp + change prop_factor_master
2669 * to 8 for channel A
2671 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2672 /* Disable AHT in Slave mode on channel A */
2673 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2675 * Enable LPLU and disable AN to 1000 in non-D0a states,
2678 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2679 /* Enable restart AN on an1000_dis change */
2680 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2681 /* Enable wh_fifo read clock in 10/100 modes */
2682 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2683 /* Restart AN, Speed selection is 1000 */
2684 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2686 return E1000_SUCCESS;
2690 * e1000_get_phy_type_from_id - Get PHY type from id
2691 * @phy_id: phy_id read from the phy
2693 * Returns the phy type from the id.
2695 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2697 enum e1000_phy_type phy_type = e1000_phy_unknown;
2700 case M88E1000_I_PHY_ID:
2701 case M88E1000_E_PHY_ID:
2702 case M88E1111_I_PHY_ID:
2703 case M88E1011_I_PHY_ID:
2704 case I347AT4_E_PHY_ID:
2705 case M88E1112_E_PHY_ID:
2706 case M88E1340M_E_PHY_ID:
2707 phy_type = e1000_phy_m88;
2709 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2710 phy_type = e1000_phy_igp_2;
2712 case GG82563_E_PHY_ID:
2713 phy_type = e1000_phy_gg82563;
2715 case IGP03E1000_E_PHY_ID:
2716 phy_type = e1000_phy_igp_3;
2719 case IFE_PLUS_E_PHY_ID:
2720 case IFE_C_E_PHY_ID:
2721 phy_type = e1000_phy_ife;
2723 case I82580_I_PHY_ID:
2724 phy_type = e1000_phy_82580;
2727 phy_type = e1000_phy_unknown;
2734 * e1000_determine_phy_address - Determines PHY address.
2735 * @hw: pointer to the HW structure
2737 * This uses a trial and error method to loop through possible PHY
2738 * addresses. It tests each by reading the PHY ID registers and
2739 * checking for a match.
2741 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2743 s32 ret_val = -E1000_ERR_PHY_TYPE;
2746 enum e1000_phy_type phy_type = e1000_phy_unknown;
2748 hw->phy.id = phy_type;
2750 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2751 hw->phy.addr = phy_addr;
2755 e1000_get_phy_id(hw);
2756 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2759 * If phy_type is valid, break - we found our
2762 if (phy_type != e1000_phy_unknown) {
2763 ret_val = E1000_SUCCESS;
2776 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2777 * @hw: pointer to the HW structure
2779 * In the case of a PHY power down to save power, or to turn off link during a
2780 * driver unload, or wake on lan is not enabled, restore the link to previous
2783 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2787 /* The PHY will retain its settings across a power down/up cycle */
2788 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2789 mii_reg &= ~MII_CR_POWER_DOWN;
2790 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2794 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2795 * @hw: pointer to the HW structure
2797 * In the case of a PHY power down to save power, or to turn off link during a
2798 * driver unload, or wake on lan is not enabled, restore the link to previous
2801 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2805 /* The PHY will retain its settings across a power down/up cycle */
2806 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2807 mii_reg |= MII_CR_POWER_DOWN;
2808 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2813 * e1000_check_polarity_82577 - Checks the polarity.
2814 * @hw: pointer to the HW structure
2816 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2818 * Polarity is determined based on the PHY specific status register.
2820 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2822 struct e1000_phy_info *phy = &hw->phy;
2826 DEBUGFUNC("e1000_check_polarity_82577");
2828 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2831 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
2832 ? e1000_rev_polarity_reversed
2833 : e1000_rev_polarity_normal;
2839 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2840 * @hw: pointer to the HW structure
2842 * Calls the PHY setup function to force speed and duplex.
2844 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2846 struct e1000_phy_info *phy = &hw->phy;
2851 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
2853 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2857 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
2859 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2865 if (phy->autoneg_wait_to_complete) {
2866 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
2868 ret_val = e1000_phy_has_link_generic(hw,
2876 DEBUGOUT("Link taking longer than expected.\n");
2879 ret_val = e1000_phy_has_link_generic(hw,
2892 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2893 * @hw: pointer to the HW structure
2895 * Read PHY status to determine if link is up. If link is up, then
2896 * set/determine 10base-T extended distance and polarity correction. Read
2897 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2898 * determine on the cable length, local and remote receiver.
2900 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
2902 struct e1000_phy_info *phy = &hw->phy;
2907 DEBUGFUNC("e1000_get_phy_info_82577");
2909 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2914 DEBUGOUT("Phy info is only valid if link is up\n");
2915 ret_val = -E1000_ERR_CONFIG;
2919 phy->polarity_correction = TRUE;
2921 ret_val = e1000_check_polarity_82577(hw);
2925 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2929 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
2931 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
2932 I82577_PHY_STATUS2_SPEED_1000MBPS) {
2933 ret_val = hw->phy.ops.get_cable_length(hw);
2937 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2941 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2942 ? e1000_1000t_rx_status_ok
2943 : e1000_1000t_rx_status_not_ok;
2945 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2946 ? e1000_1000t_rx_status_ok
2947 : e1000_1000t_rx_status_not_ok;
2949 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2950 phy->local_rx = e1000_1000t_rx_status_undefined;
2951 phy->remote_rx = e1000_1000t_rx_status_undefined;
2959 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2960 * @hw: pointer to the HW structure
2962 * Reads the diagnostic status register and verifies result is valid before
2963 * placing it in the phy_cable_length field.
2965 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
2967 struct e1000_phy_info *phy = &hw->phy;
2969 u16 phy_data, length;
2971 DEBUGFUNC("e1000_get_cable_length_82577");
2973 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
2977 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
2978 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
2980 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2981 ret_val = -E1000_ERR_PHY;
2983 phy->cable_length = length;