1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
38 u16 *data, bool read, bool page_set);
39 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
40 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
41 u16 *data, bool read);
43 /* Cable length tables */
44 static const u16 e1000_m88_cable_length_table[] = {
45 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
46 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47 (sizeof(e1000_m88_cable_length_table) / \
48 sizeof(e1000_m88_cable_length_table[0]))
50 static const u16 e1000_igp_2_cable_length_table[] = {
51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 (sizeof(e1000_igp_2_cable_length_table) / \
61 sizeof(e1000_igp_2_cable_length_table[0]))
64 * e1000_init_phy_ops_generic - Initialize PHY function pointers
65 * @hw: pointer to the HW structure
67 * Setups up the function pointers to no-op functions
69 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
71 struct e1000_phy_info *phy = &hw->phy;
72 DEBUGFUNC("e1000_init_phy_ops_generic");
74 /* Initialize function pointers */
75 phy->ops.init_params = e1000_null_ops_generic;
76 phy->ops.acquire = e1000_null_ops_generic;
77 phy->ops.check_polarity = e1000_null_ops_generic;
78 phy->ops.check_reset_block = e1000_null_ops_generic;
79 phy->ops.commit = e1000_null_ops_generic;
80 phy->ops.force_speed_duplex = e1000_null_ops_generic;
81 phy->ops.get_cfg_done = e1000_null_ops_generic;
82 phy->ops.get_cable_length = e1000_null_ops_generic;
83 phy->ops.get_info = e1000_null_ops_generic;
84 phy->ops.set_page = e1000_null_set_page;
85 phy->ops.read_reg = e1000_null_read_reg;
86 phy->ops.read_reg_locked = e1000_null_read_reg;
87 phy->ops.read_reg_page = e1000_null_read_reg;
88 phy->ops.release = e1000_null_phy_generic;
89 phy->ops.reset = e1000_null_ops_generic;
90 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
91 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
92 phy->ops.write_reg = e1000_null_write_reg;
93 phy->ops.write_reg_locked = e1000_null_write_reg;
94 phy->ops.write_reg_page = e1000_null_write_reg;
95 phy->ops.power_up = e1000_null_phy_generic;
96 phy->ops.power_down = e1000_null_phy_generic;
97 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
98 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
99 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
103 * e1000_null_set_page - No-op function, return 0
104 * @hw: pointer to the HW structure
106 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
107 u16 E1000_UNUSEDARG data)
109 DEBUGFUNC("e1000_null_set_page");
110 UNREFERENCED_2PARAMETER(hw, data);
111 return E1000_SUCCESS;
115 * e1000_null_read_reg - No-op function, return 0
116 * @hw: pointer to the HW structure
118 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
119 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
121 DEBUGFUNC("e1000_null_read_reg");
122 UNREFERENCED_3PARAMETER(hw, offset, data);
123 return E1000_SUCCESS;
127 * e1000_null_phy_generic - No-op function, return void
128 * @hw: pointer to the HW structure
130 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
132 DEBUGFUNC("e1000_null_phy_generic");
133 UNREFERENCED_1PARAMETER(hw);
138 * e1000_null_lplu_state - No-op function, return 0
139 * @hw: pointer to the HW structure
141 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
142 bool E1000_UNUSEDARG active)
144 DEBUGFUNC("e1000_null_lplu_state");
145 UNREFERENCED_2PARAMETER(hw, active);
146 return E1000_SUCCESS;
150 * e1000_null_write_reg - No-op function, return 0
151 * @hw: pointer to the HW structure
153 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
154 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
156 DEBUGFUNC("e1000_null_write_reg");
157 UNREFERENCED_3PARAMETER(hw, offset, data);
158 return E1000_SUCCESS;
162 * e1000_read_i2c_byte_null - No-op function, return 0
163 * @hw: pointer to hardware structure
164 * @byte_offset: byte offset to write
165 * @dev_addr: device address
166 * @data: data value read
169 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
170 u8 E1000_UNUSEDARG byte_offset,
171 u8 E1000_UNUSEDARG dev_addr,
172 u8 E1000_UNUSEDARG *data)
174 DEBUGFUNC("e1000_read_i2c_byte_null");
175 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
176 return E1000_SUCCESS;
180 * e1000_write_i2c_byte_null - No-op function, return 0
181 * @hw: pointer to hardware structure
182 * @byte_offset: byte offset to write
183 * @dev_addr: device address
184 * @data: data value to write
187 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
188 u8 E1000_UNUSEDARG byte_offset,
189 u8 E1000_UNUSEDARG dev_addr,
190 u8 E1000_UNUSEDARG data)
192 DEBUGFUNC("e1000_write_i2c_byte_null");
193 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
194 return E1000_SUCCESS;
198 * e1000_check_reset_block_generic - Check if PHY reset is blocked
199 * @hw: pointer to the HW structure
201 * Read the PHY management control register and check whether a PHY reset
202 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
203 * return E1000_BLK_PHY_RESET (12).
205 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
209 DEBUGFUNC("e1000_check_reset_block");
211 manc = E1000_READ_REG(hw, E1000_MANC);
213 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
214 E1000_BLK_PHY_RESET : E1000_SUCCESS;
218 * e1000_get_phy_id - Retrieve the PHY ID and revision
219 * @hw: pointer to the HW structure
221 * Reads the PHY registers and stores the PHY ID and possibly the PHY
222 * revision in the hardware structure.
224 s32 e1000_get_phy_id(struct e1000_hw *hw)
226 struct e1000_phy_info *phy = &hw->phy;
227 s32 ret_val = E1000_SUCCESS;
231 DEBUGFUNC("e1000_get_phy_id");
233 if (!phy->ops.read_reg)
234 return E1000_SUCCESS;
236 while (retry_count < 2) {
237 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
241 phy->id = (u32)(phy_id << 16);
243 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
247 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
248 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
250 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
251 return E1000_SUCCESS;
256 return E1000_SUCCESS;
260 * e1000_phy_reset_dsp_generic - Reset PHY DSP
261 * @hw: pointer to the HW structure
263 * Reset the digital signal processor.
265 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
269 DEBUGFUNC("e1000_phy_reset_dsp_generic");
271 if (!hw->phy.ops.write_reg)
272 return E1000_SUCCESS;
274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
282 * e1000_read_phy_reg_mdic - Read MDI control register
283 * @hw: pointer to the HW structure
284 * @offset: register offset to be read
285 * @data: pointer to the read data
287 * Reads the MDI control register in the PHY at offset and stores the
288 * information read to data.
290 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
292 struct e1000_phy_info *phy = &hw->phy;
295 DEBUGFUNC("e1000_read_phy_reg_mdic");
297 if (offset > MAX_PHY_REG_ADDRESS) {
298 DEBUGOUT1("PHY Address %d is out of range\n", offset);
299 return -E1000_ERR_PARAM;
302 /* Set up Op-code, Phy Address, and register offset in the MDI
303 * Control register. The MAC will take care of interfacing with the
304 * PHY to retrieve the desired data.
306 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
307 (phy->addr << E1000_MDIC_PHY_SHIFT) |
308 (E1000_MDIC_OP_READ));
310 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
312 /* Poll the ready bit to see if the MDI read completed
313 * Increasing the time out as testing showed failures with
316 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
318 mdic = E1000_READ_REG(hw, E1000_MDIC);
319 if (mdic & E1000_MDIC_READY)
322 if (!(mdic & E1000_MDIC_READY)) {
323 DEBUGOUT("MDI Read did not complete\n");
324 return -E1000_ERR_PHY;
326 if (mdic & E1000_MDIC_ERROR) {
327 DEBUGOUT("MDI Error\n");
328 return -E1000_ERR_PHY;
330 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
331 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
333 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
334 return -E1000_ERR_PHY;
338 /* Allow some time after each MDIC transaction to avoid
339 * reading duplicate data in the next MDIC transaction.
341 if (hw->mac.type == e1000_pch2lan)
344 return E1000_SUCCESS;
348 * e1000_write_phy_reg_mdic - Write MDI control register
349 * @hw: pointer to the HW structure
350 * @offset: register offset to write to
351 * @data: data to write to register at offset
353 * Writes data to MDI control register in the PHY at offset.
355 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
357 struct e1000_phy_info *phy = &hw->phy;
360 DEBUGFUNC("e1000_write_phy_reg_mdic");
362 if (offset > MAX_PHY_REG_ADDRESS) {
363 DEBUGOUT1("PHY Address %d is out of range\n", offset);
364 return -E1000_ERR_PARAM;
367 /* Set up Op-code, Phy Address, and register offset in the MDI
368 * Control register. The MAC will take care of interfacing with the
369 * PHY to retrieve the desired data.
371 mdic = (((u32)data) |
372 (offset << E1000_MDIC_REG_SHIFT) |
373 (phy->addr << E1000_MDIC_PHY_SHIFT) |
374 (E1000_MDIC_OP_WRITE));
376 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
378 /* Poll the ready bit to see if the MDI read completed
379 * Increasing the time out as testing showed failures with
382 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
384 mdic = E1000_READ_REG(hw, E1000_MDIC);
385 if (mdic & E1000_MDIC_READY)
388 if (!(mdic & E1000_MDIC_READY)) {
389 DEBUGOUT("MDI Write did not complete\n");
390 return -E1000_ERR_PHY;
392 if (mdic & E1000_MDIC_ERROR) {
393 DEBUGOUT("MDI Error\n");
394 return -E1000_ERR_PHY;
396 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
397 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
399 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
400 return -E1000_ERR_PHY;
403 /* Allow some time after each MDIC transaction to avoid
404 * reading duplicate data in the next MDIC transaction.
406 if (hw->mac.type == e1000_pch2lan)
409 return E1000_SUCCESS;
413 * e1000_read_phy_reg_i2c - Read PHY register using i2c
414 * @hw: pointer to the HW structure
415 * @offset: register offset to be read
416 * @data: pointer to the read data
418 * Reads the PHY register at offset using the i2c interface and stores the
419 * retrieved information in data.
421 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
423 struct e1000_phy_info *phy = &hw->phy;
426 DEBUGFUNC("e1000_read_phy_reg_i2c");
428 /* Set up Op-code, Phy Address, and register address in the I2CCMD
429 * register. The MAC will take care of interfacing with the
430 * PHY to retrieve the desired data.
432 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
433 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
434 (E1000_I2CCMD_OPCODE_READ));
436 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
438 /* Poll the ready bit to see if the I2C read completed */
439 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
441 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
442 if (i2ccmd & E1000_I2CCMD_READY)
445 if (!(i2ccmd & E1000_I2CCMD_READY)) {
446 DEBUGOUT("I2CCMD Read did not complete\n");
447 return -E1000_ERR_PHY;
449 if (i2ccmd & E1000_I2CCMD_ERROR) {
450 DEBUGOUT("I2CCMD Error bit set\n");
451 return -E1000_ERR_PHY;
454 /* Need to byte-swap the 16-bit value. */
455 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
457 return E1000_SUCCESS;
461 * e1000_write_phy_reg_i2c - Write PHY register using i2c
462 * @hw: pointer to the HW structure
463 * @offset: register offset to write to
464 * @data: data to write at register offset
466 * Writes the data to PHY register at the offset using the i2c interface.
468 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
470 struct e1000_phy_info *phy = &hw->phy;
472 u16 phy_data_swapped;
474 DEBUGFUNC("e1000_write_phy_reg_i2c");
476 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
477 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
478 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
480 return -E1000_ERR_CONFIG;
483 /* Swap the data bytes for the I2C interface */
484 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
486 /* Set up Op-code, Phy Address, and register address in the I2CCMD
487 * register. The MAC will take care of interfacing with the
488 * PHY to retrieve the desired data.
490 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
491 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
492 E1000_I2CCMD_OPCODE_WRITE |
495 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
497 /* Poll the ready bit to see if the I2C read completed */
498 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
500 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
501 if (i2ccmd & E1000_I2CCMD_READY)
504 if (!(i2ccmd & E1000_I2CCMD_READY)) {
505 DEBUGOUT("I2CCMD Write did not complete\n");
506 return -E1000_ERR_PHY;
508 if (i2ccmd & E1000_I2CCMD_ERROR) {
509 DEBUGOUT("I2CCMD Error bit set\n");
510 return -E1000_ERR_PHY;
513 return E1000_SUCCESS;
517 * e1000_read_sfp_data_byte - Reads SFP module data.
518 * @hw: pointer to the HW structure
519 * @offset: byte location offset to be read
520 * @data: read data buffer pointer
522 * Reads one byte from SFP module data stored
523 * in SFP resided EEPROM memory or SFP diagnostic area.
524 * Function should be called with
525 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
526 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
529 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
535 DEBUGFUNC("e1000_read_sfp_data_byte");
537 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
538 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
539 return -E1000_ERR_PHY;
542 /* Set up Op-code, EEPROM Address,in the I2CCMD
543 * register. The MAC will take care of interfacing with the
544 * EEPROM to retrieve the desired data.
546 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
547 E1000_I2CCMD_OPCODE_READ);
549 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
551 /* Poll the ready bit to see if the I2C read completed */
552 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
554 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
555 if (data_local & E1000_I2CCMD_READY)
558 if (!(data_local & E1000_I2CCMD_READY)) {
559 DEBUGOUT("I2CCMD Read did not complete\n");
560 return -E1000_ERR_PHY;
562 if (data_local & E1000_I2CCMD_ERROR) {
563 DEBUGOUT("I2CCMD Error bit set\n");
564 return -E1000_ERR_PHY;
566 *data = (u8) data_local & 0xFF;
568 return E1000_SUCCESS;
572 * e1000_write_sfp_data_byte - Writes SFP module data.
573 * @hw: pointer to the HW structure
574 * @offset: byte location offset to write to
575 * @data: data to write
577 * Writes one byte to SFP module data stored
578 * in SFP resided EEPROM memory or SFP diagnostic area.
579 * Function should be called with
580 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
581 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
584 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
590 DEBUGFUNC("e1000_write_sfp_data_byte");
592 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
593 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
594 return -E1000_ERR_PHY;
596 /* The programming interface is 16 bits wide
597 * so we need to read the whole word first
598 * then update appropriate byte lane and write
599 * the updated word back.
601 /* Set up Op-code, EEPROM Address,in the I2CCMD
602 * register. The MAC will take care of interfacing
603 * with an EEPROM to write the data given.
605 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
606 E1000_I2CCMD_OPCODE_READ);
607 /* Set a command to read single word */
608 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
609 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
611 /* Poll the ready bit to see if lastly
612 * launched I2C operation completed
614 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
615 if (i2ccmd & E1000_I2CCMD_READY) {
616 /* Check if this is READ or WRITE phase */
617 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
618 E1000_I2CCMD_OPCODE_READ) {
619 /* Write the selected byte
620 * lane and update whole word
622 data_local = i2ccmd & 0xFF00;
625 E1000_I2CCMD_REG_ADDR_SHIFT) |
626 E1000_I2CCMD_OPCODE_WRITE | data_local);
627 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
633 if (!(i2ccmd & E1000_I2CCMD_READY)) {
634 DEBUGOUT("I2CCMD Write did not complete\n");
635 return -E1000_ERR_PHY;
637 if (i2ccmd & E1000_I2CCMD_ERROR) {
638 DEBUGOUT("I2CCMD Error bit set\n");
639 return -E1000_ERR_PHY;
641 return E1000_SUCCESS;
645 * e1000_read_phy_reg_m88 - Read m88 PHY register
646 * @hw: pointer to the HW structure
647 * @offset: register offset to be read
648 * @data: pointer to the read data
650 * Acquires semaphore, if necessary, then reads the PHY register at offset
651 * and storing the retrieved information in data. Release any acquired
652 * semaphores before exiting.
654 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
658 DEBUGFUNC("e1000_read_phy_reg_m88");
660 if (!hw->phy.ops.acquire)
661 return E1000_SUCCESS;
663 ret_val = hw->phy.ops.acquire(hw);
667 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
670 hw->phy.ops.release(hw);
676 * e1000_write_phy_reg_m88 - Write m88 PHY register
677 * @hw: pointer to the HW structure
678 * @offset: register offset to write to
679 * @data: data to write at register offset
681 * Acquires semaphore, if necessary, then writes the data to PHY register
682 * at the offset. Release any acquired semaphores before exiting.
684 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
688 DEBUGFUNC("e1000_write_phy_reg_m88");
690 if (!hw->phy.ops.acquire)
691 return E1000_SUCCESS;
693 ret_val = hw->phy.ops.acquire(hw);
697 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
700 hw->phy.ops.release(hw);
706 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
707 * @hw: pointer to the HW structure
708 * @page: page to set (shifted left when necessary)
710 * Sets PHY page required for PHY register access. Assumes semaphore is
711 * already acquired. Note, this function sets phy.addr to 1 so the caller
712 * must set it appropriately (if necessary) after this function returns.
714 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
716 DEBUGFUNC("e1000_set_page_igp");
718 DEBUGOUT1("Setting page 0x%x\n", page);
722 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
726 * __e1000_read_phy_reg_igp - Read igp PHY register
727 * @hw: pointer to the HW structure
728 * @offset: register offset to be read
729 * @data: pointer to the read data
730 * @locked: semaphore has already been acquired or not
732 * Acquires semaphore, if necessary, then reads the PHY register at offset
733 * and stores the retrieved information in data. Release any acquired
734 * semaphores before exiting.
736 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
739 s32 ret_val = E1000_SUCCESS;
741 DEBUGFUNC("__e1000_read_phy_reg_igp");
744 if (!hw->phy.ops.acquire)
745 return E1000_SUCCESS;
747 ret_val = hw->phy.ops.acquire(hw);
752 if (offset > MAX_PHY_MULTI_PAGE_REG)
753 ret_val = e1000_write_phy_reg_mdic(hw,
754 IGP01E1000_PHY_PAGE_SELECT,
757 ret_val = e1000_read_phy_reg_mdic(hw,
758 MAX_PHY_REG_ADDRESS & offset,
761 hw->phy.ops.release(hw);
767 * e1000_read_phy_reg_igp - Read igp PHY register
768 * @hw: pointer to the HW structure
769 * @offset: register offset to be read
770 * @data: pointer to the read data
772 * Acquires semaphore then reads the PHY register at offset and stores the
773 * retrieved information in data.
774 * Release the acquired semaphore before exiting.
776 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
778 return __e1000_read_phy_reg_igp(hw, offset, data, false);
782 * e1000_read_phy_reg_igp_locked - Read igp PHY register
783 * @hw: pointer to the HW structure
784 * @offset: register offset to be read
785 * @data: pointer to the read data
787 * Reads the PHY register at offset and stores the retrieved information
788 * in data. Assumes semaphore already acquired.
790 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
792 return __e1000_read_phy_reg_igp(hw, offset, data, true);
796 * e1000_write_phy_reg_igp - Write igp PHY register
797 * @hw: pointer to the HW structure
798 * @offset: register offset to write to
799 * @data: data to write at register offset
800 * @locked: semaphore has already been acquired or not
802 * Acquires semaphore, if necessary, then writes the data to PHY register
803 * at the offset. Release any acquired semaphores before exiting.
805 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
808 s32 ret_val = E1000_SUCCESS;
810 DEBUGFUNC("e1000_write_phy_reg_igp");
813 if (!hw->phy.ops.acquire)
814 return E1000_SUCCESS;
816 ret_val = hw->phy.ops.acquire(hw);
821 if (offset > MAX_PHY_MULTI_PAGE_REG)
822 ret_val = e1000_write_phy_reg_mdic(hw,
823 IGP01E1000_PHY_PAGE_SELECT,
826 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
830 hw->phy.ops.release(hw);
836 * e1000_write_phy_reg_igp - Write igp PHY register
837 * @hw: pointer to the HW structure
838 * @offset: register offset to write to
839 * @data: data to write at register offset
841 * Acquires semaphore then writes the data to PHY register
842 * at the offset. Release any acquired semaphores before exiting.
844 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
846 return __e1000_write_phy_reg_igp(hw, offset, data, false);
850 * e1000_write_phy_reg_igp_locked - Write igp PHY register
851 * @hw: pointer to the HW structure
852 * @offset: register offset to write to
853 * @data: data to write at register offset
855 * Writes the data to PHY register at the offset.
856 * Assumes semaphore already acquired.
858 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
860 return __e1000_write_phy_reg_igp(hw, offset, data, true);
864 * __e1000_read_kmrn_reg - Read kumeran register
865 * @hw: pointer to the HW structure
866 * @offset: register offset to be read
867 * @data: pointer to the read data
868 * @locked: semaphore has already been acquired or not
870 * Acquires semaphore, if necessary. Then reads the PHY register at offset
871 * using the kumeran interface. The information retrieved is stored in data.
872 * Release any acquired semaphores before exiting.
874 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
879 DEBUGFUNC("__e1000_read_kmrn_reg");
882 s32 ret_val = E1000_SUCCESS;
884 if (!hw->phy.ops.acquire)
885 return E1000_SUCCESS;
887 ret_val = hw->phy.ops.acquire(hw);
892 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
893 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
894 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
895 E1000_WRITE_FLUSH(hw);
899 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
900 *data = (u16)kmrnctrlsta;
903 hw->phy.ops.release(hw);
905 return E1000_SUCCESS;
909 * e1000_read_kmrn_reg_generic - Read kumeran register
910 * @hw: pointer to the HW structure
911 * @offset: register offset to be read
912 * @data: pointer to the read data
914 * Acquires semaphore then reads the PHY register at offset using the
915 * kumeran interface. The information retrieved is stored in data.
916 * Release the acquired semaphore before exiting.
918 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
920 return __e1000_read_kmrn_reg(hw, offset, data, false);
924 * e1000_read_kmrn_reg_locked - Read kumeran register
925 * @hw: pointer to the HW structure
926 * @offset: register offset to be read
927 * @data: pointer to the read data
929 * Reads the PHY register at offset using the kumeran interface. The
930 * information retrieved is stored in data.
931 * Assumes semaphore already acquired.
933 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
935 return __e1000_read_kmrn_reg(hw, offset, data, true);
939 * __e1000_write_kmrn_reg - Write kumeran register
940 * @hw: pointer to the HW structure
941 * @offset: register offset to write to
942 * @data: data to write at register offset
943 * @locked: semaphore has already been acquired or not
945 * Acquires semaphore, if necessary. Then write the data to PHY register
946 * at the offset using the kumeran interface. Release any acquired semaphores
949 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
954 DEBUGFUNC("e1000_write_kmrn_reg_generic");
957 s32 ret_val = E1000_SUCCESS;
959 if (!hw->phy.ops.acquire)
960 return E1000_SUCCESS;
962 ret_val = hw->phy.ops.acquire(hw);
967 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
968 E1000_KMRNCTRLSTA_OFFSET) | data;
969 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
970 E1000_WRITE_FLUSH(hw);
975 hw->phy.ops.release(hw);
977 return E1000_SUCCESS;
981 * e1000_write_kmrn_reg_generic - Write kumeran register
982 * @hw: pointer to the HW structure
983 * @offset: register offset to write to
984 * @data: data to write at register offset
986 * Acquires semaphore then writes the data to the PHY register at the offset
987 * using the kumeran interface. Release the acquired semaphore before exiting.
989 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
991 return __e1000_write_kmrn_reg(hw, offset, data, false);
995 * e1000_write_kmrn_reg_locked - Write kumeran register
996 * @hw: pointer to the HW structure
997 * @offset: register offset to write to
998 * @data: data to write at register offset
1000 * Write the data to PHY register at the offset using the kumeran interface.
1001 * Assumes semaphore already acquired.
1003 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1005 return __e1000_write_kmrn_reg(hw, offset, data, true);
1009 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1010 * @hw: pointer to the HW structure
1012 * Sets up Master/slave mode
1014 STATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1019 /* Resolve Master/Slave mode */
1020 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1024 /* load defaults for future use */
1025 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1026 ((phy_data & CR_1000T_MS_VALUE) ?
1027 e1000_ms_force_master :
1028 e1000_ms_force_slave) : e1000_ms_auto;
1030 switch (hw->phy.ms_type) {
1031 case e1000_ms_force_master:
1032 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1034 case e1000_ms_force_slave:
1035 phy_data |= CR_1000T_MS_ENABLE;
1036 phy_data &= ~(CR_1000T_MS_VALUE);
1039 phy_data &= ~CR_1000T_MS_ENABLE;
1045 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1049 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1050 * @hw: pointer to the HW structure
1052 * Sets up Carrier-sense on Transmit and downshift values.
1054 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1059 DEBUGFUNC("e1000_copper_link_setup_82577");
1061 if (hw->phy.type == e1000_phy_82580) {
1062 ret_val = hw->phy.ops.reset(hw);
1064 DEBUGOUT("Error resetting the PHY.\n");
1069 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1070 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1074 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1076 /* Enable downshift */
1077 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1079 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1083 /* Set MDI/MDIX mode */
1084 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1087 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1089 * 0 - Auto (default)
1093 switch (hw->phy.mdix) {
1097 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1101 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1104 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1108 return e1000_set_master_slave_mode(hw);
1112 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1113 * @hw: pointer to the HW structure
1115 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1116 * and downshift values are set also.
1118 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1120 struct e1000_phy_info *phy = &hw->phy;
1124 DEBUGFUNC("e1000_copper_link_setup_m88");
1127 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1128 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1132 /* For BM PHY this bit is downshift enable */
1133 if (phy->type != e1000_phy_bm)
1134 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1137 * MDI/MDI-X = 0 (default)
1138 * 0 - Auto for all speeds
1141 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1143 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1145 switch (phy->mdix) {
1147 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1150 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1153 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1157 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1162 * disable_polarity_correction = 0 (default)
1163 * Automatic Correction for Reversed Cable Polarity
1167 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1168 if (phy->disable_polarity_correction)
1169 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1171 /* Enable downshift on BM (disabled by default) */
1172 if (phy->type == e1000_phy_bm) {
1173 /* For 82574/82583, first disable then enable downshift */
1174 if (phy->id == BME1000_E_PHY_ID_R2) {
1175 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1176 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1180 /* Commit the changes. */
1181 ret_val = phy->ops.commit(hw);
1183 DEBUGOUT("Error committing the PHY changes\n");
1188 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1191 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1195 if ((phy->type == e1000_phy_m88) &&
1196 (phy->revision < E1000_REVISION_4) &&
1197 (phy->id != BME1000_E_PHY_ID_R2)) {
1198 /* Force TX_CLK in the Extended PHY Specific Control Register
1201 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1206 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1208 if ((phy->revision == E1000_REVISION_2) &&
1209 (phy->id == M88E1111_I_PHY_ID)) {
1210 /* 82573L PHY - set the downshift counter to 5x. */
1211 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1212 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1214 /* Configure Master and Slave downshift values */
1215 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1216 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1217 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1218 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1220 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1226 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1227 /* Set PHY page 0, register 29 to 0x0003 */
1228 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1232 /* Set PHY page 0, register 30 to 0x0000 */
1233 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1238 /* Commit the changes. */
1239 ret_val = phy->ops.commit(hw);
1241 DEBUGOUT("Error committing the PHY changes\n");
1245 if (phy->type == e1000_phy_82578) {
1246 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1251 /* 82578 PHY - set the downshift count to 1x. */
1252 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1253 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1254 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1260 return E1000_SUCCESS;
1264 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1265 * @hw: pointer to the HW structure
1267 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1268 * Also enables and sets the downshift parameters.
1270 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1272 struct e1000_phy_info *phy = &hw->phy;
1276 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1279 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1280 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1285 * MDI/MDI-X = 0 (default)
1286 * 0 - Auto for all speeds
1289 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1291 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1293 switch (phy->mdix) {
1295 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1298 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1301 /* M88E1112 does not support this mode) */
1302 if (phy->id != M88E1112_E_PHY_ID) {
1303 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1308 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1313 * disable_polarity_correction = 0 (default)
1314 * Automatic Correction for Reversed Cable Polarity
1318 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1319 if (phy->disable_polarity_correction)
1320 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1322 /* Enable downshift and setting it to X6 */
1323 if (phy->id == M88E1543_E_PHY_ID) {
1324 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1326 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1330 ret_val = phy->ops.commit(hw);
1332 DEBUGOUT("Error committing the PHY changes\n");
1337 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1338 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1339 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1341 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1345 /* Commit the changes. */
1346 ret_val = phy->ops.commit(hw);
1348 DEBUGOUT("Error committing the PHY changes\n");
1352 ret_val = e1000_set_master_slave_mode(hw);
1356 return E1000_SUCCESS;
1360 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1361 * @hw: pointer to the HW structure
1363 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1366 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1368 struct e1000_phy_info *phy = &hw->phy;
1372 DEBUGFUNC("e1000_copper_link_setup_igp");
1375 ret_val = hw->phy.ops.reset(hw);
1377 DEBUGOUT("Error resetting the PHY.\n");
1381 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1382 * timeout issues when LFS is enabled.
1386 /* The NVM settings will configure LPLU in D3 for
1389 if (phy->type == e1000_phy_igp) {
1390 /* disable lplu d3 during driver init */
1391 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1393 DEBUGOUT("Error Disabling LPLU D3\n");
1398 /* disable lplu d0 during driver init */
1399 if (hw->phy.ops.set_d0_lplu_state) {
1400 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1402 DEBUGOUT("Error Disabling LPLU D0\n");
1406 /* Configure mdi-mdix settings */
1407 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1411 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1413 switch (phy->mdix) {
1415 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1418 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1422 data |= IGP01E1000_PSCR_AUTO_MDIX;
1425 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1429 /* set auto-master slave resolution settings */
1430 if (hw->mac.autoneg) {
1431 /* when autonegotiation advertisement is only 1000Mbps then we
1432 * should disable SmartSpeed and enable Auto MasterSlave
1433 * resolution as hardware default.
1435 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1436 /* Disable SmartSpeed */
1437 ret_val = phy->ops.read_reg(hw,
1438 IGP01E1000_PHY_PORT_CONFIG,
1443 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1444 ret_val = phy->ops.write_reg(hw,
1445 IGP01E1000_PHY_PORT_CONFIG,
1450 /* Set auto Master/Slave resolution process */
1451 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1455 data &= ~CR_1000T_MS_ENABLE;
1456 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1461 ret_val = e1000_set_master_slave_mode(hw);
1468 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1469 * @hw: pointer to the HW structure
1471 * Reads the MII auto-neg advertisement register and/or the 1000T control
1472 * register and if the PHY is already setup for auto-negotiation, then
1473 * return successful. Otherwise, setup advertisement and flow control to
1474 * the appropriate values for the wanted auto-negotiation.
1476 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1478 struct e1000_phy_info *phy = &hw->phy;
1480 u16 mii_autoneg_adv_reg;
1481 u16 mii_1000t_ctrl_reg = 0;
1483 DEBUGFUNC("e1000_phy_setup_autoneg");
1485 phy->autoneg_advertised &= phy->autoneg_mask;
1487 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1488 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1492 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1493 /* Read the MII 1000Base-T Control Register (Address 9). */
1494 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1495 &mii_1000t_ctrl_reg);
1500 /* Need to parse both autoneg_advertised and fc and set up
1501 * the appropriate PHY registers. First we will parse for
1502 * autoneg_advertised software override. Since we can advertise
1503 * a plethora of combinations, we need to check each bit
1507 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1508 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1509 * the 1000Base-T Control Register (Address 9).
1511 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1512 NWAY_AR_100TX_HD_CAPS |
1513 NWAY_AR_10T_FD_CAPS |
1514 NWAY_AR_10T_HD_CAPS);
1515 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1517 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1519 /* Do we want to advertise 10 Mb Half Duplex? */
1520 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1521 DEBUGOUT("Advertise 10mb Half duplex\n");
1522 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1525 /* Do we want to advertise 10 Mb Full Duplex? */
1526 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1527 DEBUGOUT("Advertise 10mb Full duplex\n");
1528 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1531 /* Do we want to advertise 100 Mb Half Duplex? */
1532 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1533 DEBUGOUT("Advertise 100mb Half duplex\n");
1534 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1537 /* Do we want to advertise 100 Mb Full Duplex? */
1538 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1539 DEBUGOUT("Advertise 100mb Full duplex\n");
1540 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1543 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1544 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1545 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1547 /* Do we want to advertise 1000 Mb Full Duplex? */
1548 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1549 DEBUGOUT("Advertise 1000mb Full duplex\n");
1550 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1553 /* Check for a software override of the flow control settings, and
1554 * setup the PHY advertisement registers accordingly. If
1555 * auto-negotiation is enabled, then software will have to set the
1556 * "PAUSE" bits to the correct value in the Auto-Negotiation
1557 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1560 * The possible values of the "fc" parameter are:
1561 * 0: Flow control is completely disabled
1562 * 1: Rx flow control is enabled (we can receive pause frames
1563 * but not send pause frames).
1564 * 2: Tx flow control is enabled (we can send pause frames
1565 * but we do not support receiving pause frames).
1566 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1567 * other: No software override. The flow control configuration
1568 * in the EEPROM is used.
1570 switch (hw->fc.current_mode) {
1572 /* Flow control (Rx & Tx) is completely disabled by a
1573 * software over-ride.
1575 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1577 case e1000_fc_rx_pause:
1578 /* Rx Flow control is enabled, and Tx Flow control is
1579 * disabled, by a software over-ride.
1581 * Since there really isn't a way to advertise that we are
1582 * capable of Rx Pause ONLY, we will advertise that we
1583 * support both symmetric and asymmetric Rx PAUSE. Later
1584 * (in e1000_config_fc_after_link_up) we will disable the
1585 * hw's ability to send PAUSE frames.
1587 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1589 case e1000_fc_tx_pause:
1590 /* Tx Flow control is enabled, and Rx Flow control is
1591 * disabled, by a software over-ride.
1593 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1594 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1597 /* Flow control (both Rx and Tx) is enabled by a software
1600 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1603 DEBUGOUT("Flow control param set incorrectly\n");
1604 return -E1000_ERR_CONFIG;
1607 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1611 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1613 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1614 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1615 mii_1000t_ctrl_reg);
1621 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1622 * @hw: pointer to the HW structure
1624 * Performs initial bounds checking on autoneg advertisement parameter, then
1625 * configure to advertise the full capability. Setup the PHY to autoneg
1626 * and restart the negotiation process between the link partner. If
1627 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1629 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1631 struct e1000_phy_info *phy = &hw->phy;
1635 DEBUGFUNC("e1000_copper_link_autoneg");
1637 /* Perform some bounds checking on the autoneg advertisement
1640 phy->autoneg_advertised &= phy->autoneg_mask;
1642 /* If autoneg_advertised is zero, we assume it was not defaulted
1643 * by the calling code so we set to advertise full capability.
1645 if (!phy->autoneg_advertised)
1646 phy->autoneg_advertised = phy->autoneg_mask;
1648 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1649 ret_val = e1000_phy_setup_autoneg(hw);
1651 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1654 DEBUGOUT("Restarting Auto-Neg\n");
1656 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1657 * the Auto Neg Restart bit in the PHY control register.
1659 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1663 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1664 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1668 /* Does the user want to wait for Auto-Neg to complete here, or
1669 * check at a later time (for example, callback routine).
1671 if (phy->autoneg_wait_to_complete) {
1672 ret_val = e1000_wait_autoneg(hw);
1674 DEBUGOUT("Error while waiting for autoneg to complete\n");
1679 hw->mac.get_link_status = true;
1685 * e1000_setup_copper_link_generic - Configure copper link settings
1686 * @hw: pointer to the HW structure
1688 * Calls the appropriate function to configure the link for auto-neg or forced
1689 * speed and duplex. Then we check for link, once link is established calls
1690 * to configure collision distance and flow control are called. If link is
1691 * not established, we return -E1000_ERR_PHY (-2).
1693 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1698 DEBUGFUNC("e1000_setup_copper_link_generic");
1700 if (hw->mac.autoneg) {
1701 /* Setup autoneg and flow control advertisement and perform
1704 ret_val = e1000_copper_link_autoneg(hw);
1708 /* PHY will be set to 10H, 10F, 100H or 100F
1709 * depending on user settings.
1711 DEBUGOUT("Forcing Speed and Duplex\n");
1712 ret_val = hw->phy.ops.force_speed_duplex(hw);
1714 DEBUGOUT("Error Forcing Speed and Duplex\n");
1719 /* Check link status. Wait up to 100 microseconds for link to become
1722 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1728 DEBUGOUT("Valid link established!!!\n");
1729 hw->mac.ops.config_collision_dist(hw);
1730 ret_val = e1000_config_fc_after_link_up_generic(hw);
1732 DEBUGOUT("Unable to establish link!!!\n");
1739 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1740 * @hw: pointer to the HW structure
1742 * Calls the PHY setup function to force speed and duplex. Clears the
1743 * auto-crossover to force MDI manually. Waits for link and returns
1744 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1746 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1748 struct e1000_phy_info *phy = &hw->phy;
1753 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1755 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1759 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1761 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1765 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1766 * forced whenever speed and duplex are forced.
1768 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1772 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1773 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1775 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1779 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1783 if (phy->autoneg_wait_to_complete) {
1784 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1786 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1792 DEBUGOUT("Link taking longer than expected.\n");
1795 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1803 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1804 * @hw: pointer to the HW structure
1806 * Calls the PHY setup function to force speed and duplex. Clears the
1807 * auto-crossover to force MDI manually. Resets the PHY to commit the
1808 * changes. If time expires while waiting for link up, we reset the DSP.
1809 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1810 * successful completion, else return corresponding error code.
1812 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1814 struct e1000_phy_info *phy = &hw->phy;
1819 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1821 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1822 if (phy->type != e1000_phy_i210) {
1823 /* Clear Auto-Crossover to force MDI manually. M88E1000
1824 * requires MDI forced whenever speed and duplex are forced.
1826 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1831 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1832 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1838 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1840 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1844 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1846 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1850 /* Reset the phy to commit changes. */
1851 ret_val = hw->phy.ops.commit(hw);
1855 if (phy->autoneg_wait_to_complete) {
1856 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1858 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1864 bool reset_dsp = true;
1866 switch (hw->phy.id) {
1867 case I347AT4_E_PHY_ID:
1868 case M88E1340M_E_PHY_ID:
1869 case M88E1112_E_PHY_ID:
1870 case M88E1543_E_PHY_ID:
1871 case M88E1512_E_PHY_ID:
1876 if (hw->phy.type != e1000_phy_m88)
1882 DEBUGOUT("Link taking longer than expected.\n");
1884 /* We didn't get link.
1885 * Reset the DSP and cross our fingers.
1887 ret_val = phy->ops.write_reg(hw,
1888 M88E1000_PHY_PAGE_SELECT,
1892 ret_val = e1000_phy_reset_dsp_generic(hw);
1899 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1905 if (hw->phy.type != e1000_phy_m88)
1906 return E1000_SUCCESS;
1908 if (hw->phy.id == I347AT4_E_PHY_ID ||
1909 hw->phy.id == M88E1340M_E_PHY_ID ||
1910 hw->phy.id == M88E1112_E_PHY_ID)
1911 return E1000_SUCCESS;
1912 if (hw->phy.id == I210_I_PHY_ID)
1913 return E1000_SUCCESS;
1914 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1915 (hw->phy.id == M88E1512_E_PHY_ID))
1916 return E1000_SUCCESS;
1917 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1921 /* Resetting the phy means we need to re-force TX_CLK in the
1922 * Extended PHY Specific Control Register to 25MHz clock from
1923 * the reset value of 2.5MHz.
1925 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1926 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1930 /* In addition, we must re-enable CRS on Tx for both half and full
1933 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1937 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1938 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1944 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1945 * @hw: pointer to the HW structure
1947 * Forces the speed and duplex settings of the PHY.
1948 * This is a function pointer entry point only called by
1949 * PHY setup routines.
1951 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1953 struct e1000_phy_info *phy = &hw->phy;
1958 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1960 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1964 e1000_phy_force_speed_duplex_setup(hw, &data);
1966 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1970 /* Disable MDI-X support for 10/100 */
1971 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1975 data &= ~IFE_PMC_AUTO_MDIX;
1976 data &= ~IFE_PMC_FORCE_MDIX;
1978 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1982 DEBUGOUT1("IFE PMC: %X\n", data);
1986 if (phy->autoneg_wait_to_complete) {
1987 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1989 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1995 DEBUGOUT("Link taking longer than expected.\n");
1998 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2004 return E1000_SUCCESS;
2008 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2009 * @hw: pointer to the HW structure
2010 * @phy_ctrl: pointer to current value of PHY_CONTROL
2012 * Forces speed and duplex on the PHY by doing the following: disable flow
2013 * control, force speed/duplex on the MAC, disable auto speed detection,
2014 * disable auto-negotiation, configure duplex, configure speed, configure
2015 * the collision distance, write configuration to CTRL register. The
2016 * caller must write to the PHY_CONTROL register for these settings to
2019 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2021 struct e1000_mac_info *mac = &hw->mac;
2024 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2026 /* Turn off flow control when forcing speed/duplex */
2027 hw->fc.current_mode = e1000_fc_none;
2029 /* Force speed/duplex on the mac */
2030 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2031 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2032 ctrl &= ~E1000_CTRL_SPD_SEL;
2034 /* Disable Auto Speed Detection */
2035 ctrl &= ~E1000_CTRL_ASDE;
2037 /* Disable autoneg on the phy */
2038 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2040 /* Forcing Full or Half Duplex? */
2041 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2042 ctrl &= ~E1000_CTRL_FD;
2043 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2044 DEBUGOUT("Half Duplex\n");
2046 ctrl |= E1000_CTRL_FD;
2047 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2048 DEBUGOUT("Full Duplex\n");
2051 /* Forcing 10mb or 100mb? */
2052 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2053 ctrl |= E1000_CTRL_SPD_100;
2054 *phy_ctrl |= MII_CR_SPEED_100;
2055 *phy_ctrl &= ~MII_CR_SPEED_1000;
2056 DEBUGOUT("Forcing 100mb\n");
2058 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2059 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2060 DEBUGOUT("Forcing 10mb\n");
2063 hw->mac.ops.config_collision_dist(hw);
2065 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2069 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2070 * @hw: pointer to the HW structure
2071 * @active: boolean used to enable/disable lplu
2073 * Success returns 0, Failure returns 1
2075 * The low power link up (lplu) state is set to the power management level D3
2076 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2077 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2078 * is used during Dx states where the power conservation is most important.
2079 * During driver activity, SmartSpeed should be enabled so performance is
2082 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2084 struct e1000_phy_info *phy = &hw->phy;
2088 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2090 if (!hw->phy.ops.read_reg)
2091 return E1000_SUCCESS;
2093 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2098 data &= ~IGP02E1000_PM_D3_LPLU;
2099 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2103 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2104 * during Dx states where the power conservation is most
2105 * important. During driver activity we should enable
2106 * SmartSpeed, so performance is maintained.
2108 if (phy->smart_speed == e1000_smart_speed_on) {
2109 ret_val = phy->ops.read_reg(hw,
2110 IGP01E1000_PHY_PORT_CONFIG,
2115 data |= IGP01E1000_PSCFR_SMART_SPEED;
2116 ret_val = phy->ops.write_reg(hw,
2117 IGP01E1000_PHY_PORT_CONFIG,
2121 } else if (phy->smart_speed == e1000_smart_speed_off) {
2122 ret_val = phy->ops.read_reg(hw,
2123 IGP01E1000_PHY_PORT_CONFIG,
2128 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2129 ret_val = phy->ops.write_reg(hw,
2130 IGP01E1000_PHY_PORT_CONFIG,
2135 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2136 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2137 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2138 data |= IGP02E1000_PM_D3_LPLU;
2139 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2144 /* When LPLU is enabled, we should disable SmartSpeed */
2145 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2150 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2151 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2159 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2160 * @hw: pointer to the HW structure
2162 * Success returns 0, Failure returns 1
2164 * A downshift is detected by querying the PHY link health.
2166 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2168 struct e1000_phy_info *phy = &hw->phy;
2170 u16 phy_data, offset, mask;
2172 DEBUGFUNC("e1000_check_downshift_generic");
2174 switch (phy->type) {
2175 case e1000_phy_i210:
2177 case e1000_phy_gg82563:
2179 case e1000_phy_82578:
2180 offset = M88E1000_PHY_SPEC_STATUS;
2181 mask = M88E1000_PSSR_DOWNSHIFT;
2184 case e1000_phy_igp_2:
2185 case e1000_phy_igp_3:
2186 offset = IGP01E1000_PHY_LINK_HEALTH;
2187 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2190 /* speed downshift not supported */
2191 phy->speed_downgraded = false;
2192 return E1000_SUCCESS;
2195 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2198 phy->speed_downgraded = !!(phy_data & mask);
2204 * e1000_check_polarity_m88 - Checks the polarity.
2205 * @hw: pointer to the HW structure
2207 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2209 * Polarity is determined based on the PHY specific status register.
2211 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2213 struct e1000_phy_info *phy = &hw->phy;
2217 DEBUGFUNC("e1000_check_polarity_m88");
2219 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2222 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2223 ? e1000_rev_polarity_reversed
2224 : e1000_rev_polarity_normal);
2230 * e1000_check_polarity_igp - Checks the polarity.
2231 * @hw: pointer to the HW structure
2233 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2235 * Polarity is determined based on the PHY port status register, and the
2236 * current speed (since there is no polarity at 100Mbps).
2238 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2240 struct e1000_phy_info *phy = &hw->phy;
2242 u16 data, offset, mask;
2244 DEBUGFUNC("e1000_check_polarity_igp");
2246 /* Polarity is determined based on the speed of
2249 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2253 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2254 IGP01E1000_PSSR_SPEED_1000MBPS) {
2255 offset = IGP01E1000_PHY_PCS_INIT_REG;
2256 mask = IGP01E1000_PHY_POLARITY_MASK;
2258 /* This really only applies to 10Mbps since
2259 * there is no polarity for 100Mbps (always 0).
2261 offset = IGP01E1000_PHY_PORT_STATUS;
2262 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2265 ret_val = phy->ops.read_reg(hw, offset, &data);
2268 phy->cable_polarity = ((data & mask)
2269 ? e1000_rev_polarity_reversed
2270 : e1000_rev_polarity_normal);
2276 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2277 * @hw: pointer to the HW structure
2279 * Polarity is determined on the polarity reversal feature being enabled.
2281 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2283 struct e1000_phy_info *phy = &hw->phy;
2285 u16 phy_data, offset, mask;
2287 DEBUGFUNC("e1000_check_polarity_ife");
2289 /* Polarity is determined based on the reversal feature being enabled.
2291 if (phy->polarity_correction) {
2292 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2293 mask = IFE_PESC_POLARITY_REVERSED;
2295 offset = IFE_PHY_SPECIAL_CONTROL;
2296 mask = IFE_PSC_FORCE_POLARITY;
2299 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2302 phy->cable_polarity = ((phy_data & mask)
2303 ? e1000_rev_polarity_reversed
2304 : e1000_rev_polarity_normal);
2310 * e1000_wait_autoneg - Wait for auto-neg completion
2311 * @hw: pointer to the HW structure
2313 * Waits for auto-negotiation to complete or for the auto-negotiation time
2314 * limit to expire, which ever happens first.
2316 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2318 s32 ret_val = E1000_SUCCESS;
2321 DEBUGFUNC("e1000_wait_autoneg");
2323 if (!hw->phy.ops.read_reg)
2324 return E1000_SUCCESS;
2326 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2327 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2328 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2331 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2334 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2339 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2346 * e1000_phy_has_link_generic - Polls PHY for link
2347 * @hw: pointer to the HW structure
2348 * @iterations: number of times to poll for link
2349 * @usec_interval: delay between polling attempts
2350 * @success: pointer to whether polling was successful or not
2352 * Polls the PHY status register for link, 'iterations' number of times.
2354 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2355 u32 usec_interval, bool *success)
2357 s32 ret_val = E1000_SUCCESS;
2360 DEBUGFUNC("e1000_phy_has_link_generic");
2362 if (!hw->phy.ops.read_reg)
2363 return E1000_SUCCESS;
2365 for (i = 0; i < iterations; i++) {
2366 /* Some PHYs require the PHY_STATUS register to be read
2367 * twice due to the link bit being sticky. No harm doing
2368 * it across the board.
2370 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2372 /* If the first read fails, another entity may have
2373 * ownership of the resources, wait and try again to
2374 * see if they have relinquished the resources yet.
2376 usec_delay(usec_interval);
2377 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2380 if (phy_status & MII_SR_LINK_STATUS)
2382 if (usec_interval >= 1000)
2383 msec_delay_irq(usec_interval/1000);
2385 usec_delay(usec_interval);
2388 *success = (i < iterations);
2394 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2395 * @hw: pointer to the HW structure
2397 * Reads the PHY specific status register to retrieve the cable length
2398 * information. The cable length is determined by averaging the minimum and
2399 * maximum values to get the "average" cable length. The m88 PHY has four
2400 * possible cable length values, which are:
2401 * Register Value Cable Length
2405 * 3 110 - 140 meters
2408 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2410 struct e1000_phy_info *phy = &hw->phy;
2412 u16 phy_data, index;
2414 DEBUGFUNC("e1000_get_cable_length_m88");
2416 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2420 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2421 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2423 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2424 return -E1000_ERR_PHY;
2426 phy->min_cable_length = e1000_m88_cable_length_table[index];
2427 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2429 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2431 return E1000_SUCCESS;
2434 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2436 struct e1000_phy_info *phy = &hw->phy;
2438 u16 phy_data, phy_data2, is_cm;
2439 u16 index, default_page;
2441 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2443 switch (hw->phy.id) {
2445 /* Get cable length from PHY Cable Diagnostics Control Reg */
2446 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2447 (I347AT4_PCDL + phy->addr),
2452 /* Check if the unit of cable length is meters or cm */
2453 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2454 I347AT4_PCDC, &phy_data2);
2458 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2460 /* Populate the phy structure with cable length in meters */
2461 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2462 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2463 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2465 case M88E1543_E_PHY_ID:
2466 case M88E1512_E_PHY_ID:
2467 case M88E1340M_E_PHY_ID:
2468 case I347AT4_E_PHY_ID:
2469 /* Remember the original page select and set it to 7 */
2470 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2475 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2479 /* Get cable length from PHY Cable Diagnostics Control Reg */
2480 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2485 /* Check if the unit of cable length is meters or cm */
2486 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2490 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2492 /* Populate the phy structure with cable length in meters */
2493 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2494 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2495 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2497 /* Reset the page select to its original value */
2498 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2504 case M88E1112_E_PHY_ID:
2505 /* Remember the original page select and set it to 5 */
2506 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2511 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2515 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2520 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2521 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2523 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2524 return -E1000_ERR_PHY;
2526 phy->min_cable_length = e1000_m88_cable_length_table[index];
2527 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2529 phy->cable_length = (phy->min_cable_length +
2530 phy->max_cable_length) / 2;
2532 /* Reset the page select to its original value */
2533 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2540 return -E1000_ERR_PHY;
2547 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2548 * @hw: pointer to the HW structure
2550 * The automatic gain control (agc) normalizes the amplitude of the
2551 * received signal, adjusting for the attenuation produced by the
2552 * cable. By reading the AGC registers, which represent the
2553 * combination of coarse and fine gain value, the value can be put
2554 * into a lookup table to obtain the approximate cable length
2557 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2559 struct e1000_phy_info *phy = &hw->phy;
2561 u16 phy_data, i, agc_value = 0;
2562 u16 cur_agc_index, max_agc_index = 0;
2563 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2564 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2565 IGP02E1000_PHY_AGC_A,
2566 IGP02E1000_PHY_AGC_B,
2567 IGP02E1000_PHY_AGC_C,
2568 IGP02E1000_PHY_AGC_D
2571 DEBUGFUNC("e1000_get_cable_length_igp_2");
2573 /* Read the AGC registers for all channels */
2574 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2575 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2579 /* Getting bits 15:9, which represent the combination of
2580 * coarse and fine gain values. The result is a number
2581 * that can be put into the lookup table to obtain the
2582 * approximate cable length.
2584 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2585 IGP02E1000_AGC_LENGTH_MASK);
2587 /* Array index bound check. */
2588 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2589 (cur_agc_index == 0))
2590 return -E1000_ERR_PHY;
2592 /* Remove min & max AGC values from calculation. */
2593 if (e1000_igp_2_cable_length_table[min_agc_index] >
2594 e1000_igp_2_cable_length_table[cur_agc_index])
2595 min_agc_index = cur_agc_index;
2596 if (e1000_igp_2_cable_length_table[max_agc_index] <
2597 e1000_igp_2_cable_length_table[cur_agc_index])
2598 max_agc_index = cur_agc_index;
2600 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2603 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2604 e1000_igp_2_cable_length_table[max_agc_index]);
2605 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2607 /* Calculate cable length with the error range of +/- 10 meters. */
2608 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2609 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2610 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2612 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2614 return E1000_SUCCESS;
2618 * e1000_get_phy_info_m88 - Retrieve PHY information
2619 * @hw: pointer to the HW structure
2621 * Valid for only copper links. Read the PHY status register (sticky read)
2622 * to verify that link is up. Read the PHY special control register to
2623 * determine the polarity and 10base-T extended distance. Read the PHY
2624 * special status register to determine MDI/MDIx and current speed. If
2625 * speed is 1000, then determine cable length, local and remote receiver.
2627 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2629 struct e1000_phy_info *phy = &hw->phy;
2634 DEBUGFUNC("e1000_get_phy_info_m88");
2636 if (phy->media_type != e1000_media_type_copper) {
2637 DEBUGOUT("Phy info is only valid for copper media\n");
2638 return -E1000_ERR_CONFIG;
2641 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2646 DEBUGOUT("Phy info is only valid if link is up\n");
2647 return -E1000_ERR_CONFIG;
2650 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2654 phy->polarity_correction = !!(phy_data &
2655 M88E1000_PSCR_POLARITY_REVERSAL);
2657 ret_val = e1000_check_polarity_m88(hw);
2661 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2665 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2667 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2668 ret_val = hw->phy.ops.get_cable_length(hw);
2672 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2676 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2677 ? e1000_1000t_rx_status_ok
2678 : e1000_1000t_rx_status_not_ok;
2680 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2681 ? e1000_1000t_rx_status_ok
2682 : e1000_1000t_rx_status_not_ok;
2684 /* Set values to "undefined" */
2685 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2686 phy->local_rx = e1000_1000t_rx_status_undefined;
2687 phy->remote_rx = e1000_1000t_rx_status_undefined;
2694 * e1000_get_phy_info_igp - Retrieve igp PHY information
2695 * @hw: pointer to the HW structure
2697 * Read PHY status to determine if link is up. If link is up, then
2698 * set/determine 10base-T extended distance and polarity correction. Read
2699 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2700 * determine on the cable length, local and remote receiver.
2702 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2704 struct e1000_phy_info *phy = &hw->phy;
2709 DEBUGFUNC("e1000_get_phy_info_igp");
2711 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2716 DEBUGOUT("Phy info is only valid if link is up\n");
2717 return -E1000_ERR_CONFIG;
2720 phy->polarity_correction = true;
2722 ret_val = e1000_check_polarity_igp(hw);
2726 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2730 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2732 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2733 IGP01E1000_PSSR_SPEED_1000MBPS) {
2734 ret_val = phy->ops.get_cable_length(hw);
2738 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2742 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2743 ? e1000_1000t_rx_status_ok
2744 : e1000_1000t_rx_status_not_ok;
2746 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2747 ? e1000_1000t_rx_status_ok
2748 : e1000_1000t_rx_status_not_ok;
2750 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2751 phy->local_rx = e1000_1000t_rx_status_undefined;
2752 phy->remote_rx = e1000_1000t_rx_status_undefined;
2759 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2760 * @hw: pointer to the HW structure
2762 * Populates "phy" structure with various feature states.
2764 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2766 struct e1000_phy_info *phy = &hw->phy;
2771 DEBUGFUNC("e1000_get_phy_info_ife");
2773 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2778 DEBUGOUT("Phy info is only valid if link is up\n");
2779 return -E1000_ERR_CONFIG;
2782 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2785 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2787 if (phy->polarity_correction) {
2788 ret_val = e1000_check_polarity_ife(hw);
2792 /* Polarity is forced */
2793 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2794 ? e1000_rev_polarity_reversed
2795 : e1000_rev_polarity_normal);
2798 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2802 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2804 /* The following parameters are undefined for 10/100 operation. */
2805 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2806 phy->local_rx = e1000_1000t_rx_status_undefined;
2807 phy->remote_rx = e1000_1000t_rx_status_undefined;
2809 return E1000_SUCCESS;
2813 * e1000_phy_sw_reset_generic - PHY software reset
2814 * @hw: pointer to the HW structure
2816 * Does a software reset of the PHY by reading the PHY control register and
2817 * setting/write the control register reset bit to the PHY.
2819 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2824 DEBUGFUNC("e1000_phy_sw_reset_generic");
2826 if (!hw->phy.ops.read_reg)
2827 return E1000_SUCCESS;
2829 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2833 phy_ctrl |= MII_CR_RESET;
2834 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2844 * e1000_phy_hw_reset_generic - PHY hardware reset
2845 * @hw: pointer to the HW structure
2847 * Verify the reset block is not blocking us from resetting. Acquire
2848 * semaphore (if necessary) and read/set/write the device control reset
2849 * bit in the PHY. Wait the appropriate delay time for the device to
2850 * reset and release the semaphore (if necessary).
2852 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2854 struct e1000_phy_info *phy = &hw->phy;
2858 DEBUGFUNC("e1000_phy_hw_reset_generic");
2860 if (phy->ops.check_reset_block) {
2861 ret_val = phy->ops.check_reset_block(hw);
2863 return E1000_SUCCESS;
2866 ret_val = phy->ops.acquire(hw);
2870 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2871 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2872 E1000_WRITE_FLUSH(hw);
2874 usec_delay(phy->reset_delay_us);
2876 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2877 E1000_WRITE_FLUSH(hw);
2881 phy->ops.release(hw);
2883 return phy->ops.get_cfg_done(hw);
2887 * e1000_get_cfg_done_generic - Generic configuration done
2888 * @hw: pointer to the HW structure
2890 * Generic function to wait 10 milli-seconds for configuration to complete
2891 * and return success.
2893 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2895 DEBUGFUNC("e1000_get_cfg_done_generic");
2896 UNREFERENCED_1PARAMETER(hw);
2900 return E1000_SUCCESS;
2904 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2905 * @hw: pointer to the HW structure
2907 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2909 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2911 DEBUGOUT("Running IGP 3 PHY init script\n");
2913 /* PHY init IGP 3 */
2914 /* Enable rise/fall, 10-mode work in class-A */
2915 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2916 /* Remove all caps from Replica path filter */
2917 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2918 /* Bias trimming for ADC, AFE and Driver (Default) */
2919 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2920 /* Increase Hybrid poly bias */
2921 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2922 /* Add 4% to Tx amplitude in Gig mode */
2923 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2924 /* Disable trimming (TTT) */
2925 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2926 /* Poly DC correction to 94.6% + 2% for all channels */
2927 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2928 /* ABS DC correction to 95.9% */
2929 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2930 /* BG temp curve trim */
2931 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2932 /* Increasing ADC OPAMP stage 1 currents to max */
2933 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2934 /* Force 1000 ( required for enabling PHY regs configuration) */
2935 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2936 /* Set upd_freq to 6 */
2937 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2939 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2940 /* Disable adaptive fixed FFE (Default) */
2941 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2942 /* Enable FFE hysteresis */
2943 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2944 /* Fixed FFE for short cable lengths */
2945 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2946 /* Fixed FFE for medium cable lengths */
2947 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2948 /* Fixed FFE for long cable lengths */
2949 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2950 /* Enable Adaptive Clip Threshold */
2951 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2952 /* AHT reset limit to 1 */
2953 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2954 /* Set AHT master delay to 127 msec */
2955 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2956 /* Set scan bits for AHT */
2957 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2958 /* Set AHT Preset bits */
2959 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2960 /* Change integ_factor of channel A to 3 */
2961 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2962 /* Change prop_factor of channels BCD to 8 */
2963 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2964 /* Change cg_icount + enable integbp for channels BCD */
2965 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2966 /* Change cg_icount + enable integbp + change prop_factor_master
2967 * to 8 for channel A
2969 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2970 /* Disable AHT in Slave mode on channel A */
2971 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2972 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2975 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2976 /* Enable restart AN on an1000_dis change */
2977 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2978 /* Enable wh_fifo read clock in 10/100 modes */
2979 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2980 /* Restart AN, Speed selection is 1000 */
2981 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2983 return E1000_SUCCESS;
2987 * e1000_get_phy_type_from_id - Get PHY type from id
2988 * @phy_id: phy_id read from the phy
2990 * Returns the phy type from the id.
2992 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2994 enum e1000_phy_type phy_type = e1000_phy_unknown;
2997 case M88E1000_I_PHY_ID:
2998 case M88E1000_E_PHY_ID:
2999 case M88E1111_I_PHY_ID:
3000 case M88E1011_I_PHY_ID:
3001 case M88E1543_E_PHY_ID:
3002 case M88E1512_E_PHY_ID:
3003 case I347AT4_E_PHY_ID:
3004 case M88E1112_E_PHY_ID:
3005 case M88E1340M_E_PHY_ID:
3006 phy_type = e1000_phy_m88;
3008 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3009 phy_type = e1000_phy_igp_2;
3011 case GG82563_E_PHY_ID:
3012 phy_type = e1000_phy_gg82563;
3014 case IGP03E1000_E_PHY_ID:
3015 phy_type = e1000_phy_igp_3;
3018 case IFE_PLUS_E_PHY_ID:
3019 case IFE_C_E_PHY_ID:
3020 phy_type = e1000_phy_ife;
3022 case BME1000_E_PHY_ID:
3023 case BME1000_E_PHY_ID_R2:
3024 phy_type = e1000_phy_bm;
3026 case I82578_E_PHY_ID:
3027 phy_type = e1000_phy_82578;
3029 case I82577_E_PHY_ID:
3030 phy_type = e1000_phy_82577;
3032 case I82579_E_PHY_ID:
3033 phy_type = e1000_phy_82579;
3036 phy_type = e1000_phy_i217;
3038 case I82580_I_PHY_ID:
3039 phy_type = e1000_phy_82580;
3042 phy_type = e1000_phy_i210;
3045 phy_type = e1000_phy_unknown;
3052 * e1000_determine_phy_address - Determines PHY address.
3053 * @hw: pointer to the HW structure
3055 * This uses a trial and error method to loop through possible PHY
3056 * addresses. It tests each by reading the PHY ID registers and
3057 * checking for a match.
3059 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3063 enum e1000_phy_type phy_type = e1000_phy_unknown;
3065 hw->phy.id = phy_type;
3067 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3068 hw->phy.addr = phy_addr;
3072 e1000_get_phy_id(hw);
3073 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3075 /* If phy_type is valid, break - we found our
3078 if (phy_type != e1000_phy_unknown)
3079 return E1000_SUCCESS;
3086 return -E1000_ERR_PHY_TYPE;
3090 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3091 * @page: page to access
3093 * Returns the phy address for the page requested.
3095 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3099 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3106 * e1000_write_phy_reg_bm - Write BM PHY register
3107 * @hw: pointer to the HW structure
3108 * @offset: register offset to write to
3109 * @data: data to write at register offset
3111 * Acquires semaphore, if necessary, then writes the data to PHY register
3112 * at the offset. Release any acquired semaphores before exiting.
3114 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3117 u32 page = offset >> IGP_PAGE_SHIFT;
3119 DEBUGFUNC("e1000_write_phy_reg_bm");
3121 ret_val = hw->phy.ops.acquire(hw);
3125 /* Page 800 works differently than the rest so it has its own func */
3126 if (page == BM_WUC_PAGE) {
3127 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3132 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3134 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3135 u32 page_shift, page_select;
3137 /* Page select is register 31 for phy address 1 and 22 for
3138 * phy address 2 and 3. Page select is shifted only for
3141 if (hw->phy.addr == 1) {
3142 page_shift = IGP_PAGE_SHIFT;
3143 page_select = IGP01E1000_PHY_PAGE_SELECT;
3146 page_select = BM_PHY_PAGE_SELECT;
3149 /* Page is shifted left, PHY expects (page x 32) */
3150 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3151 (page << page_shift));
3156 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3160 hw->phy.ops.release(hw);
3165 * e1000_read_phy_reg_bm - Read BM PHY register
3166 * @hw: pointer to the HW structure
3167 * @offset: register offset to be read
3168 * @data: pointer to the read data
3170 * Acquires semaphore, if necessary, then reads the PHY register at offset
3171 * and storing the retrieved information in data. Release any acquired
3172 * semaphores before exiting.
3174 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3177 u32 page = offset >> IGP_PAGE_SHIFT;
3179 DEBUGFUNC("e1000_read_phy_reg_bm");
3181 ret_val = hw->phy.ops.acquire(hw);
3185 /* Page 800 works differently than the rest so it has its own func */
3186 if (page == BM_WUC_PAGE) {
3187 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3192 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3194 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3195 u32 page_shift, page_select;
3197 /* Page select is register 31 for phy address 1 and 22 for
3198 * phy address 2 and 3. Page select is shifted only for
3201 if (hw->phy.addr == 1) {
3202 page_shift = IGP_PAGE_SHIFT;
3203 page_select = IGP01E1000_PHY_PAGE_SELECT;
3206 page_select = BM_PHY_PAGE_SELECT;
3209 /* Page is shifted left, PHY expects (page x 32) */
3210 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3211 (page << page_shift));
3216 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3219 hw->phy.ops.release(hw);
3224 * e1000_read_phy_reg_bm2 - Read BM PHY register
3225 * @hw: pointer to the HW structure
3226 * @offset: register offset to be read
3227 * @data: pointer to the read data
3229 * Acquires semaphore, if necessary, then reads the PHY register at offset
3230 * and storing the retrieved information in data. Release any acquired
3231 * semaphores before exiting.
3233 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3236 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3238 DEBUGFUNC("e1000_read_phy_reg_bm2");
3240 ret_val = hw->phy.ops.acquire(hw);
3244 /* Page 800 works differently than the rest so it has its own func */
3245 if (page == BM_WUC_PAGE) {
3246 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3253 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3254 /* Page is shifted left, PHY expects (page x 32) */
3255 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3262 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3265 hw->phy.ops.release(hw);
3270 * e1000_write_phy_reg_bm2 - Write BM PHY register
3271 * @hw: pointer to the HW structure
3272 * @offset: register offset to write to
3273 * @data: data to write at register offset
3275 * Acquires semaphore, if necessary, then writes the data to PHY register
3276 * at the offset. Release any acquired semaphores before exiting.
3278 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3281 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3283 DEBUGFUNC("e1000_write_phy_reg_bm2");
3285 ret_val = hw->phy.ops.acquire(hw);
3289 /* Page 800 works differently than the rest so it has its own func */
3290 if (page == BM_WUC_PAGE) {
3291 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3298 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3299 /* Page is shifted left, PHY expects (page x 32) */
3300 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3307 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3311 hw->phy.ops.release(hw);
3316 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3317 * @hw: pointer to the HW structure
3318 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3320 * Assumes semaphore already acquired and phy_reg points to a valid memory
3321 * address to store contents of the BM_WUC_ENABLE_REG register.
3323 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3328 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3331 return -E1000_ERR_PARAM;
3333 /* All page select, port ctrl and wakeup registers use phy address 1 */
3336 /* Select Port Control Registers page */
3337 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3339 DEBUGOUT("Could not set Port Control page\n");
3343 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3345 DEBUGOUT2("Could not read PHY register %d.%d\n",
3346 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3350 /* Enable both PHY wakeup mode and Wakeup register page writes.
3351 * Prevent a power state change by disabling ME and Host PHY wakeup.
3354 temp |= BM_WUC_ENABLE_BIT;
3355 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3357 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3359 DEBUGOUT2("Could not write PHY register %d.%d\n",
3360 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3364 /* Select Host Wakeup Registers page - caller now able to write
3365 * registers on the Wakeup registers page
3367 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3371 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3372 * @hw: pointer to the HW structure
3373 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3375 * Restore BM_WUC_ENABLE_REG to its original value.
3377 * Assumes semaphore already acquired and *phy_reg is the contents of the
3378 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3381 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3385 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3388 return -E1000_ERR_PARAM;
3390 /* Select Port Control Registers page */
3391 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3393 DEBUGOUT("Could not set Port Control page\n");
3397 /* Restore 769.17 to its original value */
3398 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3400 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3401 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3407 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3408 * @hw: pointer to the HW structure
3409 * @offset: register offset to be read or written
3410 * @data: pointer to the data to read or write
3411 * @read: determines if operation is read or write
3412 * @page_set: BM_WUC_PAGE already set and access enabled
3414 * Read the PHY register at offset and store the retrieved information in
3415 * data, or write data to PHY register at offset. Note the procedure to
3416 * access the PHY wakeup registers is different than reading the other PHY
3417 * registers. It works as such:
3418 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3419 * 2) Set page to 800 for host (801 if we were manageability)
3420 * 3) Write the address using the address opcode (0x11)
3421 * 4) Read or write the data using the data opcode (0x12)
3422 * 5) Restore 769.17.2 to its original value
3424 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3425 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3427 * Assumes semaphore is already acquired. When page_set==true, assumes
3428 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3429 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3431 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3432 u16 *data, bool read, bool page_set)
3435 u16 reg = BM_PHY_REG_NUM(offset);
3436 u16 page = BM_PHY_REG_PAGE(offset);
3439 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3441 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3442 if ((hw->mac.type == e1000_pchlan) &&
3443 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3444 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3448 /* Enable access to PHY wakeup registers */
3449 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3451 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3456 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3458 /* Write the Wakeup register page offset value using opcode 0x11 */
3459 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3461 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3466 /* Read the Wakeup register page value using opcode 0x12 */
3467 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3470 /* Write the Wakeup register page value using opcode 0x12 */
3471 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3476 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3481 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3487 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3488 * @hw: pointer to the HW structure
3490 * In the case of a PHY power down to save power, or to turn off link during a
3491 * driver unload, or wake on lan is not enabled, restore the link to previous
3494 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3499 /* The PHY will retain its settings across a power down/up cycle */
3500 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3501 mii_reg &= ~MII_CR_POWER_DOWN;
3502 if (hw->phy.type == e1000_phy_i210) {
3503 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3504 power_reg &= ~GS40G_CS_POWER_DOWN;
3505 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3507 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3511 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3512 * @hw: pointer to the HW structure
3514 * In the case of a PHY power down to save power, or to turn off link during a
3515 * driver unload, or wake on lan is not enabled, restore the link to previous
3518 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3523 /* The PHY will retain its settings across a power down/up cycle */
3524 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3525 mii_reg |= MII_CR_POWER_DOWN;
3526 /* i210 Phy requires an additional bit for power up/down */
3527 if (hw->phy.type == e1000_phy_i210) {
3528 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3529 power_reg |= GS40G_CS_POWER_DOWN;
3530 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3532 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3537 * __e1000_read_phy_reg_hv - Read HV PHY register
3538 * @hw: pointer to the HW structure
3539 * @offset: register offset to be read
3540 * @data: pointer to the read data
3541 * @locked: semaphore has already been acquired or not
3543 * Acquires semaphore, if necessary, then reads the PHY register at offset
3544 * and stores the retrieved information in data. Release any acquired
3545 * semaphore before exiting.
3547 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3548 bool locked, bool page_set)
3551 u16 page = BM_PHY_REG_PAGE(offset);
3552 u16 reg = BM_PHY_REG_NUM(offset);
3553 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3555 DEBUGFUNC("__e1000_read_phy_reg_hv");
3558 ret_val = hw->phy.ops.acquire(hw);
3563 /* Page 800 works differently than the rest so it has its own func */
3564 if (page == BM_WUC_PAGE) {
3565 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3570 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3571 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3577 if (page == HV_INTC_FC_PAGE_START)
3580 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3581 /* Page is shifted left, PHY expects (page x 32) */
3582 ret_val = e1000_set_page_igp(hw,
3583 (page << IGP_PAGE_SHIFT));
3585 hw->phy.addr = phy_addr;
3592 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3593 page << IGP_PAGE_SHIFT, reg);
3595 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3599 hw->phy.ops.release(hw);
3605 * e1000_read_phy_reg_hv - Read HV PHY register
3606 * @hw: pointer to the HW structure
3607 * @offset: register offset to be read
3608 * @data: pointer to the read data
3610 * Acquires semaphore then reads the PHY register at offset and stores
3611 * the retrieved information in data. Release the acquired semaphore
3614 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3616 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3620 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3621 * @hw: pointer to the HW structure
3622 * @offset: register offset to be read
3623 * @data: pointer to the read data
3625 * Reads the PHY register at offset and stores the retrieved information
3626 * in data. Assumes semaphore already acquired.
3628 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3630 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3634 * e1000_read_phy_reg_page_hv - Read HV PHY register
3635 * @hw: pointer to the HW structure
3636 * @offset: register offset to write to
3637 * @data: data to write at register offset
3639 * Reads the PHY register at offset and stores the retrieved information
3640 * in data. Assumes semaphore already acquired and page already set.
3642 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3644 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3648 * __e1000_write_phy_reg_hv - Write HV PHY register
3649 * @hw: pointer to the HW structure
3650 * @offset: register offset to write to
3651 * @data: data to write at register offset
3652 * @locked: semaphore has already been acquired or not
3654 * Acquires semaphore, if necessary, then writes the data to PHY register
3655 * at the offset. Release any acquired semaphores before exiting.
3657 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3658 bool locked, bool page_set)
3661 u16 page = BM_PHY_REG_PAGE(offset);
3662 u16 reg = BM_PHY_REG_NUM(offset);
3663 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3665 DEBUGFUNC("__e1000_write_phy_reg_hv");
3668 ret_val = hw->phy.ops.acquire(hw);
3673 /* Page 800 works differently than the rest so it has its own func */
3674 if (page == BM_WUC_PAGE) {
3675 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3680 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3681 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3687 if (page == HV_INTC_FC_PAGE_START)
3690 /* Workaround MDIO accesses being disabled after entering IEEE
3691 * Power Down (when bit 11 of the PHY Control register is set)
3693 if ((hw->phy.type == e1000_phy_82578) &&
3694 (hw->phy.revision >= 1) &&
3695 (hw->phy.addr == 2) &&
3696 !(MAX_PHY_REG_ADDRESS & reg) &&
3697 (data & (1 << 11))) {
3699 ret_val = e1000_access_phy_debug_regs_hv(hw,
3706 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3707 /* Page is shifted left, PHY expects (page x 32) */
3708 ret_val = e1000_set_page_igp(hw,
3709 (page << IGP_PAGE_SHIFT));
3711 hw->phy.addr = phy_addr;
3718 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3719 page << IGP_PAGE_SHIFT, reg);
3721 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3726 hw->phy.ops.release(hw);
3732 * e1000_write_phy_reg_hv - Write HV PHY register
3733 * @hw: pointer to the HW structure
3734 * @offset: register offset to write to
3735 * @data: data to write at register offset
3737 * Acquires semaphore then writes the data to PHY register at the offset.
3738 * Release the acquired semaphores before exiting.
3740 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3742 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3746 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3747 * @hw: pointer to the HW structure
3748 * @offset: register offset to write to
3749 * @data: data to write at register offset
3751 * Writes the data to PHY register at the offset. Assumes semaphore
3754 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3756 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3760 * e1000_write_phy_reg_page_hv - Write HV PHY register
3761 * @hw: pointer to the HW structure
3762 * @offset: register offset to write to
3763 * @data: data to write at register offset
3765 * Writes the data to PHY register at the offset. Assumes semaphore
3766 * already acquired and page already set.
3768 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3770 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3774 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3775 * @page: page to be accessed
3777 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page)
3781 if (page >= HV_INTC_FC_PAGE_START)
3788 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3789 * @hw: pointer to the HW structure
3790 * @offset: register offset to be read or written
3791 * @data: pointer to the data to be read or written
3792 * @read: determines if operation is read or write
3794 * Reads the PHY register at offset and stores the retreived information
3795 * in data. Assumes semaphore already acquired. Note that the procedure
3796 * to access these regs uses the address port and data port to read/write.
3797 * These accesses done with PHY address 2 and without using pages.
3799 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3800 u16 *data, bool read)
3806 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3808 /* This takes care of the difference with desktop vs mobile phy */
3809 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3810 I82578_ADDR_REG : I82577_ADDR_REG);
3811 data_reg = addr_reg + 1;
3813 /* All operations in this function are phy address 2 */
3816 /* masking with 0x3F to remove the page from offset */
3817 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3819 DEBUGOUT("Could not write the Address Offset port register\n");
3823 /* Read or write the data value next */
3825 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3827 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3830 DEBUGOUT("Could not access the Data port register\n");
3836 * e1000_link_stall_workaround_hv - Si workaround
3837 * @hw: pointer to the HW structure
3839 * This function works around a Si bug where the link partner can get
3840 * a link up indication before the PHY does. If small packets are sent
3841 * by the link partner they can be placed in the packet buffer without
3842 * being properly accounted for by the PHY and will stall preventing
3843 * further packets from being received. The workaround is to clear the
3844 * packet buffer after the PHY detects link up.
3846 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3848 s32 ret_val = E1000_SUCCESS;
3851 DEBUGFUNC("e1000_link_stall_workaround_hv");
3853 if (hw->phy.type != e1000_phy_82578)
3854 return E1000_SUCCESS;
3856 /* Do not apply workaround if in PHY loopback bit 14 set */
3857 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3858 if (data & PHY_CONTROL_LB)
3859 return E1000_SUCCESS;
3861 /* check if link is up and at 1Gbps */
3862 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3866 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3867 BM_CS_STATUS_SPEED_MASK);
3869 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3870 BM_CS_STATUS_SPEED_1000))
3871 return E1000_SUCCESS;
3875 /* flush the packets in the fifo buffer */
3876 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3877 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3878 HV_MUX_DATA_CTRL_FORCE_SPEED));
3882 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3883 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3887 * e1000_check_polarity_82577 - Checks the polarity.
3888 * @hw: pointer to the HW structure
3890 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3892 * Polarity is determined based on the PHY specific status register.
3894 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3896 struct e1000_phy_info *phy = &hw->phy;
3900 DEBUGFUNC("e1000_check_polarity_82577");
3902 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3905 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3906 ? e1000_rev_polarity_reversed
3907 : e1000_rev_polarity_normal);
3913 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3914 * @hw: pointer to the HW structure
3916 * Calls the PHY setup function to force speed and duplex.
3918 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3920 struct e1000_phy_info *phy = &hw->phy;
3925 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3927 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3931 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3933 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3939 if (phy->autoneg_wait_to_complete) {
3940 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3942 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3948 DEBUGOUT("Link taking longer than expected.\n");
3951 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3959 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3960 * @hw: pointer to the HW structure
3962 * Read PHY status to determine if link is up. If link is up, then
3963 * set/determine 10base-T extended distance and polarity correction. Read
3964 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3965 * determine on the cable length, local and remote receiver.
3967 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3969 struct e1000_phy_info *phy = &hw->phy;
3974 DEBUGFUNC("e1000_get_phy_info_82577");
3976 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3981 DEBUGOUT("Phy info is only valid if link is up\n");
3982 return -E1000_ERR_CONFIG;
3985 phy->polarity_correction = true;
3987 ret_val = e1000_check_polarity_82577(hw);
3991 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3995 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3997 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3998 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3999 ret_val = hw->phy.ops.get_cable_length(hw);
4003 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4007 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4008 ? e1000_1000t_rx_status_ok
4009 : e1000_1000t_rx_status_not_ok;
4011 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4012 ? e1000_1000t_rx_status_ok
4013 : e1000_1000t_rx_status_not_ok;
4015 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4016 phy->local_rx = e1000_1000t_rx_status_undefined;
4017 phy->remote_rx = e1000_1000t_rx_status_undefined;
4020 return E1000_SUCCESS;
4024 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4025 * @hw: pointer to the HW structure
4027 * Reads the diagnostic status register and verifies result is valid before
4028 * placing it in the phy_cable_length field.
4030 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4032 struct e1000_phy_info *phy = &hw->phy;
4034 u16 phy_data, length;
4036 DEBUGFUNC("e1000_get_cable_length_82577");
4038 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4042 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4043 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4045 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4046 return -E1000_ERR_PHY;
4048 phy->cable_length = length;
4050 return E1000_SUCCESS;
4054 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4055 * @hw: pointer to the HW structure
4056 * @offset: register offset to write to
4057 * @data: data to write at register offset
4059 * Acquires semaphore, if necessary, then writes the data to PHY register
4060 * at the offset. Release any acquired semaphores before exiting.
4062 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4065 u16 page = offset >> GS40G_PAGE_SHIFT;
4067 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4069 offset = offset & GS40G_OFFSET_MASK;
4070 ret_val = hw->phy.ops.acquire(hw);
4074 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4077 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4080 hw->phy.ops.release(hw);
4085 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4086 * @hw: pointer to the HW structure
4087 * @offset: lower half is register offset to read to
4088 * upper half is page to use.
4089 * @data: data to read at register offset
4091 * Acquires semaphore, if necessary, then reads the data in the PHY register
4092 * at the offset. Release any acquired semaphores before exiting.
4094 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4097 u16 page = offset >> GS40G_PAGE_SHIFT;
4099 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4101 offset = offset & GS40G_OFFSET_MASK;
4102 ret_val = hw->phy.ops.acquire(hw);
4106 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4109 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4112 hw->phy.ops.release(hw);
4117 * e1000_read_phy_reg_mphy - Read mPHY control register
4118 * @hw: pointer to the HW structure
4119 * @address: address to be read
4120 * @data: pointer to the read data
4122 * Reads the mPHY control register in the PHY at offset and stores the
4123 * information read to data.
4125 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4128 bool locked = false;
4131 DEBUGFUNC("e1000_read_phy_reg_mphy");
4133 /* Check if mPHY is ready to read/write operations */
4134 ready = e1000_is_mphy_ready(hw);
4136 return -E1000_ERR_PHY;
4138 /* Check if mPHY access is disabled and enable it if so */
4139 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4140 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4142 ready = e1000_is_mphy_ready(hw);
4144 return -E1000_ERR_PHY;
4145 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4146 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4149 /* Set the address that we want to read */
4150 ready = e1000_is_mphy_ready(hw);
4152 return -E1000_ERR_PHY;
4154 /* We mask address, because we want to use only current lane */
4155 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4156 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4157 (address & E1000_MPHY_ADDRESS_MASK);
4158 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4160 /* Read data from the address */
4161 ready = e1000_is_mphy_ready(hw);
4163 return -E1000_ERR_PHY;
4164 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4166 /* Disable access to mPHY if it was originally disabled */
4168 ready = e1000_is_mphy_ready(hw);
4170 return -E1000_ERR_PHY;
4171 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4172 E1000_MPHY_DIS_ACCESS);
4174 return E1000_SUCCESS;
4178 * e1000_write_phy_reg_mphy - Write mPHY control register
4179 * @hw: pointer to the HW structure
4180 * @address: address to write to
4181 * @data: data to write to register at offset
4182 * @line_override: used when we want to use different line than default one
4184 * Writes data to mPHY control register.
4186 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4190 bool locked = false;
4193 DEBUGFUNC("e1000_write_phy_reg_mphy");
4195 /* Check if mPHY is ready to read/write operations */
4196 ready = e1000_is_mphy_ready(hw);
4198 return -E1000_ERR_PHY;
4200 /* Check if mPHY access is disabled and enable it if so */
4201 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4202 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4204 ready = e1000_is_mphy_ready(hw);
4206 return -E1000_ERR_PHY;
4207 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4208 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4211 /* Set the address that we want to read */
4212 ready = e1000_is_mphy_ready(hw);
4214 return -E1000_ERR_PHY;
4216 /* We mask address, because we want to use only current lane */
4218 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4220 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4221 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4222 (address & E1000_MPHY_ADDRESS_MASK);
4223 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4225 /* Read data from the address */
4226 ready = e1000_is_mphy_ready(hw);
4228 return -E1000_ERR_PHY;
4229 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4231 /* Disable access to mPHY if it was originally disabled */
4233 ready = e1000_is_mphy_ready(hw);
4235 return -E1000_ERR_PHY;
4236 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4237 E1000_MPHY_DIS_ACCESS);
4239 return E1000_SUCCESS;
4243 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4244 * @hw: pointer to the HW structure
4246 * Returns mPHY control register status.
4248 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4250 u16 retry_count = 0;
4254 while (retry_count < 2) {
4255 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4256 if (mphy_ctrl & E1000_MPHY_BUSY) {
4266 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");