1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
37 u16 *data, bool read, bool page_set);
38 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
39 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read);
42 /* Cable length tables */
43 static const u16 e1000_m88_cable_length_table[] = {
44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
46 (sizeof(e1000_m88_cable_length_table) / \
47 sizeof(e1000_m88_cable_length_table[0]))
49 static const u16 e1000_igp_2_cable_length_table[] = {
50 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
51 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
52 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
53 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
54 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
55 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
56 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
58 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
59 (sizeof(e1000_igp_2_cable_length_table) / \
60 sizeof(e1000_igp_2_cable_length_table[0]))
63 * e1000_init_phy_ops_generic - Initialize PHY function pointers
64 * @hw: pointer to the HW structure
66 * Setups up the function pointers to no-op functions
68 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
70 struct e1000_phy_info *phy = &hw->phy;
71 DEBUGFUNC("e1000_init_phy_ops_generic");
73 /* Initialize function pointers */
74 phy->ops.init_params = e1000_null_ops_generic;
75 phy->ops.acquire = e1000_null_ops_generic;
76 phy->ops.check_polarity = e1000_null_ops_generic;
77 phy->ops.check_reset_block = e1000_null_ops_generic;
78 phy->ops.commit = e1000_null_ops_generic;
79 phy->ops.force_speed_duplex = e1000_null_ops_generic;
80 phy->ops.get_cfg_done = e1000_null_ops_generic;
81 phy->ops.get_cable_length = e1000_null_ops_generic;
82 phy->ops.get_info = e1000_null_ops_generic;
83 phy->ops.set_page = e1000_null_set_page;
84 phy->ops.read_reg = e1000_null_read_reg;
85 phy->ops.read_reg_locked = e1000_null_read_reg;
86 phy->ops.read_reg_page = e1000_null_read_reg;
87 phy->ops.release = e1000_null_phy_generic;
88 phy->ops.reset = e1000_null_ops_generic;
89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
91 phy->ops.write_reg = e1000_null_write_reg;
92 phy->ops.write_reg_locked = e1000_null_write_reg;
93 phy->ops.write_reg_page = e1000_null_write_reg;
94 phy->ops.power_up = e1000_null_phy_generic;
95 phy->ops.power_down = e1000_null_phy_generic;
96 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
97 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
98 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
102 * e1000_null_set_page - No-op function, return 0
103 * @hw: pointer to the HW structure
105 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
107 DEBUGFUNC("e1000_null_set_page");
108 return E1000_SUCCESS;
112 * e1000_null_read_reg - No-op function, return 0
113 * @hw: pointer to the HW structure
115 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
117 DEBUGFUNC("e1000_null_read_reg");
118 return E1000_SUCCESS;
122 * e1000_null_phy_generic - No-op function, return void
123 * @hw: pointer to the HW structure
125 void e1000_null_phy_generic(struct e1000_hw *hw)
127 DEBUGFUNC("e1000_null_phy_generic");
132 * e1000_null_lplu_state - No-op function, return 0
133 * @hw: pointer to the HW structure
135 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
137 DEBUGFUNC("e1000_null_lplu_state");
138 return E1000_SUCCESS;
142 * e1000_null_write_reg - No-op function, return 0
143 * @hw: pointer to the HW structure
145 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
147 DEBUGFUNC("e1000_null_write_reg");
148 return E1000_SUCCESS;
152 * e1000_read_i2c_byte_null - No-op function, return 0
153 * @hw: pointer to hardware structure
154 * @byte_offset: byte offset to write
155 * @dev_addr: device address
156 * @data: data value read
159 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
160 u8 dev_addr, u8 *data)
162 DEBUGFUNC("e1000_read_i2c_byte_null");
163 return E1000_SUCCESS;
167 * e1000_write_i2c_byte_null - No-op function, return 0
168 * @hw: pointer to hardware structure
169 * @byte_offset: byte offset to write
170 * @dev_addr: device address
171 * @data: data value to write
174 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
175 u8 dev_addr, u8 data)
177 DEBUGFUNC("e1000_write_i2c_byte_null");
178 return E1000_SUCCESS;
182 * e1000_check_reset_block_generic - Check if PHY reset is blocked
183 * @hw: pointer to the HW structure
185 * Read the PHY management control register and check whether a PHY reset
186 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
187 * return E1000_BLK_PHY_RESET (12).
189 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
193 DEBUGFUNC("e1000_check_reset_block");
195 manc = E1000_READ_REG(hw, E1000_MANC);
197 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
198 E1000_BLK_PHY_RESET : E1000_SUCCESS;
202 * e1000_get_phy_id - Retrieve the PHY ID and revision
203 * @hw: pointer to the HW structure
205 * Reads the PHY registers and stores the PHY ID and possibly the PHY
206 * revision in the hardware structure.
208 s32 e1000_get_phy_id(struct e1000_hw *hw)
210 struct e1000_phy_info *phy = &hw->phy;
211 s32 ret_val = E1000_SUCCESS;
215 DEBUGFUNC("e1000_get_phy_id");
217 if (!phy->ops.read_reg)
218 return E1000_SUCCESS;
220 while (retry_count < 2) {
221 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
225 phy->id = (u32)(phy_id << 16);
227 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
231 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
232 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
234 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
235 return E1000_SUCCESS;
240 return E1000_SUCCESS;
244 * e1000_phy_reset_dsp_generic - Reset PHY DSP
245 * @hw: pointer to the HW structure
247 * Reset the digital signal processor.
249 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
253 DEBUGFUNC("e1000_phy_reset_dsp_generic");
255 if (!hw->phy.ops.write_reg)
256 return E1000_SUCCESS;
258 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
262 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
266 * e1000_read_phy_reg_mdic - Read MDI control register
267 * @hw: pointer to the HW structure
268 * @offset: register offset to be read
269 * @data: pointer to the read data
271 * Reads the MDI control register in the PHY at offset and stores the
272 * information read to data.
274 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
276 struct e1000_phy_info *phy = &hw->phy;
279 DEBUGFUNC("e1000_read_phy_reg_mdic");
281 if (offset > MAX_PHY_REG_ADDRESS) {
282 DEBUGOUT1("PHY Address %d is out of range\n", offset);
283 return -E1000_ERR_PARAM;
286 /* Set up Op-code, Phy Address, and register offset in the MDI
287 * Control register. The MAC will take care of interfacing with the
288 * PHY to retrieve the desired data.
290 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
291 (phy->addr << E1000_MDIC_PHY_SHIFT) |
292 (E1000_MDIC_OP_READ));
294 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
296 /* Poll the ready bit to see if the MDI read completed
297 * Increasing the time out as testing showed failures with
300 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
302 mdic = E1000_READ_REG(hw, E1000_MDIC);
303 if (mdic & E1000_MDIC_READY)
306 if (!(mdic & E1000_MDIC_READY)) {
307 DEBUGOUT("MDI Read did not complete\n");
308 return -E1000_ERR_PHY;
310 if (mdic & E1000_MDIC_ERROR) {
311 DEBUGOUT("MDI Error\n");
312 return -E1000_ERR_PHY;
316 /* Allow some time after each MDIC transaction to avoid
317 * reading duplicate data in the next MDIC transaction.
319 if (hw->mac.type == e1000_pch2lan)
322 return E1000_SUCCESS;
326 * e1000_write_phy_reg_mdic - Write MDI control register
327 * @hw: pointer to the HW structure
328 * @offset: register offset to write to
329 * @data: data to write to register at offset
331 * Writes data to MDI control register in the PHY at offset.
333 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
335 struct e1000_phy_info *phy = &hw->phy;
338 DEBUGFUNC("e1000_write_phy_reg_mdic");
340 if (offset > MAX_PHY_REG_ADDRESS) {
341 DEBUGOUT1("PHY Address %d is out of range\n", offset);
342 return -E1000_ERR_PARAM;
345 /* Set up Op-code, Phy Address, and register offset in the MDI
346 * Control register. The MAC will take care of interfacing with the
347 * PHY to retrieve the desired data.
349 mdic = (((u32)data) |
350 (offset << E1000_MDIC_REG_SHIFT) |
351 (phy->addr << E1000_MDIC_PHY_SHIFT) |
352 (E1000_MDIC_OP_WRITE));
354 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
356 /* Poll the ready bit to see if the MDI read completed
357 * Increasing the time out as testing showed failures with
360 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
362 mdic = E1000_READ_REG(hw, E1000_MDIC);
363 if (mdic & E1000_MDIC_READY)
366 if (!(mdic & E1000_MDIC_READY)) {
367 DEBUGOUT("MDI Write did not complete\n");
368 return -E1000_ERR_PHY;
370 if (mdic & E1000_MDIC_ERROR) {
371 DEBUGOUT("MDI Error\n");
372 return -E1000_ERR_PHY;
375 /* Allow some time after each MDIC transaction to avoid
376 * reading duplicate data in the next MDIC transaction.
378 if (hw->mac.type == e1000_pch2lan)
381 return E1000_SUCCESS;
385 * e1000_read_phy_reg_i2c - Read PHY register using i2c
386 * @hw: pointer to the HW structure
387 * @offset: register offset to be read
388 * @data: pointer to the read data
390 * Reads the PHY register at offset using the i2c interface and stores the
391 * retrieved information in data.
393 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
395 struct e1000_phy_info *phy = &hw->phy;
398 DEBUGFUNC("e1000_read_phy_reg_i2c");
400 /* Set up Op-code, Phy Address, and register address in the I2CCMD
401 * register. The MAC will take care of interfacing with the
402 * PHY to retrieve the desired data.
404 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
405 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
406 (E1000_I2CCMD_OPCODE_READ));
408 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
410 /* Poll the ready bit to see if the I2C read completed */
411 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
413 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
414 if (i2ccmd & E1000_I2CCMD_READY)
417 if (!(i2ccmd & E1000_I2CCMD_READY)) {
418 DEBUGOUT("I2CCMD Read did not complete\n");
419 return -E1000_ERR_PHY;
421 if (i2ccmd & E1000_I2CCMD_ERROR) {
422 DEBUGOUT("I2CCMD Error bit set\n");
423 return -E1000_ERR_PHY;
426 /* Need to byte-swap the 16-bit value. */
427 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
429 return E1000_SUCCESS;
433 * e1000_write_phy_reg_i2c - Write PHY register using i2c
434 * @hw: pointer to the HW structure
435 * @offset: register offset to write to
436 * @data: data to write at register offset
438 * Writes the data to PHY register at the offset using the i2c interface.
440 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
442 struct e1000_phy_info *phy = &hw->phy;
444 u16 phy_data_swapped;
446 DEBUGFUNC("e1000_write_phy_reg_i2c");
448 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
449 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
450 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
452 return -E1000_ERR_CONFIG;
455 /* Swap the data bytes for the I2C interface */
456 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
458 /* Set up Op-code, Phy Address, and register address in the I2CCMD
459 * register. The MAC will take care of interfacing with the
460 * PHY to retrieve the desired data.
462 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
463 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
464 E1000_I2CCMD_OPCODE_WRITE |
467 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
469 /* Poll the ready bit to see if the I2C read completed */
470 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
472 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
473 if (i2ccmd & E1000_I2CCMD_READY)
476 if (!(i2ccmd & E1000_I2CCMD_READY)) {
477 DEBUGOUT("I2CCMD Write did not complete\n");
478 return -E1000_ERR_PHY;
480 if (i2ccmd & E1000_I2CCMD_ERROR) {
481 DEBUGOUT("I2CCMD Error bit set\n");
482 return -E1000_ERR_PHY;
485 return E1000_SUCCESS;
489 * e1000_read_sfp_data_byte - Reads SFP module data.
490 * @hw: pointer to the HW structure
491 * @offset: byte location offset to be read
492 * @data: read data buffer pointer
494 * Reads one byte from SFP module data stored
495 * in SFP resided EEPROM memory or SFP diagnostic area.
496 * Function should be called with
497 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
498 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
501 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
507 DEBUGFUNC("e1000_read_sfp_data_byte");
509 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
510 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
511 return -E1000_ERR_PHY;
514 /* Set up Op-code, EEPROM Address,in the I2CCMD
515 * register. The MAC will take care of interfacing with the
516 * EEPROM to retrieve the desired data.
518 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
519 E1000_I2CCMD_OPCODE_READ);
521 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
523 /* Poll the ready bit to see if the I2C read completed */
524 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
526 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
527 if (data_local & E1000_I2CCMD_READY)
530 if (!(data_local & E1000_I2CCMD_READY)) {
531 DEBUGOUT("I2CCMD Read did not complete\n");
532 return -E1000_ERR_PHY;
534 if (data_local & E1000_I2CCMD_ERROR) {
535 DEBUGOUT("I2CCMD Error bit set\n");
536 return -E1000_ERR_PHY;
538 *data = (u8) data_local & 0xFF;
540 return E1000_SUCCESS;
544 * e1000_write_sfp_data_byte - Writes SFP module data.
545 * @hw: pointer to the HW structure
546 * @offset: byte location offset to write to
547 * @data: data to write
549 * Writes one byte to SFP module data stored
550 * in SFP resided EEPROM memory or SFP diagnostic area.
551 * Function should be called with
552 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
553 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
556 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
562 DEBUGFUNC("e1000_write_sfp_data_byte");
564 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
565 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
566 return -E1000_ERR_PHY;
568 /* The programming interface is 16 bits wide
569 * so we need to read the whole word first
570 * then update appropriate byte lane and write
571 * the updated word back.
573 /* Set up Op-code, EEPROM Address,in the I2CCMD
574 * register. The MAC will take care of interfacing
575 * with an EEPROM to write the data given.
577 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
578 E1000_I2CCMD_OPCODE_READ);
579 /* Set a command to read single word */
580 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
581 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
583 /* Poll the ready bit to see if lastly
584 * launched I2C operation completed
586 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
587 if (i2ccmd & E1000_I2CCMD_READY) {
588 /* Check if this is READ or WRITE phase */
589 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
590 E1000_I2CCMD_OPCODE_READ) {
591 /* Write the selected byte
592 * lane and update whole word
594 data_local = i2ccmd & 0xFF00;
597 E1000_I2CCMD_REG_ADDR_SHIFT) |
598 E1000_I2CCMD_OPCODE_WRITE | data_local);
599 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
605 if (!(i2ccmd & E1000_I2CCMD_READY)) {
606 DEBUGOUT("I2CCMD Write did not complete\n");
607 return -E1000_ERR_PHY;
609 if (i2ccmd & E1000_I2CCMD_ERROR) {
610 DEBUGOUT("I2CCMD Error bit set\n");
611 return -E1000_ERR_PHY;
613 return E1000_SUCCESS;
617 * e1000_read_phy_reg_m88 - Read m88 PHY register
618 * @hw: pointer to the HW structure
619 * @offset: register offset to be read
620 * @data: pointer to the read data
622 * Acquires semaphore, if necessary, then reads the PHY register at offset
623 * and storing the retrieved information in data. Release any acquired
624 * semaphores before exiting.
626 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
630 DEBUGFUNC("e1000_read_phy_reg_m88");
632 if (!hw->phy.ops.acquire)
633 return E1000_SUCCESS;
635 ret_val = hw->phy.ops.acquire(hw);
639 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
642 hw->phy.ops.release(hw);
648 * e1000_write_phy_reg_m88 - Write m88 PHY register
649 * @hw: pointer to the HW structure
650 * @offset: register offset to write to
651 * @data: data to write at register offset
653 * Acquires semaphore, if necessary, then writes the data to PHY register
654 * at the offset. Release any acquired semaphores before exiting.
656 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
660 DEBUGFUNC("e1000_write_phy_reg_m88");
662 if (!hw->phy.ops.acquire)
663 return E1000_SUCCESS;
665 ret_val = hw->phy.ops.acquire(hw);
669 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
672 hw->phy.ops.release(hw);
678 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
679 * @hw: pointer to the HW structure
680 * @page: page to set (shifted left when necessary)
682 * Sets PHY page required for PHY register access. Assumes semaphore is
683 * already acquired. Note, this function sets phy.addr to 1 so the caller
684 * must set it appropriately (if necessary) after this function returns.
686 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
688 DEBUGFUNC("e1000_set_page_igp");
690 DEBUGOUT1("Setting page 0x%x\n", page);
694 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
698 * __e1000_read_phy_reg_igp - Read igp PHY register
699 * @hw: pointer to the HW structure
700 * @offset: register offset to be read
701 * @data: pointer to the read data
702 * @locked: semaphore has already been acquired or not
704 * Acquires semaphore, if necessary, then reads the PHY register at offset
705 * and stores the retrieved information in data. Release any acquired
706 * semaphores before exiting.
708 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
711 s32 ret_val = E1000_SUCCESS;
713 DEBUGFUNC("__e1000_read_phy_reg_igp");
716 if (!hw->phy.ops.acquire)
717 return E1000_SUCCESS;
719 ret_val = hw->phy.ops.acquire(hw);
724 if (offset > MAX_PHY_MULTI_PAGE_REG)
725 ret_val = e1000_write_phy_reg_mdic(hw,
726 IGP01E1000_PHY_PAGE_SELECT,
729 ret_val = e1000_read_phy_reg_mdic(hw,
730 MAX_PHY_REG_ADDRESS & offset,
733 hw->phy.ops.release(hw);
739 * e1000_read_phy_reg_igp - Read igp PHY register
740 * @hw: pointer to the HW structure
741 * @offset: register offset to be read
742 * @data: pointer to the read data
744 * Acquires semaphore then reads the PHY register at offset and stores the
745 * retrieved information in data.
746 * Release the acquired semaphore before exiting.
748 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
750 return __e1000_read_phy_reg_igp(hw, offset, data, false);
754 * e1000_read_phy_reg_igp_locked - Read igp PHY register
755 * @hw: pointer to the HW structure
756 * @offset: register offset to be read
757 * @data: pointer to the read data
759 * Reads the PHY register at offset and stores the retrieved information
760 * in data. Assumes semaphore already acquired.
762 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
764 return __e1000_read_phy_reg_igp(hw, offset, data, true);
768 * e1000_write_phy_reg_igp - Write igp PHY register
769 * @hw: pointer to the HW structure
770 * @offset: register offset to write to
771 * @data: data to write at register offset
772 * @locked: semaphore has already been acquired or not
774 * Acquires semaphore, if necessary, then writes the data to PHY register
775 * at the offset. Release any acquired semaphores before exiting.
777 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
780 s32 ret_val = E1000_SUCCESS;
782 DEBUGFUNC("e1000_write_phy_reg_igp");
785 if (!hw->phy.ops.acquire)
786 return E1000_SUCCESS;
788 ret_val = hw->phy.ops.acquire(hw);
793 if (offset > MAX_PHY_MULTI_PAGE_REG)
794 ret_val = e1000_write_phy_reg_mdic(hw,
795 IGP01E1000_PHY_PAGE_SELECT,
798 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
802 hw->phy.ops.release(hw);
808 * e1000_write_phy_reg_igp - Write igp PHY register
809 * @hw: pointer to the HW structure
810 * @offset: register offset to write to
811 * @data: data to write at register offset
813 * Acquires semaphore then writes the data to PHY register
814 * at the offset. Release any acquired semaphores before exiting.
816 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
818 return __e1000_write_phy_reg_igp(hw, offset, data, false);
822 * e1000_write_phy_reg_igp_locked - Write igp PHY register
823 * @hw: pointer to the HW structure
824 * @offset: register offset to write to
825 * @data: data to write at register offset
827 * Writes the data to PHY register at the offset.
828 * Assumes semaphore already acquired.
830 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
832 return __e1000_write_phy_reg_igp(hw, offset, data, true);
836 * __e1000_read_kmrn_reg - Read kumeran register
837 * @hw: pointer to the HW structure
838 * @offset: register offset to be read
839 * @data: pointer to the read data
840 * @locked: semaphore has already been acquired or not
842 * Acquires semaphore, if necessary. Then reads the PHY register at offset
843 * using the kumeran interface. The information retrieved is stored in data.
844 * Release any acquired semaphores before exiting.
846 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
851 DEBUGFUNC("__e1000_read_kmrn_reg");
854 s32 ret_val = E1000_SUCCESS;
856 if (!hw->phy.ops.acquire)
857 return E1000_SUCCESS;
859 ret_val = hw->phy.ops.acquire(hw);
864 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
865 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
866 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
867 E1000_WRITE_FLUSH(hw);
871 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
872 *data = (u16)kmrnctrlsta;
875 hw->phy.ops.release(hw);
877 return E1000_SUCCESS;
881 * e1000_read_kmrn_reg_generic - Read kumeran register
882 * @hw: pointer to the HW structure
883 * @offset: register offset to be read
884 * @data: pointer to the read data
886 * Acquires semaphore then reads the PHY register at offset using the
887 * kumeran interface. The information retrieved is stored in data.
888 * Release the acquired semaphore before exiting.
890 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
892 return __e1000_read_kmrn_reg(hw, offset, data, false);
896 * e1000_read_kmrn_reg_locked - Read kumeran register
897 * @hw: pointer to the HW structure
898 * @offset: register offset to be read
899 * @data: pointer to the read data
901 * Reads the PHY register at offset using the kumeran interface. The
902 * information retrieved is stored in data.
903 * Assumes semaphore already acquired.
905 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
907 return __e1000_read_kmrn_reg(hw, offset, data, true);
911 * __e1000_write_kmrn_reg - Write kumeran register
912 * @hw: pointer to the HW structure
913 * @offset: register offset to write to
914 * @data: data to write at register offset
915 * @locked: semaphore has already been acquired or not
917 * Acquires semaphore, if necessary. Then write the data to PHY register
918 * at the offset using the kumeran interface. Release any acquired semaphores
921 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
926 DEBUGFUNC("e1000_write_kmrn_reg_generic");
929 s32 ret_val = E1000_SUCCESS;
931 if (!hw->phy.ops.acquire)
932 return E1000_SUCCESS;
934 ret_val = hw->phy.ops.acquire(hw);
939 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
940 E1000_KMRNCTRLSTA_OFFSET) | data;
941 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
942 E1000_WRITE_FLUSH(hw);
947 hw->phy.ops.release(hw);
949 return E1000_SUCCESS;
953 * e1000_write_kmrn_reg_generic - Write kumeran register
954 * @hw: pointer to the HW structure
955 * @offset: register offset to write to
956 * @data: data to write at register offset
958 * Acquires semaphore then writes the data to the PHY register at the offset
959 * using the kumeran interface. Release the acquired semaphore before exiting.
961 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
963 return __e1000_write_kmrn_reg(hw, offset, data, false);
967 * e1000_write_kmrn_reg_locked - Write kumeran register
968 * @hw: pointer to the HW structure
969 * @offset: register offset to write to
970 * @data: data to write at register offset
972 * Write the data to PHY register at the offset using the kumeran interface.
973 * Assumes semaphore already acquired.
975 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
977 return __e1000_write_kmrn_reg(hw, offset, data, true);
981 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
982 * @hw: pointer to the HW structure
984 * Sets up Master/slave mode
986 STATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
991 /* Resolve Master/Slave mode */
992 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
996 /* load defaults for future use */
997 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
998 ((phy_data & CR_1000T_MS_VALUE) ?
999 e1000_ms_force_master :
1000 e1000_ms_force_slave) : e1000_ms_auto;
1002 switch (hw->phy.ms_type) {
1003 case e1000_ms_force_master:
1004 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1006 case e1000_ms_force_slave:
1007 phy_data |= CR_1000T_MS_ENABLE;
1008 phy_data &= ~(CR_1000T_MS_VALUE);
1011 phy_data &= ~CR_1000T_MS_ENABLE;
1017 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1021 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1022 * @hw: pointer to the HW structure
1024 * Sets up Carrier-sense on Transmit and downshift values.
1026 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1031 DEBUGFUNC("e1000_copper_link_setup_82577");
1033 if (hw->phy.type == e1000_phy_82580) {
1034 ret_val = hw->phy.ops.reset(hw);
1036 DEBUGOUT("Error resetting the PHY.\n");
1041 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1042 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1046 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1048 /* Enable downshift */
1049 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1051 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1055 /* Set MDI/MDIX mode */
1056 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1059 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1061 * 0 - Auto (default)
1065 switch (hw->phy.mdix) {
1069 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1073 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1076 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1080 return e1000_set_master_slave_mode(hw);
1084 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1085 * @hw: pointer to the HW structure
1087 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1088 * and downshift values are set also.
1090 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1092 struct e1000_phy_info *phy = &hw->phy;
1096 DEBUGFUNC("e1000_copper_link_setup_m88");
1099 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1100 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1104 /* For BM PHY this bit is downshift enable */
1105 if (phy->type != e1000_phy_bm)
1106 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1109 * MDI/MDI-X = 0 (default)
1110 * 0 - Auto for all speeds
1113 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1115 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1117 switch (phy->mdix) {
1119 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1122 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1125 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1129 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1134 * disable_polarity_correction = 0 (default)
1135 * Automatic Correction for Reversed Cable Polarity
1139 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1140 if (phy->disable_polarity_correction)
1141 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1143 /* Enable downshift on BM (disabled by default) */
1144 if (phy->type == e1000_phy_bm) {
1145 /* For 82574/82583, first disable then enable downshift */
1146 if (phy->id == BME1000_E_PHY_ID_R2) {
1147 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1148 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1152 /* Commit the changes. */
1153 ret_val = phy->ops.commit(hw);
1155 DEBUGOUT("Error committing the PHY changes\n");
1160 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1163 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1167 if ((phy->type == e1000_phy_m88) &&
1168 (phy->revision < E1000_REVISION_4) &&
1169 (phy->id != BME1000_E_PHY_ID_R2)) {
1170 /* Force TX_CLK in the Extended PHY Specific Control Register
1173 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1178 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1180 if ((phy->revision == E1000_REVISION_2) &&
1181 (phy->id == M88E1111_I_PHY_ID)) {
1182 /* 82573L PHY - set the downshift counter to 5x. */
1183 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1184 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1186 /* Configure Master and Slave downshift values */
1187 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1188 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1189 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1190 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1192 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1198 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1199 /* Set PHY page 0, register 29 to 0x0003 */
1200 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1204 /* Set PHY page 0, register 30 to 0x0000 */
1205 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1210 /* Commit the changes. */
1211 ret_val = phy->ops.commit(hw);
1213 DEBUGOUT("Error committing the PHY changes\n");
1217 if (phy->type == e1000_phy_82578) {
1218 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1223 /* 82578 PHY - set the downshift count to 1x. */
1224 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1225 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1226 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1232 if (phy->type == e1000_phy_i210) {
1233 ret_val = e1000_set_master_slave_mode(hw);
1238 return E1000_SUCCESS;
1242 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1243 * @hw: pointer to the HW structure
1245 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1246 * Also enables and sets the downshift parameters.
1248 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1250 struct e1000_phy_info *phy = &hw->phy;
1254 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1257 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1258 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1263 * MDI/MDI-X = 0 (default)
1264 * 0 - Auto for all speeds
1267 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1269 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1271 switch (phy->mdix) {
1273 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1276 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1279 /* M88E1112 does not support this mode) */
1280 if (phy->id != M88E1112_E_PHY_ID) {
1281 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1286 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1291 * disable_polarity_correction = 0 (default)
1292 * Automatic Correction for Reversed Cable Polarity
1296 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1297 if (phy->disable_polarity_correction)
1298 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1300 /* Enable downshift and setting it to X6 */
1301 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1302 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1303 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1305 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1309 /* Commit the changes. */
1310 ret_val = phy->ops.commit(hw);
1312 DEBUGOUT("Error committing the PHY changes\n");
1316 return E1000_SUCCESS;
1320 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1321 * @hw: pointer to the HW structure
1323 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1326 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1328 struct e1000_phy_info *phy = &hw->phy;
1332 DEBUGFUNC("e1000_copper_link_setup_igp");
1335 ret_val = hw->phy.ops.reset(hw);
1337 DEBUGOUT("Error resetting the PHY.\n");
1341 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1342 * timeout issues when LFS is enabled.
1346 /* The NVM settings will configure LPLU in D3 for
1349 if (phy->type == e1000_phy_igp) {
1350 /* disable lplu d3 during driver init */
1351 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1353 DEBUGOUT("Error Disabling LPLU D3\n");
1358 /* disable lplu d0 during driver init */
1359 if (hw->phy.ops.set_d0_lplu_state) {
1360 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1362 DEBUGOUT("Error Disabling LPLU D0\n");
1366 /* Configure mdi-mdix settings */
1367 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1371 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1373 switch (phy->mdix) {
1375 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1378 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1382 data |= IGP01E1000_PSCR_AUTO_MDIX;
1385 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1389 /* set auto-master slave resolution settings */
1390 if (hw->mac.autoneg) {
1391 /* when autonegotiation advertisement is only 1000Mbps then we
1392 * should disable SmartSpeed and enable Auto MasterSlave
1393 * resolution as hardware default.
1395 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1396 /* Disable SmartSpeed */
1397 ret_val = phy->ops.read_reg(hw,
1398 IGP01E1000_PHY_PORT_CONFIG,
1403 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1404 ret_val = phy->ops.write_reg(hw,
1405 IGP01E1000_PHY_PORT_CONFIG,
1410 /* Set auto Master/Slave resolution process */
1411 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1415 data &= ~CR_1000T_MS_ENABLE;
1416 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1421 ret_val = e1000_set_master_slave_mode(hw);
1428 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1429 * @hw: pointer to the HW structure
1431 * Reads the MII auto-neg advertisement register and/or the 1000T control
1432 * register and if the PHY is already setup for auto-negotiation, then
1433 * return successful. Otherwise, setup advertisement and flow control to
1434 * the appropriate values for the wanted auto-negotiation.
1436 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1438 struct e1000_phy_info *phy = &hw->phy;
1440 u16 mii_autoneg_adv_reg;
1441 u16 mii_1000t_ctrl_reg = 0;
1443 DEBUGFUNC("e1000_phy_setup_autoneg");
1445 phy->autoneg_advertised &= phy->autoneg_mask;
1447 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1448 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1452 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1453 /* Read the MII 1000Base-T Control Register (Address 9). */
1454 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1455 &mii_1000t_ctrl_reg);
1460 /* Need to parse both autoneg_advertised and fc and set up
1461 * the appropriate PHY registers. First we will parse for
1462 * autoneg_advertised software override. Since we can advertise
1463 * a plethora of combinations, we need to check each bit
1467 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1468 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1469 * the 1000Base-T Control Register (Address 9).
1471 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1472 NWAY_AR_100TX_HD_CAPS |
1473 NWAY_AR_10T_FD_CAPS |
1474 NWAY_AR_10T_HD_CAPS);
1475 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1477 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1479 /* Do we want to advertise 10 Mb Half Duplex? */
1480 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1481 DEBUGOUT("Advertise 10mb Half duplex\n");
1482 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1485 /* Do we want to advertise 10 Mb Full Duplex? */
1486 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1487 DEBUGOUT("Advertise 10mb Full duplex\n");
1488 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1491 /* Do we want to advertise 100 Mb Half Duplex? */
1492 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1493 DEBUGOUT("Advertise 100mb Half duplex\n");
1494 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1497 /* Do we want to advertise 100 Mb Full Duplex? */
1498 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1499 DEBUGOUT("Advertise 100mb Full duplex\n");
1500 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1503 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1504 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1505 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1507 /* Do we want to advertise 1000 Mb Full Duplex? */
1508 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1509 DEBUGOUT("Advertise 1000mb Full duplex\n");
1510 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1513 /* Check for a software override of the flow control settings, and
1514 * setup the PHY advertisement registers accordingly. If
1515 * auto-negotiation is enabled, then software will have to set the
1516 * "PAUSE" bits to the correct value in the Auto-Negotiation
1517 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1520 * The possible values of the "fc" parameter are:
1521 * 0: Flow control is completely disabled
1522 * 1: Rx flow control is enabled (we can receive pause frames
1523 * but not send pause frames).
1524 * 2: Tx flow control is enabled (we can send pause frames
1525 * but we do not support receiving pause frames).
1526 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1527 * other: No software override. The flow control configuration
1528 * in the EEPROM is used.
1530 switch (hw->fc.current_mode) {
1532 /* Flow control (Rx & Tx) is completely disabled by a
1533 * software over-ride.
1535 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1537 case e1000_fc_rx_pause:
1538 /* Rx Flow control is enabled, and Tx Flow control is
1539 * disabled, by a software over-ride.
1541 * Since there really isn't a way to advertise that we are
1542 * capable of Rx Pause ONLY, we will advertise that we
1543 * support both symmetric and asymmetric Rx PAUSE. Later
1544 * (in e1000_config_fc_after_link_up) we will disable the
1545 * hw's ability to send PAUSE frames.
1547 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1549 case e1000_fc_tx_pause:
1550 /* Tx Flow control is enabled, and Rx Flow control is
1551 * disabled, by a software over-ride.
1553 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1554 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1557 /* Flow control (both Rx and Tx) is enabled by a software
1560 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1563 DEBUGOUT("Flow control param set incorrectly\n");
1564 return -E1000_ERR_CONFIG;
1567 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1571 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1573 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1574 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1575 mii_1000t_ctrl_reg);
1581 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1582 * @hw: pointer to the HW structure
1584 * Performs initial bounds checking on autoneg advertisement parameter, then
1585 * configure to advertise the full capability. Setup the PHY to autoneg
1586 * and restart the negotiation process between the link partner. If
1587 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1589 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1591 struct e1000_phy_info *phy = &hw->phy;
1595 DEBUGFUNC("e1000_copper_link_autoneg");
1597 /* Perform some bounds checking on the autoneg advertisement
1600 phy->autoneg_advertised &= phy->autoneg_mask;
1602 /* If autoneg_advertised is zero, we assume it was not defaulted
1603 * by the calling code so we set to advertise full capability.
1605 if (!phy->autoneg_advertised)
1606 phy->autoneg_advertised = phy->autoneg_mask;
1608 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1609 ret_val = e1000_phy_setup_autoneg(hw);
1611 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1614 DEBUGOUT("Restarting Auto-Neg\n");
1616 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1617 * the Auto Neg Restart bit in the PHY control register.
1619 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1623 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1624 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1628 /* Does the user want to wait for Auto-Neg to complete here, or
1629 * check at a later time (for example, callback routine).
1631 if (phy->autoneg_wait_to_complete) {
1632 ret_val = hw->mac.ops.wait_autoneg(hw);
1634 DEBUGOUT("Error while waiting for autoneg to complete\n");
1639 hw->mac.get_link_status = true;
1645 * e1000_setup_copper_link_generic - Configure copper link settings
1646 * @hw: pointer to the HW structure
1648 * Calls the appropriate function to configure the link for auto-neg or forced
1649 * speed and duplex. Then we check for link, once link is established calls
1650 * to configure collision distance and flow control are called. If link is
1651 * not established, we return -E1000_ERR_PHY (-2).
1653 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1658 DEBUGFUNC("e1000_setup_copper_link_generic");
1660 if (hw->mac.autoneg) {
1661 /* Setup autoneg and flow control advertisement and perform
1664 ret_val = e1000_copper_link_autoneg(hw);
1668 /* PHY will be set to 10H, 10F, 100H or 100F
1669 * depending on user settings.
1671 DEBUGOUT("Forcing Speed and Duplex\n");
1672 ret_val = hw->phy.ops.force_speed_duplex(hw);
1674 DEBUGOUT("Error Forcing Speed and Duplex\n");
1679 /* Check link status. Wait up to 100 microseconds for link to become
1682 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1688 DEBUGOUT("Valid link established!!!\n");
1689 hw->mac.ops.config_collision_dist(hw);
1690 ret_val = e1000_config_fc_after_link_up_generic(hw);
1692 DEBUGOUT("Unable to establish link!!!\n");
1699 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1700 * @hw: pointer to the HW structure
1702 * Calls the PHY setup function to force speed and duplex. Clears the
1703 * auto-crossover to force MDI manually. Waits for link and returns
1704 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1706 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1708 struct e1000_phy_info *phy = &hw->phy;
1713 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1715 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1719 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1721 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1725 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1726 * forced whenever speed and duplex are forced.
1728 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1732 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1733 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1735 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1739 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1743 if (phy->autoneg_wait_to_complete) {
1744 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1746 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1752 DEBUGOUT("Link taking longer than expected.\n");
1755 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1763 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1764 * @hw: pointer to the HW structure
1766 * Calls the PHY setup function to force speed and duplex. Clears the
1767 * auto-crossover to force MDI manually. Resets the PHY to commit the
1768 * changes. If time expires while waiting for link up, we reset the DSP.
1769 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1770 * successful completion, else return corresponding error code.
1772 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1774 struct e1000_phy_info *phy = &hw->phy;
1779 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1781 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1782 if (phy->type != e1000_phy_i210) {
1783 /* Clear Auto-Crossover to force MDI manually. M88E1000
1784 * requires MDI forced whenever speed and duplex are forced.
1786 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1791 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1792 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1798 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1800 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1804 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1806 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1810 /* Reset the phy to commit changes. */
1811 ret_val = hw->phy.ops.commit(hw);
1815 if (phy->autoneg_wait_to_complete) {
1816 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1818 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1824 bool reset_dsp = true;
1826 switch (hw->phy.id) {
1827 case I347AT4_E_PHY_ID:
1828 case M88E1340M_E_PHY_ID:
1829 case M88E1112_E_PHY_ID:
1834 if (hw->phy.type != e1000_phy_m88)
1840 DEBUGOUT("Link taking longer than expected.\n");
1842 /* We didn't get link.
1843 * Reset the DSP and cross our fingers.
1845 ret_val = phy->ops.write_reg(hw,
1846 M88E1000_PHY_PAGE_SELECT,
1850 ret_val = e1000_phy_reset_dsp_generic(hw);
1857 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1863 if (hw->phy.type != e1000_phy_m88)
1864 return E1000_SUCCESS;
1866 if (hw->phy.id == I347AT4_E_PHY_ID ||
1867 hw->phy.id == M88E1340M_E_PHY_ID ||
1868 hw->phy.id == M88E1112_E_PHY_ID)
1869 return E1000_SUCCESS;
1870 if (hw->phy.id == I210_I_PHY_ID)
1871 return E1000_SUCCESS;
1872 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1876 /* Resetting the phy means we need to re-force TX_CLK in the
1877 * Extended PHY Specific Control Register to 25MHz clock from
1878 * the reset value of 2.5MHz.
1880 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1881 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1885 /* In addition, we must re-enable CRS on Tx for both half and full
1888 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1892 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1893 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1899 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1900 * @hw: pointer to the HW structure
1902 * Forces the speed and duplex settings of the PHY.
1903 * This is a function pointer entry point only called by
1904 * PHY setup routines.
1906 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1908 struct e1000_phy_info *phy = &hw->phy;
1913 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1915 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1919 e1000_phy_force_speed_duplex_setup(hw, &data);
1921 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1925 /* Disable MDI-X support for 10/100 */
1926 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1930 data &= ~IFE_PMC_AUTO_MDIX;
1931 data &= ~IFE_PMC_FORCE_MDIX;
1933 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1937 DEBUGOUT1("IFE PMC: %X\n", data);
1941 if (phy->autoneg_wait_to_complete) {
1942 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1944 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1950 DEBUGOUT("Link taking longer than expected.\n");
1953 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1959 return E1000_SUCCESS;
1963 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1964 * @hw: pointer to the HW structure
1965 * @phy_ctrl: pointer to current value of PHY_CONTROL
1967 * Forces speed and duplex on the PHY by doing the following: disable flow
1968 * control, force speed/duplex on the MAC, disable auto speed detection,
1969 * disable auto-negotiation, configure duplex, configure speed, configure
1970 * the collision distance, write configuration to CTRL register. The
1971 * caller must write to the PHY_CONTROL register for these settings to
1974 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1976 struct e1000_mac_info *mac = &hw->mac;
1979 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1981 /* Turn off flow control when forcing speed/duplex */
1982 hw->fc.current_mode = e1000_fc_none;
1984 /* Force speed/duplex on the mac */
1985 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1986 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1987 ctrl &= ~E1000_CTRL_SPD_SEL;
1989 /* Disable Auto Speed Detection */
1990 ctrl &= ~E1000_CTRL_ASDE;
1992 /* Disable autoneg on the phy */
1993 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1995 /* Forcing Full or Half Duplex? */
1996 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1997 ctrl &= ~E1000_CTRL_FD;
1998 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1999 DEBUGOUT("Half Duplex\n");
2001 ctrl |= E1000_CTRL_FD;
2002 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2003 DEBUGOUT("Full Duplex\n");
2006 /* Forcing 10mb or 100mb? */
2007 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2008 ctrl |= E1000_CTRL_SPD_100;
2009 *phy_ctrl |= MII_CR_SPEED_100;
2010 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2011 DEBUGOUT("Forcing 100mb\n");
2013 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2014 *phy_ctrl |= MII_CR_SPEED_10;
2015 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2016 DEBUGOUT("Forcing 10mb\n");
2019 hw->mac.ops.config_collision_dist(hw);
2021 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2025 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2026 * @hw: pointer to the HW structure
2027 * @active: boolean used to enable/disable lplu
2029 * Success returns 0, Failure returns 1
2031 * The low power link up (lplu) state is set to the power management level D3
2032 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2033 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2034 * is used during Dx states where the power conservation is most important.
2035 * During driver activity, SmartSpeed should be enabled so performance is
2038 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2040 struct e1000_phy_info *phy = &hw->phy;
2044 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2046 if (!hw->phy.ops.read_reg)
2047 return E1000_SUCCESS;
2049 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2054 data &= ~IGP02E1000_PM_D3_LPLU;
2055 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2059 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2060 * during Dx states where the power conservation is most
2061 * important. During driver activity we should enable
2062 * SmartSpeed, so performance is maintained.
2064 if (phy->smart_speed == e1000_smart_speed_on) {
2065 ret_val = phy->ops.read_reg(hw,
2066 IGP01E1000_PHY_PORT_CONFIG,
2071 data |= IGP01E1000_PSCFR_SMART_SPEED;
2072 ret_val = phy->ops.write_reg(hw,
2073 IGP01E1000_PHY_PORT_CONFIG,
2077 } else if (phy->smart_speed == e1000_smart_speed_off) {
2078 ret_val = phy->ops.read_reg(hw,
2079 IGP01E1000_PHY_PORT_CONFIG,
2084 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2085 ret_val = phy->ops.write_reg(hw,
2086 IGP01E1000_PHY_PORT_CONFIG,
2091 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2092 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2093 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2094 data |= IGP02E1000_PM_D3_LPLU;
2095 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2100 /* When LPLU is enabled, we should disable SmartSpeed */
2101 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2106 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2107 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2115 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2116 * @hw: pointer to the HW structure
2118 * Success returns 0, Failure returns 1
2120 * A downshift is detected by querying the PHY link health.
2122 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2124 struct e1000_phy_info *phy = &hw->phy;
2126 u16 phy_data, offset, mask;
2128 DEBUGFUNC("e1000_check_downshift_generic");
2130 switch (phy->type) {
2131 case e1000_phy_i210:
2133 case e1000_phy_gg82563:
2135 case e1000_phy_82578:
2136 offset = M88E1000_PHY_SPEC_STATUS;
2137 mask = M88E1000_PSSR_DOWNSHIFT;
2140 case e1000_phy_igp_2:
2141 case e1000_phy_igp_3:
2142 offset = IGP01E1000_PHY_LINK_HEALTH;
2143 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2146 /* speed downshift not supported */
2147 phy->speed_downgraded = false;
2148 return E1000_SUCCESS;
2151 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2154 phy->speed_downgraded = !!(phy_data & mask);
2160 * e1000_check_polarity_m88 - Checks the polarity.
2161 * @hw: pointer to the HW structure
2163 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2165 * Polarity is determined based on the PHY specific status register.
2167 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2169 struct e1000_phy_info *phy = &hw->phy;
2173 DEBUGFUNC("e1000_check_polarity_m88");
2175 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2178 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2179 ? e1000_rev_polarity_reversed
2180 : e1000_rev_polarity_normal);
2186 * e1000_check_polarity_igp - Checks the polarity.
2187 * @hw: pointer to the HW structure
2189 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2191 * Polarity is determined based on the PHY port status register, and the
2192 * current speed (since there is no polarity at 100Mbps).
2194 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2196 struct e1000_phy_info *phy = &hw->phy;
2198 u16 data, offset, mask;
2200 DEBUGFUNC("e1000_check_polarity_igp");
2202 /* Polarity is determined based on the speed of
2205 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2209 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2210 IGP01E1000_PSSR_SPEED_1000MBPS) {
2211 offset = IGP01E1000_PHY_PCS_INIT_REG;
2212 mask = IGP01E1000_PHY_POLARITY_MASK;
2214 /* This really only applies to 10Mbps since
2215 * there is no polarity for 100Mbps (always 0).
2217 offset = IGP01E1000_PHY_PORT_STATUS;
2218 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2221 ret_val = phy->ops.read_reg(hw, offset, &data);
2224 phy->cable_polarity = ((data & mask)
2225 ? e1000_rev_polarity_reversed
2226 : e1000_rev_polarity_normal);
2232 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2233 * @hw: pointer to the HW structure
2235 * Polarity is determined on the polarity reversal feature being enabled.
2237 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2239 struct e1000_phy_info *phy = &hw->phy;
2241 u16 phy_data, offset, mask;
2243 DEBUGFUNC("e1000_check_polarity_ife");
2245 /* Polarity is determined based on the reversal feature being enabled.
2247 if (phy->polarity_correction) {
2248 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2249 mask = IFE_PESC_POLARITY_REVERSED;
2251 offset = IFE_PHY_SPECIAL_CONTROL;
2252 mask = IFE_PSC_FORCE_POLARITY;
2255 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2258 phy->cable_polarity = ((phy_data & mask)
2259 ? e1000_rev_polarity_reversed
2260 : e1000_rev_polarity_normal);
2266 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2267 * @hw: pointer to the HW structure
2269 * Waits for auto-negotiation to complete or for the auto-negotiation time
2270 * limit to expire, which ever happens first.
2272 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2274 s32 ret_val = E1000_SUCCESS;
2277 DEBUGFUNC("e1000_wait_autoneg_generic");
2279 if (!hw->phy.ops.read_reg)
2280 return E1000_SUCCESS;
2282 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2283 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2284 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2287 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2290 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2295 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2302 * e1000_phy_has_link_generic - Polls PHY for link
2303 * @hw: pointer to the HW structure
2304 * @iterations: number of times to poll for link
2305 * @usec_interval: delay between polling attempts
2306 * @success: pointer to whether polling was successful or not
2308 * Polls the PHY status register for link, 'iterations' number of times.
2310 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2311 u32 usec_interval, bool *success)
2313 s32 ret_val = E1000_SUCCESS;
2316 DEBUGFUNC("e1000_phy_has_link_generic");
2318 if (!hw->phy.ops.read_reg)
2319 return E1000_SUCCESS;
2321 for (i = 0; i < iterations; i++) {
2322 /* Some PHYs require the PHY_STATUS register to be read
2323 * twice due to the link bit being sticky. No harm doing
2324 * it across the board.
2326 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2328 /* If the first read fails, another entity may have
2329 * ownership of the resources, wait and try again to
2330 * see if they have relinquished the resources yet.
2332 usec_delay(usec_interval);
2333 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2336 if (phy_status & MII_SR_LINK_STATUS)
2338 if (usec_interval >= 1000)
2339 msec_delay_irq(usec_interval/1000);
2341 usec_delay(usec_interval);
2344 *success = (i < iterations);
2350 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2351 * @hw: pointer to the HW structure
2353 * Reads the PHY specific status register to retrieve the cable length
2354 * information. The cable length is determined by averaging the minimum and
2355 * maximum values to get the "average" cable length. The m88 PHY has four
2356 * possible cable length values, which are:
2357 * Register Value Cable Length
2361 * 3 110 - 140 meters
2364 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2366 struct e1000_phy_info *phy = &hw->phy;
2368 u16 phy_data, index;
2370 DEBUGFUNC("e1000_get_cable_length_m88");
2372 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2376 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2377 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2379 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2380 return -E1000_ERR_PHY;
2382 phy->min_cable_length = e1000_m88_cable_length_table[index];
2383 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2385 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2387 return E1000_SUCCESS;
2390 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2392 struct e1000_phy_info *phy = &hw->phy;
2394 u16 phy_data, phy_data2, index, default_page, is_cm;
2396 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2398 switch (hw->phy.id) {
2400 /* Get cable length from PHY Cable Diagnostics Control Reg */
2401 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2402 (I347AT4_PCDL + phy->addr),
2407 /* Check if the unit of cable length is meters or cm */
2408 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2409 I347AT4_PCDC, &phy_data2);
2413 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2415 /* Populate the phy structure with cable length in meters */
2416 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2417 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2418 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2420 case M88E1340M_E_PHY_ID:
2421 case I347AT4_E_PHY_ID:
2422 /* Remember the original page select and set it to 7 */
2423 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2428 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2432 /* Get cable length from PHY Cable Diagnostics Control Reg */
2433 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2438 /* Check if the unit of cable length is meters or cm */
2439 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2443 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2445 /* Populate the phy structure with cable length in meters */
2446 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2447 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2448 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2450 /* Reset the page select to its original value */
2451 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2457 case M88E1112_E_PHY_ID:
2458 /* Remember the original page select and set it to 5 */
2459 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2464 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2468 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2473 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2474 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2476 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2477 return -E1000_ERR_PHY;
2479 phy->min_cable_length = e1000_m88_cable_length_table[index];
2480 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2482 phy->cable_length = (phy->min_cable_length +
2483 phy->max_cable_length) / 2;
2485 /* Reset the page select to its original value */
2486 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2493 return -E1000_ERR_PHY;
2500 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2501 * @hw: pointer to the HW structure
2503 * The automatic gain control (agc) normalizes the amplitude of the
2504 * received signal, adjusting for the attenuation produced by the
2505 * cable. By reading the AGC registers, which represent the
2506 * combination of coarse and fine gain value, the value can be put
2507 * into a lookup table to obtain the approximate cable length
2510 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2512 struct e1000_phy_info *phy = &hw->phy;
2514 u16 phy_data, i, agc_value = 0;
2515 u16 cur_agc_index, max_agc_index = 0;
2516 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2517 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2518 IGP02E1000_PHY_AGC_A,
2519 IGP02E1000_PHY_AGC_B,
2520 IGP02E1000_PHY_AGC_C,
2521 IGP02E1000_PHY_AGC_D
2524 DEBUGFUNC("e1000_get_cable_length_igp_2");
2526 /* Read the AGC registers for all channels */
2527 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2528 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2532 /* Getting bits 15:9, which represent the combination of
2533 * coarse and fine gain values. The result is a number
2534 * that can be put into the lookup table to obtain the
2535 * approximate cable length.
2537 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2538 IGP02E1000_AGC_LENGTH_MASK);
2540 /* Array index bound check. */
2541 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2542 (cur_agc_index == 0))
2543 return -E1000_ERR_PHY;
2545 /* Remove min & max AGC values from calculation. */
2546 if (e1000_igp_2_cable_length_table[min_agc_index] >
2547 e1000_igp_2_cable_length_table[cur_agc_index])
2548 min_agc_index = cur_agc_index;
2549 if (e1000_igp_2_cable_length_table[max_agc_index] <
2550 e1000_igp_2_cable_length_table[cur_agc_index])
2551 max_agc_index = cur_agc_index;
2553 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2556 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2557 e1000_igp_2_cable_length_table[max_agc_index]);
2558 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2560 /* Calculate cable length with the error range of +/- 10 meters. */
2561 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2562 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2563 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2565 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2567 return E1000_SUCCESS;
2571 * e1000_get_phy_info_m88 - Retrieve PHY information
2572 * @hw: pointer to the HW structure
2574 * Valid for only copper links. Read the PHY status register (sticky read)
2575 * to verify that link is up. Read the PHY special control register to
2576 * determine the polarity and 10base-T extended distance. Read the PHY
2577 * special status register to determine MDI/MDIx and current speed. If
2578 * speed is 1000, then determine cable length, local and remote receiver.
2580 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2582 struct e1000_phy_info *phy = &hw->phy;
2587 DEBUGFUNC("e1000_get_phy_info_m88");
2589 if (phy->media_type != e1000_media_type_copper) {
2590 DEBUGOUT("Phy info is only valid for copper media\n");
2591 return -E1000_ERR_CONFIG;
2594 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2599 DEBUGOUT("Phy info is only valid if link is up\n");
2600 return -E1000_ERR_CONFIG;
2603 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2607 phy->polarity_correction = !!(phy_data &
2608 M88E1000_PSCR_POLARITY_REVERSAL);
2610 ret_val = e1000_check_polarity_m88(hw);
2614 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2618 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2620 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2621 ret_val = hw->phy.ops.get_cable_length(hw);
2625 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2629 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2630 ? e1000_1000t_rx_status_ok
2631 : e1000_1000t_rx_status_not_ok;
2633 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2634 ? e1000_1000t_rx_status_ok
2635 : e1000_1000t_rx_status_not_ok;
2637 /* Set values to "undefined" */
2638 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2639 phy->local_rx = e1000_1000t_rx_status_undefined;
2640 phy->remote_rx = e1000_1000t_rx_status_undefined;
2647 * e1000_get_phy_info_igp - Retrieve igp PHY information
2648 * @hw: pointer to the HW structure
2650 * Read PHY status to determine if link is up. If link is up, then
2651 * set/determine 10base-T extended distance and polarity correction. Read
2652 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2653 * determine on the cable length, local and remote receiver.
2655 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2657 struct e1000_phy_info *phy = &hw->phy;
2662 DEBUGFUNC("e1000_get_phy_info_igp");
2664 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2669 DEBUGOUT("Phy info is only valid if link is up\n");
2670 return -E1000_ERR_CONFIG;
2673 phy->polarity_correction = true;
2675 ret_val = e1000_check_polarity_igp(hw);
2679 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2683 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2685 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2686 IGP01E1000_PSSR_SPEED_1000MBPS) {
2687 ret_val = phy->ops.get_cable_length(hw);
2691 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2695 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2696 ? e1000_1000t_rx_status_ok
2697 : e1000_1000t_rx_status_not_ok;
2699 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2700 ? e1000_1000t_rx_status_ok
2701 : e1000_1000t_rx_status_not_ok;
2703 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2704 phy->local_rx = e1000_1000t_rx_status_undefined;
2705 phy->remote_rx = e1000_1000t_rx_status_undefined;
2712 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2713 * @hw: pointer to the HW structure
2715 * Populates "phy" structure with various feature states.
2717 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2719 struct e1000_phy_info *phy = &hw->phy;
2724 DEBUGFUNC("e1000_get_phy_info_ife");
2726 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2731 DEBUGOUT("Phy info is only valid if link is up\n");
2732 return -E1000_ERR_CONFIG;
2735 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2738 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2740 if (phy->polarity_correction) {
2741 ret_val = e1000_check_polarity_ife(hw);
2745 /* Polarity is forced */
2746 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2747 ? e1000_rev_polarity_reversed
2748 : e1000_rev_polarity_normal);
2751 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2755 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2757 /* The following parameters are undefined for 10/100 operation. */
2758 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2759 phy->local_rx = e1000_1000t_rx_status_undefined;
2760 phy->remote_rx = e1000_1000t_rx_status_undefined;
2762 return E1000_SUCCESS;
2766 * e1000_phy_sw_reset_generic - PHY software reset
2767 * @hw: pointer to the HW structure
2769 * Does a software reset of the PHY by reading the PHY control register and
2770 * setting/write the control register reset bit to the PHY.
2772 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2777 DEBUGFUNC("e1000_phy_sw_reset_generic");
2779 if (!hw->phy.ops.read_reg)
2780 return E1000_SUCCESS;
2782 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2786 phy_ctrl |= MII_CR_RESET;
2787 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2797 * e1000_phy_hw_reset_generic - PHY hardware reset
2798 * @hw: pointer to the HW structure
2800 * Verify the reset block is not blocking us from resetting. Acquire
2801 * semaphore (if necessary) and read/set/write the device control reset
2802 * bit in the PHY. Wait the appropriate delay time for the device to
2803 * reset and release the semaphore (if necessary).
2805 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2807 struct e1000_phy_info *phy = &hw->phy;
2811 DEBUGFUNC("e1000_phy_hw_reset_generic");
2813 if (phy->ops.check_reset_block) {
2814 ret_val = phy->ops.check_reset_block(hw);
2816 return E1000_SUCCESS;
2819 ret_val = phy->ops.acquire(hw);
2823 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2824 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2825 E1000_WRITE_FLUSH(hw);
2827 usec_delay(phy->reset_delay_us);
2829 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2830 E1000_WRITE_FLUSH(hw);
2834 phy->ops.release(hw);
2836 return phy->ops.get_cfg_done(hw);
2840 * e1000_get_cfg_done_generic - Generic configuration done
2841 * @hw: pointer to the HW structure
2843 * Generic function to wait 10 milli-seconds for configuration to complete
2844 * and return success.
2846 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2848 DEBUGFUNC("e1000_get_cfg_done_generic");
2852 return E1000_SUCCESS;
2856 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2857 * @hw: pointer to the HW structure
2859 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2861 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2863 DEBUGOUT("Running IGP 3 PHY init script\n");
2865 /* PHY init IGP 3 */
2866 /* Enable rise/fall, 10-mode work in class-A */
2867 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2868 /* Remove all caps from Replica path filter */
2869 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2870 /* Bias trimming for ADC, AFE and Driver (Default) */
2871 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2872 /* Increase Hybrid poly bias */
2873 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2874 /* Add 4% to Tx amplitude in Gig mode */
2875 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2876 /* Disable trimming (TTT) */
2877 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2878 /* Poly DC correction to 94.6% + 2% for all channels */
2879 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2880 /* ABS DC correction to 95.9% */
2881 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2882 /* BG temp curve trim */
2883 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2884 /* Increasing ADC OPAMP stage 1 currents to max */
2885 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2886 /* Force 1000 ( required for enabling PHY regs configuration) */
2887 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2888 /* Set upd_freq to 6 */
2889 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2891 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2892 /* Disable adaptive fixed FFE (Default) */
2893 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2894 /* Enable FFE hysteresis */
2895 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2896 /* Fixed FFE for short cable lengths */
2897 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2898 /* Fixed FFE for medium cable lengths */
2899 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2900 /* Fixed FFE for long cable lengths */
2901 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2902 /* Enable Adaptive Clip Threshold */
2903 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2904 /* AHT reset limit to 1 */
2905 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2906 /* Set AHT master delay to 127 msec */
2907 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2908 /* Set scan bits for AHT */
2909 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2910 /* Set AHT Preset bits */
2911 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2912 /* Change integ_factor of channel A to 3 */
2913 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2914 /* Change prop_factor of channels BCD to 8 */
2915 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2916 /* Change cg_icount + enable integbp for channels BCD */
2917 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2918 /* Change cg_icount + enable integbp + change prop_factor_master
2919 * to 8 for channel A
2921 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2922 /* Disable AHT in Slave mode on channel A */
2923 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2924 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2927 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2928 /* Enable restart AN on an1000_dis change */
2929 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2930 /* Enable wh_fifo read clock in 10/100 modes */
2931 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2932 /* Restart AN, Speed selection is 1000 */
2933 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2935 return E1000_SUCCESS;
2939 * e1000_get_phy_type_from_id - Get PHY type from id
2940 * @phy_id: phy_id read from the phy
2942 * Returns the phy type from the id.
2944 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2946 enum e1000_phy_type phy_type = e1000_phy_unknown;
2949 case M88E1000_I_PHY_ID:
2950 case M88E1000_E_PHY_ID:
2951 case M88E1111_I_PHY_ID:
2952 case M88E1011_I_PHY_ID:
2953 case I347AT4_E_PHY_ID:
2954 case M88E1112_E_PHY_ID:
2955 case M88E1340M_E_PHY_ID:
2956 phy_type = e1000_phy_m88;
2958 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2959 phy_type = e1000_phy_igp_2;
2961 case GG82563_E_PHY_ID:
2962 phy_type = e1000_phy_gg82563;
2964 case IGP03E1000_E_PHY_ID:
2965 phy_type = e1000_phy_igp_3;
2968 case IFE_PLUS_E_PHY_ID:
2969 case IFE_C_E_PHY_ID:
2970 phy_type = e1000_phy_ife;
2972 case BME1000_E_PHY_ID:
2973 case BME1000_E_PHY_ID_R2:
2974 phy_type = e1000_phy_bm;
2976 case I82578_E_PHY_ID:
2977 phy_type = e1000_phy_82578;
2979 case I82577_E_PHY_ID:
2980 phy_type = e1000_phy_82577;
2982 case I82579_E_PHY_ID:
2983 phy_type = e1000_phy_82579;
2986 phy_type = e1000_phy_i217;
2988 case I82580_I_PHY_ID:
2989 phy_type = e1000_phy_82580;
2992 phy_type = e1000_phy_i210;
2995 phy_type = e1000_phy_unknown;
3002 * e1000_determine_phy_address - Determines PHY address.
3003 * @hw: pointer to the HW structure
3005 * This uses a trial and error method to loop through possible PHY
3006 * addresses. It tests each by reading the PHY ID registers and
3007 * checking for a match.
3009 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3013 enum e1000_phy_type phy_type = e1000_phy_unknown;
3015 hw->phy.id = phy_type;
3017 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3018 hw->phy.addr = phy_addr;
3022 e1000_get_phy_id(hw);
3023 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3025 /* If phy_type is valid, break - we found our
3028 if (phy_type != e1000_phy_unknown)
3029 return E1000_SUCCESS;
3036 return -E1000_ERR_PHY_TYPE;
3040 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3041 * @page: page to access
3043 * Returns the phy address for the page requested.
3045 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3049 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3056 * e1000_write_phy_reg_bm - Write BM PHY register
3057 * @hw: pointer to the HW structure
3058 * @offset: register offset to write to
3059 * @data: data to write at register offset
3061 * Acquires semaphore, if necessary, then writes the data to PHY register
3062 * at the offset. Release any acquired semaphores before exiting.
3064 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3067 u32 page = offset >> IGP_PAGE_SHIFT;
3069 DEBUGFUNC("e1000_write_phy_reg_bm");
3071 ret_val = hw->phy.ops.acquire(hw);
3075 /* Page 800 works differently than the rest so it has its own func */
3076 if (page == BM_WUC_PAGE) {
3077 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3082 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3084 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3085 u32 page_shift, page_select;
3087 /* Page select is register 31 for phy address 1 and 22 for
3088 * phy address 2 and 3. Page select is shifted only for
3091 if (hw->phy.addr == 1) {
3092 page_shift = IGP_PAGE_SHIFT;
3093 page_select = IGP01E1000_PHY_PAGE_SELECT;
3096 page_select = BM_PHY_PAGE_SELECT;
3099 /* Page is shifted left, PHY expects (page x 32) */
3100 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3101 (page << page_shift));
3106 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3110 hw->phy.ops.release(hw);
3115 * e1000_read_phy_reg_bm - Read BM PHY register
3116 * @hw: pointer to the HW structure
3117 * @offset: register offset to be read
3118 * @data: pointer to the read data
3120 * Acquires semaphore, if necessary, then reads the PHY register at offset
3121 * and storing the retrieved information in data. Release any acquired
3122 * semaphores before exiting.
3124 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3127 u32 page = offset >> IGP_PAGE_SHIFT;
3129 DEBUGFUNC("e1000_read_phy_reg_bm");
3131 ret_val = hw->phy.ops.acquire(hw);
3135 /* Page 800 works differently than the rest so it has its own func */
3136 if (page == BM_WUC_PAGE) {
3137 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3142 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3144 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3145 u32 page_shift, page_select;
3147 /* Page select is register 31 for phy address 1 and 22 for
3148 * phy address 2 and 3. Page select is shifted only for
3151 if (hw->phy.addr == 1) {
3152 page_shift = IGP_PAGE_SHIFT;
3153 page_select = IGP01E1000_PHY_PAGE_SELECT;
3156 page_select = BM_PHY_PAGE_SELECT;
3159 /* Page is shifted left, PHY expects (page x 32) */
3160 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3161 (page << page_shift));
3166 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3169 hw->phy.ops.release(hw);
3174 * e1000_read_phy_reg_bm2 - Read BM PHY register
3175 * @hw: pointer to the HW structure
3176 * @offset: register offset to be read
3177 * @data: pointer to the read data
3179 * Acquires semaphore, if necessary, then reads the PHY register at offset
3180 * and storing the retrieved information in data. Release any acquired
3181 * semaphores before exiting.
3183 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3186 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3188 DEBUGFUNC("e1000_read_phy_reg_bm2");
3190 ret_val = hw->phy.ops.acquire(hw);
3194 /* Page 800 works differently than the rest so it has its own func */
3195 if (page == BM_WUC_PAGE) {
3196 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3203 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3204 /* Page is shifted left, PHY expects (page x 32) */
3205 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3212 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3215 hw->phy.ops.release(hw);
3220 * e1000_write_phy_reg_bm2 - Write BM PHY register
3221 * @hw: pointer to the HW structure
3222 * @offset: register offset to write to
3223 * @data: data to write at register offset
3225 * Acquires semaphore, if necessary, then writes the data to PHY register
3226 * at the offset. Release any acquired semaphores before exiting.
3228 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3231 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3233 DEBUGFUNC("e1000_write_phy_reg_bm2");
3235 ret_val = hw->phy.ops.acquire(hw);
3239 /* Page 800 works differently than the rest so it has its own func */
3240 if (page == BM_WUC_PAGE) {
3241 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3248 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3249 /* Page is shifted left, PHY expects (page x 32) */
3250 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3257 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3261 hw->phy.ops.release(hw);
3266 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3267 * @hw: pointer to the HW structure
3268 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3270 * Assumes semaphore already acquired and phy_reg points to a valid memory
3271 * address to store contents of the BM_WUC_ENABLE_REG register.
3273 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3278 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3281 return -E1000_ERR_PARAM;
3283 /* All page select, port ctrl and wakeup registers use phy address 1 */
3286 /* Select Port Control Registers page */
3287 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3289 DEBUGOUT("Could not set Port Control page\n");
3293 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3295 DEBUGOUT2("Could not read PHY register %d.%d\n",
3296 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3300 /* Enable both PHY wakeup mode and Wakeup register page writes.
3301 * Prevent a power state change by disabling ME and Host PHY wakeup.
3304 temp |= BM_WUC_ENABLE_BIT;
3305 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3307 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3309 DEBUGOUT2("Could not write PHY register %d.%d\n",
3310 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3314 /* Select Host Wakeup Registers page - caller now able to write
3315 * registers on the Wakeup registers page
3317 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3321 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3322 * @hw: pointer to the HW structure
3323 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3325 * Restore BM_WUC_ENABLE_REG to its original value.
3327 * Assumes semaphore already acquired and *phy_reg is the contents of the
3328 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3331 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3335 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3338 return -E1000_ERR_PARAM;
3340 /* Select Port Control Registers page */
3341 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3343 DEBUGOUT("Could not set Port Control page\n");
3347 /* Restore 769.17 to its original value */
3348 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3350 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3351 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3357 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3358 * @hw: pointer to the HW structure
3359 * @offset: register offset to be read or written
3360 * @data: pointer to the data to read or write
3361 * @read: determines if operation is read or write
3362 * @page_set: BM_WUC_PAGE already set and access enabled
3364 * Read the PHY register at offset and store the retrieved information in
3365 * data, or write data to PHY register at offset. Note the procedure to
3366 * access the PHY wakeup registers is different than reading the other PHY
3367 * registers. It works as such:
3368 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3369 * 2) Set page to 800 for host (801 if we were manageability)
3370 * 3) Write the address using the address opcode (0x11)
3371 * 4) Read or write the data using the data opcode (0x12)
3372 * 5) Restore 769.17.2 to its original value
3374 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3375 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3377 * Assumes semaphore is already acquired. When page_set==true, assumes
3378 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3379 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3381 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3382 u16 *data, bool read, bool page_set)
3385 u16 reg = BM_PHY_REG_NUM(offset);
3386 u16 page = BM_PHY_REG_PAGE(offset);
3389 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3391 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3392 if ((hw->mac.type == e1000_pchlan) &&
3393 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3394 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3398 /* Enable access to PHY wakeup registers */
3399 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3401 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3406 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3408 /* Write the Wakeup register page offset value using opcode 0x11 */
3409 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3411 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3416 /* Read the Wakeup register page value using opcode 0x12 */
3417 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3420 /* Write the Wakeup register page value using opcode 0x12 */
3421 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3426 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3431 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3437 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3438 * @hw: pointer to the HW structure
3440 * In the case of a PHY power down to save power, or to turn off link during a
3441 * driver unload, or wake on lan is not enabled, restore the link to previous
3444 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3449 /* The PHY will retain its settings across a power down/up cycle */
3450 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3451 mii_reg &= ~MII_CR_POWER_DOWN;
3452 if (hw->phy.type == e1000_phy_i210) {
3453 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3454 power_reg &= ~GS40G_CS_POWER_DOWN;
3455 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3457 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3461 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3462 * @hw: pointer to the HW structure
3464 * In the case of a PHY power down to save power, or to turn off link during a
3465 * driver unload, or wake on lan is not enabled, restore the link to previous
3468 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3473 /* The PHY will retain its settings across a power down/up cycle */
3474 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3475 mii_reg |= MII_CR_POWER_DOWN;
3476 /* i210 Phy requires an additional bit for power up/down */
3477 if (hw->phy.type == e1000_phy_i210) {
3478 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3479 power_reg |= GS40G_CS_POWER_DOWN;
3480 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3482 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3487 * __e1000_read_phy_reg_hv - Read HV PHY register
3488 * @hw: pointer to the HW structure
3489 * @offset: register offset to be read
3490 * @data: pointer to the read data
3491 * @locked: semaphore has already been acquired or not
3493 * Acquires semaphore, if necessary, then reads the PHY register at offset
3494 * and stores the retrieved information in data. Release any acquired
3495 * semaphore before exiting.
3497 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3498 bool locked, bool page_set)
3501 u16 page = BM_PHY_REG_PAGE(offset);
3502 u16 reg = BM_PHY_REG_NUM(offset);
3503 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3505 DEBUGFUNC("__e1000_read_phy_reg_hv");
3508 ret_val = hw->phy.ops.acquire(hw);
3513 /* Page 800 works differently than the rest so it has its own func */
3514 if (page == BM_WUC_PAGE) {
3515 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3520 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3521 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3527 if (page == HV_INTC_FC_PAGE_START)
3530 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3531 /* Page is shifted left, PHY expects (page x 32) */
3532 ret_val = e1000_set_page_igp(hw,
3533 (page << IGP_PAGE_SHIFT));
3535 hw->phy.addr = phy_addr;
3542 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3543 page << IGP_PAGE_SHIFT, reg);
3545 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3549 hw->phy.ops.release(hw);
3555 * e1000_read_phy_reg_hv - Read HV PHY register
3556 * @hw: pointer to the HW structure
3557 * @offset: register offset to be read
3558 * @data: pointer to the read data
3560 * Acquires semaphore then reads the PHY register at offset and stores
3561 * the retrieved information in data. Release the acquired semaphore
3564 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3566 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3570 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3571 * @hw: pointer to the HW structure
3572 * @offset: register offset to be read
3573 * @data: pointer to the read data
3575 * Reads the PHY register at offset and stores the retrieved information
3576 * in data. Assumes semaphore already acquired.
3578 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3580 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3584 * e1000_read_phy_reg_page_hv - Read HV PHY register
3585 * @hw: pointer to the HW structure
3586 * @offset: register offset to write to
3587 * @data: data to write at register offset
3589 * Reads the PHY register at offset and stores the retrieved information
3590 * in data. Assumes semaphore already acquired and page already set.
3592 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3594 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3598 * __e1000_write_phy_reg_hv - Write HV PHY register
3599 * @hw: pointer to the HW structure
3600 * @offset: register offset to write to
3601 * @data: data to write at register offset
3602 * @locked: semaphore has already been acquired or not
3604 * Acquires semaphore, if necessary, then writes the data to PHY register
3605 * at the offset. Release any acquired semaphores before exiting.
3607 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3608 bool locked, bool page_set)
3611 u16 page = BM_PHY_REG_PAGE(offset);
3612 u16 reg = BM_PHY_REG_NUM(offset);
3613 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3615 DEBUGFUNC("__e1000_write_phy_reg_hv");
3618 ret_val = hw->phy.ops.acquire(hw);
3623 /* Page 800 works differently than the rest so it has its own func */
3624 if (page == BM_WUC_PAGE) {
3625 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3630 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3631 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3637 if (page == HV_INTC_FC_PAGE_START)
3640 /* Workaround MDIO accesses being disabled after entering IEEE
3641 * Power Down (when bit 11 of the PHY Control register is set)
3643 if ((hw->phy.type == e1000_phy_82578) &&
3644 (hw->phy.revision >= 1) &&
3645 (hw->phy.addr == 2) &&
3646 !(MAX_PHY_REG_ADDRESS & reg) &&
3647 (data & (1 << 11))) {
3649 ret_val = e1000_access_phy_debug_regs_hv(hw,
3656 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3657 /* Page is shifted left, PHY expects (page x 32) */
3658 ret_val = e1000_set_page_igp(hw,
3659 (page << IGP_PAGE_SHIFT));
3661 hw->phy.addr = phy_addr;
3668 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3669 page << IGP_PAGE_SHIFT, reg);
3671 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3676 hw->phy.ops.release(hw);
3682 * e1000_write_phy_reg_hv - Write HV PHY register
3683 * @hw: pointer to the HW structure
3684 * @offset: register offset to write to
3685 * @data: data to write at register offset
3687 * Acquires semaphore then writes the data to PHY register at the offset.
3688 * Release the acquired semaphores before exiting.
3690 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3692 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3696 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3697 * @hw: pointer to the HW structure
3698 * @offset: register offset to write to
3699 * @data: data to write at register offset
3701 * Writes the data to PHY register at the offset. Assumes semaphore
3704 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3706 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3710 * e1000_write_phy_reg_page_hv - Write HV PHY register
3711 * @hw: pointer to the HW structure
3712 * @offset: register offset to write to
3713 * @data: data to write at register offset
3715 * Writes the data to PHY register at the offset. Assumes semaphore
3716 * already acquired and page already set.
3718 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3720 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3724 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3725 * @page: page to be accessed
3727 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page)
3731 if (page >= HV_INTC_FC_PAGE_START)
3738 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3739 * @hw: pointer to the HW structure
3740 * @offset: register offset to be read or written
3741 * @data: pointer to the data to be read or written
3742 * @read: determines if operation is read or write
3744 * Reads the PHY register at offset and stores the retreived information
3745 * in data. Assumes semaphore already acquired. Note that the procedure
3746 * to access these regs uses the address port and data port to read/write.
3747 * These accesses done with PHY address 2 and without using pages.
3749 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3750 u16 *data, bool read)
3756 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3758 /* This takes care of the difference with desktop vs mobile phy */
3759 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3760 I82578_ADDR_REG : I82577_ADDR_REG);
3761 data_reg = addr_reg + 1;
3763 /* All operations in this function are phy address 2 */
3766 /* masking with 0x3F to remove the page from offset */
3767 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3769 DEBUGOUT("Could not write the Address Offset port register\n");
3773 /* Read or write the data value next */
3775 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3777 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3780 DEBUGOUT("Could not access the Data port register\n");
3786 * e1000_link_stall_workaround_hv - Si workaround
3787 * @hw: pointer to the HW structure
3789 * This function works around a Si bug where the link partner can get
3790 * a link up indication before the PHY does. If small packets are sent
3791 * by the link partner they can be placed in the packet buffer without
3792 * being properly accounted for by the PHY and will stall preventing
3793 * further packets from being received. The workaround is to clear the
3794 * packet buffer after the PHY detects link up.
3796 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3798 s32 ret_val = E1000_SUCCESS;
3801 DEBUGFUNC("e1000_link_stall_workaround_hv");
3803 if (hw->phy.type != e1000_phy_82578)
3804 return E1000_SUCCESS;
3806 /* Do not apply workaround if in PHY loopback bit 14 set */
3807 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3808 if (data & PHY_CONTROL_LB)
3809 return E1000_SUCCESS;
3811 /* check if link is up and at 1Gbps */
3812 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3816 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3817 BM_CS_STATUS_SPEED_MASK);
3819 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3820 BM_CS_STATUS_SPEED_1000))
3821 return E1000_SUCCESS;
3825 /* flush the packets in the fifo buffer */
3826 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3827 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3828 HV_MUX_DATA_CTRL_FORCE_SPEED));
3832 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3833 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3837 * e1000_check_polarity_82577 - Checks the polarity.
3838 * @hw: pointer to the HW structure
3840 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3842 * Polarity is determined based on the PHY specific status register.
3844 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3846 struct e1000_phy_info *phy = &hw->phy;
3850 DEBUGFUNC("e1000_check_polarity_82577");
3852 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3855 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3856 ? e1000_rev_polarity_reversed
3857 : e1000_rev_polarity_normal);
3863 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3864 * @hw: pointer to the HW structure
3866 * Calls the PHY setup function to force speed and duplex.
3868 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3870 struct e1000_phy_info *phy = &hw->phy;
3875 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3877 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3881 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3883 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3889 if (phy->autoneg_wait_to_complete) {
3890 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3892 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3898 DEBUGOUT("Link taking longer than expected.\n");
3901 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3909 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3910 * @hw: pointer to the HW structure
3912 * Read PHY status to determine if link is up. If link is up, then
3913 * set/determine 10base-T extended distance and polarity correction. Read
3914 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3915 * determine on the cable length, local and remote receiver.
3917 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3919 struct e1000_phy_info *phy = &hw->phy;
3924 DEBUGFUNC("e1000_get_phy_info_82577");
3926 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3931 DEBUGOUT("Phy info is only valid if link is up\n");
3932 return -E1000_ERR_CONFIG;
3935 phy->polarity_correction = true;
3937 ret_val = e1000_check_polarity_82577(hw);
3941 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3945 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3947 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3948 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3949 ret_val = hw->phy.ops.get_cable_length(hw);
3953 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3957 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3958 ? e1000_1000t_rx_status_ok
3959 : e1000_1000t_rx_status_not_ok;
3961 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3962 ? e1000_1000t_rx_status_ok
3963 : e1000_1000t_rx_status_not_ok;
3965 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3966 phy->local_rx = e1000_1000t_rx_status_undefined;
3967 phy->remote_rx = e1000_1000t_rx_status_undefined;
3970 return E1000_SUCCESS;
3974 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3975 * @hw: pointer to the HW structure
3977 * Reads the diagnostic status register and verifies result is valid before
3978 * placing it in the phy_cable_length field.
3980 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3982 struct e1000_phy_info *phy = &hw->phy;
3984 u16 phy_data, length;
3986 DEBUGFUNC("e1000_get_cable_length_82577");
3988 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3992 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3993 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3995 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3996 ret_val = -E1000_ERR_PHY;
3998 phy->cable_length = length;
4000 return E1000_SUCCESS;
4004 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4005 * @hw: pointer to the HW structure
4006 * @offset: register offset to write to
4007 * @data: data to write at register offset
4009 * Acquires semaphore, if necessary, then writes the data to PHY register
4010 * at the offset. Release any acquired semaphores before exiting.
4012 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4015 u16 page = offset >> GS40G_PAGE_SHIFT;
4017 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4019 offset = offset & GS40G_OFFSET_MASK;
4020 ret_val = hw->phy.ops.acquire(hw);
4024 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4027 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4030 hw->phy.ops.release(hw);
4035 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4036 * @hw: pointer to the HW structure
4037 * @offset: lower half is register offset to read to
4038 * upper half is page to use.
4039 * @data: data to read at register offset
4041 * Acquires semaphore, if necessary, then reads the data in the PHY register
4042 * at the offset. Release any acquired semaphores before exiting.
4044 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4047 u16 page = offset >> GS40G_PAGE_SHIFT;
4049 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4051 offset = offset & GS40G_OFFSET_MASK;
4052 ret_val = hw->phy.ops.acquire(hw);
4056 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4059 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4062 hw->phy.ops.release(hw);