1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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32 ***************************************************************************/
37 #include "e1000_osdep.h"
38 #include "e1000_regs.h"
39 #include "e1000_defines.h"
43 #define E1000_DEV_ID_82576_VF 0x10CA
44 #define E1000_DEV_ID_I350_VF 0x1520
46 #define E1000_VF_INIT_TIMEOUT 200 /* Num of retries to clear RSTI */
48 /* Additional Descriptor Control definitions */
49 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
50 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
52 /* SRRCTL bit definitions */
53 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
54 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
55 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
56 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
57 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
58 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
59 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
60 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
61 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
62 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
63 #define E1000_SRRCTL_DROP_EN 0x80000000
65 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
66 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
68 /* Interrupt Defines */
69 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
70 #define E1000_EITR(_n) (0x01680 + ((_n) << 2))
71 #define E1000_EICS 0x01520 /* Ext. Intr Cause Set -W0 */
72 #define E1000_EIMS 0x01524 /* Ext. Intr Mask Set/Read -RW */
73 #define E1000_EIMC 0x01528 /* Ext. Intr Mask Clear -WO */
74 #define E1000_EIAC 0x0152C /* Ext. Intr Auto Clear -RW */
75 #define E1000_EIAM 0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */
76 #define E1000_IVAR0 0x01700 /* Intr Vector Alloc (array) -RW */
77 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes -RW */
78 #define E1000_IVAR_VALID 0x80
80 /* Receive Descriptor - Advanced */
81 union e1000_adv_rx_desc {
83 u64 pkt_addr; /* Packet buffer address */
84 u64 hdr_addr; /* Header buffer address */
91 /* RSS type, Packet type */
93 /* Split Header, header buffer len */
98 u32 rss; /* RSS Hash */
100 u16 ip_id; /* IP id */
101 u16 csum; /* Packet Checksum */
106 u32 status_error; /* ext status/error */
107 u16 length; /* Packet length */
108 u16 vlan; /* VLAN tag */
110 } wb; /* writeback */
113 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
114 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
116 /* Transmit Descriptor - Advanced */
117 union e1000_adv_tx_desc {
119 u64 buffer_addr; /* Address of descriptor's data buf */
124 u64 rsvd; /* Reserved */
130 /* Adv Transmit Descriptor Config Masks */
131 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
132 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
133 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
134 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
135 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
136 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
137 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
138 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
139 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
141 /* Context descriptors */
142 struct e1000_adv_tx_context_desc {
149 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
150 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
151 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
152 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
153 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
155 enum e1000_mac_type {
159 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
162 struct e1000_vf_stats {
194 #include "e1000_mbx.h"
196 struct e1000_mac_operations {
197 /* Function pointers for the MAC. */
198 s32 (*init_params)(struct e1000_hw *);
199 s32 (*check_for_link)(struct e1000_hw *);
200 void (*clear_vfta)(struct e1000_hw *);
201 s32 (*get_bus_info)(struct e1000_hw *);
202 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
203 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
204 s32 (*reset_hw)(struct e1000_hw *);
205 s32 (*init_hw)(struct e1000_hw *);
206 s32 (*setup_link)(struct e1000_hw *);
207 void (*write_vfta)(struct e1000_hw *, u32, u32);
208 void (*rar_set)(struct e1000_hw *, u8*, u32);
209 s32 (*read_mac_addr)(struct e1000_hw *);
212 struct e1000_mac_info {
213 struct e1000_mac_operations ops;
217 enum e1000_mac_type type;
222 bool get_link_status;
225 struct e1000_mbx_operations {
226 s32 (*init_params)(struct e1000_hw *hw);
227 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
228 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
229 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
230 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
231 s32 (*check_for_msg)(struct e1000_hw *, u16);
232 s32 (*check_for_ack)(struct e1000_hw *, u16);
233 s32 (*check_for_rst)(struct e1000_hw *, u16);
236 struct e1000_mbx_stats {
245 struct e1000_mbx_info {
246 struct e1000_mbx_operations ops;
247 struct e1000_mbx_stats stats;
253 struct e1000_dev_spec_vf {
263 unsigned long io_base;
265 struct e1000_mac_info mac;
266 struct e1000_mbx_info mbx;
269 struct e1000_dev_spec_vf vf;
273 u16 subsystem_vendor_id;
274 u16 subsystem_device_id;
280 enum e1000_promisc_type {
281 e1000_promisc_disabled = 0, /* all promisc modes disabled */
282 e1000_promisc_unicast = 1, /* unicast promiscuous enabled */
283 e1000_promisc_multicast = 2, /* multicast promiscuous enabled */
284 e1000_promisc_enabled = 3, /* both uni and multicast promisc */
285 e1000_num_promisc_types
288 /* These functions must be implemented by drivers */
289 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
290 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
291 void e1000_rlpml_set_vf(struct e1000_hw *, u16);
292 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
293 #endif /* _E1000_VF_H_ */