4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "e1000/e1000_api.h"
57 #include "e1000_ethdev.h"
59 #define EM_EIAC 0x000DC
61 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
64 static int eth_em_configure(struct rte_eth_dev *dev);
65 static int eth_em_start(struct rte_eth_dev *dev);
66 static void eth_em_stop(struct rte_eth_dev *dev);
67 static void eth_em_close(struct rte_eth_dev *dev);
68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
72 static int eth_em_link_update(struct rte_eth_dev *dev,
73 int wait_to_complete);
74 static void eth_em_stats_get(struct rte_eth_dev *dev,
75 struct rte_eth_stats *rte_stats);
76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
77 static void eth_em_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
80 struct rte_eth_fc_conf *fc_conf);
81 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
82 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
83 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
84 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
87 static int em_hw_init(struct e1000_hw *hw);
88 static int em_hardware_init(struct e1000_hw *hw);
89 static void em_hw_control_acquire(struct e1000_hw *hw);
90 static void em_hw_control_release(struct e1000_hw *hw);
91 static void em_init_manageability(struct e1000_hw *hw);
92 static void em_release_manageability(struct e1000_hw *hw);
94 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
95 uint16_t vlan_id, int on);
96 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
97 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
98 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
99 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
100 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
103 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
104 uint16_t vlan_id, int on);
106 static int eth_em_led_on(struct rte_eth_dev *dev);
107 static int eth_em_led_off(struct rte_eth_dev *dev);
109 static void em_intr_disable(struct e1000_hw *hw);
110 static int em_get_rx_buffer_size(struct e1000_hw *hw);
111 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
112 uint32_t index, uint32_t pool);
113 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
115 #define EM_FC_PAUSE_TIME 0x0680
116 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
117 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
119 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
122 * The set of PCI devices this driver supports
124 static struct rte_pci_id pci_id_em_map[] = {
126 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
127 #include "rte_pci_dev_ids.h"
132 static struct eth_dev_ops eth_em_ops = {
133 .dev_configure = eth_em_configure,
134 .dev_start = eth_em_start,
135 .dev_stop = eth_em_stop,
136 .dev_close = eth_em_close,
137 .promiscuous_enable = eth_em_promiscuous_enable,
138 .promiscuous_disable = eth_em_promiscuous_disable,
139 .allmulticast_enable = eth_em_allmulticast_enable,
140 .allmulticast_disable = eth_em_allmulticast_disable,
141 .link_update = eth_em_link_update,
142 .stats_get = eth_em_stats_get,
143 .stats_reset = eth_em_stats_reset,
144 .dev_infos_get = eth_em_infos_get,
145 .vlan_filter_set = eth_em_vlan_filter_set,
146 .vlan_offload_set = eth_em_vlan_offload_set,
147 .rx_queue_setup = eth_em_rx_queue_setup,
148 .rx_queue_release = eth_em_rx_queue_release,
149 .rx_queue_count = eth_em_rx_queue_count,
150 .rx_descriptor_done = eth_em_rx_descriptor_done,
151 .tx_queue_setup = eth_em_tx_queue_setup,
152 .tx_queue_release = eth_em_tx_queue_release,
153 .dev_led_on = eth_em_led_on,
154 .dev_led_off = eth_em_led_off,
155 .flow_ctrl_set = eth_em_flow_ctrl_set,
156 .mac_addr_add = eth_em_rar_set,
157 .mac_addr_remove = eth_em_rar_clear,
161 * Atomically reads the link status information from global
162 * structure rte_eth_dev.
165 * - Pointer to the structure rte_eth_dev to read from.
166 * - Pointer to the buffer to be saved with the link status.
169 * - On success, zero.
170 * - On failure, negative value.
173 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
174 struct rte_eth_link *link)
176 struct rte_eth_link *dst = link;
177 struct rte_eth_link *src = &(dev->data->dev_link);
179 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
180 *(uint64_t *)src) == 0)
187 * Atomically writes the link status information into global
188 * structure rte_eth_dev.
191 * - Pointer to the structure rte_eth_dev to read from.
192 * - Pointer to the buffer to be saved with the link status.
195 * - On success, zero.
196 * - On failure, negative value.
199 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
200 struct rte_eth_link *link)
202 struct rte_eth_link *dst = &(dev->data->dev_link);
203 struct rte_eth_link *src = link;
205 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
206 *(uint64_t *)src) == 0)
213 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
214 struct rte_eth_dev *eth_dev)
216 struct rte_pci_device *pci_dev;
217 struct e1000_hw *hw =
218 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
219 struct e1000_vfta * shadow_vfta =
220 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
222 pci_dev = eth_dev->pci_dev;
223 eth_dev->dev_ops = ð_em_ops;
224 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
225 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
227 /* for secondary processes, we don't initialise any further as primary
228 * has already done this work. Only check we don't need a different
230 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
231 if (eth_dev->data->scattered_rx)
232 eth_dev->rx_pkt_burst =
233 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
237 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
238 hw->device_id = pci_dev->id.device_id;
240 /* For ICH8 support we'll need to map the flash memory BAR */
242 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
243 em_hw_init(hw) != 0) {
244 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
246 eth_dev->data->port_id, pci_dev->id.vendor_id,
247 pci_dev->id.device_id);
251 /* Allocate memory for storing MAC addresses */
252 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
253 hw->mac.rar_entry_count, 0);
254 if (eth_dev->data->mac_addrs == NULL) {
255 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
256 "store MAC addresses",
257 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
261 /* Copy the permanent MAC address */
262 ether_addr_copy((struct ether_addr *) hw->mac.addr,
263 eth_dev->data->mac_addrs);
265 /* initialize the vfta */
266 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
268 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
269 eth_dev->data->port_id, pci_dev->id.vendor_id,
270 pci_dev->id.device_id);
272 rte_intr_callback_register(&(pci_dev->intr_handle),
273 eth_em_interrupt_handler, (void *)eth_dev);
278 static struct eth_driver rte_em_pmd = {
280 .name = "rte_em_pmd",
281 .id_table = pci_id_em_map,
282 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
284 .eth_dev_init = eth_em_dev_init,
285 .dev_private_size = sizeof(struct e1000_adapter),
289 rte_em_pmd_init(void)
291 rte_eth_driver_register(&rte_em_pmd);
296 em_hw_init(struct e1000_hw *hw)
300 diag = hw->mac.ops.init_params(hw);
302 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
305 diag = hw->nvm.ops.init_params(hw);
307 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
310 diag = hw->phy.ops.init_params(hw);
312 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
315 (void) e1000_get_bus_info(hw);
318 hw->phy.autoneg_wait_to_complete = 0;
319 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
321 e1000_init_script_state_82541(hw, TRUE);
322 e1000_set_tbi_compatibility_82543(hw, TRUE);
325 if (hw->phy.media_type == e1000_media_type_copper) {
326 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
327 hw->phy.disable_polarity_correction = 0;
328 hw->phy.ms_type = e1000_ms_hw_default;
332 * Start from a known state, this is important in reading the nvm
337 /* Make sure we have a good EEPROM before we read from it */
338 if (e1000_validate_nvm_checksum(hw) < 0) {
340 * Some PCI-E parts fail the first check due to
341 * the link being in sleep state, call it again,
342 * if it fails a second time its a real issue.
344 diag = e1000_validate_nvm_checksum(hw);
346 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
351 /* Read the permanent MAC address out of the EEPROM */
352 diag = e1000_read_mac_addr(hw);
354 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
358 /* Now initialize the hardware */
359 diag = em_hardware_init(hw);
361 PMD_INIT_LOG(ERR, "Hardware initialization failed");
365 hw->mac.get_link_status = 1;
367 /* Indicate SOL/IDER usage */
368 diag = e1000_check_reset_block(hw);
370 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
376 em_hw_control_release(hw);
381 eth_em_configure(struct rte_eth_dev *dev)
383 struct e1000_interrupt *intr =
384 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
386 PMD_INIT_LOG(DEBUG, ">>");
388 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
390 PMD_INIT_LOG(DEBUG, "<<");
395 em_set_pba(struct e1000_hw *hw)
400 * Packet Buffer Allocation (PBA)
401 * Writing PBA sets the receive portion of the buffer
402 * the remainder is used for the transmit buffer.
403 * Devices before the 82547 had a Packet Buffer of 64K.
404 * After the 82547 the buffer was reduced to 40K.
406 switch (hw->mac.type) {
408 case e1000_82547_rev_2:
409 /* 82547: Total Packet Buffer is 40K */
410 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
414 case e1000_80003es2lan:
415 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
417 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
418 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
422 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
436 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
439 E1000_WRITE_REG(hw, E1000_PBA, pba);
443 eth_em_start(struct rte_eth_dev *dev)
445 struct e1000_hw *hw =
446 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
449 PMD_INIT_LOG(DEBUG, ">>");
453 e1000_power_up_phy(hw);
455 /* Set default PBA value */
458 /* Put the address into the Receive Address Array */
459 e1000_rar_set(hw, hw->mac.addr, 0);
462 * With the 82571 adapter, RAR[0] may be overwritten
463 * when the other port is reset, we make a duplicate
464 * in RAR[14] for that eventuality, this assures
465 * the interface continues to function.
467 if (hw->mac.type == e1000_82571) {
468 e1000_set_laa_state_82571(hw, TRUE);
469 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
472 /* Initialize the hardware */
473 if (em_hardware_init(hw)) {
474 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
478 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
480 /* Configure for OS presence */
481 em_init_manageability(hw);
485 ret = eth_em_rx_init(dev);
487 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
488 em_dev_clear_queues(dev);
492 e1000_clear_hw_cntrs_base_generic(hw);
494 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
495 ETH_VLAN_EXTEND_MASK;
496 eth_em_vlan_offload_set(dev, mask);
498 /* Set Interrupt Throttling Rate to maximum allowed value. */
499 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
501 /* Setup link speed and duplex */
502 switch (dev->data->dev_conf.link_speed) {
503 case ETH_LINK_SPEED_AUTONEG:
504 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
505 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
506 else if (dev->data->dev_conf.link_duplex ==
507 ETH_LINK_HALF_DUPLEX)
508 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
509 else if (dev->data->dev_conf.link_duplex ==
510 ETH_LINK_FULL_DUPLEX)
511 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
513 goto error_invalid_config;
515 case ETH_LINK_SPEED_10:
516 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
517 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
518 else if (dev->data->dev_conf.link_duplex ==
519 ETH_LINK_HALF_DUPLEX)
520 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
521 else if (dev->data->dev_conf.link_duplex ==
522 ETH_LINK_FULL_DUPLEX)
523 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
525 goto error_invalid_config;
527 case ETH_LINK_SPEED_100:
528 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
529 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
530 else if (dev->data->dev_conf.link_duplex ==
531 ETH_LINK_HALF_DUPLEX)
532 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
533 else if (dev->data->dev_conf.link_duplex ==
534 ETH_LINK_FULL_DUPLEX)
535 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
537 goto error_invalid_config;
539 case ETH_LINK_SPEED_1000:
540 if ((dev->data->dev_conf.link_duplex ==
541 ETH_LINK_AUTONEG_DUPLEX) ||
542 (dev->data->dev_conf.link_duplex ==
543 ETH_LINK_FULL_DUPLEX))
544 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
546 goto error_invalid_config;
548 case ETH_LINK_SPEED_10000:
550 goto error_invalid_config;
552 e1000_setup_link(hw);
554 /* check if lsc interrupt feature is enabled */
555 if (dev->data->dev_conf.intr_conf.lsc != 0) {
556 ret = eth_em_interrupt_setup(dev);
558 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
559 em_dev_clear_queues(dev);
564 PMD_INIT_LOG(DEBUG, "<<");
568 error_invalid_config:
569 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
570 "%u\n", dev->data->dev_conf.link_speed,
571 dev->data->dev_conf.link_duplex, dev->data->port_id);
572 em_dev_clear_queues(dev);
576 /*********************************************************************
578 * This routine disables all traffic on the adapter by issuing a
579 * global reset on the MAC.
581 **********************************************************************/
583 eth_em_stop(struct rte_eth_dev *dev)
585 struct rte_eth_link link;
586 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
590 if (hw->mac.type >= e1000_82544)
591 E1000_WRITE_REG(hw, E1000_WUC, 0);
593 /* Power down the phy. Needed to make the link go down */
594 e1000_power_down_phy(hw);
596 em_dev_clear_queues(dev);
598 /* clear the recorded link status */
599 memset(&link, 0, sizeof(link));
600 rte_em_dev_atomic_write_link_status(dev, &link);
604 eth_em_close(struct rte_eth_dev *dev)
606 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
609 e1000_phy_hw_reset(hw);
610 em_release_manageability(hw);
611 em_hw_control_release(hw);
615 em_get_rx_buffer_size(struct e1000_hw *hw)
617 uint32_t rx_buf_size;
619 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
623 /*********************************************************************
625 * Initialize the hardware
627 **********************************************************************/
629 em_hardware_init(struct e1000_hw *hw)
631 uint32_t rx_buf_size;
634 /* Issue a global reset */
637 /* Let the firmware know the OS is in control */
638 em_hw_control_acquire(hw);
641 * These parameters control the automatic generation (Tx) and
642 * response (Rx) to Ethernet PAUSE frames.
643 * - High water mark should allow for at least two standard size (1518)
644 * frames to be received after sending an XOFF.
645 * - Low water mark works best when it is very near the high water mark.
646 * This allows the receiver to restart by sending XON when it has
647 * drained a bit. Here we use an arbitary value of 1500 which will
648 * restart after one full frame is pulled from the buffer. There
649 * could be several smaller frames in the buffer and if so they will
650 * not trigger the XON until their total number reduces the buffer
652 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
654 rx_buf_size = em_get_rx_buffer_size(hw);
656 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
657 hw->fc.low_water = hw->fc.high_water - 1500;
659 if (hw->mac.type == e1000_80003es2lan)
660 hw->fc.pause_time = UINT16_MAX;
662 hw->fc.pause_time = EM_FC_PAUSE_TIME;
666 /* Set Flow control, use the tunable location if sane */
667 if (em_fc_setting <= e1000_fc_full)
668 hw->fc.requested_mode = em_fc_setting;
670 hw->fc.requested_mode = e1000_fc_none;
672 /* Workaround: no TX flow ctrl for PCH */
673 if (hw->mac.type == e1000_pchlan)
674 hw->fc.requested_mode = e1000_fc_rx_pause;
676 /* Override - settings for PCH2LAN, ya its magic :) */
677 if (hw->mac.type == e1000_pch2lan) {
678 hw->fc.high_water = 0x5C20;
679 hw->fc.low_water = 0x5048;
680 hw->fc.pause_time = 0x0650;
681 hw->fc.refresh_time = 0x0400;
684 diag = e1000_init_hw(hw);
687 e1000_check_for_link(hw);
691 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
693 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
695 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
696 struct e1000_hw_stats *stats =
697 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
700 if(hw->phy.media_type == e1000_media_type_copper ||
701 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
702 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
703 stats->sec += E1000_READ_REG(hw, E1000_SEC);
706 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
707 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
708 stats->scc += E1000_READ_REG(hw, E1000_SCC);
709 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
711 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
712 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
713 stats->colc += E1000_READ_REG(hw, E1000_COLC);
714 stats->dc += E1000_READ_REG(hw, E1000_DC);
715 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
716 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
717 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
720 * For watchdog management we need to know if we have been
721 * paused during the last interval, so capture that here.
723 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
724 stats->xoffrxc += pause_frames;
725 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
726 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
727 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
728 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
729 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
730 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
731 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
732 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
733 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
734 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
735 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
736 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
739 * For the 64-bit byte counters the low dword must be read first.
740 * Both registers clear on the read of the high dword.
743 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
744 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
745 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
746 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
748 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
749 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
750 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
751 stats->roc += E1000_READ_REG(hw, E1000_ROC);
752 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
754 stats->tor += E1000_READ_REG(hw, E1000_TORH);
755 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
757 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
758 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
759 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
760 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
761 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
762 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
763 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
764 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
765 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
766 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
768 /* Interrupt Counts */
770 if (hw->mac.type >= e1000_82571) {
771 stats->iac += E1000_READ_REG(hw, E1000_IAC);
772 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
773 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
774 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
775 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
776 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
777 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
778 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
779 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
782 if (hw->mac.type >= e1000_82543) {
783 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
784 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
785 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
786 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
787 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
788 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
791 if (rte_stats == NULL)
795 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
796 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
799 rte_stats->oerrors = stats->ecol + stats->latecol;
801 rte_stats->ipackets = stats->gprc;
802 rte_stats->opackets = stats->gptc;
803 rte_stats->ibytes = stats->gorc;
804 rte_stats->obytes = stats->gotc;
808 eth_em_stats_reset(struct rte_eth_dev *dev)
810 struct e1000_hw_stats *hw_stats =
811 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
813 /* HW registers are cleared on read */
814 eth_em_stats_get(dev, NULL);
816 /* Reset software totals */
817 memset(hw_stats, 0, sizeof(*hw_stats));
821 em_get_max_pktlen(const struct e1000_hw *hw)
823 switch (hw->mac.type) {
830 case e1000_80003es2lan: /* 9K Jumbo Frame size */
834 /* Adapters that do not support jumbo frames */
837 return (ETHER_MAX_LEN);
839 return (MAX_JUMBO_FRAME_SIZE);
844 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
846 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
848 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
849 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
850 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
853 * Starting with 631xESB hw supports 2 TX/RX queues per port.
854 * Unfortunatelly, all these nics have just one TX context.
855 * So we have few choises for TX:
856 * - Use just one TX queue.
857 * - Allow cksum offload only for one TX queue.
858 * - Don't allow TX cksum offload at all.
859 * For now, option #1 was chosen.
860 * To use second RX queue we have to use extended RX descriptor
861 * (Multiple Receive Queues are mutually exclusive with UDP
862 * fragmentation and are not supported when a legacy receive
863 * descriptor format is used).
864 * Which means separate RX routinies - as legacy nics (82540, 82545)
865 * don't support extended RXD.
866 * To avoid it we support just one RX queue for now (no RSS).
869 dev_info->max_rx_queues = 1;
870 dev_info->max_tx_queues = 1;
873 /* return 0 means link status changed, -1 means not changed */
875 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
877 struct e1000_hw *hw =
878 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
879 struct rte_eth_link link, old;
880 int link_check, count;
883 hw->mac.get_link_status = 1;
885 /* possible wait-to-complete in up to 9 seconds */
886 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
887 /* Read the real link status */
888 switch (hw->phy.media_type) {
889 case e1000_media_type_copper:
890 /* Do the work to read phy */
891 e1000_check_for_link(hw);
892 link_check = !hw->mac.get_link_status;
895 case e1000_media_type_fiber:
896 e1000_check_for_link(hw);
897 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
901 case e1000_media_type_internal_serdes:
902 e1000_check_for_link(hw);
903 link_check = hw->mac.serdes_has_link;
909 if (link_check || wait_to_complete == 0)
911 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
913 memset(&link, 0, sizeof(link));
914 rte_em_dev_atomic_read_link_status(dev, &link);
917 /* Now we check if a transition has happened */
918 if (link_check && (link.link_status == 0)) {
919 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
921 link.link_status = 1;
922 } else if (!link_check && (link.link_status == 1)) {
924 link.link_duplex = 0;
925 link.link_status = 0;
927 rte_em_dev_atomic_write_link_status(dev, &link);
930 if (old.link_status == link.link_status)
938 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
939 * For ASF and Pass Through versions of f/w this means
940 * that the driver is loaded. For AMT version type f/w
941 * this means that the network i/f is open.
944 em_hw_control_acquire(struct e1000_hw *hw)
946 uint32_t ctrl_ext, swsm;
948 /* Let firmware know the driver has taken over */
949 if (hw->mac.type == e1000_82573) {
950 swsm = E1000_READ_REG(hw, E1000_SWSM);
951 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
954 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
955 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
956 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
961 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
962 * For ASF and Pass Through versions of f/w this means that the
963 * driver is no longer loaded. For AMT versions of the
964 * f/w this means that the network i/f is closed.
967 em_hw_control_release(struct e1000_hw *hw)
969 uint32_t ctrl_ext, swsm;
971 /* Let firmware taken over control of h/w */
972 if (hw->mac.type == e1000_82573) {
973 swsm = E1000_READ_REG(hw, E1000_SWSM);
974 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
976 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
977 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
978 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
983 * Bit of a misnomer, what this really means is
984 * to enable OS management of the system... aka
985 * to disable special hardware management features.
988 em_init_manageability(struct e1000_hw *hw)
990 if (e1000_enable_mng_pass_thru(hw)) {
991 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
992 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
994 /* disable hardware interception of ARP */
995 manc &= ~(E1000_MANC_ARP_EN);
997 /* enable receiving management packets to the host */
998 manc |= E1000_MANC_EN_MNG2HOST;
999 manc2h |= 1 << 5; /* Mng Port 623 */
1000 manc2h |= 1 << 6; /* Mng Port 664 */
1001 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1002 E1000_WRITE_REG(hw, E1000_MANC, manc);
1007 * Give control back to hardware management
1008 * controller if there is one.
1011 em_release_manageability(struct e1000_hw *hw)
1015 if (e1000_enable_mng_pass_thru(hw)) {
1016 manc = E1000_READ_REG(hw, E1000_MANC);
1018 /* re-enable hardware interception of ARP */
1019 manc |= E1000_MANC_ARP_EN;
1020 manc &= ~E1000_MANC_EN_MNG2HOST;
1022 E1000_WRITE_REG(hw, E1000_MANC, manc);
1027 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1029 struct e1000_hw *hw =
1030 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033 rctl = E1000_READ_REG(hw, E1000_RCTL);
1034 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1035 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1039 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1041 struct e1000_hw *hw =
1042 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1045 rctl = E1000_READ_REG(hw, E1000_RCTL);
1046 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1047 if (dev->data->all_multicast == 1)
1048 rctl |= E1000_RCTL_MPE;
1050 rctl &= (~E1000_RCTL_MPE);
1051 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1055 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1057 struct e1000_hw *hw =
1058 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1061 rctl = E1000_READ_REG(hw, E1000_RCTL);
1062 rctl |= E1000_RCTL_MPE;
1063 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1067 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1069 struct e1000_hw *hw =
1070 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1073 if (dev->data->promiscuous == 1)
1074 return; /* must remain in all_multicast mode */
1075 rctl = E1000_READ_REG(hw, E1000_RCTL);
1076 rctl &= (~E1000_RCTL_MPE);
1077 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1081 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1083 struct e1000_hw *hw =
1084 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1085 struct e1000_vfta * shadow_vfta =
1086 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1091 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1092 E1000_VFTA_ENTRY_MASK);
1093 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1094 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1099 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1101 /* update local VFTA copy */
1102 shadow_vfta->vfta[vid_idx] = vfta;
1108 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1110 struct e1000_hw *hw =
1111 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114 /* Filter Table Disable */
1115 reg = E1000_READ_REG(hw, E1000_RCTL);
1116 reg &= ~E1000_RCTL_CFIEN;
1117 reg &= ~E1000_RCTL_VFE;
1118 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1122 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1124 struct e1000_hw *hw =
1125 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1126 struct e1000_vfta * shadow_vfta =
1127 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1131 /* Filter Table Enable, CFI not used for packet acceptance */
1132 reg = E1000_READ_REG(hw, E1000_RCTL);
1133 reg &= ~E1000_RCTL_CFIEN;
1134 reg |= E1000_RCTL_VFE;
1135 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1137 /* restore vfta from local copy */
1138 for (i = 0; i < IGB_VFTA_SIZE; i++)
1139 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1143 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1145 struct e1000_hw *hw =
1146 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149 /* VLAN Mode Disable */
1150 reg = E1000_READ_REG(hw, E1000_CTRL);
1151 reg &= ~E1000_CTRL_VME;
1152 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1157 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1159 struct e1000_hw *hw =
1160 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163 /* VLAN Mode Enable */
1164 reg = E1000_READ_REG(hw, E1000_CTRL);
1165 reg |= E1000_CTRL_VME;
1166 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1170 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1172 if(mask & ETH_VLAN_STRIP_MASK){
1173 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1174 em_vlan_hw_strip_enable(dev);
1176 em_vlan_hw_strip_disable(dev);
1179 if(mask & ETH_VLAN_FILTER_MASK){
1180 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1181 em_vlan_hw_filter_enable(dev);
1183 em_vlan_hw_filter_disable(dev);
1188 em_intr_disable(struct e1000_hw *hw)
1190 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1194 * It enables the interrupt mask and then enable the interrupt.
1197 * Pointer to struct rte_eth_dev.
1200 * - On success, zero.
1201 * - On failure, a negative value.
1204 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1206 struct e1000_hw *hw =
1207 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1210 rte_intr_enable(&(dev->pci_dev->intr_handle));
1215 * It reads ICR and gets interrupt causes, check it and set a bit flag
1216 * to update link status.
1219 * Pointer to struct rte_eth_dev.
1222 * - On success, zero.
1223 * - On failure, a negative value.
1226 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1229 struct e1000_hw *hw =
1230 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231 struct e1000_interrupt *intr =
1232 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1234 /* read-on-clear nic registers here */
1235 icr = E1000_READ_REG(hw, E1000_ICR);
1236 if (icr & E1000_ICR_LSC) {
1237 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1244 * It executes link_update after knowing an interrupt is prsent.
1247 * Pointer to struct rte_eth_dev.
1250 * - On success, zero.
1251 * - On failure, a negative value.
1254 eth_em_interrupt_action(struct rte_eth_dev *dev)
1256 struct e1000_hw *hw =
1257 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258 struct e1000_interrupt *intr =
1259 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1260 uint32_t tctl, rctl;
1261 struct rte_eth_link link;
1264 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1267 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1268 rte_intr_enable(&(dev->pci_dev->intr_handle));
1270 /* set get_link_status to check register later */
1271 hw->mac.get_link_status = 1;
1272 ret = eth_em_link_update(dev, 0);
1274 /* check if link has changed */
1278 memset(&link, 0, sizeof(link));
1279 rte_em_dev_atomic_read_link_status(dev, &link);
1280 if (link.link_status) {
1282 " Port %d: Link Up - speed %u Mbps - %s\n",
1283 dev->data->port_id, (unsigned)link.link_speed,
1284 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1285 "full-duplex" : "half-duplex");
1287 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1288 dev->data->port_id);
1290 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1291 dev->pci_dev->addr.domain,
1292 dev->pci_dev->addr.bus,
1293 dev->pci_dev->addr.devid,
1294 dev->pci_dev->addr.function);
1295 tctl = E1000_READ_REG(hw, E1000_TCTL);
1296 rctl = E1000_READ_REG(hw, E1000_RCTL);
1297 if (link.link_status) {
1299 tctl |= E1000_TCTL_EN;
1300 rctl |= E1000_RCTL_EN;
1303 tctl &= ~E1000_TCTL_EN;
1304 rctl &= ~E1000_RCTL_EN;
1306 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1307 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1308 E1000_WRITE_FLUSH(hw);
1314 * Interrupt handler which shall be registered at first.
1317 * Pointer to interrupt handle.
1319 * The address of parameter (struct rte_eth_dev *) regsitered before.
1325 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1328 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1330 eth_em_interrupt_get_status(dev);
1331 eth_em_interrupt_action(dev);
1332 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1336 eth_em_led_on(struct rte_eth_dev *dev)
1338 struct e1000_hw *hw;
1340 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1341 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1345 eth_em_led_off(struct rte_eth_dev *dev)
1347 struct e1000_hw *hw;
1349 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1354 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1356 struct e1000_hw *hw;
1358 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1364 uint32_t rx_buf_size;
1365 uint32_t max_high_water;
1368 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369 rx_buf_size = em_get_rx_buffer_size(hw);
1370 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1372 /* At least reserve one Ethernet frame for watermark */
1373 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1374 if ((fc_conf->high_water > max_high_water) ||
1375 (fc_conf->high_water < fc_conf->low_water)) {
1376 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1377 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1381 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1382 hw->fc.pause_time = fc_conf->pause_time;
1383 hw->fc.high_water = fc_conf->high_water;
1384 hw->fc.low_water = fc_conf->low_water;
1385 hw->fc.send_xon = fc_conf->send_xon;
1387 err = e1000_setup_link_generic(hw);
1388 if (err == E1000_SUCCESS) {
1390 /* check if we want to forward MAC frames - driver doesn't have native
1391 * capability to do that, so we'll write the registers ourselves */
1393 rctl = E1000_READ_REG(hw, E1000_RCTL);
1395 /* set or clear MFLCN.PMCF bit depending on configuration */
1396 if (fc_conf->mac_ctrl_frame_fwd != 0)
1397 rctl |= E1000_RCTL_PMCF;
1399 rctl &= ~E1000_RCTL_PMCF;
1401 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1402 E1000_WRITE_FLUSH(hw);
1407 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1412 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1413 uint32_t index, __rte_unused uint32_t pool)
1415 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1421 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1423 uint8_t addr[ETHER_ADDR_LEN];
1424 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 memset(addr, 0, sizeof(addr));
1428 e1000_rar_set(hw, addr, index);