lib/librte_pmd_e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54
  55 #include "e1000_logs.h"
  56 #include "e1000/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  82 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  83 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  84 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  85                                                         void *param);
  86
  87 static int em_hw_init(struct e1000_hw *hw);
  88 static int em_hardware_init(struct e1000_hw *hw);
  89 static void em_hw_control_acquire(struct e1000_hw *hw);
  90 static void em_hw_control_release(struct e1000_hw *hw);
  91 static void em_init_manageability(struct e1000_hw *hw);
  92 static void em_release_manageability(struct e1000_hw *hw);
  93
  94 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  95                 uint16_t vlan_id, int on);
  96 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  97 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  98 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  99 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 100 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 101
 102 /*
 103 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 104                                         uint16_t vlan_id, int on);
 105 */
 106 static int eth_em_led_on(struct rte_eth_dev *dev);
 107 static int eth_em_led_off(struct rte_eth_dev *dev);
 108
 109 static void em_intr_disable(struct e1000_hw *hw);
 110 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 111 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 112                 uint32_t index, uint32_t pool);
 113 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 114
 115 #define EM_FC_PAUSE_TIME 0x0680
 116 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 117 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 118
 119 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 120
 121 /*
 122  * The set of PCI devices this driver supports
 123  */
 124 static struct rte_pci_id pci_id_em_map[] = {
 125
 126 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 127 #include "rte_pci_dev_ids.h"
 128
 129 {.device_id = 0},
 130 };
 131
 132 static struct eth_dev_ops eth_em_ops = {
 133         .dev_configure        = eth_em_configure,
 134         .dev_start            = eth_em_start,
 135         .dev_stop             = eth_em_stop,
 136         .dev_close            = eth_em_close,
 137         .promiscuous_enable   = eth_em_promiscuous_enable,
 138         .promiscuous_disable  = eth_em_promiscuous_disable,
 139         .allmulticast_enable  = eth_em_allmulticast_enable,
 140         .allmulticast_disable = eth_em_allmulticast_disable,
 141         .link_update          = eth_em_link_update,
 142         .stats_get            = eth_em_stats_get,
 143         .stats_reset          = eth_em_stats_reset,
 144         .dev_infos_get        = eth_em_infos_get,
 145         .vlan_filter_set      = eth_em_vlan_filter_set,
 146         .vlan_offload_set     = eth_em_vlan_offload_set,
 147         .rx_queue_setup       = eth_em_rx_queue_setup,
 148         .rx_queue_release     = eth_em_rx_queue_release,
 149         .rx_queue_count       = eth_em_rx_queue_count,
 150         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 151         .tx_queue_setup       = eth_em_tx_queue_setup,
 152         .tx_queue_release     = eth_em_tx_queue_release,
 153         .dev_led_on           = eth_em_led_on,
 154         .dev_led_off          = eth_em_led_off,
 155         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 156         .mac_addr_add         = eth_em_rar_set,
 157         .mac_addr_remove      = eth_em_rar_clear,
 158 };
 159
 160 /**
 161  * Atomically reads the link status information from global
 162  * structure rte_eth_dev.
 163  *
 164  * @param dev
 165  *   - Pointer to the structure rte_eth_dev to read from.
 166  *   - Pointer to the buffer to be saved with the link status.
 167  *
 168  * @return
 169  *   - On success, zero.
 170  *   - On failure, negative value.
 171  */
 172 static inline int
 173 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 174                                 struct rte_eth_link *link)
 175 {
 176         struct rte_eth_link *dst = link;
 177         struct rte_eth_link *src = &(dev->data->dev_link);
 178
 179         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 180                                         *(uint64_t *)src) == 0)
 181                 return -1;
 182
 183         return 0;
 184 }
 185
 186 /**
 187  * Atomically writes the link status information into global
 188  * structure rte_eth_dev.
 189  *
 190  * @param dev
 191  *   - Pointer to the structure rte_eth_dev to read from.
 192  *   - Pointer to the buffer to be saved with the link status.
 193  *
 194  * @return
 195  *   - On success, zero.
 196  *   - On failure, negative value.
 197  */
 198 static inline int
 199 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 200                                 struct rte_eth_link *link)
 201 {
 202         struct rte_eth_link *dst = &(dev->data->dev_link);
 203         struct rte_eth_link *src = link;
 204
 205         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 206                                         *(uint64_t *)src) == 0)
 207                 return -1;
 208
 209         return 0;
 210 }
 211
 212 static int
 213 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 214                 struct rte_eth_dev *eth_dev)
 215 {
 216         struct rte_pci_device *pci_dev;
 217         struct e1000_hw *hw =
 218                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 219         struct e1000_vfta * shadow_vfta =
 220                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 221
 222         pci_dev = eth_dev->pci_dev;
 223         eth_dev->dev_ops = &eth_em_ops;
 224         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 225         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 226
 227         /* for secondary processes, we don't initialise any further as primary
 228          * has already done this work. Only check we don't need a different
 229          * RX function */
 230         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 231                 if (eth_dev->data->scattered_rx)
 232                         eth_dev->rx_pkt_burst =
 233                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 234                 return 0;
 235         }
 236
 237         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 238         hw->device_id = pci_dev->id.device_id;
 239
 240         /* For ICH8 support we'll need to map the flash memory BAR */
 241
 242         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 243                         em_hw_init(hw) != 0) {
 244                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 245                         "failed to init HW",
 246                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 247                         pci_dev->id.device_id);
 248                 return -(ENODEV);
 249         }
 250
 251         /* Allocate memory for storing MAC addresses */
 252         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 253                         hw->mac.rar_entry_count, 0);
 254         if (eth_dev->data->mac_addrs == NULL) {
 255                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 256                         "store MAC addresses",
 257                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 258                 return -(ENOMEM);
 259         }
 260
 261         /* Copy the permanent MAC address */
 262         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 263                 eth_dev->data->mac_addrs);
 264
 265         /* initialize the vfta */
 266         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 267
 268         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 269                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 270                         pci_dev->id.device_id);
 271
 272         rte_intr_callback_register(&(pci_dev->intr_handle),
 273                 eth_em_interrupt_handler, (void *)eth_dev);
 274
 275         return (0);
 276 }
 277
 278 static struct eth_driver rte_em_pmd = {
 279         {
 280                 .name = "rte_em_pmd",
 281                 .id_table = pci_id_em_map,
 282                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 283         },
 284         .eth_dev_init = eth_em_dev_init,
 285         .dev_private_size = sizeof(struct e1000_adapter),
 286 };
 287
 288 int
 289 rte_em_pmd_init(void)
 290 {
 291         rte_eth_driver_register(&rte_em_pmd);
 292         return 0;
 293 }
 294
 295 static int
 296 em_hw_init(struct e1000_hw *hw)
 297 {
 298         int diag;
 299
 300         diag = hw->mac.ops.init_params(hw);
 301         if (diag != 0) {
 302                 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
 303                 return diag;
 304         }
 305         diag = hw->nvm.ops.init_params(hw);
 306         if (diag != 0) {
 307                 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
 308                 return diag;
 309         }
 310         diag = hw->phy.ops.init_params(hw);
 311         if (diag != 0) {
 312                 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
 313                 return diag;
 314         }
 315         (void) e1000_get_bus_info(hw);
 316
 317         hw->mac.autoneg = 1;
 318         hw->phy.autoneg_wait_to_complete = 0;
 319         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 320
 321         e1000_init_script_state_82541(hw, TRUE);
 322         e1000_set_tbi_compatibility_82543(hw, TRUE);
 323
 324         /* Copper options */
 325         if (hw->phy.media_type == e1000_media_type_copper) {
 326                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 327                 hw->phy.disable_polarity_correction = 0;
 328                 hw->phy.ms_type = e1000_ms_hw_default;
 329         }
 330
 331         /*
 332          * Start from a known state, this is important in reading the nvm
 333          * and mac from that.
 334          */
 335         e1000_reset_hw(hw);
 336
 337         /* Make sure we have a good EEPROM before we read from it */
 338         if (e1000_validate_nvm_checksum(hw) < 0) {
 339                 /*
 340                  * Some PCI-E parts fail the first check due to
 341                  * the link being in sleep state, call it again,
 342                  * if it fails a second time its a real issue.
 343                  */
 344                 diag = e1000_validate_nvm_checksum(hw);
 345                 if (diag < 0) {
 346                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 347                         goto error;
 348                 }
 349         }
 350
 351         /* Read the permanent MAC address out of the EEPROM */
 352         diag = e1000_read_mac_addr(hw);
 353         if (diag != 0) {
 354                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 355                 goto error;
 356         }
 357
 358         /* Now initialize the hardware */
 359         diag = em_hardware_init(hw);
 360         if (diag != 0) {
 361                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 362                 goto error;
 363         }
 364
 365         hw->mac.get_link_status = 1;
 366
 367         /* Indicate SOL/IDER usage */
 368         diag = e1000_check_reset_block(hw);
 369         if (diag < 0) {
 370                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 371                         "SOL/IDER session");
 372         }
 373         return (0);
 374
 375 error:
 376         em_hw_control_release(hw);
 377         return (diag);
 378 }
 379
 380 static int
 381 eth_em_configure(struct rte_eth_dev *dev)
 382 {
 383         struct e1000_interrupt *intr =
 384                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 385
 386         PMD_INIT_LOG(DEBUG, ">>");
 387
 388         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 389
 390         PMD_INIT_LOG(DEBUG, "<<");
 391         return (0);
 392 }
 393
 394 static void
 395 em_set_pba(struct e1000_hw *hw)
 396 {
 397         uint32_t pba;
 398
 399         /*
 400          * Packet Buffer Allocation (PBA)
 401          * Writing PBA sets the receive portion of the buffer
 402          * the remainder is used for the transmit buffer.
 403          * Devices before the 82547 had a Packet Buffer of 64K.
 404          * After the 82547 the buffer was reduced to 40K.
 405          */
 406         switch (hw->mac.type) {
 407                 case e1000_82547:
 408                 case e1000_82547_rev_2:
 409                 /* 82547: Total Packet Buffer is 40K */
 410                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 411                         break;
 412                 case e1000_82571:
 413                 case e1000_82572:
 414                 case e1000_80003es2lan:
 415                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 416                         break;
 417                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 418                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 419                         break;
 420                 case e1000_82574:
 421                 case e1000_82583:
 422                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 423                         break;
 424                 case e1000_ich8lan:
 425                         pba = E1000_PBA_8K;
 426                         break;
 427                 case e1000_ich9lan:
 428                 case e1000_ich10lan:
 429                         pba = E1000_PBA_10K;
 430                         break;
 431                 case e1000_pchlan:
 432                 case e1000_pch2lan:
 433                         pba = E1000_PBA_26K;
 434                         break;
 435                 default:
 436                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 437         }
 438
 439         E1000_WRITE_REG(hw, E1000_PBA, pba);
 440 }
 441
 442 static int
 443 eth_em_start(struct rte_eth_dev *dev)
 444 {
 445         struct e1000_hw *hw =
 446                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 447         int ret, mask;
 448
 449         PMD_INIT_LOG(DEBUG, ">>");
 450
 451         eth_em_stop(dev);
 452
 453         e1000_power_up_phy(hw);
 454
 455         /* Set default PBA value */
 456         em_set_pba(hw);
 457
 458         /* Put the address into the Receive Address Array */
 459         e1000_rar_set(hw, hw->mac.addr, 0);
 460
 461         /*
 462          * With the 82571 adapter, RAR[0] may be overwritten
 463          * when the other port is reset, we make a duplicate
 464          * in RAR[14] for that eventuality, this assures
 465          * the interface continues to function.
 466          */
 467         if (hw->mac.type == e1000_82571) {
 468                 e1000_set_laa_state_82571(hw, TRUE);
 469                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 470         }
 471
 472         /* Initialize the hardware */
 473         if (em_hardware_init(hw)) {
 474                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 475                 return (-EIO);
 476         }
 477
 478         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 479
 480         /* Configure for OS presence */
 481         em_init_manageability(hw);
 482
 483         eth_em_tx_init(dev);
 484
 485         ret = eth_em_rx_init(dev);
 486         if (ret) {
 487                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 488                 em_dev_clear_queues(dev);
 489                 return ret;
 490         }
 491
 492         e1000_clear_hw_cntrs_base_generic(hw);
 493
 494         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 495                         ETH_VLAN_EXTEND_MASK;
 496         eth_em_vlan_offload_set(dev, mask);
 497
 498         /* Set Interrupt Throttling Rate to maximum allowed value. */
 499         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 500
 501         /* Setup link speed and duplex */
 502         switch (dev->data->dev_conf.link_speed) {
 503         case ETH_LINK_SPEED_AUTONEG:
 504                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 505                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 506                 else if (dev->data->dev_conf.link_duplex ==
 507                                         ETH_LINK_HALF_DUPLEX)
 508                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 509                 else if (dev->data->dev_conf.link_duplex ==
 510                                         ETH_LINK_FULL_DUPLEX)
 511                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 512                 else
 513                         goto error_invalid_config;
 514                 break;
 515         case ETH_LINK_SPEED_10:
 516                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 517                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 518                 else if (dev->data->dev_conf.link_duplex ==
 519                                         ETH_LINK_HALF_DUPLEX)
 520                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 521                 else if (dev->data->dev_conf.link_duplex ==
 522                                         ETH_LINK_FULL_DUPLEX)
 523                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 524                 else
 525                         goto error_invalid_config;
 526                 break;
 527         case ETH_LINK_SPEED_100:
 528                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 529                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 530                 else if (dev->data->dev_conf.link_duplex ==
 531                                         ETH_LINK_HALF_DUPLEX)
 532                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 533                 else if (dev->data->dev_conf.link_duplex ==
 534                                         ETH_LINK_FULL_DUPLEX)
 535                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 536                 else
 537                         goto error_invalid_config;
 538                 break;
 539         case ETH_LINK_SPEED_1000:
 540                 if ((dev->data->dev_conf.link_duplex ==
 541                                 ETH_LINK_AUTONEG_DUPLEX) ||
 542                         (dev->data->dev_conf.link_duplex ==
 543                                         ETH_LINK_FULL_DUPLEX))
 544                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 545                 else
 546                         goto error_invalid_config;
 547                 break;
 548         case ETH_LINK_SPEED_10000:
 549         default:
 550                 goto error_invalid_config;
 551         }
 552         e1000_setup_link(hw);
 553
 554         /* check if lsc interrupt feature is enabled */
 555         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 556                 ret = eth_em_interrupt_setup(dev);
 557                 if (ret) {
 558                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 559                         em_dev_clear_queues(dev);
 560                         return ret;
 561                 }
 562         }
 563
 564         PMD_INIT_LOG(DEBUG, "<<");
 565
 566         return (0);
 567
 568 error_invalid_config:
 569         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
 570                                 "%u\n", dev->data->dev_conf.link_speed,
 571                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 572         em_dev_clear_queues(dev);
 573         return (-EINVAL);
 574 }
 575
 576 /*********************************************************************
 577  *
 578  *  This routine disables all traffic on the adapter by issuing a
 579  *  global reset on the MAC.
 580  *
 581  **********************************************************************/
 582 static void
 583 eth_em_stop(struct rte_eth_dev *dev)
 584 {
 585         struct rte_eth_link link;
 586         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 587
 588         em_intr_disable(hw);
 589         e1000_reset_hw(hw);
 590         if (hw->mac.type >= e1000_82544)
 591                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 592
 593         /* Power down the phy. Needed to make the link go down */
 594         e1000_power_down_phy(hw);
 595
 596         em_dev_clear_queues(dev);
 597
 598         /* clear the recorded link status */
 599         memset(&link, 0, sizeof(link));
 600         rte_em_dev_atomic_write_link_status(dev, &link);
 601 }
 602
 603 static void
 604 eth_em_close(struct rte_eth_dev *dev)
 605 {
 606         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 607
 608         eth_em_stop(dev);
 609         e1000_phy_hw_reset(hw);
 610         em_release_manageability(hw);
 611         em_hw_control_release(hw);
 612 }
 613
 614 static int
 615 em_get_rx_buffer_size(struct e1000_hw *hw)
 616 {
 617         uint32_t rx_buf_size;
 618
 619         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 620         return rx_buf_size;
 621 }
 622
 623 /*********************************************************************
 624  *
 625  *  Initialize the hardware
 626  *
 627  **********************************************************************/
 628 static int
 629 em_hardware_init(struct e1000_hw *hw)
 630 {
 631         uint32_t rx_buf_size;
 632         int diag;
 633
 634         /* Issue a global reset */
 635         e1000_reset_hw(hw);
 636
 637         /* Let the firmware know the OS is in control */
 638         em_hw_control_acquire(hw);
 639
 640         /*
 641          * These parameters control the automatic generation (Tx) and
 642          * response (Rx) to Ethernet PAUSE frames.
 643          * - High water mark should allow for at least two standard size (1518)
 644          *   frames to be received after sending an XOFF.
 645          * - Low water mark works best when it is very near the high water mark.
 646          *   This allows the receiver to restart by sending XON when it has
 647          *   drained a bit. Here we use an arbitary value of 1500 which will
 648          *   restart after one full frame is pulled from the buffer. There
 649          *   could be several smaller frames in the buffer and if so they will
 650          *   not trigger the XON until their total number reduces the buffer
 651          *   by 1500.
 652          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 653          */
 654         rx_buf_size = em_get_rx_buffer_size(hw);
 655
 656         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 657         hw->fc.low_water = hw->fc.high_water - 1500;
 658
 659         if (hw->mac.type == e1000_80003es2lan)
 660                 hw->fc.pause_time = UINT16_MAX;
 661         else
 662                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 663
 664         hw->fc.send_xon = 1;
 665
 666         /* Set Flow control, use the tunable location if sane */
 667         if (em_fc_setting <= e1000_fc_full)
 668                 hw->fc.requested_mode = em_fc_setting;
 669         else
 670                 hw->fc.requested_mode = e1000_fc_none;
 671
 672         /* Workaround: no TX flow ctrl for PCH */
 673         if (hw->mac.type == e1000_pchlan)
 674                 hw->fc.requested_mode = e1000_fc_rx_pause;
 675
 676         /* Override - settings for PCH2LAN, ya its magic :) */
 677         if (hw->mac.type == e1000_pch2lan) {
 678                 hw->fc.high_water = 0x5C20;
 679                 hw->fc.low_water = 0x5048;
 680                 hw->fc.pause_time = 0x0650;
 681                 hw->fc.refresh_time = 0x0400;
 682         }
 683
 684         diag = e1000_init_hw(hw);
 685         if (diag < 0)
 686                 return (diag);
 687         e1000_check_for_link(hw);
 688         return (0);
 689 }
 690
 691 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 692 static void
 693 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 694 {
 695         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 696         struct e1000_hw_stats *stats =
 697                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 698         int pause_frames;
 699
 700         if(hw->phy.media_type == e1000_media_type_copper ||
 701                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 702                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 703                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 704         }
 705
 706         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 707         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 708         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 709         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 710
 711         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 712         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 713         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 714         stats->dc += E1000_READ_REG(hw, E1000_DC);
 715         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 716         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 717         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 718
 719         /*
 720          * For watchdog management we need to know if we have been
 721          * paused during the last interval, so capture that here.
 722          */
 723         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 724         stats->xoffrxc += pause_frames;
 725         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 726         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 727         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 728         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 729         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 730         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 731         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 732         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 733         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 734         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 735         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 736         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 737
 738         /*
 739          * For the 64-bit byte counters the low dword must be read first.
 740          * Both registers clear on the read of the high dword.
 741          */
 742
 743         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 744         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 745         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 746         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 747
 748         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 749         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 750         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 751         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 752         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 753
 754         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 755         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 756
 757         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 758         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 759         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 760         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 761         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 762         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 763         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 764         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 765         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 766         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 767
 768         /* Interrupt Counts */
 769
 770         if (hw->mac.type >= e1000_82571) {
 771                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 772                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 773                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 774                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 775                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 776                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 777                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 778                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 779                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 780         }
 781
 782         if (hw->mac.type >= e1000_82543) {
 783                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 784                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 785                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 786                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 787                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 788                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 789         }
 790
 791         if (rte_stats == NULL)
 792                 return;
 793
 794         /* Rx Errors */
 795         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 796                 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 797
 798         /* Tx Errors */
 799         rte_stats->oerrors = stats->ecol + stats->latecol;
 800
 801         rte_stats->ipackets = stats->gprc;
 802         rte_stats->opackets = stats->gptc;
 803         rte_stats->ibytes   = stats->gorc;
 804         rte_stats->obytes   = stats->gotc;
 805
 806         /* XON/XOFF pause frames stats registers */
 807         rte_stats->tx_pause_xon  = stats->xontxc;
 808         rte_stats->rx_pause_xon  = stats->xonrxc;
 809         rte_stats->tx_pause_xoff = stats->xofftxc;
 810         rte_stats->rx_pause_xoff = stats->xoffrxc;
 811 }
 812
 813 static void
 814 eth_em_stats_reset(struct rte_eth_dev *dev)
 815 {
 816         struct e1000_hw_stats *hw_stats =
 817                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 818
 819         /* HW registers are cleared on read */
 820         eth_em_stats_get(dev, NULL);
 821
 822         /* Reset software totals */
 823         memset(hw_stats, 0, sizeof(*hw_stats));
 824 }
 825
 826 static uint32_t
 827 em_get_max_pktlen(const struct e1000_hw *hw)
 828 {
 829         switch (hw->mac.type) {
 830         case e1000_82571:
 831         case e1000_82572:
 832         case e1000_ich9lan:
 833         case e1000_ich10lan:
 834         case e1000_pch2lan:
 835         case e1000_82574:
 836         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 837                 return (0x2412);
 838         case e1000_pchlan:
 839                 return (0x1000);
 840         /* Adapters that do not support jumbo frames */
 841         case e1000_82583:
 842         case e1000_ich8lan:
 843                 return (ETHER_MAX_LEN);
 844         default:
 845                 return (MAX_JUMBO_FRAME_SIZE);
 846         }
 847 }
 848
 849 static void
 850 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 851 {
 852         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 853
 854         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
 855         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
 856         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
 857
 858         /*
 859          * Starting with 631xESB hw supports 2 TX/RX queues per port.
 860          * Unfortunatelly, all these nics have just one TX context.
 861          * So we have few choises for TX:
 862          * - Use just one TX queue.
 863          * - Allow cksum offload only for one TX queue.
 864          * - Don't allow TX cksum offload at all.
 865          * For now, option #1 was chosen.
 866          * To use second RX queue we have to use extended RX descriptor
 867          * (Multiple Receive Queues are mutually exclusive with UDP
 868          * fragmentation and are not supported when a legacy receive
 869          * descriptor format is used).
 870          * Which means separate RX routinies - as legacy nics (82540, 82545)
 871          * don't support extended RXD.
 872          * To avoid it we support just one RX queue for now (no RSS).
 873          */
 874
 875         dev_info->max_rx_queues = 1;
 876         dev_info->max_tx_queues = 1;
 877 }
 878
 879 /* return 0 means link status changed, -1 means not changed */
 880 static int
 881 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 882 {
 883         struct e1000_hw *hw =
 884                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 885         struct rte_eth_link link, old;
 886         int link_check, count;
 887
 888         link_check = 0;
 889         hw->mac.get_link_status = 1;
 890
 891         /* possible wait-to-complete in up to 9 seconds */
 892         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
 893                 /* Read the real link status */
 894                 switch (hw->phy.media_type) {
 895                 case e1000_media_type_copper:
 896                         /* Do the work to read phy */
 897                         e1000_check_for_link(hw);
 898                         link_check = !hw->mac.get_link_status;
 899                         break;
 900
 901                 case e1000_media_type_fiber:
 902                         e1000_check_for_link(hw);
 903                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
 904                                         E1000_STATUS_LU);
 905                         break;
 906
 907                 case e1000_media_type_internal_serdes:
 908                         e1000_check_for_link(hw);
 909                         link_check = hw->mac.serdes_has_link;
 910                         break;
 911
 912                 default:
 913                         break;
 914                 }
 915                 if (link_check || wait_to_complete == 0)
 916                         break;
 917                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
 918         }
 919         memset(&link, 0, sizeof(link));
 920         rte_em_dev_atomic_read_link_status(dev, &link);
 921         old = link;
 922
 923         /* Now we check if a transition has happened */
 924         if (link_check && (link.link_status == 0)) {
 925                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
 926                         &link.link_duplex);
 927                 link.link_status = 1;
 928         } else if (!link_check && (link.link_status == 1)) {
 929                 link.link_speed = 0;
 930                 link.link_duplex = 0;
 931                 link.link_status = 0;
 932         }
 933         rte_em_dev_atomic_write_link_status(dev, &link);
 934
 935         /* not changed */
 936         if (old.link_status == link.link_status)
 937                 return -1;
 938
 939         /* changed */
 940         return 0;
 941 }
 942
 943 /*
 944  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
 945  * For ASF and Pass Through versions of f/w this means
 946  * that the driver is loaded. For AMT version type f/w
 947  * this means that the network i/f is open.
 948  */
 949 static void
 950 em_hw_control_acquire(struct e1000_hw *hw)
 951 {
 952         uint32_t ctrl_ext, swsm;
 953
 954         /* Let firmware know the driver has taken over */
 955         if (hw->mac.type == e1000_82573) {
 956                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 957                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
 958
 959         } else {
 960                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 961                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 962                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 963         }
 964 }
 965
 966 /*
 967  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
 968  * For ASF and Pass Through versions of f/w this means that the
 969  * driver is no longer loaded. For AMT versions of the
 970  * f/w this means that the network i/f is closed.
 971  */
 972 static void
 973 em_hw_control_release(struct e1000_hw *hw)
 974 {
 975         uint32_t ctrl_ext, swsm;
 976
 977         /* Let firmware taken over control of h/w */
 978         if (hw->mac.type == e1000_82573) {
 979                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 980                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
 981         } else {
 982                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 983                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 984                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 985         }
 986 }
 987
 988 /*
 989  * Bit of a misnomer, what this really means is
 990  * to enable OS management of the system... aka
 991  * to disable special hardware management features.
 992  */
 993 static void
 994 em_init_manageability(struct e1000_hw *hw)
 995 {
 996         if (e1000_enable_mng_pass_thru(hw)) {
 997                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
 998                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
 999
1000                 /* disable hardware interception of ARP */
1001                 manc &= ~(E1000_MANC_ARP_EN);
1002
1003                 /* enable receiving management packets to the host */
1004                 manc |= E1000_MANC_EN_MNG2HOST;
1005                 manc2h |= 1 << 5;  /* Mng Port 623 */
1006                 manc2h |= 1 << 6;  /* Mng Port 664 */
1007                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1008                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1009         }
1010 }
1011
1012 /*
1013  * Give control back to hardware management
1014  * controller if there is one.
1015  */
1016 static void
1017 em_release_manageability(struct e1000_hw *hw)
1018 {
1019         uint32_t manc;
1020
1021         if (e1000_enable_mng_pass_thru(hw)) {
1022                 manc = E1000_READ_REG(hw, E1000_MANC);
1023
1024                 /* re-enable hardware interception of ARP */
1025                 manc |= E1000_MANC_ARP_EN;
1026                 manc &= ~E1000_MANC_EN_MNG2HOST;
1027
1028                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1029         }
1030 }
1031
1032 static void
1033 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1034 {
1035         struct e1000_hw *hw =
1036                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         uint32_t rctl;
1038
1039         rctl = E1000_READ_REG(hw, E1000_RCTL);
1040         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1041         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1042 }
1043
1044 static void
1045 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1046 {
1047         struct e1000_hw *hw =
1048                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         uint32_t rctl;
1050
1051         rctl = E1000_READ_REG(hw, E1000_RCTL);
1052         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1053         if (dev->data->all_multicast == 1)
1054                 rctl |= E1000_RCTL_MPE;
1055         else
1056                 rctl &= (~E1000_RCTL_MPE);
1057         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1058 }
1059
1060 static void
1061 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1062 {
1063         struct e1000_hw *hw =
1064                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1065         uint32_t rctl;
1066
1067         rctl = E1000_READ_REG(hw, E1000_RCTL);
1068         rctl |= E1000_RCTL_MPE;
1069         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1070 }
1071
1072 static void
1073 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1074 {
1075         struct e1000_hw *hw =
1076                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1077         uint32_t rctl;
1078
1079         if (dev->data->promiscuous == 1)
1080                 return; /* must remain in all_multicast mode */
1081         rctl = E1000_READ_REG(hw, E1000_RCTL);
1082         rctl &= (~E1000_RCTL_MPE);
1083         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1084 }
1085
1086 static int
1087 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1088 {
1089         struct e1000_hw *hw =
1090                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091         struct e1000_vfta * shadow_vfta =
1092                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1093         uint32_t vfta;
1094         uint32_t vid_idx;
1095         uint32_t vid_bit;
1096
1097         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1098                               E1000_VFTA_ENTRY_MASK);
1099         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1100         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1101         if (on)
1102                 vfta |= vid_bit;
1103         else
1104                 vfta &= ~vid_bit;
1105         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1106
1107         /* update local VFTA copy */
1108         shadow_vfta->vfta[vid_idx] = vfta;
1109
1110         return 0;
1111 }
1112
1113 static void
1114 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1115 {
1116         struct e1000_hw *hw =
1117                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1118         uint32_t reg;
1119
1120         /* Filter Table Disable */
1121         reg = E1000_READ_REG(hw, E1000_RCTL);
1122         reg &= ~E1000_RCTL_CFIEN;
1123         reg &= ~E1000_RCTL_VFE;
1124         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1125 }
1126
1127 static void
1128 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1129 {
1130         struct e1000_hw *hw =
1131                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1132         struct e1000_vfta * shadow_vfta =
1133                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1134         uint32_t reg;
1135         int i;
1136
1137         /* Filter Table Enable, CFI not used for packet acceptance */
1138         reg = E1000_READ_REG(hw, E1000_RCTL);
1139         reg &= ~E1000_RCTL_CFIEN;
1140         reg |= E1000_RCTL_VFE;
1141         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1142
1143         /* restore vfta from local copy */
1144         for (i = 0; i < IGB_VFTA_SIZE; i++)
1145                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1146 }
1147
1148 static void
1149 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1150 {
1151         struct e1000_hw *hw =
1152                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153         uint32_t reg;
1154
1155         /* VLAN Mode Disable */
1156         reg = E1000_READ_REG(hw, E1000_CTRL);
1157         reg &= ~E1000_CTRL_VME;
1158         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1159
1160 }
1161
1162 static void
1163 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1164 {
1165         struct e1000_hw *hw =
1166                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167         uint32_t reg;
1168
1169         /* VLAN Mode Enable */
1170         reg = E1000_READ_REG(hw, E1000_CTRL);
1171         reg |= E1000_CTRL_VME;
1172         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1173 }
1174
1175 static void
1176 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1177 {
1178         if(mask & ETH_VLAN_STRIP_MASK){
1179                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1180                         em_vlan_hw_strip_enable(dev);
1181                 else
1182                         em_vlan_hw_strip_disable(dev);
1183         }
1184
1185         if(mask & ETH_VLAN_FILTER_MASK){
1186                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1187                         em_vlan_hw_filter_enable(dev);
1188                 else
1189                         em_vlan_hw_filter_disable(dev);
1190         }
1191 }
1192
1193 static void
1194 em_intr_disable(struct e1000_hw *hw)
1195 {
1196         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1197 }
1198
1199 /**
1200  * It enables the interrupt mask and then enable the interrupt.
1201  *
1202  * @param dev
1203  *  Pointer to struct rte_eth_dev.
1204  *
1205  * @return
1206  *  - On success, zero.
1207  *  - On failure, a negative value.
1208  */
1209 static int
1210 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1211 {
1212         struct e1000_hw *hw =
1213                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214
1215         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1216         rte_intr_enable(&(dev->pci_dev->intr_handle));
1217         return (0);
1218 }
1219
1220 /*
1221  * It reads ICR and gets interrupt causes, check it and set a bit flag
1222  * to update link status.
1223  *
1224  * @param dev
1225  *  Pointer to struct rte_eth_dev.
1226  *
1227  * @return
1228  *  - On success, zero.
1229  *  - On failure, a negative value.
1230  */
1231 static int
1232 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1233 {
1234         uint32_t icr;
1235         struct e1000_hw *hw =
1236                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237         struct e1000_interrupt *intr =
1238                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1239
1240         /* read-on-clear nic registers here */
1241         icr = E1000_READ_REG(hw, E1000_ICR);
1242         if (icr & E1000_ICR_LSC) {
1243                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1244         }
1245
1246         return 0;
1247 }
1248
1249 /*
1250  * It executes link_update after knowing an interrupt is prsent.
1251  *
1252  * @param dev
1253  *  Pointer to struct rte_eth_dev.
1254  *
1255  * @return
1256  *  - On success, zero.
1257  *  - On failure, a negative value.
1258  */
1259 static int
1260 eth_em_interrupt_action(struct rte_eth_dev *dev)
1261 {
1262         struct e1000_hw *hw =
1263                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264         struct e1000_interrupt *intr =
1265                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1266         uint32_t tctl, rctl;
1267         struct rte_eth_link link;
1268         int ret;
1269
1270         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1271                 return -1;
1272
1273         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1274         rte_intr_enable(&(dev->pci_dev->intr_handle));
1275
1276         /* set get_link_status to check register later */
1277         hw->mac.get_link_status = 1;
1278         ret = eth_em_link_update(dev, 0);
1279
1280         /* check if link has changed */
1281         if (ret < 0)
1282                 return 0;
1283
1284         memset(&link, 0, sizeof(link));
1285         rte_em_dev_atomic_read_link_status(dev, &link);
1286         if (link.link_status) {
1287                 PMD_INIT_LOG(INFO,
1288                         " Port %d: Link Up - speed %u Mbps - %s\n",
1289                         dev->data->port_id, (unsigned)link.link_speed,
1290                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1291                                 "full-duplex" : "half-duplex");
1292         } else {
1293                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1294                                         dev->data->port_id);
1295         }
1296         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1297                                 dev->pci_dev->addr.domain,
1298                                 dev->pci_dev->addr.bus,
1299                                 dev->pci_dev->addr.devid,
1300                                 dev->pci_dev->addr.function);
1301         tctl = E1000_READ_REG(hw, E1000_TCTL);
1302         rctl = E1000_READ_REG(hw, E1000_RCTL);
1303         if (link.link_status) {
1304                 /* enable Tx/Rx */
1305                 tctl |= E1000_TCTL_EN;
1306                 rctl |= E1000_RCTL_EN;
1307         } else {
1308                 /* disable Tx/Rx */
1309                 tctl &= ~E1000_TCTL_EN;
1310                 rctl &= ~E1000_RCTL_EN;
1311         }
1312         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1313         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1314         E1000_WRITE_FLUSH(hw);
1315
1316         return 0;
1317 }
1318
1319 /**
1320  * Interrupt handler which shall be registered at first.
1321  *
1322  * @param handle
1323  *  Pointer to interrupt handle.
1324  * @param param
1325  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1326  *
1327  * @return
1328  *  void
1329  */
1330 static void
1331 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1332                                                         void *param)
1333 {
1334         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1335
1336         eth_em_interrupt_get_status(dev);
1337         eth_em_interrupt_action(dev);
1338         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1339 }
1340
1341 static int
1342 eth_em_led_on(struct rte_eth_dev *dev)
1343 {
1344         struct e1000_hw *hw;
1345
1346         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1348 }
1349
1350 static int
1351 eth_em_led_off(struct rte_eth_dev *dev)
1352 {
1353         struct e1000_hw *hw;
1354
1355         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1356         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1357 }
1358
1359 static int
1360 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1361 {
1362         struct e1000_hw *hw;
1363         int err;
1364         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1365                 e1000_fc_none,
1366                 e1000_fc_rx_pause,
1367                 e1000_fc_tx_pause,
1368                 e1000_fc_full
1369         };
1370         uint32_t rx_buf_size;
1371         uint32_t max_high_water;
1372         uint32_t rctl;
1373
1374         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375         rx_buf_size = em_get_rx_buffer_size(hw);
1376         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1377
1378         /* At least reserve one Ethernet frame for watermark */
1379         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1380         if ((fc_conf->high_water > max_high_water) ||
1381                 (fc_conf->high_water < fc_conf->low_water)) {
1382                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1383                 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1384                 return (-EINVAL);
1385         }
1386
1387         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1388         hw->fc.pause_time     = fc_conf->pause_time;
1389         hw->fc.high_water     = fc_conf->high_water;
1390         hw->fc.low_water      = fc_conf->low_water;
1391         hw->fc.send_xon       = fc_conf->send_xon;
1392
1393         err = e1000_setup_link_generic(hw);
1394         if (err == E1000_SUCCESS) {
1395
1396                 /* check if we want to forward MAC frames - driver doesn't have native
1397                  * capability to do that, so we'll write the registers ourselves */
1398
1399                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1400
1401                 /* set or clear MFLCN.PMCF bit depending on configuration */
1402                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1403                         rctl |= E1000_RCTL_PMCF;
1404                 else
1405                         rctl &= ~E1000_RCTL_PMCF;
1406
1407                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1408                 E1000_WRITE_FLUSH(hw);
1409
1410                 return 0;
1411         }
1412
1413         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1414         return (-EIO);
1415 }
1416
1417 static void
1418 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1419                 uint32_t index, __rte_unused uint32_t pool)
1420 {
1421         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422
1423         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1424 }
1425
1426 static void
1427 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1428 {
1429         uint8_t addr[ETHER_ADDR_LEN];
1430         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431
1432         memset(addr, 0, sizeof(addr));
1433
1434         e1000_rar_set(hw, addr, index);
1435 }