4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
60 static int eth_igb_configure(struct rte_eth_dev *dev);
61 static int eth_igb_start(struct rte_eth_dev *dev);
62 static void eth_igb_stop(struct rte_eth_dev *dev);
63 static void eth_igb_close(struct rte_eth_dev *dev);
64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
68 static int eth_igb_link_update(struct rte_eth_dev *dev,
69 int wait_to_complete);
70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
71 struct rte_eth_stats *rte_stats);
72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
74 struct rte_eth_dev_info *dev_info);
75 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
76 struct rte_eth_fc_conf *fc_conf);
77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
82 static int igb_hardware_init(struct e1000_hw *hw);
83 static void igb_hw_control_acquire(struct e1000_hw *hw);
84 static void igb_hw_control_release(struct e1000_hw *hw);
85 static void igb_init_manageability(struct e1000_hw *hw);
86 static void igb_release_manageability(struct e1000_hw *hw);
88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
89 uint16_t vlan_id, int on);
90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
100 static int eth_igb_led_on(struct rte_eth_dev *dev);
101 static int eth_igb_led_off(struct rte_eth_dev *dev);
103 static void igb_intr_disable(struct e1000_hw *hw);
104 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
106 struct ether_addr *mac_addr,
107 uint32_t index, uint32_t pool);
108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
110 static void igbvf_intr_disable(struct e1000_hw *hw);
111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
112 static int igbvf_dev_start(struct rte_eth_dev *dev);
113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
114 static void igbvf_dev_close(struct rte_eth_dev *dev);
115 static int eth_igbvf_link_update(struct e1000_hw *hw);
116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
119 uint16_t vlan_id, int on);
120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
122 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
123 struct rte_eth_rss_reta *reta_conf);
124 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
125 struct rte_eth_rss_reta *reta_conf);
128 * Define VF Stats MACRO for Non "cleared on read" register
130 #define UPDATE_VF_STAT(reg, last, cur) \
132 u32 latest = E1000_READ_REG(hw, reg); \
133 cur += latest - last; \
138 #define IGB_FC_PAUSE_TIME 0x0680
139 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
140 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
142 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
144 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
147 * The set of PCI devices this driver supports
149 static struct rte_pci_id pci_id_igb_map[] = {
151 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
152 #include "rte_pci_dev_ids.h"
158 * The set of PCI devices this driver supports (for 82576&I350 VF)
160 static struct rte_pci_id pci_id_igbvf_map[] = {
162 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
163 #include "rte_pci_dev_ids.h"
168 static struct eth_dev_ops eth_igb_ops = {
169 .dev_configure = eth_igb_configure,
170 .dev_start = eth_igb_start,
171 .dev_stop = eth_igb_stop,
172 .dev_close = eth_igb_close,
173 .promiscuous_enable = eth_igb_promiscuous_enable,
174 .promiscuous_disable = eth_igb_promiscuous_disable,
175 .allmulticast_enable = eth_igb_allmulticast_enable,
176 .allmulticast_disable = eth_igb_allmulticast_disable,
177 .link_update = eth_igb_link_update,
178 .stats_get = eth_igb_stats_get,
179 .stats_reset = eth_igb_stats_reset,
180 .dev_infos_get = eth_igb_infos_get,
181 .vlan_filter_set = eth_igb_vlan_filter_set,
182 .vlan_tpid_set = eth_igb_vlan_tpid_set,
183 .vlan_offload_set = eth_igb_vlan_offload_set,
184 .rx_queue_setup = eth_igb_rx_queue_setup,
185 .rx_queue_release = eth_igb_rx_queue_release,
186 .rx_queue_count = eth_igb_rx_queue_count,
187 .rx_descriptor_done = eth_igb_rx_descriptor_done,
188 .tx_queue_setup = eth_igb_tx_queue_setup,
189 .tx_queue_release = eth_igb_tx_queue_release,
190 .dev_led_on = eth_igb_led_on,
191 .dev_led_off = eth_igb_led_off,
192 .flow_ctrl_set = eth_igb_flow_ctrl_set,
193 .mac_addr_add = eth_igb_rar_set,
194 .mac_addr_remove = eth_igb_rar_clear,
195 .reta_update = eth_igb_rss_reta_update,
196 .reta_query = eth_igb_rss_reta_query,
200 * dev_ops for virtual function, bare necessities for basic vf
201 * operation have been implemented
203 static struct eth_dev_ops igbvf_eth_dev_ops = {
204 .dev_configure = igbvf_dev_configure,
205 .dev_start = igbvf_dev_start,
206 .dev_stop = igbvf_dev_stop,
207 .dev_close = igbvf_dev_close,
208 .link_update = eth_igb_link_update,
209 .stats_get = eth_igbvf_stats_get,
210 .stats_reset = eth_igbvf_stats_reset,
211 .vlan_filter_set = igbvf_vlan_filter_set,
212 .dev_infos_get = eth_igb_infos_get,
213 .rx_queue_setup = eth_igb_rx_queue_setup,
214 .rx_queue_release = eth_igb_rx_queue_release,
215 .tx_queue_setup = eth_igb_tx_queue_setup,
216 .tx_queue_release = eth_igb_tx_queue_release,
220 * Atomically reads the link status information from global
221 * structure rte_eth_dev.
224 * - Pointer to the structure rte_eth_dev to read from.
225 * - Pointer to the buffer to be saved with the link status.
228 * - On success, zero.
229 * - On failure, negative value.
232 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
233 struct rte_eth_link *link)
235 struct rte_eth_link *dst = link;
236 struct rte_eth_link *src = &(dev->data->dev_link);
238 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
239 *(uint64_t *)src) == 0)
246 * Atomically writes the link status information into global
247 * structure rte_eth_dev.
250 * - Pointer to the structure rte_eth_dev to read from.
251 * - Pointer to the buffer to be saved with the link status.
254 * - On success, zero.
255 * - On failure, negative value.
258 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
259 struct rte_eth_link *link)
261 struct rte_eth_link *dst = &(dev->data->dev_link);
262 struct rte_eth_link *src = link;
264 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
265 *(uint64_t *)src) == 0)
272 igb_intr_enable(struct rte_eth_dev *dev)
274 struct e1000_interrupt *intr =
275 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
276 struct e1000_hw *hw =
277 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
279 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
280 E1000_WRITE_FLUSH(hw);
284 igb_intr_disable(struct e1000_hw *hw)
286 E1000_WRITE_REG(hw, E1000_IMC, ~0);
287 E1000_WRITE_FLUSH(hw);
290 static inline int32_t
291 igb_pf_reset_hw(struct e1000_hw *hw)
296 status = e1000_reset_hw(hw);
298 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
299 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
300 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
301 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
302 E1000_WRITE_FLUSH(hw);
308 igb_identify_hardware(struct rte_eth_dev *dev)
310 struct e1000_hw *hw =
311 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
313 hw->vendor_id = dev->pci_dev->id.vendor_id;
314 hw->device_id = dev->pci_dev->id.device_id;
315 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
316 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
318 e1000_set_mac_type(hw);
320 /* need to check if it is a vf device below */
324 igb_reset_swfw_lock(struct e1000_hw *hw)
329 * Do mac ops initialization manually here, since we will need
330 * some function pointers set by this call.
332 ret_val = e1000_init_mac_params(hw);
337 * SMBI lock should not fail in this early stage. If this is the case,
338 * it is due to an improper exit of the application.
339 * So force the release of the faulty lock.
341 if (e1000_get_hw_semaphore_generic(hw) < 0) {
342 DEBUGOUT("SMBI lock released");
344 e1000_put_hw_semaphore_generic(hw);
346 if (hw->mac.ops.acquire_swfw_sync != NULL) {
350 * Phy lock should not fail in this early stage. If this is the case,
351 * it is due to an improper exit of the application.
352 * So force the release of the faulty lock.
354 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
355 if (hw->bus.func > E1000_FUNC_1)
357 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
358 DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
360 hw->mac.ops.release_swfw_sync(hw, mask);
363 * This one is more tricky since it is common to all ports; but
364 * swfw_sync retries last long enough (1s) to be almost sure that if
365 * lock can not be taken it is due to an improper lock of the
368 mask = E1000_SWFW_EEP_SM;
369 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
370 DEBUGOUT("SWFW common locks released");
372 hw->mac.ops.release_swfw_sync(hw, mask);
375 return E1000_SUCCESS;
379 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
380 struct rte_eth_dev *eth_dev)
383 struct rte_pci_device *pci_dev;
384 struct e1000_hw *hw =
385 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
386 struct e1000_vfta * shadow_vfta =
387 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
390 pci_dev = eth_dev->pci_dev;
391 eth_dev->dev_ops = ð_igb_ops;
392 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
393 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
395 /* for secondary processes, we don't initialise any further as primary
396 * has already done this work. Only check we don't need a different
398 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
399 if (eth_dev->data->scattered_rx)
400 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
404 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
406 igb_identify_hardware(eth_dev);
407 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
412 e1000_get_bus_info(hw);
414 /* Reset any pending lock */
415 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
420 /* Finish initialization */
421 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
427 hw->phy.autoneg_wait_to_complete = 0;
428 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
431 if (hw->phy.media_type == e1000_media_type_copper) {
432 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
433 hw->phy.disable_polarity_correction = 0;
434 hw->phy.ms_type = e1000_ms_hw_default;
438 * Start from a known state, this is important in reading the nvm
443 /* Make sure we have a good EEPROM before we read from it */
444 if (e1000_validate_nvm_checksum(hw) < 0) {
446 * Some PCI-E parts fail the first check due to
447 * the link being in sleep state, call it again,
448 * if it fails a second time its a real issue.
450 if (e1000_validate_nvm_checksum(hw) < 0) {
451 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
457 /* Read the permanent MAC address out of the EEPROM */
458 if (e1000_read_mac_addr(hw) != 0) {
459 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
464 /* Allocate memory for storing MAC addresses */
465 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
466 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
467 if (eth_dev->data->mac_addrs == NULL) {
468 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
469 "store MAC addresses",
470 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
475 /* Copy the permanent MAC address */
476 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
478 /* initialize the vfta */
479 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
481 /* Now initialize the hardware */
482 if (igb_hardware_init(hw) != 0) {
483 PMD_INIT_LOG(ERR, "Hardware initialization failed");
484 rte_free(eth_dev->data->mac_addrs);
485 eth_dev->data->mac_addrs = NULL;
489 hw->mac.get_link_status = 1;
491 /* Indicate SOL/IDER usage */
492 if (e1000_check_reset_block(hw) < 0) {
493 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
497 /* initialize PF if max_vfs not zero */
498 igb_pf_host_init(eth_dev);
500 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
501 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
502 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
503 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
504 E1000_WRITE_FLUSH(hw);
506 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
507 eth_dev->data->port_id, pci_dev->id.vendor_id,
508 pci_dev->id.device_id);
510 rte_intr_callback_register(&(pci_dev->intr_handle),
511 eth_igb_interrupt_handler, (void *)eth_dev);
513 /* enable uio intr after callback register */
514 rte_intr_enable(&(pci_dev->intr_handle));
516 /* enable support intr */
517 igb_intr_enable(eth_dev);
522 igb_hw_control_release(hw);
528 * Virtual Function device init
531 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
532 struct rte_eth_dev *eth_dev)
534 struct rte_pci_device *pci_dev;
535 struct e1000_hw *hw =
536 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
539 PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
541 eth_dev->dev_ops = &igbvf_eth_dev_ops;
542 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
543 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
545 /* for secondary processes, we don't initialise any further as primary
546 * has already done this work. Only check we don't need a different
548 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
549 if (eth_dev->data->scattered_rx)
550 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
554 pci_dev = eth_dev->pci_dev;
556 hw->device_id = pci_dev->id.device_id;
557 hw->vendor_id = pci_dev->id.vendor_id;
558 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
560 /* Initialize the shared code */
561 diag = e1000_setup_init_funcs(hw, TRUE);
563 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
568 /* init_mailbox_params */
569 hw->mbx.ops.init_params(hw);
571 /* Disable the interrupts for VF */
572 igbvf_intr_disable(hw);
574 diag = hw->mac.ops.reset_hw(hw);
576 /* Allocate memory for storing MAC addresses */
577 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
578 hw->mac.rar_entry_count, 0);
579 if (eth_dev->data->mac_addrs == NULL) {
581 "Failed to allocate %d bytes needed to store MAC "
583 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
587 /* Copy the permanent MAC address */
588 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
589 ð_dev->data->mac_addrs[0]);
591 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
593 eth_dev->data->port_id, pci_dev->id.vendor_id,
594 pci_dev->id.device_id,
600 static struct eth_driver rte_igb_pmd = {
602 .name = "rte_igb_pmd",
603 .id_table = pci_id_igb_map,
604 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
606 .eth_dev_init = eth_igb_dev_init,
607 .dev_private_size = sizeof(struct e1000_adapter),
611 * virtual function driver struct
613 static struct eth_driver rte_igbvf_pmd = {
615 .name = "rte_igbvf_pmd",
616 .id_table = pci_id_igbvf_map,
617 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
619 .eth_dev_init = eth_igbvf_dev_init,
620 .dev_private_size = sizeof(struct e1000_adapter),
624 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
626 rte_eth_driver_register(&rte_igb_pmd);
631 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
633 struct e1000_hw *hw =
634 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
635 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
636 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
637 rctl |= E1000_RCTL_VFE;
638 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
642 * VF Driver initialization routine.
643 * Invoked one at EAL init time.
644 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
647 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
649 DEBUGFUNC("rte_igbvf_pmd_init");
651 rte_eth_driver_register(&rte_igbvf_pmd);
656 eth_igb_configure(struct rte_eth_dev *dev)
658 struct e1000_interrupt *intr =
659 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
661 PMD_INIT_LOG(DEBUG, ">>");
663 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
665 PMD_INIT_LOG(DEBUG, "<<");
671 eth_igb_start(struct rte_eth_dev *dev)
673 struct e1000_hw *hw =
674 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
678 PMD_INIT_LOG(DEBUG, ">>");
680 /* Power up the phy. Needed to make the link go Up */
681 e1000_power_up_phy(hw);
684 * Packet Buffer Allocation (PBA)
685 * Writing PBA sets the receive portion of the buffer
686 * the remainder is used for the transmit buffer.
688 if (hw->mac.type == e1000_82575) {
691 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
692 E1000_WRITE_REG(hw, E1000_PBA, pba);
695 /* Put the address into the Receive Address Array */
696 e1000_rar_set(hw, hw->mac.addr, 0);
698 /* Initialize the hardware */
699 if (igb_hardware_init(hw)) {
700 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
704 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
706 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
707 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
708 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
709 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
710 E1000_WRITE_FLUSH(hw);
712 /* configure PF module if SRIOV enabled */
713 igb_pf_host_configure(dev);
715 /* Configure for OS presence */
716 igb_init_manageability(hw);
718 eth_igb_tx_init(dev);
720 /* This can fail when allocating mbufs for descriptor rings */
721 ret = eth_igb_rx_init(dev);
723 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
724 igb_dev_clear_queues(dev);
728 e1000_clear_hw_cntrs_base_generic(hw);
731 * VLAN Offload Settings
733 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
734 ETH_VLAN_EXTEND_MASK;
735 eth_igb_vlan_offload_set(dev, mask);
737 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
738 /* Enable VLAN filter since VMDq always use VLAN filter */
739 igb_vmdq_vlan_hw_filter_enable(dev);
743 * Configure the Interrupt Moderation register (EITR) with the maximum
744 * possible value (0xFFFF) to minimize "System Partial Write" issued by
745 * spurious [DMA] memory updates of RX and TX ring descriptors.
747 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
748 * spurious memory updates per second should be expected.
749 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
751 * Because interrupts are not used at all, the MSI-X is not activated
752 * and interrupt moderation is controlled by EITR[0].
754 * Note that having [almost] disabled memory updates of RX and TX ring
755 * descriptors through the Interrupt Moderation mechanism, memory
756 * updates of ring descriptors are now moderated by the configurable
757 * value of Write-Back Threshold registers.
759 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
760 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
763 /* Enable all RX & TX queues in the IVAR registers */
764 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
765 for (i = 0; i < 8; i++)
766 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
768 /* Configure EITR with the maximum possible value (0xFFFF) */
769 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
772 /* Setup link speed and duplex */
773 switch (dev->data->dev_conf.link_speed) {
774 case ETH_LINK_SPEED_AUTONEG:
775 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
776 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
777 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
778 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
779 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
780 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
782 goto error_invalid_config;
784 case ETH_LINK_SPEED_10:
785 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
786 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
787 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
788 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
789 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
790 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
792 goto error_invalid_config;
794 case ETH_LINK_SPEED_100:
795 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
796 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
797 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
798 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
799 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
800 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
802 goto error_invalid_config;
804 case ETH_LINK_SPEED_1000:
805 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
806 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
807 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
809 goto error_invalid_config;
811 case ETH_LINK_SPEED_10000:
813 goto error_invalid_config;
815 e1000_setup_link(hw);
817 /* check if lsc interrupt feature is enabled */
818 if (dev->data->dev_conf.intr_conf.lsc != 0)
819 ret = eth_igb_lsc_interrupt_setup(dev);
821 /* resume enabled intr since hw reset */
822 igb_intr_enable(dev);
824 PMD_INIT_LOG(DEBUG, "<<");
828 error_invalid_config:
829 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
830 dev->data->dev_conf.link_speed,
831 dev->data->dev_conf.link_duplex, dev->data->port_id);
832 igb_dev_clear_queues(dev);
836 /*********************************************************************
838 * This routine disables all traffic on the adapter by issuing a
839 * global reset on the MAC.
841 **********************************************************************/
843 eth_igb_stop(struct rte_eth_dev *dev)
845 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
846 struct rte_eth_link link;
848 igb_intr_disable(hw);
850 E1000_WRITE_REG(hw, E1000_WUC, 0);
852 /* Set bit for Go Link disconnect */
853 if (hw->mac.type >= e1000_82580) {
856 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
857 phpm_reg |= E1000_82580_PM_GO_LINKD;
858 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
861 /* Power down the phy. Needed to make the link go Down */
862 e1000_power_down_phy(hw);
864 igb_dev_clear_queues(dev);
866 /* clear the recorded link status */
867 memset(&link, 0, sizeof(link));
868 rte_igb_dev_atomic_write_link_status(dev, &link);
872 eth_igb_close(struct rte_eth_dev *dev)
874 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875 struct rte_eth_link link;
878 e1000_phy_hw_reset(hw);
879 igb_release_manageability(hw);
880 igb_hw_control_release(hw);
882 /* Clear bit for Go Link disconnect */
883 if (hw->mac.type >= e1000_82580) {
886 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
887 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
888 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
891 igb_dev_clear_queues(dev);
893 memset(&link, 0, sizeof(link));
894 rte_igb_dev_atomic_write_link_status(dev, &link);
898 igb_get_rx_buffer_size(struct e1000_hw *hw)
900 uint32_t rx_buf_size;
901 if (hw->mac.type == e1000_82576) {
902 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
903 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
904 /* PBS needs to be translated according to a lookup table */
905 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
906 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
907 rx_buf_size = (rx_buf_size << 10);
908 } else if (hw->mac.type == e1000_i210) {
909 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
911 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
917 /*********************************************************************
919 * Initialize the hardware
921 **********************************************************************/
923 igb_hardware_init(struct e1000_hw *hw)
925 uint32_t rx_buf_size;
928 /* Let the firmware know the OS is in control */
929 igb_hw_control_acquire(hw);
932 * These parameters control the automatic generation (Tx) and
933 * response (Rx) to Ethernet PAUSE frames.
934 * - High water mark should allow for at least two standard size (1518)
935 * frames to be received after sending an XOFF.
936 * - Low water mark works best when it is very near the high water mark.
937 * This allows the receiver to restart by sending XON when it has
938 * drained a bit. Here we use an arbitrary value of 1500 which will
939 * restart after one full frame is pulled from the buffer. There
940 * could be several smaller frames in the buffer and if so they will
941 * not trigger the XON until their total number reduces the buffer
943 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
945 rx_buf_size = igb_get_rx_buffer_size(hw);
947 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
948 hw->fc.low_water = hw->fc.high_water - 1500;
949 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
952 /* Set Flow control, use the tunable location if sane */
953 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
954 hw->fc.requested_mode = igb_fc_setting;
956 hw->fc.requested_mode = e1000_fc_none;
958 /* Issue a global reset */
960 E1000_WRITE_REG(hw, E1000_WUC, 0);
962 diag = e1000_init_hw(hw);
966 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
967 e1000_get_phy_info(hw);
968 e1000_check_for_link(hw);
973 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
975 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
977 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
978 struct e1000_hw_stats *stats =
979 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
982 if(hw->phy.media_type == e1000_media_type_copper ||
983 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
985 E1000_READ_REG(hw,E1000_SYMERRS);
986 stats->sec += E1000_READ_REG(hw, E1000_SEC);
989 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
990 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
991 stats->scc += E1000_READ_REG(hw, E1000_SCC);
992 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
994 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
995 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
996 stats->colc += E1000_READ_REG(hw, E1000_COLC);
997 stats->dc += E1000_READ_REG(hw, E1000_DC);
998 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
999 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1000 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1002 ** For watchdog management we need to know if we have been
1003 ** paused during the last interval, so capture that here.
1005 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1006 stats->xoffrxc += pause_frames;
1007 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1008 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1009 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1010 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1011 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1012 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1013 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1014 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1015 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1016 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1017 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1018 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1020 /* For the 64-bit byte counters the low dword must be read first. */
1021 /* Both registers clear on the read of the high dword */
1023 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1024 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1025 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1026 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1028 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1029 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1030 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1031 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1032 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1034 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1035 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1037 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1038 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1039 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1040 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1041 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1042 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1043 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1044 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1045 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1046 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1048 /* Interrupt Counts */
1050 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1051 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1052 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1053 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1054 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1055 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1056 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1057 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1058 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1060 /* Host to Card Statistics */
1062 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1063 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1064 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1065 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1066 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1067 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1068 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1069 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1070 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1071 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1072 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1073 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1074 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1075 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1077 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1078 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1079 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1080 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1081 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1082 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1084 if (rte_stats == NULL)
1088 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
1089 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
1092 rte_stats->oerrors = stats->ecol + stats->latecol;
1094 /* XON/XOFF pause frames */
1095 rte_stats->tx_pause_xon = stats->xontxc;
1096 rte_stats->rx_pause_xon = stats->xonrxc;
1097 rte_stats->tx_pause_xoff = stats->xofftxc;
1098 rte_stats->rx_pause_xoff = stats->xoffrxc;
1100 rte_stats->ipackets = stats->gprc;
1101 rte_stats->opackets = stats->gptc;
1102 rte_stats->ibytes = stats->gorc;
1103 rte_stats->obytes = stats->gotc;
1107 eth_igb_stats_reset(struct rte_eth_dev *dev)
1109 struct e1000_hw_stats *hw_stats =
1110 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1112 /* HW registers are cleared on read */
1113 eth_igb_stats_get(dev, NULL);
1115 /* Reset software totals */
1116 memset(hw_stats, 0, sizeof(*hw_stats));
1120 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1122 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1123 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1124 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1126 /* Good Rx packets, include VF loopback */
1127 UPDATE_VF_STAT(E1000_VFGPRC,
1128 hw_stats->last_gprc, hw_stats->gprc);
1130 /* Good Rx octets, include VF loopback */
1131 UPDATE_VF_STAT(E1000_VFGORC,
1132 hw_stats->last_gorc, hw_stats->gorc);
1134 /* Good Tx packets, include VF loopback */
1135 UPDATE_VF_STAT(E1000_VFGPTC,
1136 hw_stats->last_gptc, hw_stats->gptc);
1138 /* Good Tx octets, include VF loopback */
1139 UPDATE_VF_STAT(E1000_VFGOTC,
1140 hw_stats->last_gotc, hw_stats->gotc);
1142 /* Rx Multicst packets */
1143 UPDATE_VF_STAT(E1000_VFMPRC,
1144 hw_stats->last_mprc, hw_stats->mprc);
1146 /* Good Rx loopback packets */
1147 UPDATE_VF_STAT(E1000_VFGPRLBC,
1148 hw_stats->last_gprlbc, hw_stats->gprlbc);
1150 /* Good Rx loopback octets */
1151 UPDATE_VF_STAT(E1000_VFGORLBC,
1152 hw_stats->last_gorlbc, hw_stats->gorlbc);
1154 /* Good Tx loopback packets */
1155 UPDATE_VF_STAT(E1000_VFGPTLBC,
1156 hw_stats->last_gptlbc, hw_stats->gptlbc);
1158 /* Good Tx loopback octets */
1159 UPDATE_VF_STAT(E1000_VFGOTLBC,
1160 hw_stats->last_gotlbc, hw_stats->gotlbc);
1162 if (rte_stats == NULL)
1165 memset(rte_stats, 0, sizeof(*rte_stats));
1166 rte_stats->ipackets = hw_stats->gprc;
1167 rte_stats->ibytes = hw_stats->gorc;
1168 rte_stats->opackets = hw_stats->gptc;
1169 rte_stats->obytes = hw_stats->gotc;
1170 rte_stats->imcasts = hw_stats->mprc;
1171 rte_stats->ilbpackets = hw_stats->gprlbc;
1172 rte_stats->ilbbytes = hw_stats->gorlbc;
1173 rte_stats->olbpackets = hw_stats->gptlbc;
1174 rte_stats->olbbytes = hw_stats->gotlbc;
1179 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1181 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1182 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1184 /* Sync HW register to the last stats */
1185 eth_igbvf_stats_get(dev, NULL);
1187 /* reset HW current stats*/
1188 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1189 offsetof(struct e1000_vf_stats, gprc));
1194 eth_igb_infos_get(struct rte_eth_dev *dev,
1195 struct rte_eth_dev_info *dev_info)
1197 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1200 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1201 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1202 dev_info->rx_offload_capa =
1203 DEV_RX_OFFLOAD_VLAN_STRIP |
1204 DEV_RX_OFFLOAD_IPV4_CKSUM |
1205 DEV_RX_OFFLOAD_UDP_CKSUM |
1206 DEV_RX_OFFLOAD_TCP_CKSUM;
1207 dev_info->tx_offload_capa =
1208 DEV_TX_OFFLOAD_VLAN_INSERT |
1209 DEV_TX_OFFLOAD_IPV4_CKSUM |
1210 DEV_TX_OFFLOAD_UDP_CKSUM |
1211 DEV_TX_OFFLOAD_TCP_CKSUM |
1212 DEV_TX_OFFLOAD_SCTP_CKSUM;
1214 switch (hw->mac.type) {
1216 dev_info->max_rx_queues = 4;
1217 dev_info->max_tx_queues = 4;
1218 dev_info->max_vmdq_pools = 0;
1222 dev_info->max_rx_queues = 16;
1223 dev_info->max_tx_queues = 16;
1224 dev_info->max_vmdq_pools = ETH_8_POOLS;
1228 dev_info->max_rx_queues = 8;
1229 dev_info->max_tx_queues = 8;
1230 dev_info->max_vmdq_pools = ETH_8_POOLS;
1234 dev_info->max_rx_queues = 8;
1235 dev_info->max_tx_queues = 8;
1236 dev_info->max_vmdq_pools = ETH_8_POOLS;
1240 dev_info->max_rx_queues = 8;
1241 dev_info->max_tx_queues = 8;
1245 dev_info->max_rx_queues = 4;
1246 dev_info->max_tx_queues = 4;
1247 dev_info->max_vmdq_pools = 0;
1251 dev_info->max_rx_queues = 2;
1252 dev_info->max_tx_queues = 2;
1253 dev_info->max_vmdq_pools = 0;
1256 case e1000_vfadapt_i350:
1257 dev_info->max_rx_queues = 1;
1258 dev_info->max_tx_queues = 1;
1259 dev_info->max_vmdq_pools = 0;
1263 /* Should not happen */
1264 dev_info->max_rx_queues = 0;
1265 dev_info->max_tx_queues = 0;
1266 dev_info->max_vmdq_pools = 0;
1270 /* return 0 means link status changed, -1 means not changed */
1272 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1274 struct e1000_hw *hw =
1275 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 struct rte_eth_link link, old;
1277 int link_check, count;
1280 hw->mac.get_link_status = 1;
1282 /* possible wait-to-complete in up to 9 seconds */
1283 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1284 /* Read the real link status */
1285 switch (hw->phy.media_type) {
1286 case e1000_media_type_copper:
1287 /* Do the work to read phy */
1288 e1000_check_for_link(hw);
1289 link_check = !hw->mac.get_link_status;
1292 case e1000_media_type_fiber:
1293 e1000_check_for_link(hw);
1294 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1298 case e1000_media_type_internal_serdes:
1299 e1000_check_for_link(hw);
1300 link_check = hw->mac.serdes_has_link;
1303 /* VF device is type_unknown */
1304 case e1000_media_type_unknown:
1305 eth_igbvf_link_update(hw);
1306 link_check = !hw->mac.get_link_status;
1312 if (link_check || wait_to_complete == 0)
1314 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1316 memset(&link, 0, sizeof(link));
1317 rte_igb_dev_atomic_read_link_status(dev, &link);
1320 /* Now we check if a transition has happened */
1322 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1324 link.link_status = 1;
1325 } else if (!link_check) {
1326 link.link_speed = 0;
1327 link.link_duplex = 0;
1328 link.link_status = 0;
1330 rte_igb_dev_atomic_write_link_status(dev, &link);
1333 if (old.link_status == link.link_status)
1341 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1342 * For ASF and Pass Through versions of f/w this means
1343 * that the driver is loaded.
1346 igb_hw_control_acquire(struct e1000_hw *hw)
1350 /* Let firmware know the driver has taken over */
1351 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1352 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1356 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1357 * For ASF and Pass Through versions of f/w this means that the
1358 * driver is no longer loaded.
1361 igb_hw_control_release(struct e1000_hw *hw)
1365 /* Let firmware taken over control of h/w */
1366 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1367 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1368 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1372 * Bit of a misnomer, what this really means is
1373 * to enable OS management of the system... aka
1374 * to disable special hardware management features.
1377 igb_init_manageability(struct e1000_hw *hw)
1379 if (e1000_enable_mng_pass_thru(hw)) {
1380 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1381 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1383 /* disable hardware interception of ARP */
1384 manc &= ~(E1000_MANC_ARP_EN);
1386 /* enable receiving management packets to the host */
1387 manc |= E1000_MANC_EN_MNG2HOST;
1388 manc2h |= 1 << 5; /* Mng Port 623 */
1389 manc2h |= 1 << 6; /* Mng Port 664 */
1390 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1391 E1000_WRITE_REG(hw, E1000_MANC, manc);
1396 igb_release_manageability(struct e1000_hw *hw)
1398 if (e1000_enable_mng_pass_thru(hw)) {
1399 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1401 manc |= E1000_MANC_ARP_EN;
1402 manc &= ~E1000_MANC_EN_MNG2HOST;
1404 E1000_WRITE_REG(hw, E1000_MANC, manc);
1409 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1411 struct e1000_hw *hw =
1412 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415 rctl = E1000_READ_REG(hw, E1000_RCTL);
1416 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1417 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1421 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1423 struct e1000_hw *hw =
1424 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1427 rctl = E1000_READ_REG(hw, E1000_RCTL);
1428 rctl &= (~E1000_RCTL_UPE);
1429 if (dev->data->all_multicast == 1)
1430 rctl |= E1000_RCTL_MPE;
1432 rctl &= (~E1000_RCTL_MPE);
1433 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1437 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1439 struct e1000_hw *hw =
1440 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443 rctl = E1000_READ_REG(hw, E1000_RCTL);
1444 rctl |= E1000_RCTL_MPE;
1445 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1449 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1451 struct e1000_hw *hw =
1452 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1455 if (dev->data->promiscuous == 1)
1456 return; /* must remain in all_multicast mode */
1457 rctl = E1000_READ_REG(hw, E1000_RCTL);
1458 rctl &= (~E1000_RCTL_MPE);
1459 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1463 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1465 struct e1000_hw *hw =
1466 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467 struct e1000_vfta * shadow_vfta =
1468 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1473 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1474 E1000_VFTA_ENTRY_MASK);
1475 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1476 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1481 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1483 /* update local VFTA copy */
1484 shadow_vfta->vfta[vid_idx] = vfta;
1490 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1492 struct e1000_hw *hw =
1493 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1494 uint32_t reg = ETHER_TYPE_VLAN ;
1496 reg |= (tpid << 16);
1497 E1000_WRITE_REG(hw, E1000_VET, reg);
1501 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1503 struct e1000_hw *hw =
1504 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507 /* Filter Table Disable */
1508 reg = E1000_READ_REG(hw, E1000_RCTL);
1509 reg &= ~E1000_RCTL_CFIEN;
1510 reg &= ~E1000_RCTL_VFE;
1511 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1515 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1517 struct e1000_hw *hw =
1518 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519 struct e1000_vfta * shadow_vfta =
1520 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1524 /* Filter Table Enable, CFI not used for packet acceptance */
1525 reg = E1000_READ_REG(hw, E1000_RCTL);
1526 reg &= ~E1000_RCTL_CFIEN;
1527 reg |= E1000_RCTL_VFE;
1528 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1530 /* restore VFTA table */
1531 for (i = 0; i < IGB_VFTA_SIZE; i++)
1532 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1536 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1538 struct e1000_hw *hw =
1539 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542 /* VLAN Mode Disable */
1543 reg = E1000_READ_REG(hw, E1000_CTRL);
1544 reg &= ~E1000_CTRL_VME;
1545 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1549 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1551 struct e1000_hw *hw =
1552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555 /* VLAN Mode Enable */
1556 reg = E1000_READ_REG(hw, E1000_CTRL);
1557 reg |= E1000_CTRL_VME;
1558 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1562 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1564 struct e1000_hw *hw =
1565 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568 /* CTRL_EXT: Extended VLAN */
1569 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1570 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1571 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1573 /* Update maximum packet length */
1574 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1575 E1000_WRITE_REG(hw, E1000_RLPML,
1576 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1581 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1583 struct e1000_hw *hw =
1584 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587 /* CTRL_EXT: Extended VLAN */
1588 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1589 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1590 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1592 /* Update maximum packet length */
1593 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1594 E1000_WRITE_REG(hw, E1000_RLPML,
1595 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1600 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1602 if(mask & ETH_VLAN_STRIP_MASK){
1603 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1604 igb_vlan_hw_strip_enable(dev);
1606 igb_vlan_hw_strip_disable(dev);
1609 if(mask & ETH_VLAN_FILTER_MASK){
1610 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1611 igb_vlan_hw_filter_enable(dev);
1613 igb_vlan_hw_filter_disable(dev);
1616 if(mask & ETH_VLAN_EXTEND_MASK){
1617 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1618 igb_vlan_hw_extend_enable(dev);
1620 igb_vlan_hw_extend_disable(dev);
1626 * It enables the interrupt mask and then enable the interrupt.
1629 * Pointer to struct rte_eth_dev.
1632 * - On success, zero.
1633 * - On failure, a negative value.
1636 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1638 struct e1000_interrupt *intr =
1639 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1641 intr->mask |= E1000_ICR_LSC;
1647 * It reads ICR and gets interrupt causes, check it and set a bit flag
1648 * to update link status.
1651 * Pointer to struct rte_eth_dev.
1654 * - On success, zero.
1655 * - On failure, a negative value.
1658 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1661 struct e1000_hw *hw =
1662 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 struct e1000_interrupt *intr =
1664 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1666 igb_intr_disable(hw);
1668 /* read-on-clear nic registers here */
1669 icr = E1000_READ_REG(hw, E1000_ICR);
1672 if (icr & E1000_ICR_LSC) {
1673 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1676 if (icr & E1000_ICR_VMMB)
1677 intr->flags |= E1000_FLAG_MAILBOX;
1683 * It executes link_update after knowing an interrupt is prsent.
1686 * Pointer to struct rte_eth_dev.
1689 * - On success, zero.
1690 * - On failure, a negative value.
1693 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1695 struct e1000_hw *hw =
1696 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697 struct e1000_interrupt *intr =
1698 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1699 uint32_t tctl, rctl;
1700 struct rte_eth_link link;
1703 if (intr->flags & E1000_FLAG_MAILBOX) {
1704 igb_pf_mbx_process(dev);
1705 intr->flags &= ~E1000_FLAG_MAILBOX;
1708 igb_intr_enable(dev);
1709 rte_intr_enable(&(dev->pci_dev->intr_handle));
1711 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1712 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1714 /* set get_link_status to check register later */
1715 hw->mac.get_link_status = 1;
1716 ret = eth_igb_link_update(dev, 0);
1718 /* check if link has changed */
1722 memset(&link, 0, sizeof(link));
1723 rte_igb_dev_atomic_read_link_status(dev, &link);
1724 if (link.link_status) {
1726 " Port %d: Link Up - speed %u Mbps - %s\n",
1727 dev->data->port_id, (unsigned)link.link_speed,
1728 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1729 "full-duplex" : "half-duplex");
1731 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1732 dev->data->port_id);
1734 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1735 dev->pci_dev->addr.domain,
1736 dev->pci_dev->addr.bus,
1737 dev->pci_dev->addr.devid,
1738 dev->pci_dev->addr.function);
1739 tctl = E1000_READ_REG(hw, E1000_TCTL);
1740 rctl = E1000_READ_REG(hw, E1000_RCTL);
1741 if (link.link_status) {
1743 tctl |= E1000_TCTL_EN;
1744 rctl |= E1000_RCTL_EN;
1747 tctl &= ~E1000_TCTL_EN;
1748 rctl &= ~E1000_RCTL_EN;
1750 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1751 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1752 E1000_WRITE_FLUSH(hw);
1753 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1760 * Interrupt handler which shall be registered at first.
1763 * Pointer to interrupt handle.
1765 * The address of parameter (struct rte_eth_dev *) regsitered before.
1771 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1774 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1776 eth_igb_interrupt_get_status(dev);
1777 eth_igb_interrupt_action(dev);
1781 eth_igb_led_on(struct rte_eth_dev *dev)
1783 struct e1000_hw *hw;
1785 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1790 eth_igb_led_off(struct rte_eth_dev *dev)
1792 struct e1000_hw *hw;
1794 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1799 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1801 struct e1000_hw *hw;
1803 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1809 uint32_t rx_buf_size;
1810 uint32_t max_high_water;
1813 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1814 rx_buf_size = igb_get_rx_buffer_size(hw);
1815 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1817 /* At least reserve one Ethernet frame for watermark */
1818 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1819 if ((fc_conf->high_water > max_high_water) ||
1820 (fc_conf->high_water < fc_conf->low_water)) {
1821 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1822 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1826 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1827 hw->fc.pause_time = fc_conf->pause_time;
1828 hw->fc.high_water = fc_conf->high_water;
1829 hw->fc.low_water = fc_conf->low_water;
1830 hw->fc.send_xon = fc_conf->send_xon;
1832 err = e1000_setup_link_generic(hw);
1833 if (err == E1000_SUCCESS) {
1835 /* check if we want to forward MAC frames - driver doesn't have native
1836 * capability to do that, so we'll write the registers ourselves */
1838 rctl = E1000_READ_REG(hw, E1000_RCTL);
1840 /* set or clear MFLCN.PMCF bit depending on configuration */
1841 if (fc_conf->mac_ctrl_frame_fwd != 0)
1842 rctl |= E1000_RCTL_PMCF;
1844 rctl &= ~E1000_RCTL_PMCF;
1846 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1847 E1000_WRITE_FLUSH(hw);
1852 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1856 #define E1000_RAH_POOLSEL_SHIFT (18)
1858 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1859 uint32_t index, __rte_unused uint32_t pool)
1861 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1865 rah = E1000_READ_REG(hw, E1000_RAH(index));
1866 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1867 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1871 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1873 uint8_t addr[ETHER_ADDR_LEN];
1874 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876 memset(addr, 0, sizeof(addr));
1878 e1000_rar_set(hw, addr, index);
1882 * Virtual Function operations
1885 igbvf_intr_disable(struct e1000_hw *hw)
1887 PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1889 /* Clear interrupt mask to stop from interrupts being generated */
1890 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1892 E1000_WRITE_FLUSH(hw);
1896 igbvf_stop_adapter(struct rte_eth_dev *dev)
1900 struct rte_eth_dev_info dev_info;
1901 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903 memset(&dev_info, 0, sizeof(dev_info));
1904 eth_igb_infos_get(dev, &dev_info);
1906 /* Clear interrupt mask to stop from interrupts being generated */
1907 igbvf_intr_disable(hw);
1909 /* Clear any pending interrupts, flush previous writes */
1910 E1000_READ_REG(hw, E1000_EICR);
1912 /* Disable the transmit unit. Each queue must be disabled. */
1913 for (i = 0; i < dev_info.max_tx_queues; i++)
1914 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1916 /* Disable the receive unit by stopping each queue */
1917 for (i = 0; i < dev_info.max_rx_queues; i++) {
1918 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1919 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1920 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1921 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1925 /* flush all queues disables */
1926 E1000_WRITE_FLUSH(hw);
1930 static int eth_igbvf_link_update(struct e1000_hw *hw)
1932 struct e1000_mbx_info *mbx = &hw->mbx;
1933 struct e1000_mac_info *mac = &hw->mac;
1934 int ret_val = E1000_SUCCESS;
1936 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1939 * We only want to run this if there has been a rst asserted.
1940 * in this case that could mean a link change, device reset,
1941 * or a virtual function reset
1944 /* If we were hit with a reset or timeout drop the link */
1945 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1946 mac->get_link_status = TRUE;
1948 if (!mac->get_link_status)
1951 /* if link status is down no point in checking to see if pf is up */
1952 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1955 /* if we passed all the tests above then the link is up and we no
1956 * longer need to check for link */
1957 mac->get_link_status = FALSE;
1965 igbvf_dev_configure(struct rte_eth_dev *dev)
1967 struct rte_eth_conf* conf = &dev->data->dev_conf;
1969 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1970 dev->data->port_id);
1973 * VF has no ability to enable/disable HW CRC
1974 * Keep the persistent behavior the same as Host PF
1976 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1977 if (!conf->rxmode.hw_strip_crc) {
1978 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1979 conf->rxmode.hw_strip_crc = 1;
1982 if (conf->rxmode.hw_strip_crc) {
1983 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1984 conf->rxmode.hw_strip_crc = 0;
1992 igbvf_dev_start(struct rte_eth_dev *dev)
1994 struct e1000_hw *hw =
1995 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998 PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
2000 hw->mac.ops.reset_hw(hw);
2003 igbvf_set_vfta_all(dev,1);
2005 eth_igbvf_tx_init(dev);
2007 /* This can fail when allocating mbufs for descriptor rings */
2008 ret = eth_igbvf_rx_init(dev);
2010 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2011 igb_dev_clear_queues(dev);
2019 igbvf_dev_stop(struct rte_eth_dev *dev)
2021 PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
2023 igbvf_stop_adapter(dev);
2026 * Clear what we set, but we still keep shadow_vfta to
2027 * restore after device starts
2029 igbvf_set_vfta_all(dev,0);
2031 igb_dev_clear_queues(dev);
2035 igbvf_dev_close(struct rte_eth_dev *dev)
2037 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039 PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
2043 igbvf_dev_stop(dev);
2046 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2048 struct e1000_mbx_info *mbx = &hw->mbx;
2051 /* After set vlan, vlan strip will also be enabled in igb driver*/
2052 msgbuf[0] = E1000_VF_SET_VLAN;
2054 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2056 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2058 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2061 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2063 struct e1000_hw *hw =
2064 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 struct e1000_vfta * shadow_vfta =
2066 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2067 int i = 0, j = 0, vfta = 0, mask = 1;
2069 for (i = 0; i < IGB_VFTA_SIZE; i++){
2070 vfta = shadow_vfta->vfta[i];
2073 for (j = 0; j < 32; j++){
2076 (uint16_t)((i<<5)+j), on);
2085 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2087 struct e1000_hw *hw =
2088 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089 struct e1000_vfta * shadow_vfta =
2090 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2091 uint32_t vid_idx = 0;
2092 uint32_t vid_bit = 0;
2095 PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2097 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2098 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2100 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2103 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2104 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2106 /*Save what we set and retore it after device reset*/
2108 shadow_vfta->vfta[vid_idx] |= vid_bit;
2110 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2116 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2117 struct rte_eth_rss_reta *reta_conf)
2121 struct e1000_hw *hw =
2122 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2126 * 128-entries in 32 registers
2128 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2129 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2130 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2132 mask = (uint8_t)((reta_conf->mask_hi >>
2133 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2136 /* If all 4 entries were set,don't need read RETA register */
2138 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2140 for (j = 0; j < 4; j++) {
2141 if (mask & (0x1 << j)) {
2143 reta &= ~(0xFF << 8 * j);
2144 reta |= reta_conf->reta[i + j] << 8 * j;
2147 E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2155 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2156 struct rte_eth_rss_reta *reta_conf)
2160 struct e1000_hw *hw =
2161 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2165 * 128-entries in 32 registers
2167 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2168 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2169 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2171 mask = (uint8_t)((reta_conf->mask_hi >>
2172 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2175 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2176 for (j = 0; j < 4; j++) {
2177 if (mask & (0x1 << j))
2178 reta_conf->reta[i + j] =
2179 (uint8_t)((reta >> 8 * j) & 0xFF);
2187 static struct rte_driver pmd_igb_drv = {
2189 .init = rte_igb_pmd_init,
2192 static struct rte_driver pmd_igbvf_drv = {
2194 .init = rte_igbvf_pmd_init,
2197 PMD_REGISTER_DRIVER(pmd_igb_drv);
2198 PMD_REGISTER_DRIVER(pmd_igbvf_drv);