4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
41 #include <rte_common.h>
42 #include <rte_interrupts.h>
43 #include <rte_byteorder.h>
45 #include <rte_debug.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
51 #include <rte_tailq.h>
53 #include <rte_atomic.h>
54 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
60 static int eth_igb_configure(struct rte_eth_dev *dev);
61 static int eth_igb_start(struct rte_eth_dev *dev);
62 static void eth_igb_stop(struct rte_eth_dev *dev);
63 static void eth_igb_close(struct rte_eth_dev *dev);
64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
68 static int eth_igb_link_update(struct rte_eth_dev *dev,
69 int wait_to_complete);
70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
71 struct rte_eth_stats *rte_stats);
72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
74 struct rte_eth_dev_info *dev_info);
75 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
76 struct rte_eth_fc_conf *fc_conf);
77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
82 static int igb_hardware_init(struct e1000_hw *hw);
83 static void igb_hw_control_acquire(struct e1000_hw *hw);
84 static void igb_hw_control_release(struct e1000_hw *hw);
85 static void igb_init_manageability(struct e1000_hw *hw);
86 static void igb_release_manageability(struct e1000_hw *hw);
88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
89 uint16_t vlan_id, int on);
90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
100 static int eth_igb_led_on(struct rte_eth_dev *dev);
101 static int eth_igb_led_off(struct rte_eth_dev *dev);
103 static void igb_intr_disable(struct e1000_hw *hw);
104 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
106 struct ether_addr *mac_addr,
107 uint32_t index, uint32_t pool);
108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
110 static void igbvf_intr_disable(struct e1000_hw *hw);
111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
112 static int igbvf_dev_start(struct rte_eth_dev *dev);
113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
114 static void igbvf_dev_close(struct rte_eth_dev *dev);
115 static int eth_igbvf_link_update(struct e1000_hw *hw);
116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
119 uint16_t vlan_id, int on);
120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
124 * Define VF Stats MACRO for Non "cleared on read" register
126 #define UPDATE_VF_STAT(reg, last, cur) \
128 u32 latest = E1000_READ_REG(hw, reg); \
129 cur += latest - last; \
134 #define IGB_FC_PAUSE_TIME 0x0680
135 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
136 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
138 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
141 * The set of PCI devices this driver supports
143 static struct rte_pci_id pci_id_igb_map[] = {
145 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
146 #include "rte_pci_dev_ids.h"
152 * The set of PCI devices this driver supports (for 82576&I350 VF)
154 static struct rte_pci_id pci_id_igbvf_map[] = {
156 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
157 #include "rte_pci_dev_ids.h"
162 static struct eth_dev_ops eth_igb_ops = {
163 .dev_configure = eth_igb_configure,
164 .dev_start = eth_igb_start,
165 .dev_stop = eth_igb_stop,
166 .dev_close = eth_igb_close,
167 .promiscuous_enable = eth_igb_promiscuous_enable,
168 .promiscuous_disable = eth_igb_promiscuous_disable,
169 .allmulticast_enable = eth_igb_allmulticast_enable,
170 .allmulticast_disable = eth_igb_allmulticast_disable,
171 .link_update = eth_igb_link_update,
172 .stats_get = eth_igb_stats_get,
173 .stats_reset = eth_igb_stats_reset,
174 .dev_infos_get = eth_igb_infos_get,
175 .vlan_filter_set = eth_igb_vlan_filter_set,
176 .vlan_tpid_set = eth_igb_vlan_tpid_set,
177 .vlan_offload_set = eth_igb_vlan_offload_set,
178 .rx_queue_setup = eth_igb_rx_queue_setup,
179 .rx_queue_release = eth_igb_rx_queue_release,
180 .tx_queue_setup = eth_igb_tx_queue_setup,
181 .tx_queue_release = eth_igb_tx_queue_release,
182 .dev_led_on = eth_igb_led_on,
183 .dev_led_off = eth_igb_led_off,
184 .flow_ctrl_set = eth_igb_flow_ctrl_set,
185 .mac_addr_add = eth_igb_rar_set,
186 .mac_addr_remove = eth_igb_rar_clear,
190 * dev_ops for virtual function, bare necessities for basic vf
191 * operation have been implemented
193 static struct eth_dev_ops igbvf_eth_dev_ops = {
194 .dev_configure = igbvf_dev_configure,
195 .dev_start = igbvf_dev_start,
196 .dev_stop = igbvf_dev_stop,
197 .dev_close = igbvf_dev_close,
198 .link_update = eth_igb_link_update,
199 .stats_get = eth_igbvf_stats_get,
200 .stats_reset = eth_igbvf_stats_reset,
201 .vlan_filter_set = igbvf_vlan_filter_set,
202 .dev_infos_get = eth_igb_infos_get,
203 .rx_queue_setup = eth_igb_rx_queue_setup,
204 .rx_queue_release = eth_igb_rx_queue_release,
205 .tx_queue_setup = eth_igb_tx_queue_setup,
206 .tx_queue_release = eth_igb_tx_queue_release,
210 * Atomically reads the link status information from global
211 * structure rte_eth_dev.
214 * - Pointer to the structure rte_eth_dev to read from.
215 * - Pointer to the buffer to be saved with the link status.
218 * - On success, zero.
219 * - On failure, negative value.
222 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
223 struct rte_eth_link *link)
225 struct rte_eth_link *dst = link;
226 struct rte_eth_link *src = &(dev->data->dev_link);
228 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
229 *(uint64_t *)src) == 0)
236 * Atomically writes the link status information into global
237 * structure rte_eth_dev.
240 * - Pointer to the structure rte_eth_dev to read from.
241 * - Pointer to the buffer to be saved with the link status.
244 * - On success, zero.
245 * - On failure, negative value.
248 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
249 struct rte_eth_link *link)
251 struct rte_eth_link *dst = &(dev->data->dev_link);
252 struct rte_eth_link *src = link;
254 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
255 *(uint64_t *)src) == 0)
262 igb_intr_enable(struct rte_eth_dev *dev)
264 struct e1000_interrupt *intr =
265 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
266 struct e1000_hw *hw =
267 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
269 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
270 E1000_WRITE_FLUSH(hw);
274 igb_intr_disable(struct e1000_hw *hw)
276 E1000_WRITE_REG(hw, E1000_IMC, ~0);
277 E1000_WRITE_FLUSH(hw);
281 igb_identify_hardware(struct rte_eth_dev *dev)
283 struct e1000_hw *hw =
284 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
286 hw->vendor_id = dev->pci_dev->id.vendor_id;
287 hw->device_id = dev->pci_dev->id.device_id;
288 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
289 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
291 e1000_set_mac_type(hw);
293 /* need to check if it is a vf device below */
297 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
298 struct rte_eth_dev *eth_dev)
301 struct rte_pci_device *pci_dev;
302 struct e1000_hw *hw =
303 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
304 struct e1000_vfta * shadow_vfta =
305 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
307 pci_dev = eth_dev->pci_dev;
308 eth_dev->dev_ops = ð_igb_ops;
309 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
310 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
312 /* for secondary processes, we don't initialise any further as primary
313 * has already done this work. Only check we don't need a different
315 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
316 if (eth_dev->data->scattered_rx)
317 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
321 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
323 igb_identify_hardware(eth_dev);
324 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
329 e1000_get_bus_info(hw);
332 hw->phy.autoneg_wait_to_complete = 0;
333 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
336 if (hw->phy.media_type == e1000_media_type_copper) {
337 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
338 hw->phy.disable_polarity_correction = 0;
339 hw->phy.ms_type = e1000_ms_hw_default;
343 * Start from a known state, this is important in reading the nvm
348 /* Make sure we have a good EEPROM before we read from it */
349 if (e1000_validate_nvm_checksum(hw) < 0) {
351 * Some PCI-E parts fail the first check due to
352 * the link being in sleep state, call it again,
353 * if it fails a second time its a real issue.
355 if (e1000_validate_nvm_checksum(hw) < 0) {
356 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
362 /* Read the permanent MAC address out of the EEPROM */
363 if (e1000_read_mac_addr(hw) != 0) {
364 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
369 /* Allocate memory for storing MAC addresses */
370 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
371 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
372 if (eth_dev->data->mac_addrs == NULL) {
373 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
374 "store MAC addresses",
375 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
380 /* Copy the permanent MAC address */
381 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
383 /* initialize the vfta */
384 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
386 /* Now initialize the hardware */
387 if (igb_hardware_init(hw) != 0) {
388 PMD_INIT_LOG(ERR, "Hardware initialization failed");
389 rte_free(eth_dev->data->mac_addrs);
390 eth_dev->data->mac_addrs = NULL;
394 hw->mac.get_link_status = 1;
396 /* Indicate SOL/IDER usage */
397 if (e1000_check_reset_block(hw) < 0) {
398 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
402 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
403 eth_dev->data->port_id, pci_dev->id.vendor_id,
404 pci_dev->id.device_id);
406 rte_intr_callback_register(&(pci_dev->intr_handle),
407 eth_igb_interrupt_handler, (void *)eth_dev);
409 /* enable uio intr after callback register */
410 rte_intr_enable(&(pci_dev->intr_handle));
412 /* enable support intr */
413 igb_intr_enable(eth_dev);
418 igb_hw_control_release(hw);
424 * Virtual Function device init
427 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
428 struct rte_eth_dev *eth_dev)
430 struct rte_pci_device *pci_dev;
431 struct e1000_hw *hw =
432 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
435 PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
437 eth_dev->dev_ops = &igbvf_eth_dev_ops;
438 pci_dev = eth_dev->pci_dev;
440 hw->device_id = pci_dev->id.device_id;
441 hw->vendor_id = pci_dev->id.vendor_id;
442 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
444 /* Initialize the shared code */
445 diag = e1000_setup_init_funcs(hw, TRUE);
447 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
452 /* init_mailbox_params */
453 hw->mbx.ops.init_params(hw);
455 /* Disable the interrupts for VF */
456 igbvf_intr_disable(hw);
458 diag = hw->mac.ops.reset_hw(hw);
460 /* Allocate memory for storing MAC addresses */
461 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
462 hw->mac.rar_entry_count, 0);
463 if (eth_dev->data->mac_addrs == NULL) {
465 "Failed to allocate %d bytes needed to store MAC "
467 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
470 /* Copy the permanent MAC address */
471 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
472 ð_dev->data->mac_addrs[0]);
474 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
476 eth_dev->data->port_id, pci_dev->id.vendor_id,
477 pci_dev->id.device_id,
483 static struct eth_driver rte_igb_pmd = {
485 .name = "rte_igb_pmd",
486 .id_table = pci_id_igb_map,
487 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
489 .eth_dev_init = eth_igb_dev_init,
490 .dev_private_size = sizeof(struct e1000_adapter),
494 * virtual function driver struct
496 static struct eth_driver rte_igbvf_pmd = {
498 .name = "rte_igbvf_pmd",
499 .id_table = pci_id_igbvf_map,
500 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
502 .eth_dev_init = eth_igbvf_dev_init,
503 .dev_private_size = sizeof(struct e1000_adapter),
507 rte_igb_pmd_init(void)
509 rte_eth_driver_register(&rte_igb_pmd);
514 * VF Driver initialization routine.
515 * Invoked one at EAL init time.
516 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
519 rte_igbvf_pmd_init(void)
521 DEBUGFUNC("rte_igbvf_pmd_init");
523 rte_eth_driver_register(&rte_igbvf_pmd);
528 eth_igb_configure(struct rte_eth_dev *dev)
530 struct e1000_interrupt *intr =
531 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
533 PMD_INIT_LOG(DEBUG, ">>");
535 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
537 PMD_INIT_LOG(DEBUG, "<<");
543 eth_igb_start(struct rte_eth_dev *dev)
545 struct e1000_hw *hw =
546 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
549 PMD_INIT_LOG(DEBUG, ">>");
551 /* Power up the phy. Needed to make the link go Up */
552 e1000_power_up_phy(hw);
555 * Packet Buffer Allocation (PBA)
556 * Writing PBA sets the receive portion of the buffer
557 * the remainder is used for the transmit buffer.
559 if (hw->mac.type == e1000_82575) {
562 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
563 E1000_WRITE_REG(hw, E1000_PBA, pba);
566 /* Put the address into the Receive Address Array */
567 e1000_rar_set(hw, hw->mac.addr, 0);
569 /* Initialize the hardware */
570 if (igb_hardware_init(hw)) {
571 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
575 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
577 /* Configure for OS presence */
578 igb_init_manageability(hw);
580 eth_igb_tx_init(dev);
582 /* This can fail when allocating mbufs for descriptor rings */
583 ret = eth_igb_rx_init(dev);
585 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
586 igb_dev_clear_queues(dev);
590 e1000_clear_hw_cntrs_base_generic(hw);
593 * VLAN Offload Settings
595 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
596 ETH_VLAN_EXTEND_MASK;
597 eth_igb_vlan_offload_set(dev, mask);
600 * Configure the Interrupt Moderation register (EITR) with the maximum
601 * possible value (0xFFFF) to minimize "System Partial Write" issued by
602 * spurious [DMA] memory updates of RX and TX ring descriptors.
604 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
605 * spurious memory updates per second should be expected.
606 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
608 * Because interrupts are not used at all, the MSI-X is not activated
609 * and interrupt moderation is controlled by EITR[0].
611 * Note that having [almost] disabled memory updates of RX and TX ring
612 * descriptors through the Interrupt Moderation mechanism, memory
613 * updates of ring descriptors are now moderated by the configurable
614 * value of Write-Back Threshold registers.
616 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
617 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
620 /* Enable all RX & TX queues in the IVAR registers */
621 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
622 for (i = 0; i < 8; i++)
623 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
625 /* Configure EITR with the maximum possible value (0xFFFF) */
626 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
629 /* Setup link speed and duplex */
630 switch (dev->data->dev_conf.link_speed) {
631 case ETH_LINK_SPEED_AUTONEG:
632 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
633 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
634 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
635 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
636 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
637 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
639 goto error_invalid_config;
641 case ETH_LINK_SPEED_10:
642 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
643 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
644 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
645 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
646 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
647 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
649 goto error_invalid_config;
651 case ETH_LINK_SPEED_100:
652 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
653 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
654 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
655 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
656 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
657 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
659 goto error_invalid_config;
661 case ETH_LINK_SPEED_1000:
662 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
663 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
664 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
666 goto error_invalid_config;
668 case ETH_LINK_SPEED_10000:
670 goto error_invalid_config;
672 e1000_setup_link(hw);
674 /* check if lsc interrupt feature is enabled */
675 if (dev->data->dev_conf.intr_conf.lsc != 0)
676 ret = eth_igb_lsc_interrupt_setup(dev);
678 /* resume enabled intr since hw reset */
679 igb_intr_enable(dev);
681 PMD_INIT_LOG(DEBUG, "<<");
685 error_invalid_config:
686 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
687 dev->data->dev_conf.link_speed,
688 dev->data->dev_conf.link_duplex, dev->data->port_id);
689 igb_dev_clear_queues(dev);
693 /*********************************************************************
695 * This routine disables all traffic on the adapter by issuing a
696 * global reset on the MAC.
698 **********************************************************************/
700 eth_igb_stop(struct rte_eth_dev *dev)
702 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
703 struct rte_eth_link link;
705 igb_intr_disable(hw);
707 E1000_WRITE_REG(hw, E1000_WUC, 0);
709 /* Power down the phy. Needed to make the link go Down */
710 e1000_power_down_phy(hw);
712 igb_dev_clear_queues(dev);
714 /* clear the recorded link status */
715 memset(&link, 0, sizeof(link));
716 rte_igb_dev_atomic_write_link_status(dev, &link);
720 eth_igb_close(struct rte_eth_dev *dev)
722 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
723 struct rte_eth_link link;
726 e1000_phy_hw_reset(hw);
727 igb_release_manageability(hw);
728 igb_hw_control_release(hw);
730 igb_dev_clear_queues(dev);
732 memset(&link, 0, sizeof(link));
733 rte_igb_dev_atomic_write_link_status(dev, &link);
737 igb_get_rx_buffer_size(struct e1000_hw *hw)
739 uint32_t rx_buf_size;
740 if (hw->mac.type == e1000_82576) {
741 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
742 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
743 /* PBS needs to be translated according to a lookup table */
744 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
745 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
746 rx_buf_size = (rx_buf_size << 10);
747 } else if (hw->mac.type == e1000_i210) {
748 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
750 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
756 /*********************************************************************
758 * Initialize the hardware
760 **********************************************************************/
762 igb_hardware_init(struct e1000_hw *hw)
764 uint32_t rx_buf_size;
767 /* Let the firmware know the OS is in control */
768 igb_hw_control_acquire(hw);
771 * These parameters control the automatic generation (Tx) and
772 * response (Rx) to Ethernet PAUSE frames.
773 * - High water mark should allow for at least two standard size (1518)
774 * frames to be received after sending an XOFF.
775 * - Low water mark works best when it is very near the high water mark.
776 * This allows the receiver to restart by sending XON when it has
777 * drained a bit. Here we use an arbitary value of 1500 which will
778 * restart after one full frame is pulled from the buffer. There
779 * could be several smaller frames in the buffer and if so they will
780 * not trigger the XON until their total number reduces the buffer
782 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
784 rx_buf_size = igb_get_rx_buffer_size(hw);
786 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
787 hw->fc.low_water = hw->fc.high_water - 1500;
788 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
791 /* Set Flow control, use the tunable location if sane */
792 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
793 hw->fc.requested_mode = igb_fc_setting;
795 hw->fc.requested_mode = e1000_fc_none;
797 /* Issue a global reset */
799 E1000_WRITE_REG(hw, E1000_WUC, 0);
801 diag = e1000_init_hw(hw);
805 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
806 e1000_get_phy_info(hw);
807 e1000_check_for_link(hw);
812 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
814 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
816 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
817 struct e1000_hw_stats *stats =
818 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
821 if(hw->phy.media_type == e1000_media_type_copper ||
822 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
824 E1000_READ_REG(hw,E1000_SYMERRS);
825 stats->sec += E1000_READ_REG(hw, E1000_SEC);
828 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
829 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
830 stats->scc += E1000_READ_REG(hw, E1000_SCC);
831 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
833 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
834 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
835 stats->colc += E1000_READ_REG(hw, E1000_COLC);
836 stats->dc += E1000_READ_REG(hw, E1000_DC);
837 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
838 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
839 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
841 ** For watchdog management we need to know if we have been
842 ** paused during the last interval, so capture that here.
844 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
845 stats->xoffrxc += pause_frames;
846 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
847 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
848 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
849 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
850 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
851 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
852 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
853 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
854 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
855 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
856 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
857 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
859 /* For the 64-bit byte counters the low dword must be read first. */
860 /* Both registers clear on the read of the high dword */
862 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
863 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
864 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
865 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
867 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
868 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
869 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
870 stats->roc += E1000_READ_REG(hw, E1000_ROC);
871 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
873 stats->tor += E1000_READ_REG(hw, E1000_TORH);
874 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
876 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
877 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
878 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
879 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
880 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
881 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
882 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
883 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
884 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
885 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
887 /* Interrupt Counts */
889 stats->iac += E1000_READ_REG(hw, E1000_IAC);
890 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
891 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
892 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
893 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
894 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
895 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
896 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
897 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
899 /* Host to Card Statistics */
901 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
902 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
903 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
904 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
905 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
906 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
907 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
908 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
909 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
910 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
911 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
912 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
913 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
914 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
916 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
917 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
918 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
919 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
920 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
921 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
923 if (rte_stats == NULL)
927 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
928 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
931 rte_stats->oerrors = stats->ecol + stats->latecol;
933 rte_stats->ipackets = stats->gprc;
934 rte_stats->opackets = stats->gptc;
935 rte_stats->ibytes = stats->gorc;
936 rte_stats->obytes = stats->gotc;
940 eth_igb_stats_reset(struct rte_eth_dev *dev)
942 struct e1000_hw_stats *hw_stats =
943 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
945 /* HW registers are cleared on read */
946 eth_igb_stats_get(dev, NULL);
948 /* Reset software totals */
949 memset(hw_stats, 0, sizeof(*hw_stats));
953 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
955 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
956 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
957 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
959 /* Good Rx packets, include VF loopback */
960 UPDATE_VF_STAT(E1000_VFGPRC,
961 hw_stats->last_gprc, hw_stats->gprc);
963 /* Good Rx octets, include VF loopback */
964 UPDATE_VF_STAT(E1000_VFGORC,
965 hw_stats->last_gorc, hw_stats->gorc);
967 /* Good Tx packets, include VF loopback */
968 UPDATE_VF_STAT(E1000_VFGPTC,
969 hw_stats->last_gptc, hw_stats->gptc);
971 /* Good Tx octets, include VF loopback */
972 UPDATE_VF_STAT(E1000_VFGOTC,
973 hw_stats->last_gotc, hw_stats->gotc);
975 /* Rx Multicst packets */
976 UPDATE_VF_STAT(E1000_VFMPRC,
977 hw_stats->last_mprc, hw_stats->mprc);
979 /* Good Rx loopback packets */
980 UPDATE_VF_STAT(E1000_VFGPRLBC,
981 hw_stats->last_gprlbc, hw_stats->gprlbc);
983 /* Good Rx loopback octets */
984 UPDATE_VF_STAT(E1000_VFGORLBC,
985 hw_stats->last_gorlbc, hw_stats->gorlbc);
987 /* Good Tx loopback packets */
988 UPDATE_VF_STAT(E1000_VFGPTLBC,
989 hw_stats->last_gptlbc, hw_stats->gptlbc);
991 /* Good Tx loopback octets */
992 UPDATE_VF_STAT(E1000_VFGOTLBC,
993 hw_stats->last_gotlbc, hw_stats->gotlbc);
995 if (rte_stats == NULL)
998 memset(rte_stats, 0, sizeof(*rte_stats));
999 rte_stats->ipackets = hw_stats->gprc;
1000 rte_stats->ibytes = hw_stats->gorc;
1001 rte_stats->opackets = hw_stats->gptc;
1002 rte_stats->obytes = hw_stats->gotc;
1003 rte_stats->imcasts = hw_stats->mprc;
1004 rte_stats->ilbpackets = hw_stats->gprlbc;
1005 rte_stats->ilbbytes = hw_stats->gorlbc;
1006 rte_stats->olbpackets = hw_stats->gptlbc;
1007 rte_stats->olbbytes = hw_stats->gotlbc;
1012 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1014 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1015 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1017 /* Sync HW register to the last stats */
1018 eth_igbvf_stats_get(dev, NULL);
1020 /* reset HW current stats*/
1021 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1022 offsetof(struct e1000_vf_stats, gprc));
1027 eth_igb_infos_get(struct rte_eth_dev *dev,
1028 struct rte_eth_dev_info *dev_info)
1030 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1033 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1034 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1036 switch (hw->mac.type) {
1038 dev_info->max_rx_queues = 4;
1039 dev_info->max_tx_queues = 4;
1043 dev_info->max_rx_queues = 16;
1044 dev_info->max_tx_queues = 16;
1048 dev_info->max_rx_queues = 8;
1049 dev_info->max_tx_queues = 8;
1053 dev_info->max_rx_queues = 8;
1054 dev_info->max_tx_queues = 8;
1058 dev_info->max_rx_queues = 4;
1059 dev_info->max_tx_queues = 4;
1063 dev_info->max_rx_queues = 2;
1064 dev_info->max_tx_queues = 2;
1067 case e1000_vfadapt_i350:
1068 dev_info->max_rx_queues = 1;
1069 dev_info->max_tx_queues = 1;
1073 /* Should not happen */
1074 dev_info->max_rx_queues = 0;
1075 dev_info->max_tx_queues = 0;
1079 /* return 0 means link status changed, -1 means not changed */
1081 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1083 struct e1000_hw *hw =
1084 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1085 struct rte_eth_link link, old;
1086 int link_check, count;
1089 hw->mac.get_link_status = 1;
1091 /* possible wait-to-complete in up to 9 seconds */
1092 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1093 /* Read the real link status */
1094 switch (hw->phy.media_type) {
1095 case e1000_media_type_copper:
1096 /* Do the work to read phy */
1097 e1000_check_for_link(hw);
1098 link_check = !hw->mac.get_link_status;
1101 case e1000_media_type_fiber:
1102 e1000_check_for_link(hw);
1103 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1107 case e1000_media_type_internal_serdes:
1108 e1000_check_for_link(hw);
1109 link_check = hw->mac.serdes_has_link;
1112 /* VF device is type_unknown */
1113 case e1000_media_type_unknown:
1114 eth_igbvf_link_update(hw);
1115 link_check = !hw->mac.get_link_status;
1121 if (link_check || wait_to_complete == 0)
1123 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1125 memset(&link, 0, sizeof(link));
1126 rte_igb_dev_atomic_read_link_status(dev, &link);
1129 /* Now we check if a transition has happened */
1131 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1133 link.link_status = 1;
1134 } else if (!link_check) {
1135 link.link_speed = 0;
1136 link.link_duplex = 0;
1137 link.link_status = 0;
1139 rte_igb_dev_atomic_write_link_status(dev, &link);
1142 if (old.link_status == link.link_status)
1150 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1151 * For ASF and Pass Through versions of f/w this means
1152 * that the driver is loaded.
1155 igb_hw_control_acquire(struct e1000_hw *hw)
1159 /* Let firmware know the driver has taken over */
1160 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1161 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1165 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1166 * For ASF and Pass Through versions of f/w this means that the
1167 * driver is no longer loaded.
1170 igb_hw_control_release(struct e1000_hw *hw)
1174 /* Let firmware taken over control of h/w */
1175 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1176 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1177 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1181 * Bit of a misnomer, what this really means is
1182 * to enable OS management of the system... aka
1183 * to disable special hardware management features.
1186 igb_init_manageability(struct e1000_hw *hw)
1188 if (e1000_enable_mng_pass_thru(hw)) {
1189 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1190 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1192 /* disable hardware interception of ARP */
1193 manc &= ~(E1000_MANC_ARP_EN);
1195 /* enable receiving management packets to the host */
1196 manc |= E1000_MANC_EN_MNG2HOST;
1197 manc2h |= 1 << 5; /* Mng Port 623 */
1198 manc2h |= 1 << 6; /* Mng Port 664 */
1199 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1200 E1000_WRITE_REG(hw, E1000_MANC, manc);
1205 igb_release_manageability(struct e1000_hw *hw)
1207 if (e1000_enable_mng_pass_thru(hw)) {
1208 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1210 manc |= E1000_MANC_ARP_EN;
1211 manc &= ~E1000_MANC_EN_MNG2HOST;
1213 E1000_WRITE_REG(hw, E1000_MANC, manc);
1218 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1220 struct e1000_hw *hw =
1221 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 rctl = E1000_READ_REG(hw, E1000_RCTL);
1225 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1226 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1230 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1232 struct e1000_hw *hw =
1233 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1236 rctl = E1000_READ_REG(hw, E1000_RCTL);
1237 rctl &= (~E1000_RCTL_UPE);
1238 if (dev->data->all_multicast == 1)
1239 rctl |= E1000_RCTL_MPE;
1241 rctl &= (~E1000_RCTL_MPE);
1242 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1246 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1248 struct e1000_hw *hw =
1249 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1252 rctl = E1000_READ_REG(hw, E1000_RCTL);
1253 rctl |= E1000_RCTL_MPE;
1254 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1258 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1260 struct e1000_hw *hw =
1261 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1264 if (dev->data->promiscuous == 1)
1265 return; /* must remain in all_multicast mode */
1266 rctl = E1000_READ_REG(hw, E1000_RCTL);
1267 rctl &= (~E1000_RCTL_MPE);
1268 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1272 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1274 struct e1000_hw *hw =
1275 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 struct e1000_vfta * shadow_vfta =
1277 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1282 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1283 E1000_VFTA_ENTRY_MASK);
1284 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1285 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1290 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1292 /* update local VFTA copy */
1293 shadow_vfta->vfta[vid_idx] = vfta;
1299 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1301 struct e1000_hw *hw =
1302 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303 uint32_t reg = ETHER_TYPE_VLAN ;
1305 reg |= (tpid << 16);
1306 E1000_WRITE_REG(hw, E1000_VET, reg);
1310 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1312 struct e1000_hw *hw =
1313 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 /* Filter Table Disable */
1317 reg = E1000_READ_REG(hw, E1000_RCTL);
1318 reg &= ~E1000_RCTL_CFIEN;
1319 reg &= ~E1000_RCTL_VFE;
1320 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1324 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1326 struct e1000_hw *hw =
1327 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1328 struct e1000_vfta * shadow_vfta =
1329 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1333 /* Filter Table Enable, CFI not used for packet acceptance */
1334 reg = E1000_READ_REG(hw, E1000_RCTL);
1335 reg &= ~E1000_RCTL_CFIEN;
1336 reg |= E1000_RCTL_VFE;
1337 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1339 /* restore VFTA table */
1340 for (i = 0; i < IGB_VFTA_SIZE; i++)
1341 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1345 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1347 struct e1000_hw *hw =
1348 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351 /* VLAN Mode Disable */
1352 reg = E1000_READ_REG(hw, E1000_CTRL);
1353 reg &= ~E1000_CTRL_VME;
1354 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1356 /* Update maximum frame size */
1357 E1000_WRITE_REG(hw, E1000_RLPML,
1358 dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE);
1362 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1364 struct e1000_hw *hw =
1365 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368 /* VLAN Mode Enable */
1369 reg = E1000_READ_REG(hw, E1000_CTRL);
1370 reg |= E1000_CTRL_VME;
1371 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1373 /* Update maximum frame size */
1374 E1000_WRITE_REG(hw, E1000_RLPML,
1375 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1380 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1382 struct e1000_hw *hw =
1383 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386 /* CTRL_EXT: Extended VLAN */
1387 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1388 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1389 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1394 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1396 struct e1000_hw *hw =
1397 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400 /* CTRL_EXT: Extended VLAN */
1401 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1402 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1403 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1407 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1409 if(mask & ETH_VLAN_STRIP_MASK){
1410 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1411 igb_vlan_hw_strip_enable(dev);
1413 igb_vlan_hw_strip_disable(dev);
1416 if(mask & ETH_VLAN_FILTER_MASK){
1417 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1418 igb_vlan_hw_filter_enable(dev);
1420 igb_vlan_hw_filter_disable(dev);
1423 if(mask & ETH_VLAN_EXTEND_MASK){
1424 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1425 igb_vlan_hw_extend_enable(dev);
1427 igb_vlan_hw_extend_disable(dev);
1433 * It enables the interrupt mask and then enable the interrupt.
1436 * Pointer to struct rte_eth_dev.
1439 * - On success, zero.
1440 * - On failure, a negative value.
1443 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1445 struct e1000_interrupt *intr =
1446 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1448 intr->mask |= E1000_ICR_LSC;
1454 * It reads ICR and gets interrupt causes, check it and set a bit flag
1455 * to update link status.
1458 * Pointer to struct rte_eth_dev.
1461 * - On success, zero.
1462 * - On failure, a negative value.
1465 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1468 struct e1000_hw *hw =
1469 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1470 struct e1000_interrupt *intr =
1471 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1473 igb_intr_disable(hw);
1475 /* read-on-clear nic registers here */
1476 icr = E1000_READ_REG(hw, E1000_ICR);
1479 if (icr & E1000_ICR_LSC) {
1480 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1487 * It executes link_update after knowing an interrupt is prsent.
1490 * Pointer to struct rte_eth_dev.
1493 * - On success, zero.
1494 * - On failure, a negative value.
1497 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1499 struct e1000_hw *hw =
1500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501 struct e1000_interrupt *intr =
1502 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1503 uint32_t tctl, rctl;
1504 struct rte_eth_link link;
1508 igb_intr_enable(dev);
1509 rte_intr_enable(&(dev->pci_dev->intr_handle));
1511 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1512 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1514 /* set get_link_status to check register later */
1515 hw->mac.get_link_status = 1;
1516 ret = eth_igb_link_update(dev, 0);
1518 /* check if link has changed */
1522 memset(&link, 0, sizeof(link));
1523 rte_igb_dev_atomic_read_link_status(dev, &link);
1524 if (link.link_status) {
1526 " Port %d: Link Up - speed %u Mbps - %s\n",
1527 dev->data->port_id, (unsigned)link.link_speed,
1528 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1529 "full-duplex" : "half-duplex");
1531 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1532 dev->data->port_id);
1534 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1535 dev->pci_dev->addr.domain,
1536 dev->pci_dev->addr.bus,
1537 dev->pci_dev->addr.devid,
1538 dev->pci_dev->addr.function);
1539 tctl = E1000_READ_REG(hw, E1000_TCTL);
1540 rctl = E1000_READ_REG(hw, E1000_RCTL);
1541 if (link.link_status) {
1543 tctl |= E1000_TCTL_EN;
1544 rctl |= E1000_RCTL_EN;
1547 tctl &= ~E1000_TCTL_EN;
1548 rctl &= ~E1000_RCTL_EN;
1550 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1551 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1552 E1000_WRITE_FLUSH(hw);
1553 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1560 * Interrupt handler which shall be registered at first.
1563 * Pointer to interrupt handle.
1565 * The address of parameter (struct rte_eth_dev *) regsitered before.
1571 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1574 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1576 eth_igb_interrupt_get_status(dev);
1577 eth_igb_interrupt_action(dev);
1581 eth_igb_led_on(struct rte_eth_dev *dev)
1583 struct e1000_hw *hw;
1585 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1590 eth_igb_led_off(struct rte_eth_dev *dev)
1592 struct e1000_hw *hw;
1594 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1599 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1601 struct e1000_hw *hw;
1603 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1609 uint32_t rx_buf_size;
1610 uint32_t max_high_water;
1612 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613 rx_buf_size = igb_get_rx_buffer_size(hw);
1614 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1616 /* At least reserve one Ethernet frame for watermark */
1617 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1618 if ((fc_conf->high_water > max_high_water) ||
1619 (fc_conf->high_water < fc_conf->low_water)) {
1620 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1621 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1625 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1626 hw->fc.pause_time = fc_conf->pause_time;
1627 hw->fc.high_water = fc_conf->high_water;
1628 hw->fc.low_water = fc_conf->low_water;
1629 hw->fc.send_xon = fc_conf->send_xon;
1631 err = e1000_setup_link_generic(hw);
1632 if (err == E1000_SUCCESS) {
1636 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1641 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1642 uint32_t index, __rte_unused uint32_t pool)
1644 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1650 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1652 uint8_t addr[ETHER_ADDR_LEN];
1653 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 memset(addr, 0, sizeof(addr));
1657 e1000_rar_set(hw, addr, index);
1661 * Virtual Function operations
1664 igbvf_intr_disable(struct e1000_hw *hw)
1666 PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1668 /* Clear interrupt mask to stop from interrupts being generated */
1669 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1671 E1000_WRITE_FLUSH(hw);
1675 igbvf_stop_adapter(struct rte_eth_dev *dev)
1679 struct rte_eth_dev_info dev_info;
1680 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682 memset(&dev_info, 0, sizeof(dev_info));
1683 eth_igb_infos_get(dev, &dev_info);
1685 /* Clear interrupt mask to stop from interrupts being generated */
1686 igbvf_intr_disable(hw);
1688 /* Clear any pending interrupts, flush previous writes */
1689 E1000_READ_REG(hw, E1000_EICR);
1691 /* Disable the transmit unit. Each queue must be disabled. */
1692 for (i = 0; i < dev_info.max_tx_queues; i++)
1693 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1695 /* Disable the receive unit by stopping each queue */
1696 for (i = 0; i < dev_info.max_rx_queues; i++) {
1697 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1698 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1699 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1700 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1704 /* flush all queues disables */
1705 E1000_WRITE_FLUSH(hw);
1709 static int eth_igbvf_link_update(struct e1000_hw *hw)
1711 struct e1000_mbx_info *mbx = &hw->mbx;
1712 struct e1000_mac_info *mac = &hw->mac;
1713 int ret_val = E1000_SUCCESS;
1715 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1718 * We only want to run this if there has been a rst asserted.
1719 * in this case that could mean a link change, device reset,
1720 * or a virtual function reset
1723 /* If we were hit with a reset or timeout drop the link */
1724 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1725 mac->get_link_status = TRUE;
1727 if (!mac->get_link_status)
1730 /* if link status is down no point in checking to see if pf is up */
1731 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1734 /* if we passed all the tests above then the link is up and we no
1735 * longer need to check for link */
1736 mac->get_link_status = FALSE;
1744 igbvf_dev_configure(struct rte_eth_dev *dev)
1746 struct rte_eth_conf* conf = &dev->data->dev_conf;
1748 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1749 dev->data->port_id);
1752 * VF has no ability to enable/disable HW CRC
1753 * Keep the persistent behavior the same as Host PF
1755 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1756 if (!conf->rxmode.hw_strip_crc) {
1757 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1758 conf->rxmode.hw_strip_crc = 1;
1761 if (conf->rxmode.hw_strip_crc) {
1762 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1763 conf->rxmode.hw_strip_crc = 0;
1771 igbvf_dev_start(struct rte_eth_dev *dev)
1773 struct e1000_hw *hw =
1774 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1777 PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1779 hw->mac.ops.reset_hw(hw);
1782 igbvf_set_vfta_all(dev,1);
1784 eth_igbvf_tx_init(dev);
1786 /* This can fail when allocating mbufs for descriptor rings */
1787 ret = eth_igbvf_rx_init(dev);
1789 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1790 igb_dev_clear_queues(dev);
1798 igbvf_dev_stop(struct rte_eth_dev *dev)
1800 PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1802 igbvf_stop_adapter(dev);
1805 * Clear what we set, but we still keep shadow_vfta to
1806 * restore after device starts
1808 igbvf_set_vfta_all(dev,0);
1810 igb_dev_clear_queues(dev);
1814 igbvf_dev_close(struct rte_eth_dev *dev)
1816 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1822 igbvf_dev_stop(dev);
1825 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1827 struct e1000_mbx_info *mbx = &hw->mbx;
1830 /* After set vlan, vlan strip will also be enabled in igb driver*/
1831 msgbuf[0] = E1000_VF_SET_VLAN;
1833 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1835 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1837 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1840 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1842 struct e1000_hw *hw =
1843 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1844 struct e1000_vfta * shadow_vfta =
1845 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1846 int i = 0, j = 0, vfta = 0, mask = 1;
1848 for (i = 0; i < IGB_VFTA_SIZE; i++){
1849 vfta = shadow_vfta->vfta[i];
1852 for (j = 0; j < 32; j++){
1855 (uint16_t)((i<<5)+j), on);
1864 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1866 struct e1000_hw *hw =
1867 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868 struct e1000_vfta * shadow_vfta =
1869 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1870 uint32_t vid_idx = 0;
1871 uint32_t vid_bit = 0;
1874 PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1876 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1877 ret = igbvf_set_vfta(hw, vlan_id, !!on);
1879 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1882 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1883 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1885 /*Save what we set and retore it after device reset*/
1887 shadow_vfta->vfta[vid_idx] |= vid_bit;
1889 shadow_vfta->vfta[vid_idx] &= ~vid_bit;