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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
64 #define IGB_DEFAULT_RX_PTHRESH 8
65 #define IGB_DEFAULT_RX_HTHRESH 8
66 #define IGB_DEFAULT_RX_WTHRESH 0
68 #define IGB_DEFAULT_TX_PTHRESH 32
69 #define IGB_DEFAULT_TX_HTHRESH 0
70 #define IGB_DEFAULT_TX_WTHRESH 0
72 /* Bit shift and mask */
73 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
74 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
75 #define IGB_8_BIT_WIDTH CHAR_BIT
76 #define IGB_8_BIT_MASK UINT8_MAX
78 static int eth_igb_configure(struct rte_eth_dev *dev);
79 static int eth_igb_start(struct rte_eth_dev *dev);
80 static void eth_igb_stop(struct rte_eth_dev *dev);
81 static void eth_igb_close(struct rte_eth_dev *dev);
82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static void eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
91 static void eth_igb_infos_get(struct rte_eth_dev *dev,
92 struct rte_eth_dev_info *dev_info);
93 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
94 struct rte_eth_dev_info *dev_info);
95 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
96 struct rte_eth_fc_conf *fc_conf);
97 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
98 struct rte_eth_fc_conf *fc_conf);
99 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
100 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
101 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
102 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
104 static int igb_hardware_init(struct e1000_hw *hw);
105 static void igb_hw_control_acquire(struct e1000_hw *hw);
106 static void igb_hw_control_release(struct e1000_hw *hw);
107 static void igb_init_manageability(struct e1000_hw *hw);
108 static void igb_release_manageability(struct e1000_hw *hw);
110 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
112 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
113 uint16_t vlan_id, int on);
114 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
115 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
117 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
118 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
119 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
120 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
121 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
122 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
124 static int eth_igb_led_on(struct rte_eth_dev *dev);
125 static int eth_igb_led_off(struct rte_eth_dev *dev);
127 static void igb_intr_disable(struct e1000_hw *hw);
128 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
129 static void eth_igb_rar_set(struct rte_eth_dev *dev,
130 struct ether_addr *mac_addr,
131 uint32_t index, uint32_t pool);
132 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
134 static void igbvf_intr_disable(struct e1000_hw *hw);
135 static int igbvf_dev_configure(struct rte_eth_dev *dev);
136 static int igbvf_dev_start(struct rte_eth_dev *dev);
137 static void igbvf_dev_stop(struct rte_eth_dev *dev);
138 static void igbvf_dev_close(struct rte_eth_dev *dev);
139 static int eth_igbvf_link_update(struct e1000_hw *hw);
140 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
141 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
142 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
143 uint16_t vlan_id, int on);
144 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
145 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
146 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
147 struct rte_eth_rss_reta_entry64 *reta_conf,
149 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
150 struct rte_eth_rss_reta_entry64 *reta_conf,
153 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
154 struct rte_eth_syn_filter *filter,
156 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
157 struct rte_eth_syn_filter *filter);
158 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
159 enum rte_filter_op filter_op,
161 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
162 struct rte_eth_ntuple_filter *ntuple_filter);
163 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
164 struct rte_eth_ntuple_filter *ntuple_filter);
165 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
166 struct rte_eth_flex_filter *filter,
168 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
169 struct rte_eth_flex_filter *filter);
170 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
171 enum rte_filter_op filter_op,
173 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
174 struct rte_eth_ntuple_filter *ntuple_filter);
175 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
176 struct rte_eth_ntuple_filter *ntuple_filter);
177 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
178 struct rte_eth_ntuple_filter *filter,
180 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
181 struct rte_eth_ntuple_filter *filter);
182 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
183 enum rte_filter_op filter_op,
185 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
186 struct rte_eth_ethertype_filter *filter,
188 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
189 enum rte_filter_op filter_op,
191 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
192 struct rte_eth_ethertype_filter *filter);
193 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
194 enum rte_filter_type filter_type,
195 enum rte_filter_op filter_op,
199 * Define VF Stats MACRO for Non "cleared on read" register
201 #define UPDATE_VF_STAT(reg, last, cur) \
203 u32 latest = E1000_READ_REG(hw, reg); \
204 cur += latest - last; \
209 #define IGB_FC_PAUSE_TIME 0x0680
210 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
211 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
213 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
215 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
218 * The set of PCI devices this driver supports
220 static struct rte_pci_id pci_id_igb_map[] = {
222 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
223 #include "rte_pci_dev_ids.h"
229 * The set of PCI devices this driver supports (for 82576&I350 VF)
231 static struct rte_pci_id pci_id_igbvf_map[] = {
233 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
234 #include "rte_pci_dev_ids.h"
239 static struct eth_dev_ops eth_igb_ops = {
240 .dev_configure = eth_igb_configure,
241 .dev_start = eth_igb_start,
242 .dev_stop = eth_igb_stop,
243 .dev_close = eth_igb_close,
244 .promiscuous_enable = eth_igb_promiscuous_enable,
245 .promiscuous_disable = eth_igb_promiscuous_disable,
246 .allmulticast_enable = eth_igb_allmulticast_enable,
247 .allmulticast_disable = eth_igb_allmulticast_disable,
248 .link_update = eth_igb_link_update,
249 .stats_get = eth_igb_stats_get,
250 .stats_reset = eth_igb_stats_reset,
251 .dev_infos_get = eth_igb_infos_get,
252 .mtu_set = eth_igb_mtu_set,
253 .vlan_filter_set = eth_igb_vlan_filter_set,
254 .vlan_tpid_set = eth_igb_vlan_tpid_set,
255 .vlan_offload_set = eth_igb_vlan_offload_set,
256 .rx_queue_setup = eth_igb_rx_queue_setup,
257 .rx_queue_release = eth_igb_rx_queue_release,
258 .rx_queue_count = eth_igb_rx_queue_count,
259 .rx_descriptor_done = eth_igb_rx_descriptor_done,
260 .tx_queue_setup = eth_igb_tx_queue_setup,
261 .tx_queue_release = eth_igb_tx_queue_release,
262 .dev_led_on = eth_igb_led_on,
263 .dev_led_off = eth_igb_led_off,
264 .flow_ctrl_get = eth_igb_flow_ctrl_get,
265 .flow_ctrl_set = eth_igb_flow_ctrl_set,
266 .mac_addr_add = eth_igb_rar_set,
267 .mac_addr_remove = eth_igb_rar_clear,
268 .reta_update = eth_igb_rss_reta_update,
269 .reta_query = eth_igb_rss_reta_query,
270 .rss_hash_update = eth_igb_rss_hash_update,
271 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
272 .filter_ctrl = eth_igb_filter_ctrl,
276 * dev_ops for virtual function, bare necessities for basic vf
277 * operation have been implemented
279 static struct eth_dev_ops igbvf_eth_dev_ops = {
280 .dev_configure = igbvf_dev_configure,
281 .dev_start = igbvf_dev_start,
282 .dev_stop = igbvf_dev_stop,
283 .dev_close = igbvf_dev_close,
284 .link_update = eth_igb_link_update,
285 .stats_get = eth_igbvf_stats_get,
286 .stats_reset = eth_igbvf_stats_reset,
287 .vlan_filter_set = igbvf_vlan_filter_set,
288 .dev_infos_get = eth_igbvf_infos_get,
289 .rx_queue_setup = eth_igb_rx_queue_setup,
290 .rx_queue_release = eth_igb_rx_queue_release,
291 .tx_queue_setup = eth_igb_tx_queue_setup,
292 .tx_queue_release = eth_igb_tx_queue_release,
296 * Atomically reads the link status information from global
297 * structure rte_eth_dev.
300 * - Pointer to the structure rte_eth_dev to read from.
301 * - Pointer to the buffer to be saved with the link status.
304 * - On success, zero.
305 * - On failure, negative value.
308 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
309 struct rte_eth_link *link)
311 struct rte_eth_link *dst = link;
312 struct rte_eth_link *src = &(dev->data->dev_link);
314 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
315 *(uint64_t *)src) == 0)
322 * Atomically writes the link status information into global
323 * structure rte_eth_dev.
326 * - Pointer to the structure rte_eth_dev to read from.
327 * - Pointer to the buffer to be saved with the link status.
330 * - On success, zero.
331 * - On failure, negative value.
334 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
335 struct rte_eth_link *link)
337 struct rte_eth_link *dst = &(dev->data->dev_link);
338 struct rte_eth_link *src = link;
340 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
341 *(uint64_t *)src) == 0)
348 igb_intr_enable(struct rte_eth_dev *dev)
350 struct e1000_interrupt *intr =
351 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
352 struct e1000_hw *hw =
353 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
355 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
356 E1000_WRITE_FLUSH(hw);
360 igb_intr_disable(struct e1000_hw *hw)
362 E1000_WRITE_REG(hw, E1000_IMC, ~0);
363 E1000_WRITE_FLUSH(hw);
366 static inline int32_t
367 igb_pf_reset_hw(struct e1000_hw *hw)
372 status = e1000_reset_hw(hw);
374 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
375 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
376 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
377 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
378 E1000_WRITE_FLUSH(hw);
384 igb_identify_hardware(struct rte_eth_dev *dev)
386 struct e1000_hw *hw =
387 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
389 hw->vendor_id = dev->pci_dev->id.vendor_id;
390 hw->device_id = dev->pci_dev->id.device_id;
391 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
392 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
394 e1000_set_mac_type(hw);
396 /* need to check if it is a vf device below */
400 igb_reset_swfw_lock(struct e1000_hw *hw)
405 * Do mac ops initialization manually here, since we will need
406 * some function pointers set by this call.
408 ret_val = e1000_init_mac_params(hw);
413 * SMBI lock should not fail in this early stage. If this is the case,
414 * it is due to an improper exit of the application.
415 * So force the release of the faulty lock.
417 if (e1000_get_hw_semaphore_generic(hw) < 0) {
418 PMD_DRV_LOG(DEBUG, "SMBI lock released");
420 e1000_put_hw_semaphore_generic(hw);
422 if (hw->mac.ops.acquire_swfw_sync != NULL) {
426 * Phy lock should not fail in this early stage. If this is the case,
427 * it is due to an improper exit of the application.
428 * So force the release of the faulty lock.
430 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
431 if (hw->bus.func > E1000_FUNC_1)
433 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
434 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
437 hw->mac.ops.release_swfw_sync(hw, mask);
440 * This one is more tricky since it is common to all ports; but
441 * swfw_sync retries last long enough (1s) to be almost sure that if
442 * lock can not be taken it is due to an improper lock of the
445 mask = E1000_SWFW_EEP_SM;
446 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
447 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
449 hw->mac.ops.release_swfw_sync(hw, mask);
452 return E1000_SUCCESS;
456 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
457 struct rte_eth_dev *eth_dev)
460 struct rte_pci_device *pci_dev;
461 struct e1000_hw *hw =
462 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
463 struct e1000_vfta * shadow_vfta =
464 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
465 struct e1000_filter_info *filter_info =
466 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
469 pci_dev = eth_dev->pci_dev;
470 eth_dev->dev_ops = ð_igb_ops;
471 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
472 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
474 /* for secondary processes, we don't initialise any further as primary
475 * has already done this work. Only check we don't need a different
477 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
478 if (eth_dev->data->scattered_rx)
479 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
483 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
485 igb_identify_hardware(eth_dev);
486 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
491 e1000_get_bus_info(hw);
493 /* Reset any pending lock */
494 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
499 /* Finish initialization */
500 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
506 hw->phy.autoneg_wait_to_complete = 0;
507 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
510 if (hw->phy.media_type == e1000_media_type_copper) {
511 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
512 hw->phy.disable_polarity_correction = 0;
513 hw->phy.ms_type = e1000_ms_hw_default;
517 * Start from a known state, this is important in reading the nvm
522 /* Make sure we have a good EEPROM before we read from it */
523 if (e1000_validate_nvm_checksum(hw) < 0) {
525 * Some PCI-E parts fail the first check due to
526 * the link being in sleep state, call it again,
527 * if it fails a second time its a real issue.
529 if (e1000_validate_nvm_checksum(hw) < 0) {
530 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
536 /* Read the permanent MAC address out of the EEPROM */
537 if (e1000_read_mac_addr(hw) != 0) {
538 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
543 /* Allocate memory for storing MAC addresses */
544 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
545 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
546 if (eth_dev->data->mac_addrs == NULL) {
547 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
548 "store MAC addresses",
549 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
554 /* Copy the permanent MAC address */
555 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
557 /* initialize the vfta */
558 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
560 /* Now initialize the hardware */
561 if (igb_hardware_init(hw) != 0) {
562 PMD_INIT_LOG(ERR, "Hardware initialization failed");
563 rte_free(eth_dev->data->mac_addrs);
564 eth_dev->data->mac_addrs = NULL;
568 hw->mac.get_link_status = 1;
570 /* Indicate SOL/IDER usage */
571 if (e1000_check_reset_block(hw) < 0) {
572 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
576 /* initialize PF if max_vfs not zero */
577 igb_pf_host_init(eth_dev);
579 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
580 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
581 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
582 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
583 E1000_WRITE_FLUSH(hw);
585 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
586 eth_dev->data->port_id, pci_dev->id.vendor_id,
587 pci_dev->id.device_id);
589 rte_intr_callback_register(&(pci_dev->intr_handle),
590 eth_igb_interrupt_handler, (void *)eth_dev);
592 /* enable uio intr after callback register */
593 rte_intr_enable(&(pci_dev->intr_handle));
595 /* enable support intr */
596 igb_intr_enable(eth_dev);
598 TAILQ_INIT(&filter_info->flex_list);
599 filter_info->flex_mask = 0;
600 TAILQ_INIT(&filter_info->twotuple_list);
601 filter_info->twotuple_mask = 0;
602 TAILQ_INIT(&filter_info->fivetuple_list);
603 filter_info->fivetuple_mask = 0;
608 igb_hw_control_release(hw);
614 * Virtual Function device init
617 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
618 struct rte_eth_dev *eth_dev)
620 struct rte_pci_device *pci_dev;
621 struct e1000_hw *hw =
622 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
625 PMD_INIT_FUNC_TRACE();
627 eth_dev->dev_ops = &igbvf_eth_dev_ops;
628 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
629 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
631 /* for secondary processes, we don't initialise any further as primary
632 * has already done this work. Only check we don't need a different
634 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
635 if (eth_dev->data->scattered_rx)
636 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
640 pci_dev = eth_dev->pci_dev;
642 hw->device_id = pci_dev->id.device_id;
643 hw->vendor_id = pci_dev->id.vendor_id;
644 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
646 /* Initialize the shared code (base driver) */
647 diag = e1000_setup_init_funcs(hw, TRUE);
649 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
654 /* init_mailbox_params */
655 hw->mbx.ops.init_params(hw);
657 /* Disable the interrupts for VF */
658 igbvf_intr_disable(hw);
660 diag = hw->mac.ops.reset_hw(hw);
662 /* Allocate memory for storing MAC addresses */
663 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
664 hw->mac.rar_entry_count, 0);
665 if (eth_dev->data->mac_addrs == NULL) {
667 "Failed to allocate %d bytes needed to store MAC "
669 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
673 /* Copy the permanent MAC address */
674 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
675 ð_dev->data->mac_addrs[0]);
677 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
679 eth_dev->data->port_id, pci_dev->id.vendor_id,
680 pci_dev->id.device_id, "igb_mac_82576_vf");
685 static struct eth_driver rte_igb_pmd = {
687 .name = "rte_igb_pmd",
688 .id_table = pci_id_igb_map,
689 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
691 .eth_dev_init = eth_igb_dev_init,
692 .dev_private_size = sizeof(struct e1000_adapter),
696 * virtual function driver struct
698 static struct eth_driver rte_igbvf_pmd = {
700 .name = "rte_igbvf_pmd",
701 .id_table = pci_id_igbvf_map,
702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
704 .eth_dev_init = eth_igbvf_dev_init,
705 .dev_private_size = sizeof(struct e1000_adapter),
709 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
711 rte_eth_driver_register(&rte_igb_pmd);
716 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
718 struct e1000_hw *hw =
719 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
720 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
721 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
722 rctl |= E1000_RCTL_VFE;
723 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
727 * VF Driver initialization routine.
728 * Invoked one at EAL init time.
729 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
732 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
734 PMD_INIT_FUNC_TRACE();
736 rte_eth_driver_register(&rte_igbvf_pmd);
741 eth_igb_configure(struct rte_eth_dev *dev)
743 struct e1000_interrupt *intr =
744 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
746 PMD_INIT_FUNC_TRACE();
747 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
748 PMD_INIT_FUNC_TRACE();
754 eth_igb_start(struct rte_eth_dev *dev)
756 struct e1000_hw *hw =
757 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
761 PMD_INIT_FUNC_TRACE();
763 /* Power up the phy. Needed to make the link go Up */
764 e1000_power_up_phy(hw);
767 * Packet Buffer Allocation (PBA)
768 * Writing PBA sets the receive portion of the buffer
769 * the remainder is used for the transmit buffer.
771 if (hw->mac.type == e1000_82575) {
774 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
775 E1000_WRITE_REG(hw, E1000_PBA, pba);
778 /* Put the address into the Receive Address Array */
779 e1000_rar_set(hw, hw->mac.addr, 0);
781 /* Initialize the hardware */
782 if (igb_hardware_init(hw)) {
783 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
787 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
789 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
790 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
791 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
792 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
793 E1000_WRITE_FLUSH(hw);
795 /* configure PF module if SRIOV enabled */
796 igb_pf_host_configure(dev);
798 /* Configure for OS presence */
799 igb_init_manageability(hw);
801 eth_igb_tx_init(dev);
803 /* This can fail when allocating mbufs for descriptor rings */
804 ret = eth_igb_rx_init(dev);
806 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
807 igb_dev_clear_queues(dev);
811 e1000_clear_hw_cntrs_base_generic(hw);
814 * VLAN Offload Settings
816 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
817 ETH_VLAN_EXTEND_MASK;
818 eth_igb_vlan_offload_set(dev, mask);
820 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
821 /* Enable VLAN filter since VMDq always use VLAN filter */
822 igb_vmdq_vlan_hw_filter_enable(dev);
826 * Configure the Interrupt Moderation register (EITR) with the maximum
827 * possible value (0xFFFF) to minimize "System Partial Write" issued by
828 * spurious [DMA] memory updates of RX and TX ring descriptors.
830 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
831 * spurious memory updates per second should be expected.
832 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
834 * Because interrupts are not used at all, the MSI-X is not activated
835 * and interrupt moderation is controlled by EITR[0].
837 * Note that having [almost] disabled memory updates of RX and TX ring
838 * descriptors through the Interrupt Moderation mechanism, memory
839 * updates of ring descriptors are now moderated by the configurable
840 * value of Write-Back Threshold registers.
842 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
843 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
844 (hw->mac.type == e1000_i211)) {
847 /* Enable all RX & TX queues in the IVAR registers */
848 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
849 for (i = 0; i < 8; i++)
850 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
852 /* Configure EITR with the maximum possible value (0xFFFF) */
853 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
856 /* Setup link speed and duplex */
857 switch (dev->data->dev_conf.link_speed) {
858 case ETH_LINK_SPEED_AUTONEG:
859 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
860 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
861 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
862 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
863 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
864 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
866 goto error_invalid_config;
868 case ETH_LINK_SPEED_10:
869 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
870 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
871 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
872 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
873 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
874 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
876 goto error_invalid_config;
878 case ETH_LINK_SPEED_100:
879 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
880 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
881 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
882 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
883 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
884 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
886 goto error_invalid_config;
888 case ETH_LINK_SPEED_1000:
889 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
890 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
891 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
893 goto error_invalid_config;
895 case ETH_LINK_SPEED_10000:
897 goto error_invalid_config;
899 e1000_setup_link(hw);
901 /* check if lsc interrupt feature is enabled */
902 if (dev->data->dev_conf.intr_conf.lsc != 0)
903 ret = eth_igb_lsc_interrupt_setup(dev);
905 /* resume enabled intr since hw reset */
906 igb_intr_enable(dev);
908 PMD_INIT_LOG(DEBUG, "<<");
912 error_invalid_config:
913 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
914 dev->data->dev_conf.link_speed,
915 dev->data->dev_conf.link_duplex, dev->data->port_id);
916 igb_dev_clear_queues(dev);
920 /*********************************************************************
922 * This routine disables all traffic on the adapter by issuing a
923 * global reset on the MAC.
925 **********************************************************************/
927 eth_igb_stop(struct rte_eth_dev *dev)
929 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
930 struct e1000_filter_info *filter_info =
931 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
932 struct rte_eth_link link;
933 struct e1000_flex_filter *p_flex;
934 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
935 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
937 igb_intr_disable(hw);
939 E1000_WRITE_REG(hw, E1000_WUC, 0);
941 /* Set bit for Go Link disconnect */
942 if (hw->mac.type >= e1000_82580) {
945 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
946 phpm_reg |= E1000_82580_PM_GO_LINKD;
947 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
950 /* Power down the phy. Needed to make the link go Down */
951 e1000_power_down_phy(hw);
953 igb_dev_clear_queues(dev);
955 /* clear the recorded link status */
956 memset(&link, 0, sizeof(link));
957 rte_igb_dev_atomic_write_link_status(dev, &link);
959 /* Remove all flex filters of the device */
960 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
961 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
964 filter_info->flex_mask = 0;
966 /* Remove all ntuple filters of the device */
967 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
968 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
969 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
970 TAILQ_REMOVE(&filter_info->fivetuple_list,
974 filter_info->fivetuple_mask = 0;
975 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
976 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
977 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
978 TAILQ_REMOVE(&filter_info->twotuple_list,
982 filter_info->twotuple_mask = 0;
986 eth_igb_close(struct rte_eth_dev *dev)
988 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
989 struct rte_eth_link link;
992 e1000_phy_hw_reset(hw);
993 igb_release_manageability(hw);
994 igb_hw_control_release(hw);
996 /* Clear bit for Go Link disconnect */
997 if (hw->mac.type >= e1000_82580) {
1000 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1001 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1002 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1005 igb_dev_clear_queues(dev);
1007 memset(&link, 0, sizeof(link));
1008 rte_igb_dev_atomic_write_link_status(dev, &link);
1012 igb_get_rx_buffer_size(struct e1000_hw *hw)
1014 uint32_t rx_buf_size;
1015 if (hw->mac.type == e1000_82576) {
1016 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1017 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1018 /* PBS needs to be translated according to a lookup table */
1019 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1020 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1021 rx_buf_size = (rx_buf_size << 10);
1022 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1023 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1025 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1031 /*********************************************************************
1033 * Initialize the hardware
1035 **********************************************************************/
1037 igb_hardware_init(struct e1000_hw *hw)
1039 uint32_t rx_buf_size;
1042 /* Let the firmware know the OS is in control */
1043 igb_hw_control_acquire(hw);
1046 * These parameters control the automatic generation (Tx) and
1047 * response (Rx) to Ethernet PAUSE frames.
1048 * - High water mark should allow for at least two standard size (1518)
1049 * frames to be received after sending an XOFF.
1050 * - Low water mark works best when it is very near the high water mark.
1051 * This allows the receiver to restart by sending XON when it has
1052 * drained a bit. Here we use an arbitrary value of 1500 which will
1053 * restart after one full frame is pulled from the buffer. There
1054 * could be several smaller frames in the buffer and if so they will
1055 * not trigger the XON until their total number reduces the buffer
1057 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1059 rx_buf_size = igb_get_rx_buffer_size(hw);
1061 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1062 hw->fc.low_water = hw->fc.high_water - 1500;
1063 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1064 hw->fc.send_xon = 1;
1066 /* Set Flow control, use the tunable location if sane */
1067 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1068 hw->fc.requested_mode = igb_fc_setting;
1070 hw->fc.requested_mode = e1000_fc_none;
1072 /* Issue a global reset */
1073 igb_pf_reset_hw(hw);
1074 E1000_WRITE_REG(hw, E1000_WUC, 0);
1076 diag = e1000_init_hw(hw);
1080 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1081 e1000_get_phy_info(hw);
1082 e1000_check_for_link(hw);
1087 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1089 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1091 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1092 struct e1000_hw_stats *stats =
1093 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1096 if(hw->phy.media_type == e1000_media_type_copper ||
1097 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1099 E1000_READ_REG(hw,E1000_SYMERRS);
1100 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1103 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1104 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1105 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1106 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1108 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1109 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1110 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1111 stats->dc += E1000_READ_REG(hw, E1000_DC);
1112 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1113 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1114 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1116 ** For watchdog management we need to know if we have been
1117 ** paused during the last interval, so capture that here.
1119 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1120 stats->xoffrxc += pause_frames;
1121 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1122 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1123 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1124 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1125 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1126 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1127 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1128 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1129 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1130 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1131 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1132 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1134 /* For the 64-bit byte counters the low dword must be read first. */
1135 /* Both registers clear on the read of the high dword */
1137 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1138 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1139 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1140 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1142 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1143 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1144 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1145 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1146 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1148 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1149 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1151 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1152 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1153 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1154 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1155 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1156 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1157 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1158 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1159 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1160 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1162 /* Interrupt Counts */
1164 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1165 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1166 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1167 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1168 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1169 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1170 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1171 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1172 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1174 /* Host to Card Statistics */
1176 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1177 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1178 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1179 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1180 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1181 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1182 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1183 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1184 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1185 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1186 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1187 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1188 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1189 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1191 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1192 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1193 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1194 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1195 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1196 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1198 if (rte_stats == NULL)
1202 rte_stats->ibadcrc = stats->crcerrs;
1203 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1204 rte_stats->imissed = stats->mpc;
1205 rte_stats->ierrors = rte_stats->ibadcrc +
1206 rte_stats->ibadlen +
1207 rte_stats->imissed +
1208 stats->rxerrc + stats->algnerrc + stats->cexterr;
1211 rte_stats->oerrors = stats->ecol + stats->latecol;
1213 /* XON/XOFF pause frames */
1214 rte_stats->tx_pause_xon = stats->xontxc;
1215 rte_stats->rx_pause_xon = stats->xonrxc;
1216 rte_stats->tx_pause_xoff = stats->xofftxc;
1217 rte_stats->rx_pause_xoff = stats->xoffrxc;
1219 rte_stats->ipackets = stats->gprc;
1220 rte_stats->opackets = stats->gptc;
1221 rte_stats->ibytes = stats->gorc;
1222 rte_stats->obytes = stats->gotc;
1226 eth_igb_stats_reset(struct rte_eth_dev *dev)
1228 struct e1000_hw_stats *hw_stats =
1229 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1231 /* HW registers are cleared on read */
1232 eth_igb_stats_get(dev, NULL);
1234 /* Reset software totals */
1235 memset(hw_stats, 0, sizeof(*hw_stats));
1239 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1241 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1242 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1243 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1245 /* Good Rx packets, include VF loopback */
1246 UPDATE_VF_STAT(E1000_VFGPRC,
1247 hw_stats->last_gprc, hw_stats->gprc);
1249 /* Good Rx octets, include VF loopback */
1250 UPDATE_VF_STAT(E1000_VFGORC,
1251 hw_stats->last_gorc, hw_stats->gorc);
1253 /* Good Tx packets, include VF loopback */
1254 UPDATE_VF_STAT(E1000_VFGPTC,
1255 hw_stats->last_gptc, hw_stats->gptc);
1257 /* Good Tx octets, include VF loopback */
1258 UPDATE_VF_STAT(E1000_VFGOTC,
1259 hw_stats->last_gotc, hw_stats->gotc);
1261 /* Rx Multicst packets */
1262 UPDATE_VF_STAT(E1000_VFMPRC,
1263 hw_stats->last_mprc, hw_stats->mprc);
1265 /* Good Rx loopback packets */
1266 UPDATE_VF_STAT(E1000_VFGPRLBC,
1267 hw_stats->last_gprlbc, hw_stats->gprlbc);
1269 /* Good Rx loopback octets */
1270 UPDATE_VF_STAT(E1000_VFGORLBC,
1271 hw_stats->last_gorlbc, hw_stats->gorlbc);
1273 /* Good Tx loopback packets */
1274 UPDATE_VF_STAT(E1000_VFGPTLBC,
1275 hw_stats->last_gptlbc, hw_stats->gptlbc);
1277 /* Good Tx loopback octets */
1278 UPDATE_VF_STAT(E1000_VFGOTLBC,
1279 hw_stats->last_gotlbc, hw_stats->gotlbc);
1281 if (rte_stats == NULL)
1284 rte_stats->ipackets = hw_stats->gprc;
1285 rte_stats->ibytes = hw_stats->gorc;
1286 rte_stats->opackets = hw_stats->gptc;
1287 rte_stats->obytes = hw_stats->gotc;
1288 rte_stats->imcasts = hw_stats->mprc;
1289 rte_stats->ilbpackets = hw_stats->gprlbc;
1290 rte_stats->ilbbytes = hw_stats->gorlbc;
1291 rte_stats->olbpackets = hw_stats->gptlbc;
1292 rte_stats->olbbytes = hw_stats->gotlbc;
1297 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1299 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1300 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1302 /* Sync HW register to the last stats */
1303 eth_igbvf_stats_get(dev, NULL);
1305 /* reset HW current stats*/
1306 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1307 offsetof(struct e1000_vf_stats, gprc));
1312 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1314 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1317 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1318 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1319 dev_info->rx_offload_capa =
1320 DEV_RX_OFFLOAD_VLAN_STRIP |
1321 DEV_RX_OFFLOAD_IPV4_CKSUM |
1322 DEV_RX_OFFLOAD_UDP_CKSUM |
1323 DEV_RX_OFFLOAD_TCP_CKSUM;
1324 dev_info->tx_offload_capa =
1325 DEV_TX_OFFLOAD_VLAN_INSERT |
1326 DEV_TX_OFFLOAD_IPV4_CKSUM |
1327 DEV_TX_OFFLOAD_UDP_CKSUM |
1328 DEV_TX_OFFLOAD_TCP_CKSUM |
1329 DEV_TX_OFFLOAD_SCTP_CKSUM;
1331 switch (hw->mac.type) {
1333 dev_info->max_rx_queues = 4;
1334 dev_info->max_tx_queues = 4;
1335 dev_info->max_vmdq_pools = 0;
1339 dev_info->max_rx_queues = 16;
1340 dev_info->max_tx_queues = 16;
1341 dev_info->max_vmdq_pools = ETH_8_POOLS;
1342 dev_info->vmdq_queue_num = 16;
1346 dev_info->max_rx_queues = 8;
1347 dev_info->max_tx_queues = 8;
1348 dev_info->max_vmdq_pools = ETH_8_POOLS;
1349 dev_info->vmdq_queue_num = 8;
1353 dev_info->max_rx_queues = 8;
1354 dev_info->max_tx_queues = 8;
1355 dev_info->max_vmdq_pools = ETH_8_POOLS;
1356 dev_info->vmdq_queue_num = 8;
1360 dev_info->max_rx_queues = 8;
1361 dev_info->max_tx_queues = 8;
1365 dev_info->max_rx_queues = 4;
1366 dev_info->max_tx_queues = 4;
1367 dev_info->max_vmdq_pools = 0;
1371 dev_info->max_rx_queues = 2;
1372 dev_info->max_tx_queues = 2;
1373 dev_info->max_vmdq_pools = 0;
1377 /* Should not happen */
1380 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1381 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1383 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1385 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1386 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1387 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1389 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1393 dev_info->default_txconf = (struct rte_eth_txconf) {
1395 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1396 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1397 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1404 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1406 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1409 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1410 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1411 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1412 DEV_RX_OFFLOAD_IPV4_CKSUM |
1413 DEV_RX_OFFLOAD_UDP_CKSUM |
1414 DEV_RX_OFFLOAD_TCP_CKSUM;
1415 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1416 DEV_TX_OFFLOAD_IPV4_CKSUM |
1417 DEV_TX_OFFLOAD_UDP_CKSUM |
1418 DEV_TX_OFFLOAD_TCP_CKSUM |
1419 DEV_TX_OFFLOAD_SCTP_CKSUM;
1420 switch (hw->mac.type) {
1422 dev_info->max_rx_queues = 2;
1423 dev_info->max_tx_queues = 2;
1425 case e1000_vfadapt_i350:
1426 dev_info->max_rx_queues = 1;
1427 dev_info->max_tx_queues = 1;
1430 /* Should not happen */
1434 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1436 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1437 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1438 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1440 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1444 dev_info->default_txconf = (struct rte_eth_txconf) {
1446 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1447 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1448 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1454 /* return 0 means link status changed, -1 means not changed */
1456 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1458 struct e1000_hw *hw =
1459 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1460 struct rte_eth_link link, old;
1461 int link_check, count;
1464 hw->mac.get_link_status = 1;
1466 /* possible wait-to-complete in up to 9 seconds */
1467 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1468 /* Read the real link status */
1469 switch (hw->phy.media_type) {
1470 case e1000_media_type_copper:
1471 /* Do the work to read phy */
1472 e1000_check_for_link(hw);
1473 link_check = !hw->mac.get_link_status;
1476 case e1000_media_type_fiber:
1477 e1000_check_for_link(hw);
1478 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1482 case e1000_media_type_internal_serdes:
1483 e1000_check_for_link(hw);
1484 link_check = hw->mac.serdes_has_link;
1487 /* VF device is type_unknown */
1488 case e1000_media_type_unknown:
1489 eth_igbvf_link_update(hw);
1490 link_check = !hw->mac.get_link_status;
1496 if (link_check || wait_to_complete == 0)
1498 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1500 memset(&link, 0, sizeof(link));
1501 rte_igb_dev_atomic_read_link_status(dev, &link);
1504 /* Now we check if a transition has happened */
1506 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1508 link.link_status = 1;
1509 } else if (!link_check) {
1510 link.link_speed = 0;
1511 link.link_duplex = 0;
1512 link.link_status = 0;
1514 rte_igb_dev_atomic_write_link_status(dev, &link);
1517 if (old.link_status == link.link_status)
1525 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1526 * For ASF and Pass Through versions of f/w this means
1527 * that the driver is loaded.
1530 igb_hw_control_acquire(struct e1000_hw *hw)
1534 /* Let firmware know the driver has taken over */
1535 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1536 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1540 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1541 * For ASF and Pass Through versions of f/w this means that the
1542 * driver is no longer loaded.
1545 igb_hw_control_release(struct e1000_hw *hw)
1549 /* Let firmware taken over control of h/w */
1550 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1551 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1552 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1556 * Bit of a misnomer, what this really means is
1557 * to enable OS management of the system... aka
1558 * to disable special hardware management features.
1561 igb_init_manageability(struct e1000_hw *hw)
1563 if (e1000_enable_mng_pass_thru(hw)) {
1564 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1565 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1567 /* disable hardware interception of ARP */
1568 manc &= ~(E1000_MANC_ARP_EN);
1570 /* enable receiving management packets to the host */
1571 manc |= E1000_MANC_EN_MNG2HOST;
1572 manc2h |= 1 << 5; /* Mng Port 623 */
1573 manc2h |= 1 << 6; /* Mng Port 664 */
1574 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1575 E1000_WRITE_REG(hw, E1000_MANC, manc);
1580 igb_release_manageability(struct e1000_hw *hw)
1582 if (e1000_enable_mng_pass_thru(hw)) {
1583 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1585 manc |= E1000_MANC_ARP_EN;
1586 manc &= ~E1000_MANC_EN_MNG2HOST;
1588 E1000_WRITE_REG(hw, E1000_MANC, manc);
1593 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1595 struct e1000_hw *hw =
1596 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599 rctl = E1000_READ_REG(hw, E1000_RCTL);
1600 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1601 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1605 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1607 struct e1000_hw *hw =
1608 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611 rctl = E1000_READ_REG(hw, E1000_RCTL);
1612 rctl &= (~E1000_RCTL_UPE);
1613 if (dev->data->all_multicast == 1)
1614 rctl |= E1000_RCTL_MPE;
1616 rctl &= (~E1000_RCTL_MPE);
1617 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1621 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1623 struct e1000_hw *hw =
1624 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627 rctl = E1000_READ_REG(hw, E1000_RCTL);
1628 rctl |= E1000_RCTL_MPE;
1629 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1633 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1635 struct e1000_hw *hw =
1636 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639 if (dev->data->promiscuous == 1)
1640 return; /* must remain in all_multicast mode */
1641 rctl = E1000_READ_REG(hw, E1000_RCTL);
1642 rctl &= (~E1000_RCTL_MPE);
1643 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1647 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1649 struct e1000_hw *hw =
1650 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651 struct e1000_vfta * shadow_vfta =
1652 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1657 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1658 E1000_VFTA_ENTRY_MASK);
1659 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1660 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1665 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1667 /* update local VFTA copy */
1668 shadow_vfta->vfta[vid_idx] = vfta;
1674 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1676 struct e1000_hw *hw =
1677 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678 uint32_t reg = ETHER_TYPE_VLAN ;
1680 reg |= (tpid << 16);
1681 E1000_WRITE_REG(hw, E1000_VET, reg);
1685 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1687 struct e1000_hw *hw =
1688 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 /* Filter Table Disable */
1692 reg = E1000_READ_REG(hw, E1000_RCTL);
1693 reg &= ~E1000_RCTL_CFIEN;
1694 reg &= ~E1000_RCTL_VFE;
1695 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1699 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1701 struct e1000_hw *hw =
1702 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703 struct e1000_vfta * shadow_vfta =
1704 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1708 /* Filter Table Enable, CFI not used for packet acceptance */
1709 reg = E1000_READ_REG(hw, E1000_RCTL);
1710 reg &= ~E1000_RCTL_CFIEN;
1711 reg |= E1000_RCTL_VFE;
1712 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1714 /* restore VFTA table */
1715 for (i = 0; i < IGB_VFTA_SIZE; i++)
1716 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1720 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1722 struct e1000_hw *hw =
1723 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726 /* VLAN Mode Disable */
1727 reg = E1000_READ_REG(hw, E1000_CTRL);
1728 reg &= ~E1000_CTRL_VME;
1729 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1733 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1735 struct e1000_hw *hw =
1736 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739 /* VLAN Mode Enable */
1740 reg = E1000_READ_REG(hw, E1000_CTRL);
1741 reg |= E1000_CTRL_VME;
1742 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1746 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1748 struct e1000_hw *hw =
1749 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752 /* CTRL_EXT: Extended VLAN */
1753 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1754 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1755 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1757 /* Update maximum packet length */
1758 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1759 E1000_WRITE_REG(hw, E1000_RLPML,
1760 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1765 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1767 struct e1000_hw *hw =
1768 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771 /* CTRL_EXT: Extended VLAN */
1772 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1773 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1774 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1776 /* Update maximum packet length */
1777 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1778 E1000_WRITE_REG(hw, E1000_RLPML,
1779 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1784 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1786 if(mask & ETH_VLAN_STRIP_MASK){
1787 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1788 igb_vlan_hw_strip_enable(dev);
1790 igb_vlan_hw_strip_disable(dev);
1793 if(mask & ETH_VLAN_FILTER_MASK){
1794 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1795 igb_vlan_hw_filter_enable(dev);
1797 igb_vlan_hw_filter_disable(dev);
1800 if(mask & ETH_VLAN_EXTEND_MASK){
1801 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1802 igb_vlan_hw_extend_enable(dev);
1804 igb_vlan_hw_extend_disable(dev);
1810 * It enables the interrupt mask and then enable the interrupt.
1813 * Pointer to struct rte_eth_dev.
1816 * - On success, zero.
1817 * - On failure, a negative value.
1820 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1822 struct e1000_interrupt *intr =
1823 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1825 intr->mask |= E1000_ICR_LSC;
1831 * It reads ICR and gets interrupt causes, check it and set a bit flag
1832 * to update link status.
1835 * Pointer to struct rte_eth_dev.
1838 * - On success, zero.
1839 * - On failure, a negative value.
1842 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1845 struct e1000_hw *hw =
1846 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 struct e1000_interrupt *intr =
1848 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1850 igb_intr_disable(hw);
1852 /* read-on-clear nic registers here */
1853 icr = E1000_READ_REG(hw, E1000_ICR);
1856 if (icr & E1000_ICR_LSC) {
1857 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1860 if (icr & E1000_ICR_VMMB)
1861 intr->flags |= E1000_FLAG_MAILBOX;
1867 * It executes link_update after knowing an interrupt is prsent.
1870 * Pointer to struct rte_eth_dev.
1873 * - On success, zero.
1874 * - On failure, a negative value.
1877 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1879 struct e1000_hw *hw =
1880 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881 struct e1000_interrupt *intr =
1882 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1883 uint32_t tctl, rctl;
1884 struct rte_eth_link link;
1887 if (intr->flags & E1000_FLAG_MAILBOX) {
1888 igb_pf_mbx_process(dev);
1889 intr->flags &= ~E1000_FLAG_MAILBOX;
1892 igb_intr_enable(dev);
1893 rte_intr_enable(&(dev->pci_dev->intr_handle));
1895 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1896 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1898 /* set get_link_status to check register later */
1899 hw->mac.get_link_status = 1;
1900 ret = eth_igb_link_update(dev, 0);
1902 /* check if link has changed */
1906 memset(&link, 0, sizeof(link));
1907 rte_igb_dev_atomic_read_link_status(dev, &link);
1908 if (link.link_status) {
1910 " Port %d: Link Up - speed %u Mbps - %s",
1912 (unsigned)link.link_speed,
1913 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1914 "full-duplex" : "half-duplex");
1916 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1917 dev->data->port_id);
1919 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1920 dev->pci_dev->addr.domain,
1921 dev->pci_dev->addr.bus,
1922 dev->pci_dev->addr.devid,
1923 dev->pci_dev->addr.function);
1924 tctl = E1000_READ_REG(hw, E1000_TCTL);
1925 rctl = E1000_READ_REG(hw, E1000_RCTL);
1926 if (link.link_status) {
1928 tctl |= E1000_TCTL_EN;
1929 rctl |= E1000_RCTL_EN;
1932 tctl &= ~E1000_TCTL_EN;
1933 rctl &= ~E1000_RCTL_EN;
1935 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1936 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1937 E1000_WRITE_FLUSH(hw);
1938 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1945 * Interrupt handler which shall be registered at first.
1948 * Pointer to interrupt handle.
1950 * The address of parameter (struct rte_eth_dev *) regsitered before.
1956 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1959 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1961 eth_igb_interrupt_get_status(dev);
1962 eth_igb_interrupt_action(dev);
1966 eth_igb_led_on(struct rte_eth_dev *dev)
1968 struct e1000_hw *hw;
1970 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1971 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1975 eth_igb_led_off(struct rte_eth_dev *dev)
1977 struct e1000_hw *hw;
1979 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1984 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1986 struct e1000_hw *hw;
1991 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992 fc_conf->pause_time = hw->fc.pause_time;
1993 fc_conf->high_water = hw->fc.high_water;
1994 fc_conf->low_water = hw->fc.low_water;
1995 fc_conf->send_xon = hw->fc.send_xon;
1996 fc_conf->autoneg = hw->mac.autoneg;
1999 * Return rx_pause and tx_pause status according to actual setting of
2000 * the TFCE and RFCE bits in the CTRL register.
2002 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2003 if (ctrl & E1000_CTRL_TFCE)
2008 if (ctrl & E1000_CTRL_RFCE)
2013 if (rx_pause && tx_pause)
2014 fc_conf->mode = RTE_FC_FULL;
2016 fc_conf->mode = RTE_FC_RX_PAUSE;
2018 fc_conf->mode = RTE_FC_TX_PAUSE;
2020 fc_conf->mode = RTE_FC_NONE;
2026 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2028 struct e1000_hw *hw;
2030 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2036 uint32_t rx_buf_size;
2037 uint32_t max_high_water;
2040 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041 if (fc_conf->autoneg != hw->mac.autoneg)
2043 rx_buf_size = igb_get_rx_buffer_size(hw);
2044 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2046 /* At least reserve one Ethernet frame for watermark */
2047 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2048 if ((fc_conf->high_water > max_high_water) ||
2049 (fc_conf->high_water < fc_conf->low_water)) {
2050 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2051 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2055 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2056 hw->fc.pause_time = fc_conf->pause_time;
2057 hw->fc.high_water = fc_conf->high_water;
2058 hw->fc.low_water = fc_conf->low_water;
2059 hw->fc.send_xon = fc_conf->send_xon;
2061 err = e1000_setup_link_generic(hw);
2062 if (err == E1000_SUCCESS) {
2064 /* check if we want to forward MAC frames - driver doesn't have native
2065 * capability to do that, so we'll write the registers ourselves */
2067 rctl = E1000_READ_REG(hw, E1000_RCTL);
2069 /* set or clear MFLCN.PMCF bit depending on configuration */
2070 if (fc_conf->mac_ctrl_frame_fwd != 0)
2071 rctl |= E1000_RCTL_PMCF;
2073 rctl &= ~E1000_RCTL_PMCF;
2075 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2076 E1000_WRITE_FLUSH(hw);
2081 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2085 #define E1000_RAH_POOLSEL_SHIFT (18)
2087 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2088 uint32_t index, __rte_unused uint32_t pool)
2090 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2094 rah = E1000_READ_REG(hw, E1000_RAH(index));
2095 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2096 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2100 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2102 uint8_t addr[ETHER_ADDR_LEN];
2103 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105 memset(addr, 0, sizeof(addr));
2107 e1000_rar_set(hw, addr, index);
2111 * Virtual Function operations
2114 igbvf_intr_disable(struct e1000_hw *hw)
2116 PMD_INIT_FUNC_TRACE();
2118 /* Clear interrupt mask to stop from interrupts being generated */
2119 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2121 E1000_WRITE_FLUSH(hw);
2125 igbvf_stop_adapter(struct rte_eth_dev *dev)
2129 struct rte_eth_dev_info dev_info;
2130 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132 memset(&dev_info, 0, sizeof(dev_info));
2133 eth_igbvf_infos_get(dev, &dev_info);
2135 /* Clear interrupt mask to stop from interrupts being generated */
2136 igbvf_intr_disable(hw);
2138 /* Clear any pending interrupts, flush previous writes */
2139 E1000_READ_REG(hw, E1000_EICR);
2141 /* Disable the transmit unit. Each queue must be disabled. */
2142 for (i = 0; i < dev_info.max_tx_queues; i++)
2143 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2145 /* Disable the receive unit by stopping each queue */
2146 for (i = 0; i < dev_info.max_rx_queues; i++) {
2147 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2148 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2149 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2150 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2154 /* flush all queues disables */
2155 E1000_WRITE_FLUSH(hw);
2159 static int eth_igbvf_link_update(struct e1000_hw *hw)
2161 struct e1000_mbx_info *mbx = &hw->mbx;
2162 struct e1000_mac_info *mac = &hw->mac;
2163 int ret_val = E1000_SUCCESS;
2165 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2168 * We only want to run this if there has been a rst asserted.
2169 * in this case that could mean a link change, device reset,
2170 * or a virtual function reset
2173 /* If we were hit with a reset or timeout drop the link */
2174 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2175 mac->get_link_status = TRUE;
2177 if (!mac->get_link_status)
2180 /* if link status is down no point in checking to see if pf is up */
2181 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2184 /* if we passed all the tests above then the link is up and we no
2185 * longer need to check for link */
2186 mac->get_link_status = FALSE;
2194 igbvf_dev_configure(struct rte_eth_dev *dev)
2196 struct rte_eth_conf* conf = &dev->data->dev_conf;
2198 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2199 dev->data->port_id);
2202 * VF has no ability to enable/disable HW CRC
2203 * Keep the persistent behavior the same as Host PF
2205 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2206 if (!conf->rxmode.hw_strip_crc) {
2207 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2208 conf->rxmode.hw_strip_crc = 1;
2211 if (conf->rxmode.hw_strip_crc) {
2212 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2213 conf->rxmode.hw_strip_crc = 0;
2221 igbvf_dev_start(struct rte_eth_dev *dev)
2223 struct e1000_hw *hw =
2224 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 PMD_INIT_FUNC_TRACE();
2229 hw->mac.ops.reset_hw(hw);
2232 igbvf_set_vfta_all(dev,1);
2234 eth_igbvf_tx_init(dev);
2236 /* This can fail when allocating mbufs for descriptor rings */
2237 ret = eth_igbvf_rx_init(dev);
2239 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2240 igb_dev_clear_queues(dev);
2248 igbvf_dev_stop(struct rte_eth_dev *dev)
2250 PMD_INIT_FUNC_TRACE();
2252 igbvf_stop_adapter(dev);
2255 * Clear what we set, but we still keep shadow_vfta to
2256 * restore after device starts
2258 igbvf_set_vfta_all(dev,0);
2260 igb_dev_clear_queues(dev);
2264 igbvf_dev_close(struct rte_eth_dev *dev)
2266 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2268 PMD_INIT_FUNC_TRACE();
2272 igbvf_dev_stop(dev);
2275 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2277 struct e1000_mbx_info *mbx = &hw->mbx;
2280 /* After set vlan, vlan strip will also be enabled in igb driver*/
2281 msgbuf[0] = E1000_VF_SET_VLAN;
2283 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2285 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2287 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2290 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2292 struct e1000_hw *hw =
2293 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2294 struct e1000_vfta * shadow_vfta =
2295 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2296 int i = 0, j = 0, vfta = 0, mask = 1;
2298 for (i = 0; i < IGB_VFTA_SIZE; i++){
2299 vfta = shadow_vfta->vfta[i];
2302 for (j = 0; j < 32; j++){
2305 (uint16_t)((i<<5)+j), on);
2314 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2316 struct e1000_hw *hw =
2317 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2318 struct e1000_vfta * shadow_vfta =
2319 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2320 uint32_t vid_idx = 0;
2321 uint32_t vid_bit = 0;
2324 PMD_INIT_FUNC_TRACE();
2326 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2327 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2329 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2332 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2333 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2335 /*Save what we set and retore it after device reset*/
2337 shadow_vfta->vfta[vid_idx] |= vid_bit;
2339 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2345 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2346 struct rte_eth_rss_reta_entry64 *reta_conf,
2351 uint16_t idx, shift;
2352 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2355 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2356 "(%d) doesn't match the number hardware can supported "
2357 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2361 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2362 idx = i / RTE_RETA_GROUP_SIZE;
2363 shift = i % RTE_RETA_GROUP_SIZE;
2364 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2368 if (mask == IGB_4_BIT_MASK)
2371 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2372 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2373 if (mask & (0x1 << j))
2374 reta |= reta_conf[idx].reta[shift + j] <<
2377 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2379 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2386 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2387 struct rte_eth_rss_reta_entry64 *reta_conf,
2392 uint16_t idx, shift;
2393 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2396 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2397 "(%d) doesn't match the number hardware can supported "
2398 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2402 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2403 idx = i / RTE_RETA_GROUP_SIZE;
2404 shift = i % RTE_RETA_GROUP_SIZE;
2405 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2409 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2410 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2411 if (mask & (0x1 << j))
2412 reta_conf[idx].reta[shift + j] =
2413 ((reta >> (CHAR_BIT * j)) &
2421 #define MAC_TYPE_FILTER_SUP(type) do {\
2422 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2423 (type) != e1000_82576)\
2428 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2429 struct rte_eth_syn_filter *filter,
2432 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433 uint32_t synqf, rfctl;
2435 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2438 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2441 if (synqf & E1000_SYN_FILTER_ENABLE)
2444 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2445 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2447 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2448 if (filter->hig_pri)
2449 rfctl |= E1000_RFCTL_SYNQFP;
2451 rfctl &= ~E1000_RFCTL_SYNQFP;
2453 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2455 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2460 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2461 E1000_WRITE_FLUSH(hw);
2466 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2467 struct rte_eth_syn_filter *filter)
2469 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470 uint32_t synqf, rfctl;
2472 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2473 if (synqf & E1000_SYN_FILTER_ENABLE) {
2474 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2475 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2476 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2477 E1000_SYN_FILTER_QUEUE_SHIFT);
2485 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2486 enum rte_filter_op filter_op,
2489 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492 MAC_TYPE_FILTER_SUP(hw->mac.type);
2494 if (filter_op == RTE_ETH_FILTER_NOP)
2498 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2503 switch (filter_op) {
2504 case RTE_ETH_FILTER_ADD:
2505 ret = eth_igb_syn_filter_set(dev,
2506 (struct rte_eth_syn_filter *)arg,
2509 case RTE_ETH_FILTER_DELETE:
2510 ret = eth_igb_syn_filter_set(dev,
2511 (struct rte_eth_syn_filter *)arg,
2514 case RTE_ETH_FILTER_GET:
2515 ret = eth_igb_syn_filter_get(dev,
2516 (struct rte_eth_syn_filter *)arg);
2519 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2527 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2528 if ((type) != e1000_82580 && (type) != e1000_i350)\
2532 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2534 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2535 struct e1000_2tuple_filter_info *filter_info)
2537 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2539 if (filter->priority > E1000_2TUPLE_MAX_PRI)
2540 return -EINVAL; /* filter index is out of range. */
2541 if (filter->tcp_flags > TCP_FLAG_ALL)
2542 return -EINVAL; /* flags is invalid. */
2544 switch (filter->dst_port_mask) {
2546 filter_info->dst_port_mask = 0;
2547 filter_info->dst_port = filter->dst_port;
2550 filter_info->dst_port_mask = 1;
2553 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2557 switch (filter->proto_mask) {
2559 filter_info->proto_mask = 0;
2560 filter_info->proto = filter->proto;
2563 filter_info->proto_mask = 1;
2566 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2570 filter_info->priority = (uint8_t)filter->priority;
2571 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2572 filter_info->tcp_flags = filter->tcp_flags;
2574 filter_info->tcp_flags = 0;
2579 static inline struct e1000_2tuple_filter *
2580 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2581 struct e1000_2tuple_filter_info *key)
2583 struct e1000_2tuple_filter *it;
2585 TAILQ_FOREACH(it, filter_list, entries) {
2586 if (memcmp(key, &it->filter_info,
2587 sizeof(struct e1000_2tuple_filter_info)) == 0) {
2595 * igb_add_2tuple_filter - add a 2tuple filter
2598 * dev: Pointer to struct rte_eth_dev.
2599 * ntuple_filter: ponter to the filter that will be added.
2602 * - On success, zero.
2603 * - On failure, a negative value.
2606 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2607 struct rte_eth_ntuple_filter *ntuple_filter)
2609 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610 struct e1000_filter_info *filter_info =
2611 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2612 struct e1000_2tuple_filter *filter;
2613 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2614 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2617 filter = rte_zmalloc("e1000_2tuple_filter",
2618 sizeof(struct e1000_2tuple_filter), 0);
2622 ret = ntuple_filter_to_2tuple(ntuple_filter,
2623 &filter->filter_info);
2628 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2629 &filter->filter_info) != NULL) {
2630 PMD_DRV_LOG(ERR, "filter exists.");
2634 filter->queue = ntuple_filter->queue;
2637 * look for an unused 2tuple filter index,
2638 * and insert the filter to list.
2640 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2641 if (!(filter_info->twotuple_mask & (1 << i))) {
2642 filter_info->twotuple_mask |= 1 << i;
2644 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2650 if (i >= E1000_MAX_TTQF_FILTERS) {
2651 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2656 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2657 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2658 imir |= E1000_IMIR_PORT_BP;
2660 imir &= ~E1000_IMIR_PORT_BP;
2662 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2664 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2665 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2666 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2667 if (filter->filter_info.proto_mask == 0)
2668 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2670 /* tcp flags bits setting. */
2671 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2672 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2673 imir_ext |= E1000_IMIREXT_CTRL_URG;
2674 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2675 imir_ext |= E1000_IMIREXT_CTRL_ACK;
2676 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2677 imir_ext |= E1000_IMIREXT_CTRL_PSH;
2678 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2679 imir_ext |= E1000_IMIREXT_CTRL_RST;
2680 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2681 imir_ext |= E1000_IMIREXT_CTRL_SYN;
2682 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2683 imir_ext |= E1000_IMIREXT_CTRL_FIN;
2685 imir_ext |= E1000_IMIREXT_CTRL_BP;
2686 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2687 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2688 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2693 * igb_remove_2tuple_filter - remove a 2tuple filter
2696 * dev: Pointer to struct rte_eth_dev.
2697 * ntuple_filter: ponter to the filter that will be removed.
2700 * - On success, zero.
2701 * - On failure, a negative value.
2704 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2705 struct rte_eth_ntuple_filter *ntuple_filter)
2707 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708 struct e1000_filter_info *filter_info =
2709 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2710 struct e1000_2tuple_filter_info filter_2tuple;
2711 struct e1000_2tuple_filter *filter;
2714 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2715 ret = ntuple_filter_to_2tuple(ntuple_filter,
2720 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2722 if (filter == NULL) {
2723 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2727 filter_info->twotuple_mask &= ~(1 << filter->index);
2728 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2731 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2732 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2733 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2737 static inline struct e1000_flex_filter *
2738 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2739 struct e1000_flex_filter_info *key)
2741 struct e1000_flex_filter *it;
2743 TAILQ_FOREACH(it, filter_list, entries) {
2744 if (memcmp(key, &it->filter_info,
2745 sizeof(struct e1000_flex_filter_info)) == 0)
2753 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2754 struct rte_eth_flex_filter *filter,
2757 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2758 struct e1000_filter_info *filter_info =
2759 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2760 struct e1000_flex_filter *flex_filter, *it;
2761 uint32_t wufc, queueing, mask;
2763 uint8_t shift, i, j = 0;
2765 flex_filter = rte_zmalloc("e1000_flex_filter",
2766 sizeof(struct e1000_flex_filter), 0);
2767 if (flex_filter == NULL)
2770 flex_filter->filter_info.len = filter->len;
2771 flex_filter->filter_info.priority = filter->priority;
2772 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2773 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2775 /* reverse bits in flex filter's mask*/
2776 for (shift = 0; shift < CHAR_BIT; shift++) {
2777 if (filter->mask[i] & (0x01 << shift))
2778 mask |= (0x80 >> shift);
2780 flex_filter->filter_info.mask[i] = mask;
2783 wufc = E1000_READ_REG(hw, E1000_WUFC);
2784 if (flex_filter->index < E1000_MAX_FHFT)
2785 reg_off = E1000_FHFT(flex_filter->index);
2787 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2790 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2791 &flex_filter->filter_info) != NULL) {
2792 PMD_DRV_LOG(ERR, "filter exists.");
2793 rte_free(flex_filter);
2796 flex_filter->queue = filter->queue;
2798 * look for an unused flex filter index
2799 * and insert the filter into the list.
2801 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2802 if (!(filter_info->flex_mask & (1 << i))) {
2803 filter_info->flex_mask |= 1 << i;
2804 flex_filter->index = i;
2805 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2811 if (i >= E1000_MAX_FLEX_FILTERS) {
2812 PMD_DRV_LOG(ERR, "flex filters are full.");
2813 rte_free(flex_filter);
2817 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2818 (E1000_WUFC_FLX0 << flex_filter->index));
2819 queueing = filter->len |
2820 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2821 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2822 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2824 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2825 E1000_WRITE_REG(hw, reg_off,
2826 flex_filter->filter_info.dwords[j]);
2827 reg_off += sizeof(uint32_t);
2828 E1000_WRITE_REG(hw, reg_off,
2829 flex_filter->filter_info.dwords[++j]);
2830 reg_off += sizeof(uint32_t);
2831 E1000_WRITE_REG(hw, reg_off,
2832 (uint32_t)flex_filter->filter_info.mask[i]);
2833 reg_off += sizeof(uint32_t) * 2;
2837 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2838 &flex_filter->filter_info);
2840 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2841 rte_free(flex_filter);
2845 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
2846 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
2847 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
2848 (~(E1000_WUFC_FLX0 << it->index)));
2850 filter_info->flex_mask &= ~(1 << it->index);
2851 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
2853 rte_free(flex_filter);
2860 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
2861 struct rte_eth_flex_filter *filter)
2863 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864 struct e1000_filter_info *filter_info =
2865 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2866 struct e1000_flex_filter flex_filter, *it;
2867 uint32_t wufc, queueing, wufc_en = 0;
2869 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
2870 flex_filter.filter_info.len = filter->len;
2871 flex_filter.filter_info.priority = filter->priority;
2872 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
2873 memcpy(flex_filter.filter_info.mask, filter->mask,
2874 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
2876 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2877 &flex_filter.filter_info);
2879 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2883 wufc = E1000_READ_REG(hw, E1000_WUFC);
2884 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
2886 if ((wufc & wufc_en) == wufc_en) {
2887 uint32_t reg_off = 0;
2888 if (it->index < E1000_MAX_FHFT)
2889 reg_off = E1000_FHFT(it->index);
2891 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
2893 queueing = E1000_READ_REG(hw,
2894 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2895 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2896 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2897 E1000_FHFT_QUEUEING_PRIO_SHIFT;
2898 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2899 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2906 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
2907 enum rte_filter_op filter_op,
2910 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911 struct rte_eth_flex_filter *filter;
2914 MAC_TYPE_FILTER_SUP(hw->mac.type);
2916 if (filter_op == RTE_ETH_FILTER_NOP)
2920 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2925 filter = (struct rte_eth_flex_filter *)arg;
2926 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
2927 || filter->len % sizeof(uint64_t) != 0) {
2928 PMD_DRV_LOG(ERR, "filter's length is out of range");
2931 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
2932 PMD_DRV_LOG(ERR, "filter's priority is out of range");
2936 switch (filter_op) {
2937 case RTE_ETH_FILTER_ADD:
2938 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
2940 case RTE_ETH_FILTER_DELETE:
2941 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
2943 case RTE_ETH_FILTER_GET:
2944 ret = eth_igb_get_flex_filter(dev, filter);
2947 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
2955 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
2957 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
2958 struct e1000_5tuple_filter_info *filter_info)
2960 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2962 if (filter->priority > E1000_2TUPLE_MAX_PRI)
2963 return -EINVAL; /* filter index is out of range. */
2964 if (filter->tcp_flags > TCP_FLAG_ALL)
2965 return -EINVAL; /* flags is invalid. */
2967 switch (filter->dst_ip_mask) {
2969 filter_info->dst_ip_mask = 0;
2970 filter_info->dst_ip = filter->dst_ip;
2973 filter_info->dst_ip_mask = 1;
2976 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2980 switch (filter->src_ip_mask) {
2982 filter_info->src_ip_mask = 0;
2983 filter_info->src_ip = filter->src_ip;
2986 filter_info->src_ip_mask = 1;
2989 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2993 switch (filter->dst_port_mask) {
2995 filter_info->dst_port_mask = 0;
2996 filter_info->dst_port = filter->dst_port;
2999 filter_info->dst_port_mask = 1;
3002 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3006 switch (filter->src_port_mask) {
3008 filter_info->src_port_mask = 0;
3009 filter_info->src_port = filter->src_port;
3012 filter_info->src_port_mask = 1;
3015 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3019 switch (filter->proto_mask) {
3021 filter_info->proto_mask = 0;
3022 filter_info->proto = filter->proto;
3025 filter_info->proto_mask = 1;
3028 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3032 filter_info->priority = (uint8_t)filter->priority;
3033 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3034 filter_info->tcp_flags = filter->tcp_flags;
3036 filter_info->tcp_flags = 0;
3041 static inline struct e1000_5tuple_filter *
3042 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3043 struct e1000_5tuple_filter_info *key)
3045 struct e1000_5tuple_filter *it;
3047 TAILQ_FOREACH(it, filter_list, entries) {
3048 if (memcmp(key, &it->filter_info,
3049 sizeof(struct e1000_5tuple_filter_info)) == 0) {
3057 * igb_add_5tuple_filter_82576 - add a 5tuple filter
3060 * dev: Pointer to struct rte_eth_dev.
3061 * ntuple_filter: ponter to the filter that will be added.
3064 * - On success, zero.
3065 * - On failure, a negative value.
3068 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3069 struct rte_eth_ntuple_filter *ntuple_filter)
3071 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072 struct e1000_filter_info *filter_info =
3073 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3074 struct e1000_5tuple_filter *filter;
3075 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3076 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3080 filter = rte_zmalloc("e1000_5tuple_filter",
3081 sizeof(struct e1000_5tuple_filter), 0);
3085 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3086 &filter->filter_info);
3092 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3093 &filter->filter_info) != NULL) {
3094 PMD_DRV_LOG(ERR, "filter exists.");
3098 filter->queue = ntuple_filter->queue;
3101 * look for an unused 5tuple filter index,
3102 * and insert the filter to list.
3104 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3105 if (!(filter_info->fivetuple_mask & (1 << i))) {
3106 filter_info->fivetuple_mask |= 1 << i;
3108 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3114 if (i >= E1000_MAX_FTQF_FILTERS) {
3115 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3120 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3121 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3122 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3123 if (filter->filter_info.dst_ip_mask == 0)
3124 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3125 if (filter->filter_info.src_port_mask == 0)
3126 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3127 if (filter->filter_info.proto_mask == 0)
3128 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3129 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3130 E1000_FTQF_QUEUE_MASK;
3131 ftqf |= E1000_FTQF_QUEUE_ENABLE;
3132 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3133 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3134 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3136 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3137 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3139 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3140 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3141 imir |= E1000_IMIR_PORT_BP;
3143 imir &= ~E1000_IMIR_PORT_BP;
3144 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3146 /* tcp flags bits setting. */
3147 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3148 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3149 imir_ext |= E1000_IMIREXT_CTRL_URG;
3150 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3151 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3152 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3153 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3154 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3155 imir_ext |= E1000_IMIREXT_CTRL_RST;
3156 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3157 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3158 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3159 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3161 imir_ext |= E1000_IMIREXT_CTRL_BP;
3162 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3163 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3168 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3171 * dev: Pointer to struct rte_eth_dev.
3172 * ntuple_filter: ponter to the filter that will be removed.
3175 * - On success, zero.
3176 * - On failure, a negative value.
3179 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3180 struct rte_eth_ntuple_filter *ntuple_filter)
3182 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183 struct e1000_filter_info *filter_info =
3184 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3185 struct e1000_5tuple_filter_info filter_5tuple;
3186 struct e1000_5tuple_filter *filter;
3189 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3190 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3195 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3197 if (filter == NULL) {
3198 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3202 filter_info->fivetuple_mask &= ~(1 << filter->index);
3203 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3206 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3207 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3208 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3209 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3210 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3211 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3212 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3217 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3220 struct e1000_hw *hw;
3221 struct rte_eth_dev_info dev_info;
3222 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3225 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3227 #ifdef RTE_LIBRTE_82571_SUPPORT
3228 /* XXX: not bigger than max_rx_pktlen */
3229 if (hw->mac.type == e1000_82571)
3232 eth_igb_infos_get(dev, &dev_info);
3234 /* check that mtu is within the allowed range */
3235 if ((mtu < ETHER_MIN_MTU) ||
3236 (frame_size > dev_info.max_rx_pktlen))
3239 /* refuse mtu that requires the support of scattered packets when this
3240 * feature has not been enabled before. */
3241 if (!dev->data->scattered_rx &&
3242 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3245 rctl = E1000_READ_REG(hw, E1000_RCTL);
3247 /* switch to jumbo mode if needed */
3248 if (frame_size > ETHER_MAX_LEN) {
3249 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3250 rctl |= E1000_RCTL_LPE;
3252 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3253 rctl &= ~E1000_RCTL_LPE;
3255 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3257 /* update max frame size */
3258 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3260 E1000_WRITE_REG(hw, E1000_RLPML,
3261 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3267 * igb_add_del_ntuple_filter - add or delete a ntuple filter
3270 * dev: Pointer to struct rte_eth_dev.
3271 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3272 * add: if true, add filter, if false, remove filter
3275 * - On success, zero.
3276 * - On failure, a negative value.
3279 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3280 struct rte_eth_ntuple_filter *ntuple_filter,
3283 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286 switch (ntuple_filter->flags) {
3287 case RTE_5TUPLE_FLAGS:
3288 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3289 if (hw->mac.type != e1000_82576)
3292 ret = igb_add_5tuple_filter_82576(dev,
3295 ret = igb_remove_5tuple_filter_82576(dev,
3298 case RTE_2TUPLE_FLAGS:
3299 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3300 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3303 ret = igb_add_2tuple_filter(dev, ntuple_filter);
3305 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3316 * igb_get_ntuple_filter - get a ntuple filter
3319 * dev: Pointer to struct rte_eth_dev.
3320 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3323 * - On success, zero.
3324 * - On failure, a negative value.
3327 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3328 struct rte_eth_ntuple_filter *ntuple_filter)
3330 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331 struct e1000_filter_info *filter_info =
3332 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3333 struct e1000_5tuple_filter_info filter_5tuple;
3334 struct e1000_2tuple_filter_info filter_2tuple;
3335 struct e1000_5tuple_filter *p_5tuple_filter;
3336 struct e1000_2tuple_filter *p_2tuple_filter;
3339 switch (ntuple_filter->flags) {
3340 case RTE_5TUPLE_FLAGS:
3341 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3342 if (hw->mac.type != e1000_82576)
3344 memset(&filter_5tuple,
3346 sizeof(struct e1000_5tuple_filter_info));
3347 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3351 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3352 &filter_info->fivetuple_list,
3354 if (p_5tuple_filter == NULL) {
3355 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3358 ntuple_filter->queue = p_5tuple_filter->queue;
3360 case RTE_2TUPLE_FLAGS:
3361 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3362 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3364 memset(&filter_2tuple,
3366 sizeof(struct e1000_2tuple_filter_info));
3367 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3370 p_2tuple_filter = igb_2tuple_filter_lookup(
3371 &filter_info->twotuple_list,
3373 if (p_2tuple_filter == NULL) {
3374 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3377 ntuple_filter->queue = p_2tuple_filter->queue;
3388 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3389 * @dev: pointer to rte_eth_dev structure
3390 * @filter_op:operation will be taken.
3391 * @arg: a pointer to specific structure corresponding to the filter_op
3394 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3395 enum rte_filter_op filter_op,
3398 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401 MAC_TYPE_FILTER_SUP(hw->mac.type);
3403 if (filter_op == RTE_ETH_FILTER_NOP)
3407 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3412 switch (filter_op) {
3413 case RTE_ETH_FILTER_ADD:
3414 ret = igb_add_del_ntuple_filter(dev,
3415 (struct rte_eth_ntuple_filter *)arg,
3418 case RTE_ETH_FILTER_DELETE:
3419 ret = igb_add_del_ntuple_filter(dev,
3420 (struct rte_eth_ntuple_filter *)arg,
3423 case RTE_ETH_FILTER_GET:
3424 ret = igb_get_ntuple_filter(dev,
3425 (struct rte_eth_ntuple_filter *)arg);
3428 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3436 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3441 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3442 if (filter_info->ethertype_filters[i] == ethertype &&
3443 (filter_info->ethertype_mask & (1 << i)))
3450 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3455 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3456 if (!(filter_info->ethertype_mask & (1 << i))) {
3457 filter_info->ethertype_mask |= 1 << i;
3458 filter_info->ethertype_filters[i] = ethertype;
3466 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3469 if (idx >= E1000_MAX_ETQF_FILTERS)
3471 filter_info->ethertype_mask &= ~(1 << idx);
3472 filter_info->ethertype_filters[idx] = 0;
3478 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3479 struct rte_eth_ethertype_filter *filter,
3482 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483 struct e1000_filter_info *filter_info =
3484 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3488 if (filter->ether_type == ETHER_TYPE_IPv4 ||
3489 filter->ether_type == ETHER_TYPE_IPv6) {
3490 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3491 " ethertype filter.", filter->ether_type);
3495 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3496 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3499 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3500 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3504 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3505 if (ret >= 0 && add) {
3506 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3507 filter->ether_type);
3510 if (ret < 0 && !add) {
3511 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3512 filter->ether_type);
3517 ret = igb_ethertype_filter_insert(filter_info,
3518 filter->ether_type);
3520 PMD_DRV_LOG(ERR, "ethertype filters are full.");
3524 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3525 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3526 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3528 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3532 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3533 E1000_WRITE_FLUSH(hw);
3539 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3540 struct rte_eth_ethertype_filter *filter)
3542 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543 struct e1000_filter_info *filter_info =
3544 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3548 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3550 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3551 filter->ether_type);
3555 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3556 if (etqf & E1000_ETQF_FILTER_ENABLE) {
3557 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3559 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3560 E1000_ETQF_QUEUE_SHIFT;
3568 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3569 * @dev: pointer to rte_eth_dev structure
3570 * @filter_op:operation will be taken.
3571 * @arg: a pointer to specific structure corresponding to the filter_op
3574 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3575 enum rte_filter_op filter_op,
3578 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581 MAC_TYPE_FILTER_SUP(hw->mac.type);
3583 if (filter_op == RTE_ETH_FILTER_NOP)
3587 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3592 switch (filter_op) {
3593 case RTE_ETH_FILTER_ADD:
3594 ret = igb_add_del_ethertype_filter(dev,
3595 (struct rte_eth_ethertype_filter *)arg,
3598 case RTE_ETH_FILTER_DELETE:
3599 ret = igb_add_del_ethertype_filter(dev,
3600 (struct rte_eth_ethertype_filter *)arg,
3603 case RTE_ETH_FILTER_GET:
3604 ret = igb_get_ethertype_filter(dev,
3605 (struct rte_eth_ethertype_filter *)arg);
3608 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3616 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3617 enum rte_filter_type filter_type,
3618 enum rte_filter_op filter_op,
3623 switch (filter_type) {
3624 case RTE_ETH_FILTER_NTUPLE:
3625 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3627 case RTE_ETH_FILTER_ETHERTYPE:
3628 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3630 case RTE_ETH_FILTER_SYN:
3631 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3633 case RTE_ETH_FILTER_FLEXIBLE:
3634 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3637 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3645 static struct rte_driver pmd_igb_drv = {
3647 .init = rte_igb_pmd_init,
3650 static struct rte_driver pmd_igbvf_drv = {
3652 .init = rte_igbvf_pmd_init,
3655 PMD_REGISTER_DRIVER(pmd_igb_drv);
3656 PMD_REGISTER_DRIVER(pmd_igbvf_drv);