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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
60 static int eth_igb_configure(struct rte_eth_dev *dev);
61 static int eth_igb_start(struct rte_eth_dev *dev);
62 static void eth_igb_stop(struct rte_eth_dev *dev);
63 static void eth_igb_close(struct rte_eth_dev *dev);
64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
68 static int eth_igb_link_update(struct rte_eth_dev *dev,
69 int wait_to_complete);
70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
71 struct rte_eth_stats *rte_stats);
72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
74 struct rte_eth_dev_info *dev_info);
75 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
76 struct rte_eth_fc_conf *fc_conf);
77 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
78 struct rte_eth_fc_conf *fc_conf);
79 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
80 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
81 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
82 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
84 static int igb_hardware_init(struct e1000_hw *hw);
85 static void igb_hw_control_acquire(struct e1000_hw *hw);
86 static void igb_hw_control_release(struct e1000_hw *hw);
87 static void igb_init_manageability(struct e1000_hw *hw);
88 static void igb_release_manageability(struct e1000_hw *hw);
90 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
92 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
93 uint16_t vlan_id, int on);
94 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
95 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
97 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
98 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
99 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
100 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
101 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
102 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
104 static int eth_igb_led_on(struct rte_eth_dev *dev);
105 static int eth_igb_led_off(struct rte_eth_dev *dev);
107 static void igb_intr_disable(struct e1000_hw *hw);
108 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
109 static void eth_igb_rar_set(struct rte_eth_dev *dev,
110 struct ether_addr *mac_addr,
111 uint32_t index, uint32_t pool);
112 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
114 static void igbvf_intr_disable(struct e1000_hw *hw);
115 static int igbvf_dev_configure(struct rte_eth_dev *dev);
116 static int igbvf_dev_start(struct rte_eth_dev *dev);
117 static void igbvf_dev_stop(struct rte_eth_dev *dev);
118 static void igbvf_dev_close(struct rte_eth_dev *dev);
119 static int eth_igbvf_link_update(struct e1000_hw *hw);
120 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
121 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
122 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
123 uint16_t vlan_id, int on);
124 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
125 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
126 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
127 struct rte_eth_rss_reta *reta_conf);
128 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
129 struct rte_eth_rss_reta *reta_conf);
131 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
132 struct rte_syn_filter *filter, uint16_t rx_queue);
133 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
134 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
135 struct rte_syn_filter *filter, uint16_t *rx_queue);
136 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
138 struct rte_ethertype_filter *filter, uint16_t rx_queue);
139 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
141 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
143 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
144 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
146 struct rte_2tuple_filter *filter, uint16_t rx_queue);
147 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
149 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
151 struct rte_2tuple_filter *filter, uint16_t *rx_queue);
152 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
154 struct rte_flex_filter *filter, uint16_t rx_queue);
155 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
157 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
159 struct rte_flex_filter *filter, uint16_t *rx_queue);
160 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
162 struct rte_5tuple_filter *filter, uint16_t rx_queue);
163 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
165 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
167 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
170 * Define VF Stats MACRO for Non "cleared on read" register
172 #define UPDATE_VF_STAT(reg, last, cur) \
174 u32 latest = E1000_READ_REG(hw, reg); \
175 cur += latest - last; \
180 #define IGB_FC_PAUSE_TIME 0x0680
181 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
182 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
184 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
186 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
189 * The set of PCI devices this driver supports
191 static struct rte_pci_id pci_id_igb_map[] = {
193 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
194 #include "rte_pci_dev_ids.h"
200 * The set of PCI devices this driver supports (for 82576&I350 VF)
202 static struct rte_pci_id pci_id_igbvf_map[] = {
204 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
205 #include "rte_pci_dev_ids.h"
210 static struct eth_dev_ops eth_igb_ops = {
211 .dev_configure = eth_igb_configure,
212 .dev_start = eth_igb_start,
213 .dev_stop = eth_igb_stop,
214 .dev_close = eth_igb_close,
215 .promiscuous_enable = eth_igb_promiscuous_enable,
216 .promiscuous_disable = eth_igb_promiscuous_disable,
217 .allmulticast_enable = eth_igb_allmulticast_enable,
218 .allmulticast_disable = eth_igb_allmulticast_disable,
219 .link_update = eth_igb_link_update,
220 .stats_get = eth_igb_stats_get,
221 .stats_reset = eth_igb_stats_reset,
222 .dev_infos_get = eth_igb_infos_get,
223 .mtu_set = eth_igb_mtu_set,
224 .vlan_filter_set = eth_igb_vlan_filter_set,
225 .vlan_tpid_set = eth_igb_vlan_tpid_set,
226 .vlan_offload_set = eth_igb_vlan_offload_set,
227 .rx_queue_setup = eth_igb_rx_queue_setup,
228 .rx_queue_release = eth_igb_rx_queue_release,
229 .rx_queue_count = eth_igb_rx_queue_count,
230 .rx_descriptor_done = eth_igb_rx_descriptor_done,
231 .tx_queue_setup = eth_igb_tx_queue_setup,
232 .tx_queue_release = eth_igb_tx_queue_release,
233 .dev_led_on = eth_igb_led_on,
234 .dev_led_off = eth_igb_led_off,
235 .flow_ctrl_get = eth_igb_flow_ctrl_get,
236 .flow_ctrl_set = eth_igb_flow_ctrl_set,
237 .mac_addr_add = eth_igb_rar_set,
238 .mac_addr_remove = eth_igb_rar_clear,
239 .reta_update = eth_igb_rss_reta_update,
240 .reta_query = eth_igb_rss_reta_query,
241 .rss_hash_update = eth_igb_rss_hash_update,
242 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
243 .add_syn_filter = eth_igb_add_syn_filter,
244 .remove_syn_filter = eth_igb_remove_syn_filter,
245 .get_syn_filter = eth_igb_get_syn_filter,
246 .add_ethertype_filter = eth_igb_add_ethertype_filter,
247 .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
248 .get_ethertype_filter = eth_igb_get_ethertype_filter,
249 .add_2tuple_filter = eth_igb_add_2tuple_filter,
250 .remove_2tuple_filter = eth_igb_remove_2tuple_filter,
251 .get_2tuple_filter = eth_igb_get_2tuple_filter,
252 .add_flex_filter = eth_igb_add_flex_filter,
253 .remove_flex_filter = eth_igb_remove_flex_filter,
254 .get_flex_filter = eth_igb_get_flex_filter,
255 .add_5tuple_filter = eth_igb_add_5tuple_filter,
256 .remove_5tuple_filter = eth_igb_remove_5tuple_filter,
257 .get_5tuple_filter = eth_igb_get_5tuple_filter,
261 * dev_ops for virtual function, bare necessities for basic vf
262 * operation have been implemented
264 static struct eth_dev_ops igbvf_eth_dev_ops = {
265 .dev_configure = igbvf_dev_configure,
266 .dev_start = igbvf_dev_start,
267 .dev_stop = igbvf_dev_stop,
268 .dev_close = igbvf_dev_close,
269 .link_update = eth_igb_link_update,
270 .stats_get = eth_igbvf_stats_get,
271 .stats_reset = eth_igbvf_stats_reset,
272 .vlan_filter_set = igbvf_vlan_filter_set,
273 .dev_infos_get = eth_igb_infos_get,
274 .rx_queue_setup = eth_igb_rx_queue_setup,
275 .rx_queue_release = eth_igb_rx_queue_release,
276 .tx_queue_setup = eth_igb_tx_queue_setup,
277 .tx_queue_release = eth_igb_tx_queue_release,
281 * Atomically reads the link status information from global
282 * structure rte_eth_dev.
285 * - Pointer to the structure rte_eth_dev to read from.
286 * - Pointer to the buffer to be saved with the link status.
289 * - On success, zero.
290 * - On failure, negative value.
293 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
294 struct rte_eth_link *link)
296 struct rte_eth_link *dst = link;
297 struct rte_eth_link *src = &(dev->data->dev_link);
299 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
300 *(uint64_t *)src) == 0)
307 * Atomically writes the link status information into global
308 * structure rte_eth_dev.
311 * - Pointer to the structure rte_eth_dev to read from.
312 * - Pointer to the buffer to be saved with the link status.
315 * - On success, zero.
316 * - On failure, negative value.
319 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
320 struct rte_eth_link *link)
322 struct rte_eth_link *dst = &(dev->data->dev_link);
323 struct rte_eth_link *src = link;
325 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
326 *(uint64_t *)src) == 0)
333 igb_intr_enable(struct rte_eth_dev *dev)
335 struct e1000_interrupt *intr =
336 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
337 struct e1000_hw *hw =
338 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
340 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
341 E1000_WRITE_FLUSH(hw);
345 igb_intr_disable(struct e1000_hw *hw)
347 E1000_WRITE_REG(hw, E1000_IMC, ~0);
348 E1000_WRITE_FLUSH(hw);
351 static inline int32_t
352 igb_pf_reset_hw(struct e1000_hw *hw)
357 status = e1000_reset_hw(hw);
359 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
360 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
361 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
362 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
363 E1000_WRITE_FLUSH(hw);
369 igb_identify_hardware(struct rte_eth_dev *dev)
371 struct e1000_hw *hw =
372 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
374 hw->vendor_id = dev->pci_dev->id.vendor_id;
375 hw->device_id = dev->pci_dev->id.device_id;
376 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
377 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
379 e1000_set_mac_type(hw);
381 /* need to check if it is a vf device below */
385 igb_reset_swfw_lock(struct e1000_hw *hw)
390 * Do mac ops initialization manually here, since we will need
391 * some function pointers set by this call.
393 ret_val = e1000_init_mac_params(hw);
398 * SMBI lock should not fail in this early stage. If this is the case,
399 * it is due to an improper exit of the application.
400 * So force the release of the faulty lock.
402 if (e1000_get_hw_semaphore_generic(hw) < 0) {
403 PMD_DRV_LOG(DEBUG, "SMBI lock released");
405 e1000_put_hw_semaphore_generic(hw);
407 if (hw->mac.ops.acquire_swfw_sync != NULL) {
411 * Phy lock should not fail in this early stage. If this is the case,
412 * it is due to an improper exit of the application.
413 * So force the release of the faulty lock.
415 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
416 if (hw->bus.func > E1000_FUNC_1)
418 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
419 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
422 hw->mac.ops.release_swfw_sync(hw, mask);
425 * This one is more tricky since it is common to all ports; but
426 * swfw_sync retries last long enough (1s) to be almost sure that if
427 * lock can not be taken it is due to an improper lock of the
430 mask = E1000_SWFW_EEP_SM;
431 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
432 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
434 hw->mac.ops.release_swfw_sync(hw, mask);
437 return E1000_SUCCESS;
441 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
442 struct rte_eth_dev *eth_dev)
445 struct rte_pci_device *pci_dev;
446 struct e1000_hw *hw =
447 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
448 struct e1000_vfta * shadow_vfta =
449 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
452 pci_dev = eth_dev->pci_dev;
453 eth_dev->dev_ops = ð_igb_ops;
454 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
455 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
457 /* for secondary processes, we don't initialise any further as primary
458 * has already done this work. Only check we don't need a different
460 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
461 if (eth_dev->data->scattered_rx)
462 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
466 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
468 igb_identify_hardware(eth_dev);
469 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
474 e1000_get_bus_info(hw);
476 /* Reset any pending lock */
477 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
482 /* Finish initialization */
483 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
489 hw->phy.autoneg_wait_to_complete = 0;
490 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
493 if (hw->phy.media_type == e1000_media_type_copper) {
494 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
495 hw->phy.disable_polarity_correction = 0;
496 hw->phy.ms_type = e1000_ms_hw_default;
500 * Start from a known state, this is important in reading the nvm
505 /* Make sure we have a good EEPROM before we read from it */
506 if (e1000_validate_nvm_checksum(hw) < 0) {
508 * Some PCI-E parts fail the first check due to
509 * the link being in sleep state, call it again,
510 * if it fails a second time its a real issue.
512 if (e1000_validate_nvm_checksum(hw) < 0) {
513 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
519 /* Read the permanent MAC address out of the EEPROM */
520 if (e1000_read_mac_addr(hw) != 0) {
521 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
526 /* Allocate memory for storing MAC addresses */
527 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
528 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
529 if (eth_dev->data->mac_addrs == NULL) {
530 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
531 "store MAC addresses",
532 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
537 /* Copy the permanent MAC address */
538 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
540 /* initialize the vfta */
541 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
543 /* Now initialize the hardware */
544 if (igb_hardware_init(hw) != 0) {
545 PMD_INIT_LOG(ERR, "Hardware initialization failed");
546 rte_free(eth_dev->data->mac_addrs);
547 eth_dev->data->mac_addrs = NULL;
551 hw->mac.get_link_status = 1;
553 /* Indicate SOL/IDER usage */
554 if (e1000_check_reset_block(hw) < 0) {
555 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
559 /* initialize PF if max_vfs not zero */
560 igb_pf_host_init(eth_dev);
562 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
563 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
564 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
565 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
566 E1000_WRITE_FLUSH(hw);
568 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
569 eth_dev->data->port_id, pci_dev->id.vendor_id,
570 pci_dev->id.device_id);
572 rte_intr_callback_register(&(pci_dev->intr_handle),
573 eth_igb_interrupt_handler, (void *)eth_dev);
575 /* enable uio intr after callback register */
576 rte_intr_enable(&(pci_dev->intr_handle));
578 /* enable support intr */
579 igb_intr_enable(eth_dev);
584 igb_hw_control_release(hw);
590 * Virtual Function device init
593 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
594 struct rte_eth_dev *eth_dev)
596 struct rte_pci_device *pci_dev;
597 struct e1000_hw *hw =
598 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
601 PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
603 eth_dev->dev_ops = &igbvf_eth_dev_ops;
604 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
605 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
607 /* for secondary processes, we don't initialise any further as primary
608 * has already done this work. Only check we don't need a different
610 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
611 if (eth_dev->data->scattered_rx)
612 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
616 pci_dev = eth_dev->pci_dev;
618 hw->device_id = pci_dev->id.device_id;
619 hw->vendor_id = pci_dev->id.vendor_id;
620 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
622 /* Initialize the shared code (base driver) */
623 diag = e1000_setup_init_funcs(hw, TRUE);
625 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
630 /* init_mailbox_params */
631 hw->mbx.ops.init_params(hw);
633 /* Disable the interrupts for VF */
634 igbvf_intr_disable(hw);
636 diag = hw->mac.ops.reset_hw(hw);
638 /* Allocate memory for storing MAC addresses */
639 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
640 hw->mac.rar_entry_count, 0);
641 if (eth_dev->data->mac_addrs == NULL) {
643 "Failed to allocate %d bytes needed to store MAC "
645 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
649 /* Copy the permanent MAC address */
650 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
651 ð_dev->data->mac_addrs[0]);
653 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
655 eth_dev->data->port_id, pci_dev->id.vendor_id,
656 pci_dev->id.device_id, "igb_mac_82576_vf");
661 static struct eth_driver rte_igb_pmd = {
663 .name = "rte_igb_pmd",
664 .id_table = pci_id_igb_map,
665 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
667 .eth_dev_init = eth_igb_dev_init,
668 .dev_private_size = sizeof(struct e1000_adapter),
672 * virtual function driver struct
674 static struct eth_driver rte_igbvf_pmd = {
676 .name = "rte_igbvf_pmd",
677 .id_table = pci_id_igbvf_map,
678 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
680 .eth_dev_init = eth_igbvf_dev_init,
681 .dev_private_size = sizeof(struct e1000_adapter),
685 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
687 rte_eth_driver_register(&rte_igb_pmd);
692 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
694 struct e1000_hw *hw =
695 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
696 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
697 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
698 rctl |= E1000_RCTL_VFE;
699 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
703 * VF Driver initialization routine.
704 * Invoked one at EAL init time.
705 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
708 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
710 PMD_INIT_FUNC_TRACE();
712 rte_eth_driver_register(&rte_igbvf_pmd);
717 eth_igb_configure(struct rte_eth_dev *dev)
719 struct e1000_interrupt *intr =
720 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
722 PMD_INIT_LOG(DEBUG, ">>");
724 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
726 PMD_INIT_LOG(DEBUG, "<<");
732 eth_igb_start(struct rte_eth_dev *dev)
734 struct e1000_hw *hw =
735 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
739 PMD_INIT_LOG(DEBUG, ">>");
741 /* Power up the phy. Needed to make the link go Up */
742 e1000_power_up_phy(hw);
745 * Packet Buffer Allocation (PBA)
746 * Writing PBA sets the receive portion of the buffer
747 * the remainder is used for the transmit buffer.
749 if (hw->mac.type == e1000_82575) {
752 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
753 E1000_WRITE_REG(hw, E1000_PBA, pba);
756 /* Put the address into the Receive Address Array */
757 e1000_rar_set(hw, hw->mac.addr, 0);
759 /* Initialize the hardware */
760 if (igb_hardware_init(hw)) {
761 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
765 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
767 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
768 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
769 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
770 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
771 E1000_WRITE_FLUSH(hw);
773 /* configure PF module if SRIOV enabled */
774 igb_pf_host_configure(dev);
776 /* Configure for OS presence */
777 igb_init_manageability(hw);
779 eth_igb_tx_init(dev);
781 /* This can fail when allocating mbufs for descriptor rings */
782 ret = eth_igb_rx_init(dev);
784 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
785 igb_dev_clear_queues(dev);
789 e1000_clear_hw_cntrs_base_generic(hw);
792 * VLAN Offload Settings
794 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
795 ETH_VLAN_EXTEND_MASK;
796 eth_igb_vlan_offload_set(dev, mask);
798 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
799 /* Enable VLAN filter since VMDq always use VLAN filter */
800 igb_vmdq_vlan_hw_filter_enable(dev);
804 * Configure the Interrupt Moderation register (EITR) with the maximum
805 * possible value (0xFFFF) to minimize "System Partial Write" issued by
806 * spurious [DMA] memory updates of RX and TX ring descriptors.
808 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
809 * spurious memory updates per second should be expected.
810 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
812 * Because interrupts are not used at all, the MSI-X is not activated
813 * and interrupt moderation is controlled by EITR[0].
815 * Note that having [almost] disabled memory updates of RX and TX ring
816 * descriptors through the Interrupt Moderation mechanism, memory
817 * updates of ring descriptors are now moderated by the configurable
818 * value of Write-Back Threshold registers.
820 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
821 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
824 /* Enable all RX & TX queues in the IVAR registers */
825 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
826 for (i = 0; i < 8; i++)
827 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
829 /* Configure EITR with the maximum possible value (0xFFFF) */
830 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
833 /* Setup link speed and duplex */
834 switch (dev->data->dev_conf.link_speed) {
835 case ETH_LINK_SPEED_AUTONEG:
836 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
837 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
838 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
839 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
840 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
841 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
843 goto error_invalid_config;
845 case ETH_LINK_SPEED_10:
846 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
847 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
848 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
849 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
850 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
851 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
853 goto error_invalid_config;
855 case ETH_LINK_SPEED_100:
856 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
857 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
858 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
859 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
860 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
861 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
863 goto error_invalid_config;
865 case ETH_LINK_SPEED_1000:
866 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
867 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
868 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
870 goto error_invalid_config;
872 case ETH_LINK_SPEED_10000:
874 goto error_invalid_config;
876 e1000_setup_link(hw);
878 /* check if lsc interrupt feature is enabled */
879 if (dev->data->dev_conf.intr_conf.lsc != 0)
880 ret = eth_igb_lsc_interrupt_setup(dev);
882 /* resume enabled intr since hw reset */
883 igb_intr_enable(dev);
885 PMD_INIT_LOG(DEBUG, "<<");
889 error_invalid_config:
890 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
891 dev->data->dev_conf.link_speed,
892 dev->data->dev_conf.link_duplex, dev->data->port_id);
893 igb_dev_clear_queues(dev);
897 /*********************************************************************
899 * This routine disables all traffic on the adapter by issuing a
900 * global reset on the MAC.
902 **********************************************************************/
904 eth_igb_stop(struct rte_eth_dev *dev)
906 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
907 struct rte_eth_link link;
909 igb_intr_disable(hw);
911 E1000_WRITE_REG(hw, E1000_WUC, 0);
913 /* Set bit for Go Link disconnect */
914 if (hw->mac.type >= e1000_82580) {
917 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
918 phpm_reg |= E1000_82580_PM_GO_LINKD;
919 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
922 /* Power down the phy. Needed to make the link go Down */
923 e1000_power_down_phy(hw);
925 igb_dev_clear_queues(dev);
927 /* clear the recorded link status */
928 memset(&link, 0, sizeof(link));
929 rte_igb_dev_atomic_write_link_status(dev, &link);
933 eth_igb_close(struct rte_eth_dev *dev)
935 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 struct rte_eth_link link;
939 e1000_phy_hw_reset(hw);
940 igb_release_manageability(hw);
941 igb_hw_control_release(hw);
943 /* Clear bit for Go Link disconnect */
944 if (hw->mac.type >= e1000_82580) {
947 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
948 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
949 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
952 igb_dev_clear_queues(dev);
954 memset(&link, 0, sizeof(link));
955 rte_igb_dev_atomic_write_link_status(dev, &link);
959 igb_get_rx_buffer_size(struct e1000_hw *hw)
961 uint32_t rx_buf_size;
962 if (hw->mac.type == e1000_82576) {
963 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
964 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
965 /* PBS needs to be translated according to a lookup table */
966 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
967 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
968 rx_buf_size = (rx_buf_size << 10);
969 } else if (hw->mac.type == e1000_i210) {
970 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
972 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
978 /*********************************************************************
980 * Initialize the hardware
982 **********************************************************************/
984 igb_hardware_init(struct e1000_hw *hw)
986 uint32_t rx_buf_size;
989 /* Let the firmware know the OS is in control */
990 igb_hw_control_acquire(hw);
993 * These parameters control the automatic generation (Tx) and
994 * response (Rx) to Ethernet PAUSE frames.
995 * - High water mark should allow for at least two standard size (1518)
996 * frames to be received after sending an XOFF.
997 * - Low water mark works best when it is very near the high water mark.
998 * This allows the receiver to restart by sending XON when it has
999 * drained a bit. Here we use an arbitrary value of 1500 which will
1000 * restart after one full frame is pulled from the buffer. There
1001 * could be several smaller frames in the buffer and if so they will
1002 * not trigger the XON until their total number reduces the buffer
1004 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1006 rx_buf_size = igb_get_rx_buffer_size(hw);
1008 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1009 hw->fc.low_water = hw->fc.high_water - 1500;
1010 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1011 hw->fc.send_xon = 1;
1013 /* Set Flow control, use the tunable location if sane */
1014 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1015 hw->fc.requested_mode = igb_fc_setting;
1017 hw->fc.requested_mode = e1000_fc_none;
1019 /* Issue a global reset */
1020 igb_pf_reset_hw(hw);
1021 E1000_WRITE_REG(hw, E1000_WUC, 0);
1023 diag = e1000_init_hw(hw);
1027 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1028 e1000_get_phy_info(hw);
1029 e1000_check_for_link(hw);
1034 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1036 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1038 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 struct e1000_hw_stats *stats =
1040 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1043 if(hw->phy.media_type == e1000_media_type_copper ||
1044 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1046 E1000_READ_REG(hw,E1000_SYMERRS);
1047 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1050 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1051 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1052 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1053 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1055 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1056 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1057 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1058 stats->dc += E1000_READ_REG(hw, E1000_DC);
1059 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1060 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1061 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1063 ** For watchdog management we need to know if we have been
1064 ** paused during the last interval, so capture that here.
1066 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1067 stats->xoffrxc += pause_frames;
1068 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1069 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1070 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1071 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1072 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1073 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1074 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1075 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1076 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1077 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1078 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1079 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1081 /* For the 64-bit byte counters the low dword must be read first. */
1082 /* Both registers clear on the read of the high dword */
1084 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1085 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1086 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1087 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1089 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1090 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1091 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1092 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1093 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1095 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1096 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1098 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1099 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1100 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1101 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1102 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1103 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1104 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1105 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1106 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1107 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1109 /* Interrupt Counts */
1111 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1112 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1113 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1114 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1115 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1116 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1117 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1118 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1119 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1121 /* Host to Card Statistics */
1123 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1124 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1125 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1126 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1127 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1128 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1129 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1130 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1131 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1132 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1133 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1134 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1135 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1136 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1138 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1139 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1140 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1141 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1142 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1143 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1145 if (rte_stats == NULL)
1149 rte_stats->ibadcrc = stats->crcerrs;
1150 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1151 rte_stats->imissed = stats->mpc;
1152 rte_stats->ierrors = rte_stats->ibadcrc +
1153 rte_stats->ibadlen +
1154 rte_stats->imissed +
1155 stats->rxerrc + stats->algnerrc + stats->cexterr;
1158 rte_stats->oerrors = stats->ecol + stats->latecol;
1160 /* XON/XOFF pause frames */
1161 rte_stats->tx_pause_xon = stats->xontxc;
1162 rte_stats->rx_pause_xon = stats->xonrxc;
1163 rte_stats->tx_pause_xoff = stats->xofftxc;
1164 rte_stats->rx_pause_xoff = stats->xoffrxc;
1166 rte_stats->ipackets = stats->gprc;
1167 rte_stats->opackets = stats->gptc;
1168 rte_stats->ibytes = stats->gorc;
1169 rte_stats->obytes = stats->gotc;
1173 eth_igb_stats_reset(struct rte_eth_dev *dev)
1175 struct e1000_hw_stats *hw_stats =
1176 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1178 /* HW registers are cleared on read */
1179 eth_igb_stats_get(dev, NULL);
1181 /* Reset software totals */
1182 memset(hw_stats, 0, sizeof(*hw_stats));
1186 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1188 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1190 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1192 /* Good Rx packets, include VF loopback */
1193 UPDATE_VF_STAT(E1000_VFGPRC,
1194 hw_stats->last_gprc, hw_stats->gprc);
1196 /* Good Rx octets, include VF loopback */
1197 UPDATE_VF_STAT(E1000_VFGORC,
1198 hw_stats->last_gorc, hw_stats->gorc);
1200 /* Good Tx packets, include VF loopback */
1201 UPDATE_VF_STAT(E1000_VFGPTC,
1202 hw_stats->last_gptc, hw_stats->gptc);
1204 /* Good Tx octets, include VF loopback */
1205 UPDATE_VF_STAT(E1000_VFGOTC,
1206 hw_stats->last_gotc, hw_stats->gotc);
1208 /* Rx Multicst packets */
1209 UPDATE_VF_STAT(E1000_VFMPRC,
1210 hw_stats->last_mprc, hw_stats->mprc);
1212 /* Good Rx loopback packets */
1213 UPDATE_VF_STAT(E1000_VFGPRLBC,
1214 hw_stats->last_gprlbc, hw_stats->gprlbc);
1216 /* Good Rx loopback octets */
1217 UPDATE_VF_STAT(E1000_VFGORLBC,
1218 hw_stats->last_gorlbc, hw_stats->gorlbc);
1220 /* Good Tx loopback packets */
1221 UPDATE_VF_STAT(E1000_VFGPTLBC,
1222 hw_stats->last_gptlbc, hw_stats->gptlbc);
1224 /* Good Tx loopback octets */
1225 UPDATE_VF_STAT(E1000_VFGOTLBC,
1226 hw_stats->last_gotlbc, hw_stats->gotlbc);
1228 if (rte_stats == NULL)
1231 memset(rte_stats, 0, sizeof(*rte_stats));
1232 rte_stats->ipackets = hw_stats->gprc;
1233 rte_stats->ibytes = hw_stats->gorc;
1234 rte_stats->opackets = hw_stats->gptc;
1235 rte_stats->obytes = hw_stats->gotc;
1236 rte_stats->imcasts = hw_stats->mprc;
1237 rte_stats->ilbpackets = hw_stats->gprlbc;
1238 rte_stats->ilbbytes = hw_stats->gorlbc;
1239 rte_stats->olbpackets = hw_stats->gptlbc;
1240 rte_stats->olbbytes = hw_stats->gotlbc;
1245 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1247 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1248 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1250 /* Sync HW register to the last stats */
1251 eth_igbvf_stats_get(dev, NULL);
1253 /* reset HW current stats*/
1254 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1255 offsetof(struct e1000_vf_stats, gprc));
1260 eth_igb_infos_get(struct rte_eth_dev *dev,
1261 struct rte_eth_dev_info *dev_info)
1263 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1265 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1266 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1267 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1268 dev_info->rx_offload_capa =
1269 DEV_RX_OFFLOAD_VLAN_STRIP |
1270 DEV_RX_OFFLOAD_IPV4_CKSUM |
1271 DEV_RX_OFFLOAD_UDP_CKSUM |
1272 DEV_RX_OFFLOAD_TCP_CKSUM;
1273 dev_info->tx_offload_capa =
1274 DEV_TX_OFFLOAD_VLAN_INSERT |
1275 DEV_TX_OFFLOAD_IPV4_CKSUM |
1276 DEV_TX_OFFLOAD_UDP_CKSUM |
1277 DEV_TX_OFFLOAD_TCP_CKSUM |
1278 DEV_TX_OFFLOAD_SCTP_CKSUM;
1280 switch (hw->mac.type) {
1282 dev_info->max_rx_queues = 4;
1283 dev_info->max_tx_queues = 4;
1284 dev_info->max_vmdq_pools = 0;
1288 dev_info->max_rx_queues = 16;
1289 dev_info->max_tx_queues = 16;
1290 dev_info->max_vmdq_pools = ETH_8_POOLS;
1294 dev_info->max_rx_queues = 8;
1295 dev_info->max_tx_queues = 8;
1296 dev_info->max_vmdq_pools = ETH_8_POOLS;
1300 dev_info->max_rx_queues = 8;
1301 dev_info->max_tx_queues = 8;
1302 dev_info->max_vmdq_pools = ETH_8_POOLS;
1306 dev_info->max_rx_queues = 8;
1307 dev_info->max_tx_queues = 8;
1311 dev_info->max_rx_queues = 4;
1312 dev_info->max_tx_queues = 4;
1313 dev_info->max_vmdq_pools = 0;
1317 dev_info->max_rx_queues = 2;
1318 dev_info->max_tx_queues = 2;
1319 dev_info->max_vmdq_pools = 0;
1322 case e1000_vfadapt_i350:
1323 dev_info->max_rx_queues = 1;
1324 dev_info->max_tx_queues = 1;
1325 dev_info->max_vmdq_pools = 0;
1329 /* Should not happen */
1330 dev_info->max_rx_queues = 0;
1331 dev_info->max_tx_queues = 0;
1332 dev_info->max_vmdq_pools = 0;
1336 /* return 0 means link status changed, -1 means not changed */
1338 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1340 struct e1000_hw *hw =
1341 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342 struct rte_eth_link link, old;
1343 int link_check, count;
1346 hw->mac.get_link_status = 1;
1348 /* possible wait-to-complete in up to 9 seconds */
1349 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1350 /* Read the real link status */
1351 switch (hw->phy.media_type) {
1352 case e1000_media_type_copper:
1353 /* Do the work to read phy */
1354 e1000_check_for_link(hw);
1355 link_check = !hw->mac.get_link_status;
1358 case e1000_media_type_fiber:
1359 e1000_check_for_link(hw);
1360 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1364 case e1000_media_type_internal_serdes:
1365 e1000_check_for_link(hw);
1366 link_check = hw->mac.serdes_has_link;
1369 /* VF device is type_unknown */
1370 case e1000_media_type_unknown:
1371 eth_igbvf_link_update(hw);
1372 link_check = !hw->mac.get_link_status;
1378 if (link_check || wait_to_complete == 0)
1380 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1382 memset(&link, 0, sizeof(link));
1383 rte_igb_dev_atomic_read_link_status(dev, &link);
1386 /* Now we check if a transition has happened */
1388 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1390 link.link_status = 1;
1391 } else if (!link_check) {
1392 link.link_speed = 0;
1393 link.link_duplex = 0;
1394 link.link_status = 0;
1396 rte_igb_dev_atomic_write_link_status(dev, &link);
1399 if (old.link_status == link.link_status)
1407 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1408 * For ASF and Pass Through versions of f/w this means
1409 * that the driver is loaded.
1412 igb_hw_control_acquire(struct e1000_hw *hw)
1416 /* Let firmware know the driver has taken over */
1417 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1418 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1422 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1423 * For ASF and Pass Through versions of f/w this means that the
1424 * driver is no longer loaded.
1427 igb_hw_control_release(struct e1000_hw *hw)
1431 /* Let firmware taken over control of h/w */
1432 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1433 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1434 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1438 * Bit of a misnomer, what this really means is
1439 * to enable OS management of the system... aka
1440 * to disable special hardware management features.
1443 igb_init_manageability(struct e1000_hw *hw)
1445 if (e1000_enable_mng_pass_thru(hw)) {
1446 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1447 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1449 /* disable hardware interception of ARP */
1450 manc &= ~(E1000_MANC_ARP_EN);
1452 /* enable receiving management packets to the host */
1453 manc |= E1000_MANC_EN_MNG2HOST;
1454 manc2h |= 1 << 5; /* Mng Port 623 */
1455 manc2h |= 1 << 6; /* Mng Port 664 */
1456 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1457 E1000_WRITE_REG(hw, E1000_MANC, manc);
1462 igb_release_manageability(struct e1000_hw *hw)
1464 if (e1000_enable_mng_pass_thru(hw)) {
1465 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1467 manc |= E1000_MANC_ARP_EN;
1468 manc &= ~E1000_MANC_EN_MNG2HOST;
1470 E1000_WRITE_REG(hw, E1000_MANC, manc);
1475 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1477 struct e1000_hw *hw =
1478 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481 rctl = E1000_READ_REG(hw, E1000_RCTL);
1482 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1483 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1487 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1489 struct e1000_hw *hw =
1490 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493 rctl = E1000_READ_REG(hw, E1000_RCTL);
1494 rctl &= (~E1000_RCTL_UPE);
1495 if (dev->data->all_multicast == 1)
1496 rctl |= E1000_RCTL_MPE;
1498 rctl &= (~E1000_RCTL_MPE);
1499 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1503 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1505 struct e1000_hw *hw =
1506 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509 rctl = E1000_READ_REG(hw, E1000_RCTL);
1510 rctl |= E1000_RCTL_MPE;
1511 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1515 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1517 struct e1000_hw *hw =
1518 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 if (dev->data->promiscuous == 1)
1522 return; /* must remain in all_multicast mode */
1523 rctl = E1000_READ_REG(hw, E1000_RCTL);
1524 rctl &= (~E1000_RCTL_MPE);
1525 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1529 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1531 struct e1000_hw *hw =
1532 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533 struct e1000_vfta * shadow_vfta =
1534 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1539 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1540 E1000_VFTA_ENTRY_MASK);
1541 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1542 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1547 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1549 /* update local VFTA copy */
1550 shadow_vfta->vfta[vid_idx] = vfta;
1556 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1558 struct e1000_hw *hw =
1559 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560 uint32_t reg = ETHER_TYPE_VLAN ;
1562 reg |= (tpid << 16);
1563 E1000_WRITE_REG(hw, E1000_VET, reg);
1567 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1569 struct e1000_hw *hw =
1570 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573 /* Filter Table Disable */
1574 reg = E1000_READ_REG(hw, E1000_RCTL);
1575 reg &= ~E1000_RCTL_CFIEN;
1576 reg &= ~E1000_RCTL_VFE;
1577 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1581 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1583 struct e1000_hw *hw =
1584 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585 struct e1000_vfta * shadow_vfta =
1586 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1590 /* Filter Table Enable, CFI not used for packet acceptance */
1591 reg = E1000_READ_REG(hw, E1000_RCTL);
1592 reg &= ~E1000_RCTL_CFIEN;
1593 reg |= E1000_RCTL_VFE;
1594 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1596 /* restore VFTA table */
1597 for (i = 0; i < IGB_VFTA_SIZE; i++)
1598 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1602 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1604 struct e1000_hw *hw =
1605 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608 /* VLAN Mode Disable */
1609 reg = E1000_READ_REG(hw, E1000_CTRL);
1610 reg &= ~E1000_CTRL_VME;
1611 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1615 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1617 struct e1000_hw *hw =
1618 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621 /* VLAN Mode Enable */
1622 reg = E1000_READ_REG(hw, E1000_CTRL);
1623 reg |= E1000_CTRL_VME;
1624 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1628 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1630 struct e1000_hw *hw =
1631 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634 /* CTRL_EXT: Extended VLAN */
1635 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1636 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1637 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1639 /* Update maximum packet length */
1640 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1641 E1000_WRITE_REG(hw, E1000_RLPML,
1642 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1647 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1649 struct e1000_hw *hw =
1650 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653 /* CTRL_EXT: Extended VLAN */
1654 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1655 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1656 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1658 /* Update maximum packet length */
1659 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1660 E1000_WRITE_REG(hw, E1000_RLPML,
1661 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1666 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1668 if(mask & ETH_VLAN_STRIP_MASK){
1669 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1670 igb_vlan_hw_strip_enable(dev);
1672 igb_vlan_hw_strip_disable(dev);
1675 if(mask & ETH_VLAN_FILTER_MASK){
1676 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1677 igb_vlan_hw_filter_enable(dev);
1679 igb_vlan_hw_filter_disable(dev);
1682 if(mask & ETH_VLAN_EXTEND_MASK){
1683 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1684 igb_vlan_hw_extend_enable(dev);
1686 igb_vlan_hw_extend_disable(dev);
1692 * It enables the interrupt mask and then enable the interrupt.
1695 * Pointer to struct rte_eth_dev.
1698 * - On success, zero.
1699 * - On failure, a negative value.
1702 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1704 struct e1000_interrupt *intr =
1705 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1707 intr->mask |= E1000_ICR_LSC;
1713 * It reads ICR and gets interrupt causes, check it and set a bit flag
1714 * to update link status.
1717 * Pointer to struct rte_eth_dev.
1720 * - On success, zero.
1721 * - On failure, a negative value.
1724 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1727 struct e1000_hw *hw =
1728 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729 struct e1000_interrupt *intr =
1730 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1732 igb_intr_disable(hw);
1734 /* read-on-clear nic registers here */
1735 icr = E1000_READ_REG(hw, E1000_ICR);
1738 if (icr & E1000_ICR_LSC) {
1739 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1742 if (icr & E1000_ICR_VMMB)
1743 intr->flags |= E1000_FLAG_MAILBOX;
1749 * It executes link_update after knowing an interrupt is prsent.
1752 * Pointer to struct rte_eth_dev.
1755 * - On success, zero.
1756 * - On failure, a negative value.
1759 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1761 struct e1000_hw *hw =
1762 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763 struct e1000_interrupt *intr =
1764 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1765 uint32_t tctl, rctl;
1766 struct rte_eth_link link;
1769 if (intr->flags & E1000_FLAG_MAILBOX) {
1770 igb_pf_mbx_process(dev);
1771 intr->flags &= ~E1000_FLAG_MAILBOX;
1774 igb_intr_enable(dev);
1775 rte_intr_enable(&(dev->pci_dev->intr_handle));
1777 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1778 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1780 /* set get_link_status to check register later */
1781 hw->mac.get_link_status = 1;
1782 ret = eth_igb_link_update(dev, 0);
1784 /* check if link has changed */
1788 memset(&link, 0, sizeof(link));
1789 rte_igb_dev_atomic_read_link_status(dev, &link);
1790 if (link.link_status) {
1792 " Port %d: Link Up - speed %u Mbps - %s\n",
1794 (unsigned)link.link_speed,
1795 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1796 "full-duplex" : "half-duplex");
1798 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1799 dev->data->port_id);
1801 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1802 dev->pci_dev->addr.domain,
1803 dev->pci_dev->addr.bus,
1804 dev->pci_dev->addr.devid,
1805 dev->pci_dev->addr.function);
1806 tctl = E1000_READ_REG(hw, E1000_TCTL);
1807 rctl = E1000_READ_REG(hw, E1000_RCTL);
1808 if (link.link_status) {
1810 tctl |= E1000_TCTL_EN;
1811 rctl |= E1000_RCTL_EN;
1814 tctl &= ~E1000_TCTL_EN;
1815 rctl &= ~E1000_RCTL_EN;
1817 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1818 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1819 E1000_WRITE_FLUSH(hw);
1820 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1827 * Interrupt handler which shall be registered at first.
1830 * Pointer to interrupt handle.
1832 * The address of parameter (struct rte_eth_dev *) regsitered before.
1838 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1841 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1843 eth_igb_interrupt_get_status(dev);
1844 eth_igb_interrupt_action(dev);
1848 eth_igb_led_on(struct rte_eth_dev *dev)
1850 struct e1000_hw *hw;
1852 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1857 eth_igb_led_off(struct rte_eth_dev *dev)
1859 struct e1000_hw *hw;
1861 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1866 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1868 struct e1000_hw *hw;
1873 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874 fc_conf->pause_time = hw->fc.pause_time;
1875 fc_conf->high_water = hw->fc.high_water;
1876 fc_conf->low_water = hw->fc.low_water;
1877 fc_conf->send_xon = hw->fc.send_xon;
1878 fc_conf->autoneg = hw->mac.autoneg;
1881 * Return rx_pause and tx_pause status according to actual setting of
1882 * the TFCE and RFCE bits in the CTRL register.
1884 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1885 if (ctrl & E1000_CTRL_TFCE)
1890 if (ctrl & E1000_CTRL_RFCE)
1895 if (rx_pause && tx_pause)
1896 fc_conf->mode = RTE_FC_FULL;
1898 fc_conf->mode = RTE_FC_RX_PAUSE;
1900 fc_conf->mode = RTE_FC_TX_PAUSE;
1902 fc_conf->mode = RTE_FC_NONE;
1908 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1910 struct e1000_hw *hw;
1912 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1918 uint32_t rx_buf_size;
1919 uint32_t max_high_water;
1922 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923 if (fc_conf->autoneg != hw->mac.autoneg)
1925 rx_buf_size = igb_get_rx_buffer_size(hw);
1926 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1928 /* At least reserve one Ethernet frame for watermark */
1929 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1930 if ((fc_conf->high_water > max_high_water) ||
1931 (fc_conf->high_water < fc_conf->low_water)) {
1932 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1933 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1937 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1938 hw->fc.pause_time = fc_conf->pause_time;
1939 hw->fc.high_water = fc_conf->high_water;
1940 hw->fc.low_water = fc_conf->low_water;
1941 hw->fc.send_xon = fc_conf->send_xon;
1943 err = e1000_setup_link_generic(hw);
1944 if (err == E1000_SUCCESS) {
1946 /* check if we want to forward MAC frames - driver doesn't have native
1947 * capability to do that, so we'll write the registers ourselves */
1949 rctl = E1000_READ_REG(hw, E1000_RCTL);
1951 /* set or clear MFLCN.PMCF bit depending on configuration */
1952 if (fc_conf->mac_ctrl_frame_fwd != 0)
1953 rctl |= E1000_RCTL_PMCF;
1955 rctl &= ~E1000_RCTL_PMCF;
1957 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1958 E1000_WRITE_FLUSH(hw);
1963 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1967 #define E1000_RAH_POOLSEL_SHIFT (18)
1969 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1970 uint32_t index, __rte_unused uint32_t pool)
1972 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1976 rah = E1000_READ_REG(hw, E1000_RAH(index));
1977 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1978 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1982 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1984 uint8_t addr[ETHER_ADDR_LEN];
1985 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987 memset(addr, 0, sizeof(addr));
1989 e1000_rar_set(hw, addr, index);
1993 * Virtual Function operations
1996 igbvf_intr_disable(struct e1000_hw *hw)
1998 PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
2000 /* Clear interrupt mask to stop from interrupts being generated */
2001 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2003 E1000_WRITE_FLUSH(hw);
2007 igbvf_stop_adapter(struct rte_eth_dev *dev)
2011 struct rte_eth_dev_info dev_info;
2012 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014 memset(&dev_info, 0, sizeof(dev_info));
2015 eth_igb_infos_get(dev, &dev_info);
2017 /* Clear interrupt mask to stop from interrupts being generated */
2018 igbvf_intr_disable(hw);
2020 /* Clear any pending interrupts, flush previous writes */
2021 E1000_READ_REG(hw, E1000_EICR);
2023 /* Disable the transmit unit. Each queue must be disabled. */
2024 for (i = 0; i < dev_info.max_tx_queues; i++)
2025 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2027 /* Disable the receive unit by stopping each queue */
2028 for (i = 0; i < dev_info.max_rx_queues; i++) {
2029 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2030 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2031 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2032 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2036 /* flush all queues disables */
2037 E1000_WRITE_FLUSH(hw);
2041 static int eth_igbvf_link_update(struct e1000_hw *hw)
2043 struct e1000_mbx_info *mbx = &hw->mbx;
2044 struct e1000_mac_info *mac = &hw->mac;
2045 int ret_val = E1000_SUCCESS;
2047 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2050 * We only want to run this if there has been a rst asserted.
2051 * in this case that could mean a link change, device reset,
2052 * or a virtual function reset
2055 /* If we were hit with a reset or timeout drop the link */
2056 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2057 mac->get_link_status = TRUE;
2059 if (!mac->get_link_status)
2062 /* if link status is down no point in checking to see if pf is up */
2063 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2066 /* if we passed all the tests above then the link is up and we no
2067 * longer need to check for link */
2068 mac->get_link_status = FALSE;
2076 igbvf_dev_configure(struct rte_eth_dev *dev)
2078 struct rte_eth_conf* conf = &dev->data->dev_conf;
2080 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2081 dev->data->port_id);
2084 * VF has no ability to enable/disable HW CRC
2085 * Keep the persistent behavior the same as Host PF
2087 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2088 if (!conf->rxmode.hw_strip_crc) {
2089 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2090 conf->rxmode.hw_strip_crc = 1;
2093 if (conf->rxmode.hw_strip_crc) {
2094 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2095 conf->rxmode.hw_strip_crc = 0;
2103 igbvf_dev_start(struct rte_eth_dev *dev)
2105 struct e1000_hw *hw =
2106 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109 PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
2111 hw->mac.ops.reset_hw(hw);
2114 igbvf_set_vfta_all(dev,1);
2116 eth_igbvf_tx_init(dev);
2118 /* This can fail when allocating mbufs for descriptor rings */
2119 ret = eth_igbvf_rx_init(dev);
2121 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2122 igb_dev_clear_queues(dev);
2130 igbvf_dev_stop(struct rte_eth_dev *dev)
2132 PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
2134 igbvf_stop_adapter(dev);
2137 * Clear what we set, but we still keep shadow_vfta to
2138 * restore after device starts
2140 igbvf_set_vfta_all(dev,0);
2142 igb_dev_clear_queues(dev);
2146 igbvf_dev_close(struct rte_eth_dev *dev)
2148 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
2154 igbvf_dev_stop(dev);
2157 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2159 struct e1000_mbx_info *mbx = &hw->mbx;
2162 /* After set vlan, vlan strip will also be enabled in igb driver*/
2163 msgbuf[0] = E1000_VF_SET_VLAN;
2165 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2167 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2169 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2174 struct e1000_hw *hw =
2175 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176 struct e1000_vfta * shadow_vfta =
2177 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2178 int i = 0, j = 0, vfta = 0, mask = 1;
2180 for (i = 0; i < IGB_VFTA_SIZE; i++){
2181 vfta = shadow_vfta->vfta[i];
2184 for (j = 0; j < 32; j++){
2187 (uint16_t)((i<<5)+j), on);
2196 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2198 struct e1000_hw *hw =
2199 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200 struct e1000_vfta * shadow_vfta =
2201 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2202 uint32_t vid_idx = 0;
2203 uint32_t vid_bit = 0;
2206 PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2208 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2209 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2211 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2214 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2215 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2217 /*Save what we set and retore it after device reset*/
2219 shadow_vfta->vfta[vid_idx] |= vid_bit;
2221 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2227 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2228 struct rte_eth_rss_reta *reta_conf)
2232 struct e1000_hw *hw =
2233 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2237 * 128-entries in 32 registers
2239 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2240 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2241 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2243 mask = (uint8_t)((reta_conf->mask_hi >>
2244 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2247 /* If all 4 entries were set,don't need read RETA register */
2249 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2251 for (j = 0; j < 4; j++) {
2252 if (mask & (0x1 << j)) {
2254 reta &= ~(0xFF << 8 * j);
2255 reta |= reta_conf->reta[i + j] << 8 * j;
2258 E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2266 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2267 struct rte_eth_rss_reta *reta_conf)
2271 struct e1000_hw *hw =
2272 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2276 * 128-entries in 32 registers
2278 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2279 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2280 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2282 mask = (uint8_t)((reta_conf->mask_hi >>
2283 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2286 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2287 for (j = 0; j < 4; j++) {
2288 if (mask & (0x1 << j))
2289 reta_conf->reta[i + j] =
2290 (uint8_t)((reta >> 8 * j) & 0xFF);
2298 #define MAC_TYPE_FILTER_SUP(type) do {\
2299 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2300 (type) != e1000_82576)\
2305 * add the syn filter
2308 * dev: Pointer to struct rte_eth_dev.
2309 * filter: ponter to the filter that will be added.
2310 * rx_queue: the queue id the filter assigned to.
2313 * - On success, zero.
2314 * - On failure, a negative value.
2317 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2318 struct rte_syn_filter *filter, uint16_t rx_queue)
2320 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321 uint32_t synqf, rfctl;
2323 MAC_TYPE_FILTER_SUP(hw->mac.type);
2325 if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2328 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2329 if (synqf & E1000_SYN_FILTER_ENABLE)
2332 synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2333 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2335 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2336 if (filter->hig_pri)
2337 rfctl |= E1000_RFCTL_SYNQFP;
2339 rfctl &= ~E1000_RFCTL_SYNQFP;
2341 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2342 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2347 * remove the syn filter
2350 * dev: Pointer to struct rte_eth_dev.
2353 * - On success, zero.
2354 * - On failure, a negative value.
2357 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2359 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 MAC_TYPE_FILTER_SUP(hw->mac.type);
2363 E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2368 * get the syn filter's info
2371 * dev: Pointer to struct rte_eth_dev.
2372 * filter: ponter to the filter that returns.
2373 * *rx_queue: pointer to the queue id the filter assigned to.
2376 * - On success, zero.
2377 * - On failure, a negative value.
2380 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2381 struct rte_syn_filter *filter, uint16_t *rx_queue)
2383 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384 uint32_t synqf, rfctl;
2386 MAC_TYPE_FILTER_SUP(hw->mac.type);
2387 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2388 if (synqf & E1000_SYN_FILTER_ENABLE) {
2389 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2390 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2391 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2392 E1000_SYN_FILTER_QUEUE_SHIFT);
2399 * add an ethertype filter
2402 * dev: Pointer to struct rte_eth_dev.
2403 * index: the index the filter allocates.
2404 * filter: ponter to the filter that will be added.
2405 * rx_queue: the queue id the filter assigned to.
2408 * - On success, zero.
2409 * - On failure, a negative value.
2412 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2413 struct rte_ethertype_filter *filter, uint16_t rx_queue)
2415 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418 MAC_TYPE_FILTER_SUP(hw->mac.type);
2420 if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2423 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2424 if (etqf & E1000_ETQF_FILTER_ENABLE)
2425 return -EINVAL; /* filter index is in use. */
2429 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2430 etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2431 etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2433 if (filter->priority_en) {
2434 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2435 " in E1000.", filter->priority);
2439 E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2444 * remove an ethertype filter
2447 * dev: Pointer to struct rte_eth_dev.
2448 * index: the index the filter allocates.
2451 * - On success, zero.
2452 * - On failure, a negative value.
2455 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2457 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459 MAC_TYPE_FILTER_SUP(hw->mac.type);
2461 if (index >= E1000_MAX_ETQF_FILTERS)
2464 E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2469 * get an ethertype filter
2472 * dev: Pointer to struct rte_eth_dev.
2473 * index: the index the filter allocates.
2474 * filter: ponter to the filter that will be gotten.
2475 * *rx_queue: the ponited of the queue id the filter assigned to.
2478 * - On success, zero.
2479 * - On failure, a negative value.
2482 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2483 struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2485 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488 MAC_TYPE_FILTER_SUP(hw->mac.type);
2490 if (index >= E1000_MAX_ETQF_FILTERS)
2493 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2494 if (etqf & E1000_ETQF_FILTER_ENABLE) {
2495 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2496 filter->priority_en = 0;
2497 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2503 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2504 if ((type) != e1000_82580 && (type) != e1000_i350)\
2509 * add a 2tuple filter
2512 * dev: Pointer to struct rte_eth_dev.
2513 * index: the index the filter allocates.
2514 * filter: ponter to the filter that will be added.
2515 * rx_queue: the queue id the filter assigned to.
2518 * - On success, zero.
2519 * - On failure, a negative value.
2522 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2523 struct rte_2tuple_filter *filter, uint16_t rx_queue)
2525 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526 uint32_t ttqf, imir = 0;
2527 uint32_t imir_ext = 0;
2529 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2531 if (index >= E1000_MAX_TTQF_FILTERS ||
2532 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2533 filter->priority > E1000_2TUPLE_MAX_PRI)
2534 return -EINVAL; /* filter index is out of range. */
2535 if (filter->tcp_flags > TCP_FLAG_ALL)
2536 return -EINVAL; /* flags is invalid. */
2538 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2539 if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2540 return -EINVAL; /* filter index is in use. */
2542 imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2543 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2544 imir |= E1000_IMIR_PORT_BP;
2546 imir &= ~E1000_IMIR_PORT_BP;
2548 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2551 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2552 ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2553 ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2554 if (filter->protocol_mask == 1)
2555 ttqf |= E1000_TTQF_MASK_ENABLE;
2557 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2559 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2560 /* tcp flags bits setting. */
2561 if (filter->tcp_flags & TCP_FLAG_ALL) {
2562 if (filter->tcp_flags & TCP_UGR_FLAG)
2563 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2564 if (filter->tcp_flags & TCP_ACK_FLAG)
2565 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2566 if (filter->tcp_flags & TCP_PSH_FLAG)
2567 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2568 if (filter->tcp_flags & TCP_RST_FLAG)
2569 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2570 if (filter->tcp_flags & TCP_SYN_FLAG)
2571 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2572 if (filter->tcp_flags & TCP_FIN_FLAG)
2573 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2574 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2576 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2577 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2578 E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2579 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2584 * remove a 2tuple filter
2587 * dev: Pointer to struct rte_eth_dev.
2588 * index: the index the filter allocates.
2591 * - On success, zero.
2592 * - On failure, a negative value.
2595 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2598 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2600 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2602 if (index >= E1000_MAX_TTQF_FILTERS)
2603 return -EINVAL; /* filter index is out of range */
2605 E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2606 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2607 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2612 * get a 2tuple filter
2615 * dev: Pointer to struct rte_eth_dev.
2616 * index: the index the filter allocates.
2617 * filter: ponter to the filter that returns.
2618 * *rx_queue: pointer of the queue id the filter assigned to.
2621 * - On success, zero.
2622 * - On failure, a negative value.
2625 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2626 struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2628 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629 uint32_t imir, ttqf, imir_ext;
2631 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2633 if (index >= E1000_MAX_TTQF_FILTERS)
2634 return -EINVAL; /* filter index is out of range. */
2636 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2637 if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2638 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2639 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2640 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2641 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2642 E1000_TTQF_QUEUE_SHIFT;
2643 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2644 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2645 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2646 E1000_IMIR_PRIORITY_SHIFT;
2648 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2649 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2650 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2651 filter->tcp_flags |= TCP_UGR_FLAG;
2652 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2653 filter->tcp_flags |= TCP_ACK_FLAG;
2654 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2655 filter->tcp_flags |= TCP_PSH_FLAG;
2656 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2657 filter->tcp_flags |= TCP_RST_FLAG;
2658 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2659 filter->tcp_flags |= TCP_SYN_FLAG;
2660 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2661 filter->tcp_flags |= TCP_FIN_FLAG;
2663 filter->tcp_flags = 0;
2673 * dev: Pointer to struct rte_eth_dev.
2674 * index: the index the filter allocates.
2675 * filter: ponter to the filter that will be added.
2676 * rx_queue: the queue id the filter assigned to.
2679 * - On success, zero.
2680 * - On failure, a negative value.
2683 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2684 struct rte_flex_filter *filter, uint16_t rx_queue)
2686 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687 uint32_t wufc, en_bits = 0;
2688 uint32_t queueing = 0;
2689 uint32_t reg_off = 0;
2692 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2694 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2695 return -EINVAL; /* filter index is out of range. */
2697 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2698 filter->len % 8 != 0 ||
2699 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2702 wufc = E1000_READ_REG(hw, E1000_WUFC);
2703 en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2704 if ((wufc & en_bits) == en_bits)
2705 return -EINVAL; /* the filter is in use. */
2707 E1000_WRITE_REG(hw, E1000_WUFC,
2708 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2711 if (index < E1000_MAX_FHFT)
2712 reg_off = E1000_FHFT(index);
2714 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2716 for (i = 0; i < 16; i++) {
2717 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2718 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2719 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2720 (uint32_t)filter->mask[i]);
2723 queueing |= filter->len |
2724 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2725 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2726 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2731 * remove a flex filter
2734 * dev: Pointer to struct rte_eth_dev.
2735 * index: the index the filter allocates.
2738 * - On success, zero.
2739 * - On failure, a negative value.
2742 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2745 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746 uint32_t wufc, reg_off = 0;
2749 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2751 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2752 return -EINVAL; /* filter index is out of range. */
2754 wufc = E1000_READ_REG(hw, E1000_WUFC);
2755 E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2757 if (index < E1000_MAX_FHFT)
2758 reg_off = E1000_FHFT(index);
2760 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2762 for (i = 0; i < 64; i++)
2763 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2771 * dev: Pointer to struct rte_eth_dev.
2772 * index: the index the filter allocates.
2773 * filter: ponter to the filter that returns.
2774 * *rx_queue: the pointer of the queue id the filter assigned to.
2777 * - On success, zero.
2778 * - On failure, a negative value.
2781 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2782 struct rte_flex_filter *filter, uint16_t *rx_queue)
2784 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785 uint32_t wufc, queueing, wufc_en = 0;
2788 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2790 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2791 return -EINVAL; /* filter index is out of range. */
2793 wufc = E1000_READ_REG(hw, E1000_WUFC);
2794 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2796 if ((wufc & wufc_en) == wufc_en) {
2797 uint32_t reg_off = 0;
2799 if (index < E1000_MAX_FHFT)
2800 reg_off = E1000_FHFT(index);
2802 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2804 for (i = 0; i < 16; i++, j = i * 2) {
2806 E1000_READ_REG(hw, reg_off + i*4*4);
2807 filter->dwords[j+1] =
2808 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2810 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2812 queueing = E1000_READ_REG(hw,
2813 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2814 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2815 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2816 E1000_FHFT_QUEUEING_PRIO_SHIFT;
2817 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2818 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2825 * add a 5tuple filter
2828 * dev: Pointer to struct rte_eth_dev.
2829 * index: the index the filter allocates.
2830 * filter: ponter to the filter that will be added.
2831 * rx_queue: the queue id the filter assigned to.
2834 * - On success, zero.
2835 * - On failure, a negative value.
2838 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2839 struct rte_5tuple_filter *filter, uint16_t rx_queue)
2841 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 uint32_t ftqf, spqf = 0;
2844 uint32_t imir_ext = 0;
2846 if (hw->mac.type != e1000_82576)
2849 if (index >= E1000_MAX_FTQF_FILTERS ||
2850 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2851 return -EINVAL; /* filter index is out of range. */
2853 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2854 if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2855 return -EINVAL; /* filter index is in use. */
2858 ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2859 if (filter->src_ip_mask == 1) /* 1b means not compare. */
2860 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2861 if (filter->dst_ip_mask == 1)
2862 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2863 if (filter->src_port_mask == 1)
2864 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2865 if (filter->protocol_mask == 1)
2866 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2867 ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2868 ftqf |= E1000_FTQF_VF_MASK_EN;
2869 ftqf |= E1000_FTQF_QUEUE_ENABLE;
2870 E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2871 E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2872 E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2874 spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2875 E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2877 imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2878 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2879 imir |= E1000_IMIR_PORT_BP;
2881 imir &= ~E1000_IMIR_PORT_BP;
2882 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2884 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2885 /* tcp flags bits setting. */
2886 if (filter->tcp_flags & TCP_FLAG_ALL) {
2887 if (filter->tcp_flags & TCP_UGR_FLAG)
2888 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2889 if (filter->tcp_flags & TCP_ACK_FLAG)
2890 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2891 if (filter->tcp_flags & TCP_PSH_FLAG)
2892 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2893 if (filter->tcp_flags & TCP_RST_FLAG)
2894 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2895 if (filter->tcp_flags & TCP_SYN_FLAG)
2896 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2897 if (filter->tcp_flags & TCP_FIN_FLAG)
2898 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2900 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2901 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2902 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2907 * remove a 5tuple filter
2910 * dev: Pointer to struct rte_eth_dev.
2911 * index: the index the filter allocates
2914 * - On success, zero.
2915 * - On failure, a negative value.
2918 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2921 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923 if (hw->mac.type != e1000_82576)
2926 if (index >= E1000_MAX_FTQF_FILTERS)
2927 return -EINVAL; /* filter index is out of range. */
2929 E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2930 E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2931 E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2932 E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2933 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2934 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2939 * get a 5tuple filter
2942 * dev: Pointer to struct rte_eth_dev.
2943 * index: the index the filter allocates
2944 * filter: ponter to the filter that returns
2945 * *rx_queue: pointer of the queue id the filter assigned to
2948 * - On success, zero.
2949 * - On failure, a negative value.
2952 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2953 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2955 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956 uint32_t spqf, ftqf, imir, imir_ext;
2958 if (hw->mac.type != e1000_82576)
2961 if (index >= E1000_MAX_FTQF_FILTERS)
2962 return -EINVAL; /* filter index is out of range. */
2964 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2965 if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2966 filter->src_ip_mask =
2967 (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2968 filter->dst_ip_mask =
2969 (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2970 filter->src_port_mask =
2971 (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2972 filter->protocol_mask =
2973 (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2975 (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2976 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2977 E1000_FTQF_QUEUE_SHIFT);
2979 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2980 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2982 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2983 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2985 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2986 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2987 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2988 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2989 E1000_IMIR_PRIORITY_SHIFT;
2991 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2992 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2993 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2994 filter->tcp_flags |= TCP_UGR_FLAG;
2995 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2996 filter->tcp_flags |= TCP_ACK_FLAG;
2997 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2998 filter->tcp_flags |= TCP_PSH_FLAG;
2999 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
3000 filter->tcp_flags |= TCP_RST_FLAG;
3001 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3002 filter->tcp_flags |= TCP_SYN_FLAG;
3003 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3004 filter->tcp_flags |= TCP_FIN_FLAG;
3006 filter->tcp_flags = 0;
3013 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3016 struct e1000_hw *hw;
3017 struct rte_eth_dev_info dev_info;
3018 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3021 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023 #ifdef RTE_LIBRTE_82571_SUPPORT
3024 /* XXX: not bigger than max_rx_pktlen */
3025 if (hw->mac.type == e1000_82571)
3028 eth_igb_infos_get(dev, &dev_info);
3030 /* check that mtu is within the allowed range */
3031 if ((mtu < ETHER_MIN_MTU) ||
3032 (frame_size > dev_info.max_rx_pktlen))
3035 /* refuse mtu that requires the support of scattered packets when this
3036 * feature has not been enabled before. */
3037 if (!dev->data->scattered_rx &&
3038 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3041 rctl = E1000_READ_REG(hw, E1000_RCTL);
3043 /* switch to jumbo mode if needed */
3044 if (frame_size > ETHER_MAX_LEN) {
3045 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3046 rctl |= E1000_RCTL_LPE;
3048 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3049 rctl &= ~E1000_RCTL_LPE;
3051 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3053 /* update max frame size */
3054 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3056 E1000_WRITE_REG(hw, E1000_RLPML,
3057 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3062 static struct rte_driver pmd_igb_drv = {
3064 .init = rte_igb_pmd_init,
3067 static struct rte_driver pmd_igbvf_drv = {
3069 .init = rte_igbvf_pmd_init,
3072 PMD_REGISTER_DRIVER(pmd_igb_drv);
3073 PMD_REGISTER_DRIVER(pmd_igbvf_drv);