lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 /* Bit shift and mask */
  73 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  74 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  75 #define IGB_8_BIT_WIDTH  CHAR_BIT
  76 #define IGB_8_BIT_MASK   UINT8_MAX
  77
  78 static int  eth_igb_configure(struct rte_eth_dev *dev);
  79 static int  eth_igb_start(struct rte_eth_dev *dev);
  80 static void eth_igb_stop(struct rte_eth_dev *dev);
  81 static void eth_igb_close(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  91 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_dev_info *dev_info);
  93 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
  94                                 struct rte_eth_dev_info *dev_info);
  95 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  96                                 struct rte_eth_fc_conf *fc_conf);
  97 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  98                                 struct rte_eth_fc_conf *fc_conf);
  99 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 100 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 101 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 102 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 103                                                         void *param);
 104 static int  igb_hardware_init(struct e1000_hw *hw);
 105 static void igb_hw_control_acquire(struct e1000_hw *hw);
 106 static void igb_hw_control_release(struct e1000_hw *hw);
 107 static void igb_init_manageability(struct e1000_hw *hw);
 108 static void igb_release_manageability(struct e1000_hw *hw);
 109
 110 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 111
 112 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 113                 uint16_t vlan_id, int on);
 114 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 115 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 116
 117 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 118 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 119 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 120 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 121 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 122 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 123
 124 static int eth_igb_led_on(struct rte_eth_dev *dev);
 125 static int eth_igb_led_off(struct rte_eth_dev *dev);
 126
 127 static void igb_intr_disable(struct e1000_hw *hw);
 128 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 129 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 130                 struct ether_addr *mac_addr,
 131                 uint32_t index, uint32_t pool);
 132 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 133
 134 static void igbvf_intr_disable(struct e1000_hw *hw);
 135 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 136 static int igbvf_dev_start(struct rte_eth_dev *dev);
 137 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 138 static void igbvf_dev_close(struct rte_eth_dev *dev);
 139 static int eth_igbvf_link_update(struct e1000_hw *hw);
 140 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 141 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 142 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 143                 uint16_t vlan_id, int on);
 144 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 145 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 146 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 147                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 148                                    uint16_t reta_size);
 149 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 150                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                   uint16_t reta_size);
 152 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 153                         struct rte_syn_filter *filter, uint16_t rx_queue);
 154 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 155 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 156                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 157 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 158                         uint16_t index,
 159                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 160 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 161                         uint16_t index);
 162 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 163                         uint16_t index,
 164                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 165 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 166                         uint16_t index,
 167                         struct rte_flex_filter *filter, uint16_t rx_queue);
 168 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 169                         uint16_t index);
 170 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 171                         uint16_t index,
 172                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 173 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 174                         uint16_t index,
 175                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 176 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 177                         uint16_t index);
 178 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 179                         uint16_t index,
 180                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 181 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 182                         struct rte_eth_ethertype_filter *filter,
 183                         bool add);
 184 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 185                                 enum rte_filter_op filter_op,
 186                                 void *arg);
 187 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 188                         struct rte_eth_ethertype_filter *filter);
 189 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 190                      enum rte_filter_type filter_type,
 191                      enum rte_filter_op filter_op,
 192                      void *arg);
 193
 194 /*
 195  * Define VF Stats MACRO for Non "cleared on read" register
 196  */
 197 #define UPDATE_VF_STAT(reg, last, cur)            \
 198 {                                                 \
 199         u32 latest = E1000_READ_REG(hw, reg);     \
 200         cur += latest - last;                     \
 201         last = latest;                            \
 202 }
 203
 204
 205 #define IGB_FC_PAUSE_TIME 0x0680
 206 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 207 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 208
 209 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 210
 211 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 212
 213 /*
 214  * The set of PCI devices this driver supports
 215  */
 216 static struct rte_pci_id pci_id_igb_map[] = {
 217
 218 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 219 #include "rte_pci_dev_ids.h"
 220
 221 {.device_id = 0},
 222 };
 223
 224 /*
 225  * The set of PCI devices this driver supports (for 82576&I350 VF)
 226  */
 227 static struct rte_pci_id pci_id_igbvf_map[] = {
 228
 229 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 230 #include "rte_pci_dev_ids.h"
 231
 232 {.device_id = 0},
 233 };
 234
 235 static struct eth_dev_ops eth_igb_ops = {
 236         .dev_configure        = eth_igb_configure,
 237         .dev_start            = eth_igb_start,
 238         .dev_stop             = eth_igb_stop,
 239         .dev_close            = eth_igb_close,
 240         .promiscuous_enable   = eth_igb_promiscuous_enable,
 241         .promiscuous_disable  = eth_igb_promiscuous_disable,
 242         .allmulticast_enable  = eth_igb_allmulticast_enable,
 243         .allmulticast_disable = eth_igb_allmulticast_disable,
 244         .link_update          = eth_igb_link_update,
 245         .stats_get            = eth_igb_stats_get,
 246         .stats_reset          = eth_igb_stats_reset,
 247         .dev_infos_get        = eth_igb_infos_get,
 248         .mtu_set              = eth_igb_mtu_set,
 249         .vlan_filter_set      = eth_igb_vlan_filter_set,
 250         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 251         .vlan_offload_set     = eth_igb_vlan_offload_set,
 252         .rx_queue_setup       = eth_igb_rx_queue_setup,
 253         .rx_queue_release     = eth_igb_rx_queue_release,
 254         .rx_queue_count       = eth_igb_rx_queue_count,
 255         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 256         .tx_queue_setup       = eth_igb_tx_queue_setup,
 257         .tx_queue_release     = eth_igb_tx_queue_release,
 258         .dev_led_on           = eth_igb_led_on,
 259         .dev_led_off          = eth_igb_led_off,
 260         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 261         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 262         .mac_addr_add         = eth_igb_rar_set,
 263         .mac_addr_remove      = eth_igb_rar_clear,
 264         .reta_update          = eth_igb_rss_reta_update,
 265         .reta_query           = eth_igb_rss_reta_query,
 266         .rss_hash_update      = eth_igb_rss_hash_update,
 267         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 268         .add_syn_filter          = eth_igb_add_syn_filter,
 269         .remove_syn_filter       = eth_igb_remove_syn_filter,
 270         .get_syn_filter          = eth_igb_get_syn_filter,
 271         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 272         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 273         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 274         .add_flex_filter         = eth_igb_add_flex_filter,
 275         .remove_flex_filter      = eth_igb_remove_flex_filter,
 276         .get_flex_filter         = eth_igb_get_flex_filter,
 277         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 278         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 279         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 280         .filter_ctrl             = eth_igb_filter_ctrl,
 281 };
 282
 283 /*
 284  * dev_ops for virtual function, bare necessities for basic vf
 285  * operation have been implemented
 286  */
 287 static struct eth_dev_ops igbvf_eth_dev_ops = {
 288         .dev_configure        = igbvf_dev_configure,
 289         .dev_start            = igbvf_dev_start,
 290         .dev_stop             = igbvf_dev_stop,
 291         .dev_close            = igbvf_dev_close,
 292         .link_update          = eth_igb_link_update,
 293         .stats_get            = eth_igbvf_stats_get,
 294         .stats_reset          = eth_igbvf_stats_reset,
 295         .vlan_filter_set      = igbvf_vlan_filter_set,
 296         .dev_infos_get        = eth_igbvf_infos_get,
 297         .rx_queue_setup       = eth_igb_rx_queue_setup,
 298         .rx_queue_release     = eth_igb_rx_queue_release,
 299         .tx_queue_setup       = eth_igb_tx_queue_setup,
 300         .tx_queue_release     = eth_igb_tx_queue_release,
 301 };
 302
 303 /**
 304  * Atomically reads the link status information from global
 305  * structure rte_eth_dev.
 306  *
 307  * @param dev
 308  *   - Pointer to the structure rte_eth_dev to read from.
 309  *   - Pointer to the buffer to be saved with the link status.
 310  *
 311  * @return
 312  *   - On success, zero.
 313  *   - On failure, negative value.
 314  */
 315 static inline int
 316 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 317                                 struct rte_eth_link *link)
 318 {
 319         struct rte_eth_link *dst = link;
 320         struct rte_eth_link *src = &(dev->data->dev_link);
 321
 322         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 323                                         *(uint64_t *)src) == 0)
 324                 return -1;
 325
 326         return 0;
 327 }
 328
 329 /**
 330  * Atomically writes the link status information into global
 331  * structure rte_eth_dev.
 332  *
 333  * @param dev
 334  *   - Pointer to the structure rte_eth_dev to read from.
 335  *   - Pointer to the buffer to be saved with the link status.
 336  *
 337  * @return
 338  *   - On success, zero.
 339  *   - On failure, negative value.
 340  */
 341 static inline int
 342 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 343                                 struct rte_eth_link *link)
 344 {
 345         struct rte_eth_link *dst = &(dev->data->dev_link);
 346         struct rte_eth_link *src = link;
 347
 348         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 349                                         *(uint64_t *)src) == 0)
 350                 return -1;
 351
 352         return 0;
 353 }
 354
 355 static inline void
 356 igb_intr_enable(struct rte_eth_dev *dev)
 357 {
 358         struct e1000_interrupt *intr =
 359                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 360         struct e1000_hw *hw =
 361                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 362
 363         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 364         E1000_WRITE_FLUSH(hw);
 365 }
 366
 367 static void
 368 igb_intr_disable(struct e1000_hw *hw)
 369 {
 370         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 371         E1000_WRITE_FLUSH(hw);
 372 }
 373
 374 static inline int32_t
 375 igb_pf_reset_hw(struct e1000_hw *hw)
 376 {
 377         uint32_t ctrl_ext;
 378         int32_t status;
 379
 380         status = e1000_reset_hw(hw);
 381
 382         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 383         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 384         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 385         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 386         E1000_WRITE_FLUSH(hw);
 387
 388         return status;
 389 }
 390
 391 static void
 392 igb_identify_hardware(struct rte_eth_dev *dev)
 393 {
 394         struct e1000_hw *hw =
 395                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 396
 397         hw->vendor_id = dev->pci_dev->id.vendor_id;
 398         hw->device_id = dev->pci_dev->id.device_id;
 399         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 400         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 401
 402         e1000_set_mac_type(hw);
 403
 404         /* need to check if it is a vf device below */
 405 }
 406
 407 static int
 408 igb_reset_swfw_lock(struct e1000_hw *hw)
 409 {
 410         int ret_val;
 411
 412         /*
 413          * Do mac ops initialization manually here, since we will need
 414          * some function pointers set by this call.
 415          */
 416         ret_val = e1000_init_mac_params(hw);
 417         if (ret_val)
 418                 return ret_val;
 419
 420         /*
 421          * SMBI lock should not fail in this early stage. If this is the case,
 422          * it is due to an improper exit of the application.
 423          * So force the release of the faulty lock.
 424          */
 425         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 426                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 427         }
 428         e1000_put_hw_semaphore_generic(hw);
 429
 430         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 431                 uint16_t mask;
 432
 433                 /*
 434                  * Phy lock should not fail in this early stage. If this is the case,
 435                  * it is due to an improper exit of the application.
 436                  * So force the release of the faulty lock.
 437                  */
 438                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 439                 if (hw->bus.func > E1000_FUNC_1)
 440                         mask <<= 2;
 441                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 442                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 443                                     hw->bus.func);
 444                 }
 445                 hw->mac.ops.release_swfw_sync(hw, mask);
 446
 447                 /*
 448                  * This one is more tricky since it is common to all ports; but
 449                  * swfw_sync retries last long enough (1s) to be almost sure that if
 450                  * lock can not be taken it is due to an improper lock of the
 451                  * semaphore.
 452                  */
 453                 mask = E1000_SWFW_EEP_SM;
 454                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 455                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 456                 }
 457                 hw->mac.ops.release_swfw_sync(hw, mask);
 458         }
 459
 460         return E1000_SUCCESS;
 461 }
 462
 463 static int
 464 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 465                    struct rte_eth_dev *eth_dev)
 466 {
 467         int error = 0;
 468         struct rte_pci_device *pci_dev;
 469         struct e1000_hw *hw =
 470                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 471         struct e1000_vfta * shadow_vfta =
 472                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 473         uint32_t ctrl_ext;
 474
 475         pci_dev = eth_dev->pci_dev;
 476         eth_dev->dev_ops = &eth_igb_ops;
 477         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 478         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 479
 480         /* for secondary processes, we don't initialise any further as primary
 481          * has already done this work. Only check we don't need a different
 482          * RX function */
 483         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 484                 if (eth_dev->data->scattered_rx)
 485                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 486                 return 0;
 487         }
 488
 489         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 490
 491         igb_identify_hardware(eth_dev);
 492         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 493                 error = -EIO;
 494                 goto err_late;
 495         }
 496
 497         e1000_get_bus_info(hw);
 498
 499         /* Reset any pending lock */
 500         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 501                 error = -EIO;
 502                 goto err_late;
 503         }
 504
 505         /* Finish initialization */
 506         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 507                 error = -EIO;
 508                 goto err_late;
 509         }
 510
 511         hw->mac.autoneg = 1;
 512         hw->phy.autoneg_wait_to_complete = 0;
 513         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 514
 515         /* Copper options */
 516         if (hw->phy.media_type == e1000_media_type_copper) {
 517                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 518                 hw->phy.disable_polarity_correction = 0;
 519                 hw->phy.ms_type = e1000_ms_hw_default;
 520         }
 521
 522         /*
 523          * Start from a known state, this is important in reading the nvm
 524          * and mac from that.
 525          */
 526         igb_pf_reset_hw(hw);
 527
 528         /* Make sure we have a good EEPROM before we read from it */
 529         if (e1000_validate_nvm_checksum(hw) < 0) {
 530                 /*
 531                  * Some PCI-E parts fail the first check due to
 532                  * the link being in sleep state, call it again,
 533                  * if it fails a second time its a real issue.
 534                  */
 535                 if (e1000_validate_nvm_checksum(hw) < 0) {
 536                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 537                         error = -EIO;
 538                         goto err_late;
 539                 }
 540         }
 541
 542         /* Read the permanent MAC address out of the EEPROM */
 543         if (e1000_read_mac_addr(hw) != 0) {
 544                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 545                 error = -EIO;
 546                 goto err_late;
 547         }
 548
 549         /* Allocate memory for storing MAC addresses */
 550         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 551                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 552         if (eth_dev->data->mac_addrs == NULL) {
 553                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 554                                                 "store MAC addresses",
 555                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 556                 error = -ENOMEM;
 557                 goto err_late;
 558         }
 559
 560         /* Copy the permanent MAC address */
 561         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 562
 563         /* initialize the vfta */
 564         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 565
 566         /* Now initialize the hardware */
 567         if (igb_hardware_init(hw) != 0) {
 568                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 569                 rte_free(eth_dev->data->mac_addrs);
 570                 eth_dev->data->mac_addrs = NULL;
 571                 error = -ENODEV;
 572                 goto err_late;
 573         }
 574         hw->mac.get_link_status = 1;
 575
 576         /* Indicate SOL/IDER usage */
 577         if (e1000_check_reset_block(hw) < 0) {
 578                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 579                                         "SOL/IDER session");
 580         }
 581
 582         /* initialize PF if max_vfs not zero */
 583         igb_pf_host_init(eth_dev);
 584
 585         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 586         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 587         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 588         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 589         E1000_WRITE_FLUSH(hw);
 590
 591         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 592                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 593                      pci_dev->id.device_id);
 594
 595         rte_intr_callback_register(&(pci_dev->intr_handle),
 596                 eth_igb_interrupt_handler, (void *)eth_dev);
 597
 598         /* enable uio intr after callback register */
 599         rte_intr_enable(&(pci_dev->intr_handle));
 600
 601         /* enable support intr */
 602         igb_intr_enable(eth_dev);
 603
 604         return 0;
 605
 606 err_late:
 607         igb_hw_control_release(hw);
 608
 609         return (error);
 610 }
 611
 612 /*
 613  * Virtual Function device init
 614  */
 615 static int
 616 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 617                 struct rte_eth_dev *eth_dev)
 618 {
 619         struct rte_pci_device *pci_dev;
 620         struct e1000_hw *hw =
 621                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 622         int diag;
 623
 624         PMD_INIT_FUNC_TRACE();
 625
 626         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 627         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 628         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 629
 630         /* for secondary processes, we don't initialise any further as primary
 631          * has already done this work. Only check we don't need a different
 632          * RX function */
 633         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 634                 if (eth_dev->data->scattered_rx)
 635                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 636                 return 0;
 637         }
 638
 639         pci_dev = eth_dev->pci_dev;
 640
 641         hw->device_id = pci_dev->id.device_id;
 642         hw->vendor_id = pci_dev->id.vendor_id;
 643         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 644
 645         /* Initialize the shared code (base driver) */
 646         diag = e1000_setup_init_funcs(hw, TRUE);
 647         if (diag != 0) {
 648                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 649                         diag);
 650                 return -EIO;
 651         }
 652
 653         /* init_mailbox_params */
 654         hw->mbx.ops.init_params(hw);
 655
 656         /* Disable the interrupts for VF */
 657         igbvf_intr_disable(hw);
 658
 659         diag = hw->mac.ops.reset_hw(hw);
 660
 661         /* Allocate memory for storing MAC addresses */
 662         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 663                 hw->mac.rar_entry_count, 0);
 664         if (eth_dev->data->mac_addrs == NULL) {
 665                 PMD_INIT_LOG(ERR,
 666                         "Failed to allocate %d bytes needed to store MAC "
 667                         "addresses",
 668                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 669                 return -ENOMEM;
 670         }
 671
 672         /* Copy the permanent MAC address */
 673         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 674                         &eth_dev->data->mac_addrs[0]);
 675
 676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 677                      "mac.type=%s",
 678                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 679                      pci_dev->id.device_id, "igb_mac_82576_vf");
 680
 681         return 0;
 682 }
 683
 684 static struct eth_driver rte_igb_pmd = {
 685         {
 686                 .name = "rte_igb_pmd",
 687                 .id_table = pci_id_igb_map,
 688                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 689         },
 690         .eth_dev_init = eth_igb_dev_init,
 691         .dev_private_size = sizeof(struct e1000_adapter),
 692 };
 693
 694 /*
 695  * virtual function driver struct
 696  */
 697 static struct eth_driver rte_igbvf_pmd = {
 698         {
 699                 .name = "rte_igbvf_pmd",
 700                 .id_table = pci_id_igbvf_map,
 701                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 702         },
 703         .eth_dev_init = eth_igbvf_dev_init,
 704         .dev_private_size = sizeof(struct e1000_adapter),
 705 };
 706
 707 static int
 708 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 709 {
 710         rte_eth_driver_register(&rte_igb_pmd);
 711         return 0;
 712 }
 713
 714 static void
 715 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 716 {
 717         struct e1000_hw *hw =
 718                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 719         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 720         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 721         rctl |= E1000_RCTL_VFE;
 722         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 723 }
 724
 725 /*
 726  * VF Driver initialization routine.
 727  * Invoked one at EAL init time.
 728  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 729  */
 730 static int
 731 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 732 {
 733         PMD_INIT_FUNC_TRACE();
 734
 735         rte_eth_driver_register(&rte_igbvf_pmd);
 736         return (0);
 737 }
 738
 739 static int
 740 eth_igb_configure(struct rte_eth_dev *dev)
 741 {
 742         struct e1000_interrupt *intr =
 743                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 744
 745         PMD_INIT_FUNC_TRACE();
 746         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 747         PMD_INIT_FUNC_TRACE();
 748
 749         return (0);
 750 }
 751
 752 static int
 753 eth_igb_start(struct rte_eth_dev *dev)
 754 {
 755         struct e1000_hw *hw =
 756                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 757         int ret, i, mask;
 758         uint32_t ctrl_ext;
 759
 760         PMD_INIT_FUNC_TRACE();
 761
 762         /* Power up the phy. Needed to make the link go Up */
 763         e1000_power_up_phy(hw);
 764
 765         /*
 766          * Packet Buffer Allocation (PBA)
 767          * Writing PBA sets the receive portion of the buffer
 768          * the remainder is used for the transmit buffer.
 769          */
 770         if (hw->mac.type == e1000_82575) {
 771                 uint32_t pba;
 772
 773                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 774                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 775         }
 776
 777         /* Put the address into the Receive Address Array */
 778         e1000_rar_set(hw, hw->mac.addr, 0);
 779
 780         /* Initialize the hardware */
 781         if (igb_hardware_init(hw)) {
 782                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 783                 return (-EIO);
 784         }
 785
 786         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 787
 788         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 789         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 790         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 791         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 792         E1000_WRITE_FLUSH(hw);
 793
 794         /* configure PF module if SRIOV enabled */
 795         igb_pf_host_configure(dev);
 796
 797         /* Configure for OS presence */
 798         igb_init_manageability(hw);
 799
 800         eth_igb_tx_init(dev);
 801
 802         /* This can fail when allocating mbufs for descriptor rings */
 803         ret = eth_igb_rx_init(dev);
 804         if (ret) {
 805                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 806                 igb_dev_clear_queues(dev);
 807                 return ret;
 808         }
 809
 810         e1000_clear_hw_cntrs_base_generic(hw);
 811
 812         /*
 813          * VLAN Offload Settings
 814          */
 815         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 816                         ETH_VLAN_EXTEND_MASK;
 817         eth_igb_vlan_offload_set(dev, mask);
 818
 819         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 820                 /* Enable VLAN filter since VMDq always use VLAN filter */
 821                 igb_vmdq_vlan_hw_filter_enable(dev);
 822         }
 823
 824         /*
 825          * Configure the Interrupt Moderation register (EITR) with the maximum
 826          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 827          * spurious [DMA] memory updates of RX and TX ring descriptors.
 828          *
 829          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 830          * spurious memory updates per second should be expected.
 831          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 832          *
 833          * Because interrupts are not used at all, the MSI-X is not activated
 834          * and interrupt moderation is controlled by EITR[0].
 835          *
 836          * Note that having [almost] disabled memory updates of RX and TX ring
 837          * descriptors through the Interrupt Moderation mechanism, memory
 838          * updates of ring descriptors are now moderated by the configurable
 839          * value of Write-Back Threshold registers.
 840          */
 841         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 842                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 843                 (hw->mac.type == e1000_i211)) {
 844                 uint32_t ivar;
 845
 846                 /* Enable all RX & TX queues in the IVAR registers */
 847                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 848                 for (i = 0; i < 8; i++)
 849                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 850
 851                 /* Configure EITR with the maximum possible value (0xFFFF) */
 852                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 853         }
 854
 855         /* Setup link speed and duplex */
 856         switch (dev->data->dev_conf.link_speed) {
 857         case ETH_LINK_SPEED_AUTONEG:
 858                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 859                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 860                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 861                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 862                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 863                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 864                 else
 865                         goto error_invalid_config;
 866                 break;
 867         case ETH_LINK_SPEED_10:
 868                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 869                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 870                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 871                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 872                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 873                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 874                 else
 875                         goto error_invalid_config;
 876                 break;
 877         case ETH_LINK_SPEED_100:
 878                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 879                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 880                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 881                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 882                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 883                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 884                 else
 885                         goto error_invalid_config;
 886                 break;
 887         case ETH_LINK_SPEED_1000:
 888                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 889                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 890                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 891                 else
 892                         goto error_invalid_config;
 893                 break;
 894         case ETH_LINK_SPEED_10000:
 895         default:
 896                 goto error_invalid_config;
 897         }
 898         e1000_setup_link(hw);
 899
 900         /* check if lsc interrupt feature is enabled */
 901         if (dev->data->dev_conf.intr_conf.lsc != 0)
 902                 ret = eth_igb_lsc_interrupt_setup(dev);
 903
 904         /* resume enabled intr since hw reset */
 905         igb_intr_enable(dev);
 906
 907         PMD_INIT_LOG(DEBUG, "<<");
 908
 909         return (0);
 910
 911 error_invalid_config:
 912         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 913                      dev->data->dev_conf.link_speed,
 914                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 915         igb_dev_clear_queues(dev);
 916         return (-EINVAL);
 917 }
 918
 919 /*********************************************************************
 920  *
 921  *  This routine disables all traffic on the adapter by issuing a
 922  *  global reset on the MAC.
 923  *
 924  **********************************************************************/
 925 static void
 926 eth_igb_stop(struct rte_eth_dev *dev)
 927 {
 928         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929         struct rte_eth_link link;
 930
 931         igb_intr_disable(hw);
 932         igb_pf_reset_hw(hw);
 933         E1000_WRITE_REG(hw, E1000_WUC, 0);
 934
 935         /* Set bit for Go Link disconnect */
 936         if (hw->mac.type >= e1000_82580) {
 937                 uint32_t phpm_reg;
 938
 939                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 940                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 941                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 942         }
 943
 944         /* Power down the phy. Needed to make the link go Down */
 945         e1000_power_down_phy(hw);
 946
 947         igb_dev_clear_queues(dev);
 948
 949         /* clear the recorded link status */
 950         memset(&link, 0, sizeof(link));
 951         rte_igb_dev_atomic_write_link_status(dev, &link);
 952 }
 953
 954 static void
 955 eth_igb_close(struct rte_eth_dev *dev)
 956 {
 957         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 958         struct rte_eth_link link;
 959
 960         eth_igb_stop(dev);
 961         e1000_phy_hw_reset(hw);
 962         igb_release_manageability(hw);
 963         igb_hw_control_release(hw);
 964
 965         /* Clear bit for Go Link disconnect */
 966         if (hw->mac.type >= e1000_82580) {
 967                 uint32_t phpm_reg;
 968
 969                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 970                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 971                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 972         }
 973
 974         igb_dev_clear_queues(dev);
 975
 976         memset(&link, 0, sizeof(link));
 977         rte_igb_dev_atomic_write_link_status(dev, &link);
 978 }
 979
 980 static int
 981 igb_get_rx_buffer_size(struct e1000_hw *hw)
 982 {
 983         uint32_t rx_buf_size;
 984         if (hw->mac.type == e1000_82576) {
 985                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 986         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 987                 /* PBS needs to be translated according to a lookup table */
 988                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 989                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 990                 rx_buf_size = (rx_buf_size << 10);
 991         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
 992                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 993         } else {
 994                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 995         }
 996
 997         return rx_buf_size;
 998 }
 999
1000 /*********************************************************************
1001  *
1002  *  Initialize the hardware
1003  *
1004  **********************************************************************/
1005 static int
1006 igb_hardware_init(struct e1000_hw *hw)
1007 {
1008         uint32_t rx_buf_size;
1009         int diag;
1010
1011         /* Let the firmware know the OS is in control */
1012         igb_hw_control_acquire(hw);
1013
1014         /*
1015          * These parameters control the automatic generation (Tx) and
1016          * response (Rx) to Ethernet PAUSE frames.
1017          * - High water mark should allow for at least two standard size (1518)
1018          *   frames to be received after sending an XOFF.
1019          * - Low water mark works best when it is very near the high water mark.
1020          *   This allows the receiver to restart by sending XON when it has
1021          *   drained a bit. Here we use an arbitrary value of 1500 which will
1022          *   restart after one full frame is pulled from the buffer. There
1023          *   could be several smaller frames in the buffer and if so they will
1024          *   not trigger the XON until their total number reduces the buffer
1025          *   by 1500.
1026          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1027          */
1028         rx_buf_size = igb_get_rx_buffer_size(hw);
1029
1030         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1031         hw->fc.low_water = hw->fc.high_water - 1500;
1032         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1033         hw->fc.send_xon = 1;
1034
1035         /* Set Flow control, use the tunable location if sane */
1036         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1037                 hw->fc.requested_mode = igb_fc_setting;
1038         else
1039                 hw->fc.requested_mode = e1000_fc_none;
1040
1041         /* Issue a global reset */
1042         igb_pf_reset_hw(hw);
1043         E1000_WRITE_REG(hw, E1000_WUC, 0);
1044
1045         diag = e1000_init_hw(hw);
1046         if (diag < 0)
1047                 return (diag);
1048
1049         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1050         e1000_get_phy_info(hw);
1051         e1000_check_for_link(hw);
1052
1053         return (0);
1054 }
1055
1056 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1057 static void
1058 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1059 {
1060         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1061         struct e1000_hw_stats *stats =
1062                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1063         int pause_frames;
1064
1065         if(hw->phy.media_type == e1000_media_type_copper ||
1066             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1067                 stats->symerrs +=
1068                     E1000_READ_REG(hw,E1000_SYMERRS);
1069                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1070         }
1071
1072         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1073         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1074         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1075         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1076
1077         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1078         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1079         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1080         stats->dc += E1000_READ_REG(hw, E1000_DC);
1081         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1082         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1083         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1084         /*
1085         ** For watchdog management we need to know if we have been
1086         ** paused during the last interval, so capture that here.
1087         */
1088         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1089         stats->xoffrxc += pause_frames;
1090         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1091         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1092         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1093         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1094         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1095         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1096         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1097         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1098         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1099         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1100         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1101         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1102
1103         /* For the 64-bit byte counters the low dword must be read first. */
1104         /* Both registers clear on the read of the high dword */
1105
1106         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1107         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1108         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1109         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1110
1111         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1112         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1113         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1114         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1115         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1116
1117         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1118         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1119
1120         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1121         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1122         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1123         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1124         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1125         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1126         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1127         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1128         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1129         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1130
1131         /* Interrupt Counts */
1132
1133         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1134         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1135         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1136         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1137         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1138         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1139         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1140         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1141         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1142
1143         /* Host to Card Statistics */
1144
1145         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1146         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1147         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1148         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1149         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1150         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1151         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1152         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1153         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1154         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1155         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1156         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1157         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1158         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1159
1160         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1161         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1162         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1163         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1164         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1165         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1166
1167         if (rte_stats == NULL)
1168                 return;
1169
1170         /* Rx Errors */
1171         rte_stats->ibadcrc = stats->crcerrs;
1172         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1173         rte_stats->imissed = stats->mpc;
1174         rte_stats->ierrors = rte_stats->ibadcrc +
1175                              rte_stats->ibadlen +
1176                              rte_stats->imissed +
1177                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1178
1179         /* Tx Errors */
1180         rte_stats->oerrors = stats->ecol + stats->latecol;
1181
1182         /* XON/XOFF pause frames */
1183         rte_stats->tx_pause_xon  = stats->xontxc;
1184         rte_stats->rx_pause_xon  = stats->xonrxc;
1185         rte_stats->tx_pause_xoff = stats->xofftxc;
1186         rte_stats->rx_pause_xoff = stats->xoffrxc;
1187
1188         rte_stats->ipackets = stats->gprc;
1189         rte_stats->opackets = stats->gptc;
1190         rte_stats->ibytes   = stats->gorc;
1191         rte_stats->obytes   = stats->gotc;
1192 }
1193
1194 static void
1195 eth_igb_stats_reset(struct rte_eth_dev *dev)
1196 {
1197         struct e1000_hw_stats *hw_stats =
1198                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1199
1200         /* HW registers are cleared on read */
1201         eth_igb_stats_get(dev, NULL);
1202
1203         /* Reset software totals */
1204         memset(hw_stats, 0, sizeof(*hw_stats));
1205 }
1206
1207 static void
1208 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1209 {
1210         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1212                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1213
1214         /* Good Rx packets, include VF loopback */
1215         UPDATE_VF_STAT(E1000_VFGPRC,
1216             hw_stats->last_gprc, hw_stats->gprc);
1217
1218         /* Good Rx octets, include VF loopback */
1219         UPDATE_VF_STAT(E1000_VFGORC,
1220             hw_stats->last_gorc, hw_stats->gorc);
1221
1222         /* Good Tx packets, include VF loopback */
1223         UPDATE_VF_STAT(E1000_VFGPTC,
1224             hw_stats->last_gptc, hw_stats->gptc);
1225
1226         /* Good Tx octets, include VF loopback */
1227         UPDATE_VF_STAT(E1000_VFGOTC,
1228             hw_stats->last_gotc, hw_stats->gotc);
1229
1230         /* Rx Multicst packets */
1231         UPDATE_VF_STAT(E1000_VFMPRC,
1232             hw_stats->last_mprc, hw_stats->mprc);
1233
1234         /* Good Rx loopback packets */
1235         UPDATE_VF_STAT(E1000_VFGPRLBC,
1236             hw_stats->last_gprlbc, hw_stats->gprlbc);
1237
1238         /* Good Rx loopback octets */
1239         UPDATE_VF_STAT(E1000_VFGORLBC,
1240             hw_stats->last_gorlbc, hw_stats->gorlbc);
1241
1242         /* Good Tx loopback packets */
1243         UPDATE_VF_STAT(E1000_VFGPTLBC,
1244             hw_stats->last_gptlbc, hw_stats->gptlbc);
1245
1246         /* Good Tx loopback octets */
1247         UPDATE_VF_STAT(E1000_VFGOTLBC,
1248             hw_stats->last_gotlbc, hw_stats->gotlbc);
1249
1250         if (rte_stats == NULL)
1251                 return;
1252
1253         memset(rte_stats, 0, sizeof(*rte_stats));
1254         rte_stats->ipackets = hw_stats->gprc;
1255         rte_stats->ibytes = hw_stats->gorc;
1256         rte_stats->opackets = hw_stats->gptc;
1257         rte_stats->obytes = hw_stats->gotc;
1258         rte_stats->imcasts = hw_stats->mprc;
1259         rte_stats->ilbpackets = hw_stats->gprlbc;
1260         rte_stats->ilbbytes = hw_stats->gorlbc;
1261         rte_stats->olbpackets = hw_stats->gptlbc;
1262         rte_stats->olbbytes = hw_stats->gotlbc;
1263
1264 }
1265
1266 static void
1267 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1268 {
1269         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1270                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1271
1272         /* Sync HW register to the last stats */
1273         eth_igbvf_stats_get(dev, NULL);
1274
1275         /* reset HW current stats*/
1276         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1277                offsetof(struct e1000_vf_stats, gprc));
1278
1279 }
1280
1281 static void
1282 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1283 {
1284         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285
1286         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1287         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1288         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1289         dev_info->rx_offload_capa =
1290                 DEV_RX_OFFLOAD_VLAN_STRIP |
1291                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1292                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1293                 DEV_RX_OFFLOAD_TCP_CKSUM;
1294         dev_info->tx_offload_capa =
1295                 DEV_TX_OFFLOAD_VLAN_INSERT |
1296                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1297                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1298                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1299                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1300
1301         switch (hw->mac.type) {
1302         case e1000_82575:
1303                 dev_info->max_rx_queues = 4;
1304                 dev_info->max_tx_queues = 4;
1305                 dev_info->max_vmdq_pools = 0;
1306                 break;
1307
1308         case e1000_82576:
1309                 dev_info->max_rx_queues = 16;
1310                 dev_info->max_tx_queues = 16;
1311                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1312                 dev_info->vmdq_queue_num = 16;
1313                 break;
1314
1315         case e1000_82580:
1316                 dev_info->max_rx_queues = 8;
1317                 dev_info->max_tx_queues = 8;
1318                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1319                 dev_info->vmdq_queue_num = 8;
1320                 break;
1321
1322         case e1000_i350:
1323                 dev_info->max_rx_queues = 8;
1324                 dev_info->max_tx_queues = 8;
1325                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1326                 dev_info->vmdq_queue_num = 8;
1327                 break;
1328
1329         case e1000_i354:
1330                 dev_info->max_rx_queues = 8;
1331                 dev_info->max_tx_queues = 8;
1332                 break;
1333
1334         case e1000_i210:
1335                 dev_info->max_rx_queues = 4;
1336                 dev_info->max_tx_queues = 4;
1337                 dev_info->max_vmdq_pools = 0;
1338                 break;
1339
1340         case e1000_i211:
1341                 dev_info->max_rx_queues = 2;
1342                 dev_info->max_tx_queues = 2;
1343                 dev_info->max_vmdq_pools = 0;
1344                 break;
1345
1346         default:
1347                 /* Should not happen */
1348                 break;
1349         }
1350         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1351
1352         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1353                 .rx_thresh = {
1354                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1355                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1356                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1357                 },
1358                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1359                 .rx_drop_en = 0,
1360         };
1361
1362         dev_info->default_txconf = (struct rte_eth_txconf) {
1363                 .tx_thresh = {
1364                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1365                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1366                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1367                 },
1368                 .txq_flags = 0,
1369         };
1370 }
1371
1372 static void
1373 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1374 {
1375         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376
1377         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1378         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1379         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1380         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1381                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1382                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1383                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1384         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1385                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1386                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1387                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1388                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1389         switch (hw->mac.type) {
1390         case e1000_vfadapt:
1391                 dev_info->max_rx_queues = 2;
1392                 dev_info->max_tx_queues = 2;
1393                 break;
1394         case e1000_vfadapt_i350:
1395                 dev_info->max_rx_queues = 1;
1396                 dev_info->max_tx_queues = 1;
1397                 break;
1398         default:
1399                 /* Should not happen */
1400                 break;
1401         }
1402
1403         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1404                 .rx_thresh = {
1405                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1406                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1407                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1408                 },
1409                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1410                 .rx_drop_en = 0,
1411         };
1412
1413         dev_info->default_txconf = (struct rte_eth_txconf) {
1414                 .tx_thresh = {
1415                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1416                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1417                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1418                 },
1419                 .txq_flags = 0,
1420         };
1421 }
1422
1423 /* return 0 means link status changed, -1 means not changed */
1424 static int
1425 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1426 {
1427         struct e1000_hw *hw =
1428                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429         struct rte_eth_link link, old;
1430         int link_check, count;
1431
1432         link_check = 0;
1433         hw->mac.get_link_status = 1;
1434
1435         /* possible wait-to-complete in up to 9 seconds */
1436         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1437                 /* Read the real link status */
1438                 switch (hw->phy.media_type) {
1439                 case e1000_media_type_copper:
1440                         /* Do the work to read phy */
1441                         e1000_check_for_link(hw);
1442                         link_check = !hw->mac.get_link_status;
1443                         break;
1444
1445                 case e1000_media_type_fiber:
1446                         e1000_check_for_link(hw);
1447                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1448                                       E1000_STATUS_LU);
1449                         break;
1450
1451                 case e1000_media_type_internal_serdes:
1452                         e1000_check_for_link(hw);
1453                         link_check = hw->mac.serdes_has_link;
1454                         break;
1455
1456                 /* VF device is type_unknown */
1457                 case e1000_media_type_unknown:
1458                         eth_igbvf_link_update(hw);
1459                         link_check = !hw->mac.get_link_status;
1460                         break;
1461
1462                 default:
1463                         break;
1464                 }
1465                 if (link_check || wait_to_complete == 0)
1466                         break;
1467                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1468         }
1469         memset(&link, 0, sizeof(link));
1470         rte_igb_dev_atomic_read_link_status(dev, &link);
1471         old = link;
1472
1473         /* Now we check if a transition has happened */
1474         if (link_check) {
1475                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1476                                           &link.link_duplex);
1477                 link.link_status = 1;
1478         } else if (!link_check) {
1479                 link.link_speed = 0;
1480                 link.link_duplex = 0;
1481                 link.link_status = 0;
1482         }
1483         rte_igb_dev_atomic_write_link_status(dev, &link);
1484
1485         /* not changed */
1486         if (old.link_status == link.link_status)
1487                 return -1;
1488
1489         /* changed */
1490         return 0;
1491 }
1492
1493 /*
1494  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1495  * For ASF and Pass Through versions of f/w this means
1496  * that the driver is loaded.
1497  */
1498 static void
1499 igb_hw_control_acquire(struct e1000_hw *hw)
1500 {
1501         uint32_t ctrl_ext;
1502
1503         /* Let firmware know the driver has taken over */
1504         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1505         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1506 }
1507
1508 /*
1509  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1510  * For ASF and Pass Through versions of f/w this means that the
1511  * driver is no longer loaded.
1512  */
1513 static void
1514 igb_hw_control_release(struct e1000_hw *hw)
1515 {
1516         uint32_t ctrl_ext;
1517
1518         /* Let firmware taken over control of h/w */
1519         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1520         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1521                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1522 }
1523
1524 /*
1525  * Bit of a misnomer, what this really means is
1526  * to enable OS management of the system... aka
1527  * to disable special hardware management features.
1528  */
1529 static void
1530 igb_init_manageability(struct e1000_hw *hw)
1531 {
1532         if (e1000_enable_mng_pass_thru(hw)) {
1533                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1534                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1535
1536                 /* disable hardware interception of ARP */
1537                 manc &= ~(E1000_MANC_ARP_EN);
1538
1539                 /* enable receiving management packets to the host */
1540                 manc |= E1000_MANC_EN_MNG2HOST;
1541                 manc2h |= 1 << 5;  /* Mng Port 623 */
1542                 manc2h |= 1 << 6;  /* Mng Port 664 */
1543                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1544                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1545         }
1546 }
1547
1548 static void
1549 igb_release_manageability(struct e1000_hw *hw)
1550 {
1551         if (e1000_enable_mng_pass_thru(hw)) {
1552                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1553
1554                 manc |= E1000_MANC_ARP_EN;
1555                 manc &= ~E1000_MANC_EN_MNG2HOST;
1556
1557                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1558         }
1559 }
1560
1561 static void
1562 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1563 {
1564         struct e1000_hw *hw =
1565                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         uint32_t rctl;
1567
1568         rctl = E1000_READ_REG(hw, E1000_RCTL);
1569         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1570         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1571 }
1572
1573 static void
1574 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1575 {
1576         struct e1000_hw *hw =
1577                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578         uint32_t rctl;
1579
1580         rctl = E1000_READ_REG(hw, E1000_RCTL);
1581         rctl &= (~E1000_RCTL_UPE);
1582         if (dev->data->all_multicast == 1)
1583                 rctl |= E1000_RCTL_MPE;
1584         else
1585                 rctl &= (~E1000_RCTL_MPE);
1586         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1587 }
1588
1589 static void
1590 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1591 {
1592         struct e1000_hw *hw =
1593                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1594         uint32_t rctl;
1595
1596         rctl = E1000_READ_REG(hw, E1000_RCTL);
1597         rctl |= E1000_RCTL_MPE;
1598         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1599 }
1600
1601 static void
1602 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1603 {
1604         struct e1000_hw *hw =
1605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         uint32_t rctl;
1607
1608         if (dev->data->promiscuous == 1)
1609                 return; /* must remain in all_multicast mode */
1610         rctl = E1000_READ_REG(hw, E1000_RCTL);
1611         rctl &= (~E1000_RCTL_MPE);
1612         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1613 }
1614
1615 static int
1616 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1617 {
1618         struct e1000_hw *hw =
1619                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620         struct e1000_vfta * shadow_vfta =
1621                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1622         uint32_t vfta;
1623         uint32_t vid_idx;
1624         uint32_t vid_bit;
1625
1626         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1627                               E1000_VFTA_ENTRY_MASK);
1628         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1629         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1630         if (on)
1631                 vfta |= vid_bit;
1632         else
1633                 vfta &= ~vid_bit;
1634         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1635
1636         /* update local VFTA copy */
1637         shadow_vfta->vfta[vid_idx] = vfta;
1638
1639         return 0;
1640 }
1641
1642 static void
1643 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1644 {
1645         struct e1000_hw *hw =
1646                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647         uint32_t reg = ETHER_TYPE_VLAN ;
1648
1649         reg |= (tpid << 16);
1650         E1000_WRITE_REG(hw, E1000_VET, reg);
1651 }
1652
1653 static void
1654 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1655 {
1656         struct e1000_hw *hw =
1657                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658         uint32_t reg;
1659
1660         /* Filter Table Disable */
1661         reg = E1000_READ_REG(hw, E1000_RCTL);
1662         reg &= ~E1000_RCTL_CFIEN;
1663         reg &= ~E1000_RCTL_VFE;
1664         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1665 }
1666
1667 static void
1668 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1669 {
1670         struct e1000_hw *hw =
1671                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1672         struct e1000_vfta * shadow_vfta =
1673                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1674         uint32_t reg;
1675         int i;
1676
1677         /* Filter Table Enable, CFI not used for packet acceptance */
1678         reg = E1000_READ_REG(hw, E1000_RCTL);
1679         reg &= ~E1000_RCTL_CFIEN;
1680         reg |= E1000_RCTL_VFE;
1681         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1682
1683         /* restore VFTA table */
1684         for (i = 0; i < IGB_VFTA_SIZE; i++)
1685                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1686 }
1687
1688 static void
1689 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1690 {
1691         struct e1000_hw *hw =
1692                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693         uint32_t reg;
1694
1695         /* VLAN Mode Disable */
1696         reg = E1000_READ_REG(hw, E1000_CTRL);
1697         reg &= ~E1000_CTRL_VME;
1698         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1699 }
1700
1701 static void
1702 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1703 {
1704         struct e1000_hw *hw =
1705                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706         uint32_t reg;
1707
1708         /* VLAN Mode Enable */
1709         reg = E1000_READ_REG(hw, E1000_CTRL);
1710         reg |= E1000_CTRL_VME;
1711         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1712 }
1713
1714 static void
1715 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1716 {
1717         struct e1000_hw *hw =
1718                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719         uint32_t reg;
1720
1721         /* CTRL_EXT: Extended VLAN */
1722         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1723         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1724         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1725
1726         /* Update maximum packet length */
1727         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1728                 E1000_WRITE_REG(hw, E1000_RLPML,
1729                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1730                                                 VLAN_TAG_SIZE);
1731 }
1732
1733 static void
1734 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1735 {
1736         struct e1000_hw *hw =
1737                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738         uint32_t reg;
1739
1740         /* CTRL_EXT: Extended VLAN */
1741         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1742         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1743         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1744
1745         /* Update maximum packet length */
1746         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1747                 E1000_WRITE_REG(hw, E1000_RLPML,
1748                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1749                                                 2 * VLAN_TAG_SIZE);
1750 }
1751
1752 static void
1753 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1754 {
1755         if(mask & ETH_VLAN_STRIP_MASK){
1756                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1757                         igb_vlan_hw_strip_enable(dev);
1758                 else
1759                         igb_vlan_hw_strip_disable(dev);
1760         }
1761
1762         if(mask & ETH_VLAN_FILTER_MASK){
1763                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1764                         igb_vlan_hw_filter_enable(dev);
1765                 else
1766                         igb_vlan_hw_filter_disable(dev);
1767         }
1768
1769         if(mask & ETH_VLAN_EXTEND_MASK){
1770                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1771                         igb_vlan_hw_extend_enable(dev);
1772                 else
1773                         igb_vlan_hw_extend_disable(dev);
1774         }
1775 }
1776
1777
1778 /**
1779  * It enables the interrupt mask and then enable the interrupt.
1780  *
1781  * @param dev
1782  *  Pointer to struct rte_eth_dev.
1783  *
1784  * @return
1785  *  - On success, zero.
1786  *  - On failure, a negative value.
1787  */
1788 static int
1789 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1790 {
1791         struct e1000_interrupt *intr =
1792                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1793
1794         intr->mask |= E1000_ICR_LSC;
1795
1796         return 0;
1797 }
1798
1799 /*
1800  * It reads ICR and gets interrupt causes, check it and set a bit flag
1801  * to update link status.
1802  *
1803  * @param dev
1804  *  Pointer to struct rte_eth_dev.
1805  *
1806  * @return
1807  *  - On success, zero.
1808  *  - On failure, a negative value.
1809  */
1810 static int
1811 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1812 {
1813         uint32_t icr;
1814         struct e1000_hw *hw =
1815                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         struct e1000_interrupt *intr =
1817                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1818
1819         igb_intr_disable(hw);
1820
1821         /* read-on-clear nic registers here */
1822         icr = E1000_READ_REG(hw, E1000_ICR);
1823
1824         intr->flags = 0;
1825         if (icr & E1000_ICR_LSC) {
1826                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1827         }
1828
1829         if (icr & E1000_ICR_VMMB)
1830                 intr->flags |= E1000_FLAG_MAILBOX;
1831
1832         return 0;
1833 }
1834
1835 /*
1836  * It executes link_update after knowing an interrupt is prsent.
1837  *
1838  * @param dev
1839  *  Pointer to struct rte_eth_dev.
1840  *
1841  * @return
1842  *  - On success, zero.
1843  *  - On failure, a negative value.
1844  */
1845 static int
1846 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1847 {
1848         struct e1000_hw *hw =
1849                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         struct e1000_interrupt *intr =
1851                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1852         uint32_t tctl, rctl;
1853         struct rte_eth_link link;
1854         int ret;
1855
1856         if (intr->flags & E1000_FLAG_MAILBOX) {
1857                 igb_pf_mbx_process(dev);
1858                 intr->flags &= ~E1000_FLAG_MAILBOX;
1859         }
1860
1861         igb_intr_enable(dev);
1862         rte_intr_enable(&(dev->pci_dev->intr_handle));
1863
1864         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1865                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1866
1867                 /* set get_link_status to check register later */
1868                 hw->mac.get_link_status = 1;
1869                 ret = eth_igb_link_update(dev, 0);
1870
1871                 /* check if link has changed */
1872                 if (ret < 0)
1873                         return 0;
1874
1875                 memset(&link, 0, sizeof(link));
1876                 rte_igb_dev_atomic_read_link_status(dev, &link);
1877                 if (link.link_status) {
1878                         PMD_INIT_LOG(INFO,
1879                                      " Port %d: Link Up - speed %u Mbps - %s",
1880                                      dev->data->port_id,
1881                                      (unsigned)link.link_speed,
1882                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1883                                      "full-duplex" : "half-duplex");
1884                 } else {
1885                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1886                                      dev->data->port_id);
1887                 }
1888                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1889                              dev->pci_dev->addr.domain,
1890                              dev->pci_dev->addr.bus,
1891                              dev->pci_dev->addr.devid,
1892                              dev->pci_dev->addr.function);
1893                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1894                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1895                 if (link.link_status) {
1896                         /* enable Tx/Rx */
1897                         tctl |= E1000_TCTL_EN;
1898                         rctl |= E1000_RCTL_EN;
1899                 } else {
1900                         /* disable Tx/Rx */
1901                         tctl &= ~E1000_TCTL_EN;
1902                         rctl &= ~E1000_RCTL_EN;
1903                 }
1904                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1905                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1906                 E1000_WRITE_FLUSH(hw);
1907                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1908         }
1909
1910         return 0;
1911 }
1912
1913 /**
1914  * Interrupt handler which shall be registered at first.
1915  *
1916  * @param handle
1917  *  Pointer to interrupt handle.
1918  * @param param
1919  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1920  *
1921  * @return
1922  *  void
1923  */
1924 static void
1925 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1926                                                         void *param)
1927 {
1928         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1929
1930         eth_igb_interrupt_get_status(dev);
1931         eth_igb_interrupt_action(dev);
1932 }
1933
1934 static int
1935 eth_igb_led_on(struct rte_eth_dev *dev)
1936 {
1937         struct e1000_hw *hw;
1938
1939         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1941 }
1942
1943 static int
1944 eth_igb_led_off(struct rte_eth_dev *dev)
1945 {
1946         struct e1000_hw *hw;
1947
1948         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1950 }
1951
1952 static int
1953 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1954 {
1955         struct e1000_hw *hw;
1956         uint32_t ctrl;
1957         int tx_pause;
1958         int rx_pause;
1959
1960         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         fc_conf->pause_time = hw->fc.pause_time;
1962         fc_conf->high_water = hw->fc.high_water;
1963         fc_conf->low_water = hw->fc.low_water;
1964         fc_conf->send_xon = hw->fc.send_xon;
1965         fc_conf->autoneg = hw->mac.autoneg;
1966
1967         /*
1968          * Return rx_pause and tx_pause status according to actual setting of
1969          * the TFCE and RFCE bits in the CTRL register.
1970          */
1971         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1972         if (ctrl & E1000_CTRL_TFCE)
1973                 tx_pause = 1;
1974         else
1975                 tx_pause = 0;
1976
1977         if (ctrl & E1000_CTRL_RFCE)
1978                 rx_pause = 1;
1979         else
1980                 rx_pause = 0;
1981
1982         if (rx_pause && tx_pause)
1983                 fc_conf->mode = RTE_FC_FULL;
1984         else if (rx_pause)
1985                 fc_conf->mode = RTE_FC_RX_PAUSE;
1986         else if (tx_pause)
1987                 fc_conf->mode = RTE_FC_TX_PAUSE;
1988         else
1989                 fc_conf->mode = RTE_FC_NONE;
1990
1991         return 0;
1992 }
1993
1994 static int
1995 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1996 {
1997         struct e1000_hw *hw;
1998         int err;
1999         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2000                 e1000_fc_none,
2001                 e1000_fc_rx_pause,
2002                 e1000_fc_tx_pause,
2003                 e1000_fc_full
2004         };
2005         uint32_t rx_buf_size;
2006         uint32_t max_high_water;
2007         uint32_t rctl;
2008
2009         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         if (fc_conf->autoneg != hw->mac.autoneg)
2011                 return -ENOTSUP;
2012         rx_buf_size = igb_get_rx_buffer_size(hw);
2013         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2014
2015         /* At least reserve one Ethernet frame for watermark */
2016         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2017         if ((fc_conf->high_water > max_high_water) ||
2018             (fc_conf->high_water < fc_conf->low_water)) {
2019                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2020                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2021                 return (-EINVAL);
2022         }
2023
2024         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2025         hw->fc.pause_time     = fc_conf->pause_time;
2026         hw->fc.high_water     = fc_conf->high_water;
2027         hw->fc.low_water      = fc_conf->low_water;
2028         hw->fc.send_xon       = fc_conf->send_xon;
2029
2030         err = e1000_setup_link_generic(hw);
2031         if (err == E1000_SUCCESS) {
2032
2033                 /* check if we want to forward MAC frames - driver doesn't have native
2034                  * capability to do that, so we'll write the registers ourselves */
2035
2036                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2037
2038                 /* set or clear MFLCN.PMCF bit depending on configuration */
2039                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2040                         rctl |= E1000_RCTL_PMCF;
2041                 else
2042                         rctl &= ~E1000_RCTL_PMCF;
2043
2044                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2045                 E1000_WRITE_FLUSH(hw);
2046
2047                 return 0;
2048         }
2049
2050         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2051         return (-EIO);
2052 }
2053
2054 #define E1000_RAH_POOLSEL_SHIFT      (18)
2055 static void
2056 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2057                 uint32_t index, __rte_unused uint32_t pool)
2058 {
2059         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t rah;
2061
2062         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2063         rah = E1000_READ_REG(hw, E1000_RAH(index));
2064         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2065         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2066 }
2067
2068 static void
2069 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2070 {
2071         uint8_t addr[ETHER_ADDR_LEN];
2072         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073
2074         memset(addr, 0, sizeof(addr));
2075
2076         e1000_rar_set(hw, addr, index);
2077 }
2078
2079 /*
2080  * Virtual Function operations
2081  */
2082 static void
2083 igbvf_intr_disable(struct e1000_hw *hw)
2084 {
2085         PMD_INIT_FUNC_TRACE();
2086
2087         /* Clear interrupt mask to stop from interrupts being generated */
2088         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2089
2090         E1000_WRITE_FLUSH(hw);
2091 }
2092
2093 static void
2094 igbvf_stop_adapter(struct rte_eth_dev *dev)
2095 {
2096         u32 reg_val;
2097         u16 i;
2098         struct rte_eth_dev_info dev_info;
2099         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100
2101         memset(&dev_info, 0, sizeof(dev_info));
2102         eth_igbvf_infos_get(dev, &dev_info);
2103
2104         /* Clear interrupt mask to stop from interrupts being generated */
2105         igbvf_intr_disable(hw);
2106
2107         /* Clear any pending interrupts, flush previous writes */
2108         E1000_READ_REG(hw, E1000_EICR);
2109
2110         /* Disable the transmit unit.  Each queue must be disabled. */
2111         for (i = 0; i < dev_info.max_tx_queues; i++)
2112                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2113
2114         /* Disable the receive unit by stopping each queue */
2115         for (i = 0; i < dev_info.max_rx_queues; i++) {
2116                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2117                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2118                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2119                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2120                         ;
2121         }
2122
2123         /* flush all queues disables */
2124         E1000_WRITE_FLUSH(hw);
2125         msec_delay(2);
2126 }
2127
2128 static int eth_igbvf_link_update(struct e1000_hw *hw)
2129 {
2130         struct e1000_mbx_info *mbx = &hw->mbx;
2131         struct e1000_mac_info *mac = &hw->mac;
2132         int ret_val = E1000_SUCCESS;
2133
2134         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2135
2136         /*
2137          * We only want to run this if there has been a rst asserted.
2138          * in this case that could mean a link change, device reset,
2139          * or a virtual function reset
2140          */
2141
2142         /* If we were hit with a reset or timeout drop the link */
2143         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2144                 mac->get_link_status = TRUE;
2145
2146         if (!mac->get_link_status)
2147                 goto out;
2148
2149         /* if link status is down no point in checking to see if pf is up */
2150         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2151                 goto out;
2152
2153         /* if we passed all the tests above then the link is up and we no
2154          * longer need to check for link */
2155         mac->get_link_status = FALSE;
2156
2157 out:
2158         return ret_val;
2159 }
2160
2161
2162 static int
2163 igbvf_dev_configure(struct rte_eth_dev *dev)
2164 {
2165         struct rte_eth_conf* conf = &dev->data->dev_conf;
2166
2167         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2168                      dev->data->port_id);
2169
2170         /*
2171          * VF has no ability to enable/disable HW CRC
2172          * Keep the persistent behavior the same as Host PF
2173          */
2174 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2175         if (!conf->rxmode.hw_strip_crc) {
2176                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2177                 conf->rxmode.hw_strip_crc = 1;
2178         }
2179 #else
2180         if (conf->rxmode.hw_strip_crc) {
2181                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2182                 conf->rxmode.hw_strip_crc = 0;
2183         }
2184 #endif
2185
2186         return 0;
2187 }
2188
2189 static int
2190 igbvf_dev_start(struct rte_eth_dev *dev)
2191 {
2192         struct e1000_hw *hw =
2193                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194         int ret;
2195
2196         PMD_INIT_FUNC_TRACE();
2197
2198         hw->mac.ops.reset_hw(hw);
2199
2200         /* Set all vfta */
2201         igbvf_set_vfta_all(dev,1);
2202
2203         eth_igbvf_tx_init(dev);
2204
2205         /* This can fail when allocating mbufs for descriptor rings */
2206         ret = eth_igbvf_rx_init(dev);
2207         if (ret) {
2208                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2209                 igb_dev_clear_queues(dev);
2210                 return ret;
2211         }
2212
2213         return 0;
2214 }
2215
2216 static void
2217 igbvf_dev_stop(struct rte_eth_dev *dev)
2218 {
2219         PMD_INIT_FUNC_TRACE();
2220
2221         igbvf_stop_adapter(dev);
2222
2223         /*
2224           * Clear what we set, but we still keep shadow_vfta to
2225           * restore after device starts
2226           */
2227         igbvf_set_vfta_all(dev,0);
2228
2229         igb_dev_clear_queues(dev);
2230 }
2231
2232 static void
2233 igbvf_dev_close(struct rte_eth_dev *dev)
2234 {
2235         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236
2237         PMD_INIT_FUNC_TRACE();
2238
2239         e1000_reset_hw(hw);
2240
2241         igbvf_dev_stop(dev);
2242 }
2243
2244 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2245 {
2246         struct e1000_mbx_info *mbx = &hw->mbx;
2247         uint32_t msgbuf[2];
2248
2249         /* After set vlan, vlan strip will also be enabled in igb driver*/
2250         msgbuf[0] = E1000_VF_SET_VLAN;
2251         msgbuf[1] = vid;
2252         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2253         if (on)
2254                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2255
2256         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2257 }
2258
2259 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2260 {
2261         struct e1000_hw *hw =
2262                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263         struct e1000_vfta * shadow_vfta =
2264                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2265         int i = 0, j = 0, vfta = 0, mask = 1;
2266
2267         for (i = 0; i < IGB_VFTA_SIZE; i++){
2268                 vfta = shadow_vfta->vfta[i];
2269                 if(vfta){
2270                         mask = 1;
2271                         for (j = 0; j < 32; j++){
2272                                 if(vfta & mask)
2273                                         igbvf_set_vfta(hw,
2274                                                 (uint16_t)((i<<5)+j), on);
2275                                 mask<<=1;
2276                         }
2277                 }
2278         }
2279
2280 }
2281
2282 static int
2283 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2284 {
2285         struct e1000_hw *hw =
2286                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         struct e1000_vfta * shadow_vfta =
2288                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2289         uint32_t vid_idx = 0;
2290         uint32_t vid_bit = 0;
2291         int ret = 0;
2292
2293         PMD_INIT_FUNC_TRACE();
2294
2295         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2296         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2297         if(ret){
2298                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2299                 return ret;
2300         }
2301         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2302         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2303
2304         /*Save what we set and retore it after device reset*/
2305         if (on)
2306                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2307         else
2308                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2309
2310         return 0;
2311 }
2312
2313 static int
2314 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2315                         struct rte_eth_rss_reta_entry64 *reta_conf,
2316                         uint16_t reta_size)
2317 {
2318         uint8_t i, j, mask;
2319         uint32_t reta, r;
2320         uint16_t idx, shift;
2321         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322
2323         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2324                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2325                         "(%d) doesn't match the number hardware can supported "
2326                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2327                 return -EINVAL;
2328         }
2329
2330         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2331                 idx = i / RTE_RETA_GROUP_SIZE;
2332                 shift = i % RTE_RETA_GROUP_SIZE;
2333                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2334                                                 IGB_4_BIT_MASK);
2335                 if (!mask)
2336                         continue;
2337                 if (mask == IGB_4_BIT_MASK)
2338                         r = 0;
2339                 else
2340                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2341                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2342                         if (mask & (0x1 << j))
2343                                 reta |= reta_conf[idx].reta[shift + j] <<
2344                                                         (CHAR_BIT * j);
2345                         else
2346                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2347                 }
2348                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2349         }
2350
2351         return 0;
2352 }
2353
2354 static int
2355 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2356                        struct rte_eth_rss_reta_entry64 *reta_conf,
2357                        uint16_t reta_size)
2358 {
2359         uint8_t i, j, mask;
2360         uint32_t reta;
2361         uint16_t idx, shift;
2362         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363
2364         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2365                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2366                         "(%d) doesn't match the number hardware can supported "
2367                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2368                 return -EINVAL;
2369         }
2370
2371         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2372                 idx = i / RTE_RETA_GROUP_SIZE;
2373                 shift = i % RTE_RETA_GROUP_SIZE;
2374                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2375                                                 IGB_4_BIT_MASK);
2376                 if (!mask)
2377                         continue;
2378                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2379                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2380                         if (mask & (0x1 << j))
2381                                 reta_conf[idx].reta[shift + j] =
2382                                         ((reta >> (CHAR_BIT * j)) &
2383                                                 IGB_8_BIT_MASK);
2384                 }
2385         }
2386
2387         return 0;
2388 }
2389
2390 #define MAC_TYPE_FILTER_SUP(type)    do {\
2391         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2392                 (type) != e1000_82576)\
2393                 return -ENOTSUP;\
2394 } while (0)
2395
2396 /*
2397  * add the syn filter
2398  *
2399  * @param
2400  * dev: Pointer to struct rte_eth_dev.
2401  * filter: ponter to the filter that will be added.
2402  * rx_queue: the queue id the filter assigned to.
2403  *
2404  * @return
2405  *    - On success, zero.
2406  *    - On failure, a negative value.
2407  */
2408 static int
2409 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2410                         struct rte_syn_filter *filter, uint16_t rx_queue)
2411 {
2412         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413         uint32_t synqf, rfctl;
2414
2415         MAC_TYPE_FILTER_SUP(hw->mac.type);
2416
2417         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2418                 return -EINVAL;
2419
2420         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2421         if (synqf & E1000_SYN_FILTER_ENABLE)
2422                 return -EINVAL;
2423
2424         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2425                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2426
2427         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2428         if (filter->hig_pri)
2429                 rfctl |= E1000_RFCTL_SYNQFP;
2430         else
2431                 rfctl &= ~E1000_RFCTL_SYNQFP;
2432
2433         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2434         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2435         return 0;
2436 }
2437
2438 /*
2439  * remove the syn filter
2440  *
2441  * @param
2442  * dev: Pointer to struct rte_eth_dev.
2443  *
2444  * @return
2445  *    - On success, zero.
2446  *    - On failure, a negative value.
2447  */
2448 static int
2449 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2450 {
2451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452
2453         MAC_TYPE_FILTER_SUP(hw->mac.type);
2454
2455         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2456         return 0;
2457 }
2458
2459 /*
2460  * get the syn filter's info
2461  *
2462  * @param
2463  * dev: Pointer to struct rte_eth_dev.
2464  * filter: ponter to the filter that returns.
2465  * *rx_queue: pointer to the queue id the filter assigned to.
2466  *
2467  * @return
2468  *    - On success, zero.
2469  *    - On failure, a negative value.
2470  */
2471 static int
2472 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2473                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2474 {
2475         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         uint32_t synqf, rfctl;
2477
2478         MAC_TYPE_FILTER_SUP(hw->mac.type);
2479         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2480         if (synqf & E1000_SYN_FILTER_ENABLE) {
2481                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2482                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2483                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2484                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2485                 return 0;
2486         }
2487         return -ENOENT;
2488 }
2489
2490 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2491         if ((type) != e1000_82580 && (type) != e1000_i350)\
2492                 return -ENOSYS; \
2493 } while (0)
2494
2495 /*
2496  * add a 2tuple filter
2497  *
2498  * @param
2499  * dev: Pointer to struct rte_eth_dev.
2500  * index: the index the filter allocates.
2501  * filter: ponter to the filter that will be added.
2502  * rx_queue: the queue id the filter assigned to.
2503  *
2504  * @return
2505  *    - On success, zero.
2506  *    - On failure, a negative value.
2507  */
2508 static int
2509 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2510                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2511 {
2512         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         uint32_t ttqf, imir = 0;
2514         uint32_t imir_ext = 0;
2515
2516         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2517
2518         if (index >= E1000_MAX_TTQF_FILTERS ||
2519                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2520                 filter->priority > E1000_2TUPLE_MAX_PRI)
2521                 return -EINVAL;  /* filter index is out of range. */
2522         if  (filter->tcp_flags > TCP_FLAG_ALL)
2523                 return -EINVAL;  /* flags is invalid. */
2524
2525         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2526         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2527                 return -EINVAL;  /* filter index is in use. */
2528
2529         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2530         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2531                 imir |= E1000_IMIR_PORT_BP;
2532         else
2533                 imir &= ~E1000_IMIR_PORT_BP;
2534
2535         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2536
2537         ttqf = 0;
2538         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2539         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2540         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2541         if (filter->protocol_mask == 1)
2542                 ttqf |= E1000_TTQF_MASK_ENABLE;
2543         else
2544                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2545
2546         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2547         /* tcp flags bits setting. */
2548         if (filter->tcp_flags & TCP_FLAG_ALL) {
2549                 if (filter->tcp_flags & TCP_UGR_FLAG)
2550                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2551                 if (filter->tcp_flags & TCP_ACK_FLAG)
2552                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2553                 if (filter->tcp_flags & TCP_PSH_FLAG)
2554                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2555                 if (filter->tcp_flags & TCP_RST_FLAG)
2556                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2557                 if (filter->tcp_flags & TCP_SYN_FLAG)
2558                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2559                 if (filter->tcp_flags & TCP_FIN_FLAG)
2560                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2561                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2562         } else
2563                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2564         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2565         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2566         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2567         return 0;
2568 }
2569
2570 /*
2571  * remove a 2tuple filter
2572  *
2573  * @param
2574  * dev: Pointer to struct rte_eth_dev.
2575  * index: the index the filter allocates.
2576  *
2577  * @return
2578  *    - On success, zero.
2579  *    - On failure, a negative value.
2580  */
2581 static int
2582 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2583                         uint16_t index)
2584 {
2585         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586
2587         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2588
2589         if (index >= E1000_MAX_TTQF_FILTERS)
2590                 return -EINVAL;  /* filter index is out of range */
2591
2592         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2593         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2594         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2595         return 0;
2596 }
2597
2598 /*
2599  * get a 2tuple filter
2600  *
2601  * @param
2602  * dev: Pointer to struct rte_eth_dev.
2603  * index: the index the filter allocates.
2604  * filter: ponter to the filter that returns.
2605  * *rx_queue: pointer of the queue id the filter assigned to.
2606  *
2607  * @return
2608  *    - On success, zero.
2609  *    - On failure, a negative value.
2610  */
2611 static int
2612 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2613                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2614 {
2615         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         uint32_t imir, ttqf, imir_ext;
2617
2618         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2619
2620         if (index >= E1000_MAX_TTQF_FILTERS)
2621                 return -EINVAL;  /* filter index is out of range. */
2622
2623         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2624         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2625                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2626                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2627                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2628                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2629                                 E1000_TTQF_QUEUE_SHIFT;
2630                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2631                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2632                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2633                         E1000_IMIR_PRIORITY_SHIFT;
2634
2635                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2636                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2637                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2638                                 filter->tcp_flags |= TCP_UGR_FLAG;
2639                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2640                                 filter->tcp_flags |= TCP_ACK_FLAG;
2641                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2642                                 filter->tcp_flags |= TCP_PSH_FLAG;
2643                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2644                                 filter->tcp_flags |= TCP_RST_FLAG;
2645                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2646                                 filter->tcp_flags |= TCP_SYN_FLAG;
2647                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2648                                 filter->tcp_flags |= TCP_FIN_FLAG;
2649                 } else
2650                         filter->tcp_flags = 0;
2651                 return 0;
2652         }
2653         return -ENOENT;
2654 }
2655
2656 /*
2657  * add a flex filter
2658  *
2659  * @param
2660  * dev: Pointer to struct rte_eth_dev.
2661  * index: the index the filter allocates.
2662  * filter: ponter to the filter that will be added.
2663  * rx_queue: the queue id the filter assigned to.
2664  *
2665  * @return
2666  *    - On success, zero.
2667  *     - On failure, a negative value.
2668  */
2669 static int
2670 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2671                         struct rte_flex_filter *filter, uint16_t rx_queue)
2672 {
2673         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674         uint32_t wufc, en_bits = 0;
2675         uint32_t queueing = 0;
2676         uint32_t reg_off = 0;
2677         uint8_t i, j = 0;
2678
2679         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2680
2681         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2682                 return -EINVAL;  /* filter index is out of range. */
2683
2684         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2685                 filter->len % 8 != 0 ||
2686                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2687                 return -EINVAL;
2688
2689         wufc = E1000_READ_REG(hw, E1000_WUFC);
2690         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2691         if ((wufc & en_bits) == en_bits)
2692                 return -EINVAL;  /* the filter is in use. */
2693
2694         E1000_WRITE_REG(hw, E1000_WUFC,
2695                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2696
2697         j = 0;
2698         if (index < E1000_MAX_FHFT)
2699                 reg_off = E1000_FHFT(index);
2700         else
2701                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2702
2703         for (i = 0; i < 16; i++) {
2704                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2705                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2706                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2707                                 (uint32_t)filter->mask[i]);
2708                 ++j;
2709         }
2710         queueing |= filter->len |
2711                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2712                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2713         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2714         return 0;
2715 }
2716
2717 /*
2718  * remove a flex filter
2719  *
2720  * @param
2721  * dev: Pointer to struct rte_eth_dev.
2722  * index: the index the filter allocates.
2723  *
2724  * @return
2725  *    - On success, zero.
2726  *    - On failure, a negative value.
2727  */
2728 static int
2729 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2730                                 uint16_t index)
2731 {
2732         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733         uint32_t wufc, reg_off = 0;
2734         uint8_t i;
2735
2736         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2737
2738         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2739                 return -EINVAL;  /* filter index is out of range. */
2740
2741         wufc = E1000_READ_REG(hw, E1000_WUFC);
2742         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2743
2744         if (index < E1000_MAX_FHFT)
2745                 reg_off = E1000_FHFT(index);
2746         else
2747                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2748
2749         for (i = 0; i < 64; i++)
2750                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2751         return 0;
2752 }
2753
2754 /*
2755  * get a flex filter
2756  *
2757  * @param
2758  * dev: Pointer to struct rte_eth_dev.
2759  * index: the index the filter allocates.
2760  * filter: ponter to the filter that returns.
2761  * *rx_queue: the pointer of the queue id the filter assigned to.
2762  *
2763  * @return
2764  *    - On success, zero.
2765  *    - On failure, a negative value.
2766  */
2767 static int
2768 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2769                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2770 {
2771         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772         uint32_t wufc, queueing, wufc_en = 0;
2773         uint8_t i, j;
2774
2775         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2776
2777         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2778                 return -EINVAL;  /* filter index is out of range. */
2779
2780         wufc = E1000_READ_REG(hw, E1000_WUFC);
2781         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2782
2783         if ((wufc & wufc_en) == wufc_en) {
2784                 uint32_t reg_off = 0;
2785                 j = 0;
2786                 if (index < E1000_MAX_FHFT)
2787                         reg_off = E1000_FHFT(index);
2788                 else
2789                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2790
2791                 for (i = 0; i < 16; i++, j = i * 2) {
2792                         filter->dwords[j] =
2793                                 E1000_READ_REG(hw, reg_off + i*4*4);
2794                         filter->dwords[j+1] =
2795                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2796                         filter->mask[i] =
2797                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2798                 }
2799                 queueing = E1000_READ_REG(hw,
2800                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2801                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2802                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2803                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2804                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2805                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2806                 return 0;
2807         }
2808         return -ENOENT;
2809 }
2810
2811 /*
2812  * add a 5tuple filter
2813  *
2814  * @param
2815  * dev: Pointer to struct rte_eth_dev.
2816  * index: the index the filter allocates.
2817  * filter: ponter to the filter that will be added.
2818  * rx_queue: the queue id the filter assigned to.
2819  *
2820  * @return
2821  *    - On success, zero.
2822  *    - On failure, a negative value.
2823  */
2824 static int
2825 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2826                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2827 {
2828         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829         uint32_t ftqf, spqf = 0;
2830         uint32_t imir = 0;
2831         uint32_t imir_ext = 0;
2832
2833         if (hw->mac.type != e1000_82576)
2834                 return -ENOSYS;
2835
2836         if (index >= E1000_MAX_FTQF_FILTERS ||
2837                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2838                 return -EINVAL;  /* filter index is out of range. */
2839
2840         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2841         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2842                 return -EINVAL;  /* filter index is in use. */
2843
2844         ftqf = 0;
2845         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2846         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2847                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2848         if (filter->dst_ip_mask == 1)
2849                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2850         if (filter->src_port_mask == 1)
2851                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2852         if (filter->protocol_mask == 1)
2853                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2854         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2855         ftqf |= E1000_FTQF_VF_MASK_EN;
2856         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2857         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2858         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2859         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2860
2861         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2862         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2863
2864         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2865         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2866                 imir |= E1000_IMIR_PORT_BP;
2867         else
2868                 imir &= ~E1000_IMIR_PORT_BP;
2869         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2870
2871         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2872         /* tcp flags bits setting. */
2873         if (filter->tcp_flags & TCP_FLAG_ALL) {
2874                 if (filter->tcp_flags & TCP_UGR_FLAG)
2875                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2876                 if (filter->tcp_flags & TCP_ACK_FLAG)
2877                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2878                 if (filter->tcp_flags & TCP_PSH_FLAG)
2879                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2880                 if (filter->tcp_flags & TCP_RST_FLAG)
2881                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2882                 if (filter->tcp_flags & TCP_SYN_FLAG)
2883                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2884                 if (filter->tcp_flags & TCP_FIN_FLAG)
2885                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2886         } else
2887                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2888         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2889         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2890         return 0;
2891 }
2892
2893 /*
2894  * remove a 5tuple filter
2895  *
2896  * @param
2897  * dev: Pointer to struct rte_eth_dev.
2898  * index: the index the filter allocates
2899  *
2900  * @return
2901  *    - On success, zero.
2902  *    - On failure, a negative value.
2903  */
2904 static int
2905 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2906                                 uint16_t index)
2907 {
2908         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2909
2910         if (hw->mac.type != e1000_82576)
2911                 return -ENOSYS;
2912
2913         if (index >= E1000_MAX_FTQF_FILTERS)
2914                 return -EINVAL;  /* filter index is out of range. */
2915
2916         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2917         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2918         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2919         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2920         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2921         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2922         return 0;
2923 }
2924
2925 /*
2926  * get a 5tuple filter
2927  *
2928  * @param
2929  * dev: Pointer to struct rte_eth_dev.
2930  * index: the index the filter allocates
2931  * filter: ponter to the filter that returns
2932  * *rx_queue: pointer of the queue id the filter assigned to
2933  *
2934  * @return
2935  *    - On success, zero.
2936  *    - On failure, a negative value.
2937  */
2938 static int
2939 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2940                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2941 {
2942         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943         uint32_t spqf, ftqf, imir, imir_ext;
2944
2945         if (hw->mac.type != e1000_82576)
2946                 return -ENOSYS;
2947
2948         if (index >= E1000_MAX_FTQF_FILTERS)
2949                 return -EINVAL;  /* filter index is out of range. */
2950
2951         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2952         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2953                 filter->src_ip_mask =
2954                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2955                 filter->dst_ip_mask =
2956                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2957                 filter->src_port_mask =
2958                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2959                 filter->protocol_mask =
2960                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2961                 filter->protocol =
2962                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2963                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2964                                 E1000_FTQF_QUEUE_SHIFT);
2965
2966                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2967                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2968
2969                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2970                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2971
2972                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2973                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2974                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2975                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2976                         E1000_IMIR_PRIORITY_SHIFT;
2977
2978                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2979                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2980                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2981                                 filter->tcp_flags |= TCP_UGR_FLAG;
2982                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2983                                 filter->tcp_flags |= TCP_ACK_FLAG;
2984                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2985                                 filter->tcp_flags |= TCP_PSH_FLAG;
2986                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2987                                 filter->tcp_flags |= TCP_RST_FLAG;
2988                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2989                                 filter->tcp_flags |= TCP_SYN_FLAG;
2990                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2991                                 filter->tcp_flags |= TCP_FIN_FLAG;
2992                 } else
2993                         filter->tcp_flags = 0;
2994                 return 0;
2995         }
2996         return -ENOENT;
2997 }
2998
2999 static int
3000 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3001 {
3002         uint32_t rctl;
3003         struct e1000_hw *hw;
3004         struct rte_eth_dev_info dev_info;
3005         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3006                                      VLAN_TAG_SIZE);
3007
3008         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009
3010 #ifdef RTE_LIBRTE_82571_SUPPORT
3011         /* XXX: not bigger than max_rx_pktlen */
3012         if (hw->mac.type == e1000_82571)
3013                 return -ENOTSUP;
3014 #endif
3015         eth_igb_infos_get(dev, &dev_info);
3016
3017         /* check that mtu is within the allowed range */
3018         if ((mtu < ETHER_MIN_MTU) ||
3019             (frame_size > dev_info.max_rx_pktlen))
3020                 return -EINVAL;
3021
3022         /* refuse mtu that requires the support of scattered packets when this
3023          * feature has not been enabled before. */
3024         if (!dev->data->scattered_rx &&
3025             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3026                 return -EINVAL;
3027
3028         rctl = E1000_READ_REG(hw, E1000_RCTL);
3029
3030         /* switch to jumbo mode if needed */
3031         if (frame_size > ETHER_MAX_LEN) {
3032                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3033                 rctl |= E1000_RCTL_LPE;
3034         } else {
3035                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3036                 rctl &= ~E1000_RCTL_LPE;
3037         }
3038         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3039
3040         /* update max frame size */
3041         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3042
3043         E1000_WRITE_REG(hw, E1000_RLPML,
3044                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3045
3046         return 0;
3047 }
3048
3049 static inline int
3050 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3051                         uint16_t ethertype)
3052 {
3053         int i;
3054
3055         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3056                 if (filter_info->ethertype_filters[i] == ethertype &&
3057                     (filter_info->ethertype_mask & (1 << i)))
3058                         return i;
3059         }
3060         return -1;
3061 }
3062
3063 static inline int
3064 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3065                         uint16_t ethertype)
3066 {
3067         int i;
3068
3069         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3070                 if (!(filter_info->ethertype_mask & (1 << i))) {
3071                         filter_info->ethertype_mask |= 1 << i;
3072                         filter_info->ethertype_filters[i] = ethertype;
3073                         return i;
3074                 }
3075         }
3076         return -1;
3077 }
3078
3079 static inline int
3080 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3081                         uint8_t idx)
3082 {
3083         if (idx >= E1000_MAX_ETQF_FILTERS)
3084                 return -1;
3085         filter_info->ethertype_mask &= ~(1 << idx);
3086         filter_info->ethertype_filters[idx] = 0;
3087         return idx;
3088 }
3089
3090
3091 static int
3092 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3093                         struct rte_eth_ethertype_filter *filter,
3094                         bool add)
3095 {
3096         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097         struct e1000_filter_info *filter_info =
3098                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3099         uint32_t etqf = 0;
3100         int ret;
3101
3102         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3103                 filter->ether_type == ETHER_TYPE_IPv6) {
3104                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3105                         " ethertype filter.", filter->ether_type);
3106                 return -EINVAL;
3107         }
3108
3109         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3110                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3111                 return -EINVAL;
3112         }
3113         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3114                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3115                 return -EINVAL;
3116         }
3117
3118         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3119         if (ret >= 0 && add) {
3120                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3121                             filter->ether_type);
3122                 return -EEXIST;
3123         }
3124         if (ret < 0 && !add) {
3125                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3126                             filter->ether_type);
3127                 return -ENOENT;
3128         }
3129
3130         if (add) {
3131                 ret = igb_ethertype_filter_insert(filter_info,
3132                         filter->ether_type);
3133                 if (ret < 0) {
3134                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3135                         return -ENOSYS;
3136                 }
3137
3138                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3139                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3140                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3141         } else {
3142                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3143                 if (ret < 0)
3144                         return -ENOSYS;
3145         }
3146         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3147         E1000_WRITE_FLUSH(hw);
3148
3149         return 0;
3150 }
3151
3152 static int
3153 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3154                         struct rte_eth_ethertype_filter *filter)
3155 {
3156         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3157         struct e1000_filter_info *filter_info =
3158                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3159         uint32_t etqf;
3160         int ret;
3161
3162         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3163         if (ret < 0) {
3164                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3165                             filter->ether_type);
3166                 return -ENOENT;
3167         }
3168
3169         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3170         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3171                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3172                 filter->flags = 0;
3173                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3174                                 E1000_ETQF_QUEUE_SHIFT;
3175                 return 0;
3176         }
3177
3178         return -ENOENT;
3179 }
3180
3181 /*
3182  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3183  * @dev: pointer to rte_eth_dev structure
3184  * @filter_op:operation will be taken.
3185  * @arg: a pointer to specific structure corresponding to the filter_op
3186  */
3187 static int
3188 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3189                                 enum rte_filter_op filter_op,
3190                                 void *arg)
3191 {
3192         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3193         int ret;
3194
3195         MAC_TYPE_FILTER_SUP(hw->mac.type);
3196
3197         if (filter_op == RTE_ETH_FILTER_NOP)
3198                 return 0;
3199
3200         if (arg == NULL) {
3201                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3202                             filter_op);
3203                 return -EINVAL;
3204         }
3205
3206         switch (filter_op) {
3207         case RTE_ETH_FILTER_ADD:
3208                 ret = igb_add_del_ethertype_filter(dev,
3209                         (struct rte_eth_ethertype_filter *)arg,
3210                         TRUE);
3211                 break;
3212         case RTE_ETH_FILTER_DELETE:
3213                 ret = igb_add_del_ethertype_filter(dev,
3214                         (struct rte_eth_ethertype_filter *)arg,
3215                         FALSE);
3216                 break;
3217         case RTE_ETH_FILTER_GET:
3218                 ret = igb_get_ethertype_filter(dev,
3219                         (struct rte_eth_ethertype_filter *)arg);
3220                 break;
3221         default:
3222                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3223                 ret = -EINVAL;
3224                 break;
3225         }
3226         return ret;
3227 }
3228
3229 static int
3230 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3231                      enum rte_filter_type filter_type,
3232                      enum rte_filter_op filter_op,
3233                      void *arg)
3234 {
3235         int ret = -EINVAL;
3236
3237         switch (filter_type) {
3238         case RTE_ETH_FILTER_ETHERTYPE:
3239                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3240                 break;
3241         default:
3242                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3243                                                         filter_type);
3244                 break;
3245         }
3246
3247         return ret;
3248 }
3249
3250 static struct rte_driver pmd_igb_drv = {
3251         .type = PMD_PDEV,
3252         .init = rte_igb_pmd_init,
3253 };
3254
3255 static struct rte_driver pmd_igbvf_drv = {
3256         .type = PMD_PDEV,
3257         .init = rte_igbvf_pmd_init,
3258 };
3259
3260 PMD_REGISTER_DRIVER(pmd_igb_drv);
3261 PMD_REGISTER_DRIVER(pmd_igbvf_drv);