4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
64 #define IGB_DEFAULT_RX_PTHRESH 8
65 #define IGB_DEFAULT_RX_HTHRESH 8
66 #define IGB_DEFAULT_RX_WTHRESH 0
68 #define IGB_DEFAULT_TX_PTHRESH 32
69 #define IGB_DEFAULT_TX_HTHRESH 0
70 #define IGB_DEFAULT_TX_WTHRESH 0
72 /* Bit shift and mask */
73 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
74 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
75 #define IGB_8_BIT_WIDTH CHAR_BIT
76 #define IGB_8_BIT_MASK UINT8_MAX
78 static int eth_igb_configure(struct rte_eth_dev *dev);
79 static int eth_igb_start(struct rte_eth_dev *dev);
80 static void eth_igb_stop(struct rte_eth_dev *dev);
81 static void eth_igb_close(struct rte_eth_dev *dev);
82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static void eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
91 static void eth_igb_infos_get(struct rte_eth_dev *dev,
92 struct rte_eth_dev_info *dev_info);
93 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
94 struct rte_eth_dev_info *dev_info);
95 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
96 struct rte_eth_fc_conf *fc_conf);
97 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
98 struct rte_eth_fc_conf *fc_conf);
99 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
100 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
101 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
102 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
104 static int igb_hardware_init(struct e1000_hw *hw);
105 static void igb_hw_control_acquire(struct e1000_hw *hw);
106 static void igb_hw_control_release(struct e1000_hw *hw);
107 static void igb_init_manageability(struct e1000_hw *hw);
108 static void igb_release_manageability(struct e1000_hw *hw);
110 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
112 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
113 uint16_t vlan_id, int on);
114 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
115 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
117 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
118 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
119 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
120 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
121 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
122 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
124 static int eth_igb_led_on(struct rte_eth_dev *dev);
125 static int eth_igb_led_off(struct rte_eth_dev *dev);
127 static void igb_intr_disable(struct e1000_hw *hw);
128 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
129 static void eth_igb_rar_set(struct rte_eth_dev *dev,
130 struct ether_addr *mac_addr,
131 uint32_t index, uint32_t pool);
132 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
134 static void igbvf_intr_disable(struct e1000_hw *hw);
135 static int igbvf_dev_configure(struct rte_eth_dev *dev);
136 static int igbvf_dev_start(struct rte_eth_dev *dev);
137 static void igbvf_dev_stop(struct rte_eth_dev *dev);
138 static void igbvf_dev_close(struct rte_eth_dev *dev);
139 static int eth_igbvf_link_update(struct e1000_hw *hw);
140 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
141 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
142 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
143 uint16_t vlan_id, int on);
144 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
145 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
146 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
147 struct rte_eth_rss_reta_entry64 *reta_conf,
149 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
150 struct rte_eth_rss_reta_entry64 *reta_conf,
152 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
153 struct rte_syn_filter *filter, uint16_t rx_queue);
154 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
155 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
156 struct rte_syn_filter *filter, uint16_t *rx_queue);
157 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
159 struct rte_2tuple_filter *filter, uint16_t rx_queue);
160 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
162 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
164 struct rte_2tuple_filter *filter, uint16_t *rx_queue);
165 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
167 struct rte_flex_filter *filter, uint16_t rx_queue);
168 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
170 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
172 struct rte_flex_filter *filter, uint16_t *rx_queue);
173 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
175 struct rte_5tuple_filter *filter, uint16_t rx_queue);
176 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
178 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
180 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
181 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
182 struct rte_eth_ethertype_filter *filter,
184 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
185 enum rte_filter_op filter_op,
187 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
188 struct rte_eth_ethertype_filter *filter);
189 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
190 enum rte_filter_type filter_type,
191 enum rte_filter_op filter_op,
195 * Define VF Stats MACRO for Non "cleared on read" register
197 #define UPDATE_VF_STAT(reg, last, cur) \
199 u32 latest = E1000_READ_REG(hw, reg); \
200 cur += latest - last; \
205 #define IGB_FC_PAUSE_TIME 0x0680
206 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
207 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
209 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
211 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
214 * The set of PCI devices this driver supports
216 static struct rte_pci_id pci_id_igb_map[] = {
218 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
219 #include "rte_pci_dev_ids.h"
225 * The set of PCI devices this driver supports (for 82576&I350 VF)
227 static struct rte_pci_id pci_id_igbvf_map[] = {
229 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
230 #include "rte_pci_dev_ids.h"
235 static struct eth_dev_ops eth_igb_ops = {
236 .dev_configure = eth_igb_configure,
237 .dev_start = eth_igb_start,
238 .dev_stop = eth_igb_stop,
239 .dev_close = eth_igb_close,
240 .promiscuous_enable = eth_igb_promiscuous_enable,
241 .promiscuous_disable = eth_igb_promiscuous_disable,
242 .allmulticast_enable = eth_igb_allmulticast_enable,
243 .allmulticast_disable = eth_igb_allmulticast_disable,
244 .link_update = eth_igb_link_update,
245 .stats_get = eth_igb_stats_get,
246 .stats_reset = eth_igb_stats_reset,
247 .dev_infos_get = eth_igb_infos_get,
248 .mtu_set = eth_igb_mtu_set,
249 .vlan_filter_set = eth_igb_vlan_filter_set,
250 .vlan_tpid_set = eth_igb_vlan_tpid_set,
251 .vlan_offload_set = eth_igb_vlan_offload_set,
252 .rx_queue_setup = eth_igb_rx_queue_setup,
253 .rx_queue_release = eth_igb_rx_queue_release,
254 .rx_queue_count = eth_igb_rx_queue_count,
255 .rx_descriptor_done = eth_igb_rx_descriptor_done,
256 .tx_queue_setup = eth_igb_tx_queue_setup,
257 .tx_queue_release = eth_igb_tx_queue_release,
258 .dev_led_on = eth_igb_led_on,
259 .dev_led_off = eth_igb_led_off,
260 .flow_ctrl_get = eth_igb_flow_ctrl_get,
261 .flow_ctrl_set = eth_igb_flow_ctrl_set,
262 .mac_addr_add = eth_igb_rar_set,
263 .mac_addr_remove = eth_igb_rar_clear,
264 .reta_update = eth_igb_rss_reta_update,
265 .reta_query = eth_igb_rss_reta_query,
266 .rss_hash_update = eth_igb_rss_hash_update,
267 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
268 .add_syn_filter = eth_igb_add_syn_filter,
269 .remove_syn_filter = eth_igb_remove_syn_filter,
270 .get_syn_filter = eth_igb_get_syn_filter,
271 .add_2tuple_filter = eth_igb_add_2tuple_filter,
272 .remove_2tuple_filter = eth_igb_remove_2tuple_filter,
273 .get_2tuple_filter = eth_igb_get_2tuple_filter,
274 .add_flex_filter = eth_igb_add_flex_filter,
275 .remove_flex_filter = eth_igb_remove_flex_filter,
276 .get_flex_filter = eth_igb_get_flex_filter,
277 .add_5tuple_filter = eth_igb_add_5tuple_filter,
278 .remove_5tuple_filter = eth_igb_remove_5tuple_filter,
279 .get_5tuple_filter = eth_igb_get_5tuple_filter,
280 .filter_ctrl = eth_igb_filter_ctrl,
284 * dev_ops for virtual function, bare necessities for basic vf
285 * operation have been implemented
287 static struct eth_dev_ops igbvf_eth_dev_ops = {
288 .dev_configure = igbvf_dev_configure,
289 .dev_start = igbvf_dev_start,
290 .dev_stop = igbvf_dev_stop,
291 .dev_close = igbvf_dev_close,
292 .link_update = eth_igb_link_update,
293 .stats_get = eth_igbvf_stats_get,
294 .stats_reset = eth_igbvf_stats_reset,
295 .vlan_filter_set = igbvf_vlan_filter_set,
296 .dev_infos_get = eth_igbvf_infos_get,
297 .rx_queue_setup = eth_igb_rx_queue_setup,
298 .rx_queue_release = eth_igb_rx_queue_release,
299 .tx_queue_setup = eth_igb_tx_queue_setup,
300 .tx_queue_release = eth_igb_tx_queue_release,
304 * Atomically reads the link status information from global
305 * structure rte_eth_dev.
308 * - Pointer to the structure rte_eth_dev to read from.
309 * - Pointer to the buffer to be saved with the link status.
312 * - On success, zero.
313 * - On failure, negative value.
316 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
317 struct rte_eth_link *link)
319 struct rte_eth_link *dst = link;
320 struct rte_eth_link *src = &(dev->data->dev_link);
322 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
323 *(uint64_t *)src) == 0)
330 * Atomically writes the link status information into global
331 * structure rte_eth_dev.
334 * - Pointer to the structure rte_eth_dev to read from.
335 * - Pointer to the buffer to be saved with the link status.
338 * - On success, zero.
339 * - On failure, negative value.
342 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
343 struct rte_eth_link *link)
345 struct rte_eth_link *dst = &(dev->data->dev_link);
346 struct rte_eth_link *src = link;
348 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
349 *(uint64_t *)src) == 0)
356 igb_intr_enable(struct rte_eth_dev *dev)
358 struct e1000_interrupt *intr =
359 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
360 struct e1000_hw *hw =
361 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
363 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
364 E1000_WRITE_FLUSH(hw);
368 igb_intr_disable(struct e1000_hw *hw)
370 E1000_WRITE_REG(hw, E1000_IMC, ~0);
371 E1000_WRITE_FLUSH(hw);
374 static inline int32_t
375 igb_pf_reset_hw(struct e1000_hw *hw)
380 status = e1000_reset_hw(hw);
382 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
383 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
384 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
385 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
386 E1000_WRITE_FLUSH(hw);
392 igb_identify_hardware(struct rte_eth_dev *dev)
394 struct e1000_hw *hw =
395 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
397 hw->vendor_id = dev->pci_dev->id.vendor_id;
398 hw->device_id = dev->pci_dev->id.device_id;
399 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
400 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
402 e1000_set_mac_type(hw);
404 /* need to check if it is a vf device below */
408 igb_reset_swfw_lock(struct e1000_hw *hw)
413 * Do mac ops initialization manually here, since we will need
414 * some function pointers set by this call.
416 ret_val = e1000_init_mac_params(hw);
421 * SMBI lock should not fail in this early stage. If this is the case,
422 * it is due to an improper exit of the application.
423 * So force the release of the faulty lock.
425 if (e1000_get_hw_semaphore_generic(hw) < 0) {
426 PMD_DRV_LOG(DEBUG, "SMBI lock released");
428 e1000_put_hw_semaphore_generic(hw);
430 if (hw->mac.ops.acquire_swfw_sync != NULL) {
434 * Phy lock should not fail in this early stage. If this is the case,
435 * it is due to an improper exit of the application.
436 * So force the release of the faulty lock.
438 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
439 if (hw->bus.func > E1000_FUNC_1)
441 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
442 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
445 hw->mac.ops.release_swfw_sync(hw, mask);
448 * This one is more tricky since it is common to all ports; but
449 * swfw_sync retries last long enough (1s) to be almost sure that if
450 * lock can not be taken it is due to an improper lock of the
453 mask = E1000_SWFW_EEP_SM;
454 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
455 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
457 hw->mac.ops.release_swfw_sync(hw, mask);
460 return E1000_SUCCESS;
464 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
465 struct rte_eth_dev *eth_dev)
468 struct rte_pci_device *pci_dev;
469 struct e1000_hw *hw =
470 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
471 struct e1000_vfta * shadow_vfta =
472 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
475 pci_dev = eth_dev->pci_dev;
476 eth_dev->dev_ops = ð_igb_ops;
477 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
478 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
480 /* for secondary processes, we don't initialise any further as primary
481 * has already done this work. Only check we don't need a different
483 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
484 if (eth_dev->data->scattered_rx)
485 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
489 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
491 igb_identify_hardware(eth_dev);
492 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
497 e1000_get_bus_info(hw);
499 /* Reset any pending lock */
500 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
505 /* Finish initialization */
506 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
512 hw->phy.autoneg_wait_to_complete = 0;
513 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
516 if (hw->phy.media_type == e1000_media_type_copper) {
517 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
518 hw->phy.disable_polarity_correction = 0;
519 hw->phy.ms_type = e1000_ms_hw_default;
523 * Start from a known state, this is important in reading the nvm
528 /* Make sure we have a good EEPROM before we read from it */
529 if (e1000_validate_nvm_checksum(hw) < 0) {
531 * Some PCI-E parts fail the first check due to
532 * the link being in sleep state, call it again,
533 * if it fails a second time its a real issue.
535 if (e1000_validate_nvm_checksum(hw) < 0) {
536 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
542 /* Read the permanent MAC address out of the EEPROM */
543 if (e1000_read_mac_addr(hw) != 0) {
544 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
549 /* Allocate memory for storing MAC addresses */
550 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
551 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
552 if (eth_dev->data->mac_addrs == NULL) {
553 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
554 "store MAC addresses",
555 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
560 /* Copy the permanent MAC address */
561 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
563 /* initialize the vfta */
564 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
566 /* Now initialize the hardware */
567 if (igb_hardware_init(hw) != 0) {
568 PMD_INIT_LOG(ERR, "Hardware initialization failed");
569 rte_free(eth_dev->data->mac_addrs);
570 eth_dev->data->mac_addrs = NULL;
574 hw->mac.get_link_status = 1;
576 /* Indicate SOL/IDER usage */
577 if (e1000_check_reset_block(hw) < 0) {
578 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
582 /* initialize PF if max_vfs not zero */
583 igb_pf_host_init(eth_dev);
585 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
586 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
587 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
588 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
589 E1000_WRITE_FLUSH(hw);
591 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
592 eth_dev->data->port_id, pci_dev->id.vendor_id,
593 pci_dev->id.device_id);
595 rte_intr_callback_register(&(pci_dev->intr_handle),
596 eth_igb_interrupt_handler, (void *)eth_dev);
598 /* enable uio intr after callback register */
599 rte_intr_enable(&(pci_dev->intr_handle));
601 /* enable support intr */
602 igb_intr_enable(eth_dev);
607 igb_hw_control_release(hw);
613 * Virtual Function device init
616 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
617 struct rte_eth_dev *eth_dev)
619 struct rte_pci_device *pci_dev;
620 struct e1000_hw *hw =
621 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
624 PMD_INIT_FUNC_TRACE();
626 eth_dev->dev_ops = &igbvf_eth_dev_ops;
627 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
628 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
630 /* for secondary processes, we don't initialise any further as primary
631 * has already done this work. Only check we don't need a different
633 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
634 if (eth_dev->data->scattered_rx)
635 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
639 pci_dev = eth_dev->pci_dev;
641 hw->device_id = pci_dev->id.device_id;
642 hw->vendor_id = pci_dev->id.vendor_id;
643 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
645 /* Initialize the shared code (base driver) */
646 diag = e1000_setup_init_funcs(hw, TRUE);
648 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
653 /* init_mailbox_params */
654 hw->mbx.ops.init_params(hw);
656 /* Disable the interrupts for VF */
657 igbvf_intr_disable(hw);
659 diag = hw->mac.ops.reset_hw(hw);
661 /* Allocate memory for storing MAC addresses */
662 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
663 hw->mac.rar_entry_count, 0);
664 if (eth_dev->data->mac_addrs == NULL) {
666 "Failed to allocate %d bytes needed to store MAC "
668 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
672 /* Copy the permanent MAC address */
673 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
674 ð_dev->data->mac_addrs[0]);
676 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
678 eth_dev->data->port_id, pci_dev->id.vendor_id,
679 pci_dev->id.device_id, "igb_mac_82576_vf");
684 static struct eth_driver rte_igb_pmd = {
686 .name = "rte_igb_pmd",
687 .id_table = pci_id_igb_map,
688 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
690 .eth_dev_init = eth_igb_dev_init,
691 .dev_private_size = sizeof(struct e1000_adapter),
695 * virtual function driver struct
697 static struct eth_driver rte_igbvf_pmd = {
699 .name = "rte_igbvf_pmd",
700 .id_table = pci_id_igbvf_map,
701 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
703 .eth_dev_init = eth_igbvf_dev_init,
704 .dev_private_size = sizeof(struct e1000_adapter),
708 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
710 rte_eth_driver_register(&rte_igb_pmd);
715 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
717 struct e1000_hw *hw =
718 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
719 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
720 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
721 rctl |= E1000_RCTL_VFE;
722 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
726 * VF Driver initialization routine.
727 * Invoked one at EAL init time.
728 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
731 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
733 PMD_INIT_FUNC_TRACE();
735 rte_eth_driver_register(&rte_igbvf_pmd);
740 eth_igb_configure(struct rte_eth_dev *dev)
742 struct e1000_interrupt *intr =
743 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
745 PMD_INIT_FUNC_TRACE();
746 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
747 PMD_INIT_FUNC_TRACE();
753 eth_igb_start(struct rte_eth_dev *dev)
755 struct e1000_hw *hw =
756 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
760 PMD_INIT_FUNC_TRACE();
762 /* Power up the phy. Needed to make the link go Up */
763 e1000_power_up_phy(hw);
766 * Packet Buffer Allocation (PBA)
767 * Writing PBA sets the receive portion of the buffer
768 * the remainder is used for the transmit buffer.
770 if (hw->mac.type == e1000_82575) {
773 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
774 E1000_WRITE_REG(hw, E1000_PBA, pba);
777 /* Put the address into the Receive Address Array */
778 e1000_rar_set(hw, hw->mac.addr, 0);
780 /* Initialize the hardware */
781 if (igb_hardware_init(hw)) {
782 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
786 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
788 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
789 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
790 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
791 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
792 E1000_WRITE_FLUSH(hw);
794 /* configure PF module if SRIOV enabled */
795 igb_pf_host_configure(dev);
797 /* Configure for OS presence */
798 igb_init_manageability(hw);
800 eth_igb_tx_init(dev);
802 /* This can fail when allocating mbufs for descriptor rings */
803 ret = eth_igb_rx_init(dev);
805 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
806 igb_dev_clear_queues(dev);
810 e1000_clear_hw_cntrs_base_generic(hw);
813 * VLAN Offload Settings
815 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
816 ETH_VLAN_EXTEND_MASK;
817 eth_igb_vlan_offload_set(dev, mask);
819 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
820 /* Enable VLAN filter since VMDq always use VLAN filter */
821 igb_vmdq_vlan_hw_filter_enable(dev);
825 * Configure the Interrupt Moderation register (EITR) with the maximum
826 * possible value (0xFFFF) to minimize "System Partial Write" issued by
827 * spurious [DMA] memory updates of RX and TX ring descriptors.
829 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
830 * spurious memory updates per second should be expected.
831 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
833 * Because interrupts are not used at all, the MSI-X is not activated
834 * and interrupt moderation is controlled by EITR[0].
836 * Note that having [almost] disabled memory updates of RX and TX ring
837 * descriptors through the Interrupt Moderation mechanism, memory
838 * updates of ring descriptors are now moderated by the configurable
839 * value of Write-Back Threshold registers.
841 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
842 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
843 (hw->mac.type == e1000_i211)) {
846 /* Enable all RX & TX queues in the IVAR registers */
847 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
848 for (i = 0; i < 8; i++)
849 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
851 /* Configure EITR with the maximum possible value (0xFFFF) */
852 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
855 /* Setup link speed and duplex */
856 switch (dev->data->dev_conf.link_speed) {
857 case ETH_LINK_SPEED_AUTONEG:
858 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
859 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
860 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
861 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
862 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
863 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
865 goto error_invalid_config;
867 case ETH_LINK_SPEED_10:
868 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
869 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
870 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
871 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
872 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
873 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
875 goto error_invalid_config;
877 case ETH_LINK_SPEED_100:
878 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
879 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
880 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
881 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
882 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
883 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
885 goto error_invalid_config;
887 case ETH_LINK_SPEED_1000:
888 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
889 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
890 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
892 goto error_invalid_config;
894 case ETH_LINK_SPEED_10000:
896 goto error_invalid_config;
898 e1000_setup_link(hw);
900 /* check if lsc interrupt feature is enabled */
901 if (dev->data->dev_conf.intr_conf.lsc != 0)
902 ret = eth_igb_lsc_interrupt_setup(dev);
904 /* resume enabled intr since hw reset */
905 igb_intr_enable(dev);
907 PMD_INIT_LOG(DEBUG, "<<");
911 error_invalid_config:
912 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
913 dev->data->dev_conf.link_speed,
914 dev->data->dev_conf.link_duplex, dev->data->port_id);
915 igb_dev_clear_queues(dev);
919 /*********************************************************************
921 * This routine disables all traffic on the adapter by issuing a
922 * global reset on the MAC.
924 **********************************************************************/
926 eth_igb_stop(struct rte_eth_dev *dev)
928 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
929 struct rte_eth_link link;
931 igb_intr_disable(hw);
933 E1000_WRITE_REG(hw, E1000_WUC, 0);
935 /* Set bit for Go Link disconnect */
936 if (hw->mac.type >= e1000_82580) {
939 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
940 phpm_reg |= E1000_82580_PM_GO_LINKD;
941 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
944 /* Power down the phy. Needed to make the link go Down */
945 e1000_power_down_phy(hw);
947 igb_dev_clear_queues(dev);
949 /* clear the recorded link status */
950 memset(&link, 0, sizeof(link));
951 rte_igb_dev_atomic_write_link_status(dev, &link);
955 eth_igb_close(struct rte_eth_dev *dev)
957 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
958 struct rte_eth_link link;
961 e1000_phy_hw_reset(hw);
962 igb_release_manageability(hw);
963 igb_hw_control_release(hw);
965 /* Clear bit for Go Link disconnect */
966 if (hw->mac.type >= e1000_82580) {
969 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
970 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
971 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
974 igb_dev_clear_queues(dev);
976 memset(&link, 0, sizeof(link));
977 rte_igb_dev_atomic_write_link_status(dev, &link);
981 igb_get_rx_buffer_size(struct e1000_hw *hw)
983 uint32_t rx_buf_size;
984 if (hw->mac.type == e1000_82576) {
985 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
986 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
987 /* PBS needs to be translated according to a lookup table */
988 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
989 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
990 rx_buf_size = (rx_buf_size << 10);
991 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
992 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
994 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1000 /*********************************************************************
1002 * Initialize the hardware
1004 **********************************************************************/
1006 igb_hardware_init(struct e1000_hw *hw)
1008 uint32_t rx_buf_size;
1011 /* Let the firmware know the OS is in control */
1012 igb_hw_control_acquire(hw);
1015 * These parameters control the automatic generation (Tx) and
1016 * response (Rx) to Ethernet PAUSE frames.
1017 * - High water mark should allow for at least two standard size (1518)
1018 * frames to be received after sending an XOFF.
1019 * - Low water mark works best when it is very near the high water mark.
1020 * This allows the receiver to restart by sending XON when it has
1021 * drained a bit. Here we use an arbitrary value of 1500 which will
1022 * restart after one full frame is pulled from the buffer. There
1023 * could be several smaller frames in the buffer and if so they will
1024 * not trigger the XON until their total number reduces the buffer
1026 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1028 rx_buf_size = igb_get_rx_buffer_size(hw);
1030 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1031 hw->fc.low_water = hw->fc.high_water - 1500;
1032 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1033 hw->fc.send_xon = 1;
1035 /* Set Flow control, use the tunable location if sane */
1036 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1037 hw->fc.requested_mode = igb_fc_setting;
1039 hw->fc.requested_mode = e1000_fc_none;
1041 /* Issue a global reset */
1042 igb_pf_reset_hw(hw);
1043 E1000_WRITE_REG(hw, E1000_WUC, 0);
1045 diag = e1000_init_hw(hw);
1049 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1050 e1000_get_phy_info(hw);
1051 e1000_check_for_link(hw);
1056 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1058 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1060 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1061 struct e1000_hw_stats *stats =
1062 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1065 if(hw->phy.media_type == e1000_media_type_copper ||
1066 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1068 E1000_READ_REG(hw,E1000_SYMERRS);
1069 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1072 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1073 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1074 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1075 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1077 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1078 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1079 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1080 stats->dc += E1000_READ_REG(hw, E1000_DC);
1081 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1082 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1083 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1085 ** For watchdog management we need to know if we have been
1086 ** paused during the last interval, so capture that here.
1088 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1089 stats->xoffrxc += pause_frames;
1090 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1091 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1092 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1093 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1094 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1095 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1096 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1097 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1098 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1099 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1100 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1101 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1103 /* For the 64-bit byte counters the low dword must be read first. */
1104 /* Both registers clear on the read of the high dword */
1106 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1107 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1108 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1109 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1111 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1112 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1113 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1114 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1115 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1117 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1118 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1120 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1121 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1122 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1123 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1124 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1125 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1126 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1127 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1128 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1129 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1131 /* Interrupt Counts */
1133 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1134 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1135 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1136 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1137 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1138 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1139 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1140 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1141 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1143 /* Host to Card Statistics */
1145 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1146 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1147 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1148 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1149 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1150 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1151 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1152 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1153 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1154 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1155 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1156 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1157 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1158 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1160 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1161 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1162 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1163 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1164 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1165 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1167 if (rte_stats == NULL)
1171 rte_stats->ibadcrc = stats->crcerrs;
1172 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1173 rte_stats->imissed = stats->mpc;
1174 rte_stats->ierrors = rte_stats->ibadcrc +
1175 rte_stats->ibadlen +
1176 rte_stats->imissed +
1177 stats->rxerrc + stats->algnerrc + stats->cexterr;
1180 rte_stats->oerrors = stats->ecol + stats->latecol;
1182 /* XON/XOFF pause frames */
1183 rte_stats->tx_pause_xon = stats->xontxc;
1184 rte_stats->rx_pause_xon = stats->xonrxc;
1185 rte_stats->tx_pause_xoff = stats->xofftxc;
1186 rte_stats->rx_pause_xoff = stats->xoffrxc;
1188 rte_stats->ipackets = stats->gprc;
1189 rte_stats->opackets = stats->gptc;
1190 rte_stats->ibytes = stats->gorc;
1191 rte_stats->obytes = stats->gotc;
1195 eth_igb_stats_reset(struct rte_eth_dev *dev)
1197 struct e1000_hw_stats *hw_stats =
1198 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1200 /* HW registers are cleared on read */
1201 eth_igb_stats_get(dev, NULL);
1203 /* Reset software totals */
1204 memset(hw_stats, 0, sizeof(*hw_stats));
1208 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1210 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1212 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1214 /* Good Rx packets, include VF loopback */
1215 UPDATE_VF_STAT(E1000_VFGPRC,
1216 hw_stats->last_gprc, hw_stats->gprc);
1218 /* Good Rx octets, include VF loopback */
1219 UPDATE_VF_STAT(E1000_VFGORC,
1220 hw_stats->last_gorc, hw_stats->gorc);
1222 /* Good Tx packets, include VF loopback */
1223 UPDATE_VF_STAT(E1000_VFGPTC,
1224 hw_stats->last_gptc, hw_stats->gptc);
1226 /* Good Tx octets, include VF loopback */
1227 UPDATE_VF_STAT(E1000_VFGOTC,
1228 hw_stats->last_gotc, hw_stats->gotc);
1230 /* Rx Multicst packets */
1231 UPDATE_VF_STAT(E1000_VFMPRC,
1232 hw_stats->last_mprc, hw_stats->mprc);
1234 /* Good Rx loopback packets */
1235 UPDATE_VF_STAT(E1000_VFGPRLBC,
1236 hw_stats->last_gprlbc, hw_stats->gprlbc);
1238 /* Good Rx loopback octets */
1239 UPDATE_VF_STAT(E1000_VFGORLBC,
1240 hw_stats->last_gorlbc, hw_stats->gorlbc);
1242 /* Good Tx loopback packets */
1243 UPDATE_VF_STAT(E1000_VFGPTLBC,
1244 hw_stats->last_gptlbc, hw_stats->gptlbc);
1246 /* Good Tx loopback octets */
1247 UPDATE_VF_STAT(E1000_VFGOTLBC,
1248 hw_stats->last_gotlbc, hw_stats->gotlbc);
1250 if (rte_stats == NULL)
1253 memset(rte_stats, 0, sizeof(*rte_stats));
1254 rte_stats->ipackets = hw_stats->gprc;
1255 rte_stats->ibytes = hw_stats->gorc;
1256 rte_stats->opackets = hw_stats->gptc;
1257 rte_stats->obytes = hw_stats->gotc;
1258 rte_stats->imcasts = hw_stats->mprc;
1259 rte_stats->ilbpackets = hw_stats->gprlbc;
1260 rte_stats->ilbbytes = hw_stats->gorlbc;
1261 rte_stats->olbpackets = hw_stats->gptlbc;
1262 rte_stats->olbbytes = hw_stats->gotlbc;
1267 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1269 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1270 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1272 /* Sync HW register to the last stats */
1273 eth_igbvf_stats_get(dev, NULL);
1275 /* reset HW current stats*/
1276 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1277 offsetof(struct e1000_vf_stats, gprc));
1282 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1284 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1286 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1287 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1288 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1289 dev_info->rx_offload_capa =
1290 DEV_RX_OFFLOAD_VLAN_STRIP |
1291 DEV_RX_OFFLOAD_IPV4_CKSUM |
1292 DEV_RX_OFFLOAD_UDP_CKSUM |
1293 DEV_RX_OFFLOAD_TCP_CKSUM;
1294 dev_info->tx_offload_capa =
1295 DEV_TX_OFFLOAD_VLAN_INSERT |
1296 DEV_TX_OFFLOAD_IPV4_CKSUM |
1297 DEV_TX_OFFLOAD_UDP_CKSUM |
1298 DEV_TX_OFFLOAD_TCP_CKSUM |
1299 DEV_TX_OFFLOAD_SCTP_CKSUM;
1301 switch (hw->mac.type) {
1303 dev_info->max_rx_queues = 4;
1304 dev_info->max_tx_queues = 4;
1305 dev_info->max_vmdq_pools = 0;
1309 dev_info->max_rx_queues = 16;
1310 dev_info->max_tx_queues = 16;
1311 dev_info->max_vmdq_pools = ETH_8_POOLS;
1312 dev_info->vmdq_queue_num = 16;
1316 dev_info->max_rx_queues = 8;
1317 dev_info->max_tx_queues = 8;
1318 dev_info->max_vmdq_pools = ETH_8_POOLS;
1319 dev_info->vmdq_queue_num = 8;
1323 dev_info->max_rx_queues = 8;
1324 dev_info->max_tx_queues = 8;
1325 dev_info->max_vmdq_pools = ETH_8_POOLS;
1326 dev_info->vmdq_queue_num = 8;
1330 dev_info->max_rx_queues = 8;
1331 dev_info->max_tx_queues = 8;
1335 dev_info->max_rx_queues = 4;
1336 dev_info->max_tx_queues = 4;
1337 dev_info->max_vmdq_pools = 0;
1341 dev_info->max_rx_queues = 2;
1342 dev_info->max_tx_queues = 2;
1343 dev_info->max_vmdq_pools = 0;
1347 /* Should not happen */
1350 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1352 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1354 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1355 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1356 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1358 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1362 dev_info->default_txconf = (struct rte_eth_txconf) {
1364 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1365 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1366 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1373 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1375 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1377 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1378 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1379 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1380 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1381 DEV_RX_OFFLOAD_IPV4_CKSUM |
1382 DEV_RX_OFFLOAD_UDP_CKSUM |
1383 DEV_RX_OFFLOAD_TCP_CKSUM;
1384 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1385 DEV_TX_OFFLOAD_IPV4_CKSUM |
1386 DEV_TX_OFFLOAD_UDP_CKSUM |
1387 DEV_TX_OFFLOAD_TCP_CKSUM |
1388 DEV_TX_OFFLOAD_SCTP_CKSUM;
1389 switch (hw->mac.type) {
1391 dev_info->max_rx_queues = 2;
1392 dev_info->max_tx_queues = 2;
1394 case e1000_vfadapt_i350:
1395 dev_info->max_rx_queues = 1;
1396 dev_info->max_tx_queues = 1;
1399 /* Should not happen */
1403 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1405 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1406 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1407 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1409 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1413 dev_info->default_txconf = (struct rte_eth_txconf) {
1415 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1416 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1417 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1423 /* return 0 means link status changed, -1 means not changed */
1425 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1427 struct e1000_hw *hw =
1428 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429 struct rte_eth_link link, old;
1430 int link_check, count;
1433 hw->mac.get_link_status = 1;
1435 /* possible wait-to-complete in up to 9 seconds */
1436 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1437 /* Read the real link status */
1438 switch (hw->phy.media_type) {
1439 case e1000_media_type_copper:
1440 /* Do the work to read phy */
1441 e1000_check_for_link(hw);
1442 link_check = !hw->mac.get_link_status;
1445 case e1000_media_type_fiber:
1446 e1000_check_for_link(hw);
1447 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1451 case e1000_media_type_internal_serdes:
1452 e1000_check_for_link(hw);
1453 link_check = hw->mac.serdes_has_link;
1456 /* VF device is type_unknown */
1457 case e1000_media_type_unknown:
1458 eth_igbvf_link_update(hw);
1459 link_check = !hw->mac.get_link_status;
1465 if (link_check || wait_to_complete == 0)
1467 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1469 memset(&link, 0, sizeof(link));
1470 rte_igb_dev_atomic_read_link_status(dev, &link);
1473 /* Now we check if a transition has happened */
1475 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1477 link.link_status = 1;
1478 } else if (!link_check) {
1479 link.link_speed = 0;
1480 link.link_duplex = 0;
1481 link.link_status = 0;
1483 rte_igb_dev_atomic_write_link_status(dev, &link);
1486 if (old.link_status == link.link_status)
1494 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1495 * For ASF and Pass Through versions of f/w this means
1496 * that the driver is loaded.
1499 igb_hw_control_acquire(struct e1000_hw *hw)
1503 /* Let firmware know the driver has taken over */
1504 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1505 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1509 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1510 * For ASF and Pass Through versions of f/w this means that the
1511 * driver is no longer loaded.
1514 igb_hw_control_release(struct e1000_hw *hw)
1518 /* Let firmware taken over control of h/w */
1519 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1520 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1521 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1525 * Bit of a misnomer, what this really means is
1526 * to enable OS management of the system... aka
1527 * to disable special hardware management features.
1530 igb_init_manageability(struct e1000_hw *hw)
1532 if (e1000_enable_mng_pass_thru(hw)) {
1533 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1534 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1536 /* disable hardware interception of ARP */
1537 manc &= ~(E1000_MANC_ARP_EN);
1539 /* enable receiving management packets to the host */
1540 manc |= E1000_MANC_EN_MNG2HOST;
1541 manc2h |= 1 << 5; /* Mng Port 623 */
1542 manc2h |= 1 << 6; /* Mng Port 664 */
1543 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1544 E1000_WRITE_REG(hw, E1000_MANC, manc);
1549 igb_release_manageability(struct e1000_hw *hw)
1551 if (e1000_enable_mng_pass_thru(hw)) {
1552 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1554 manc |= E1000_MANC_ARP_EN;
1555 manc &= ~E1000_MANC_EN_MNG2HOST;
1557 E1000_WRITE_REG(hw, E1000_MANC, manc);
1562 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1564 struct e1000_hw *hw =
1565 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568 rctl = E1000_READ_REG(hw, E1000_RCTL);
1569 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1570 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1574 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1576 struct e1000_hw *hw =
1577 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1580 rctl = E1000_READ_REG(hw, E1000_RCTL);
1581 rctl &= (~E1000_RCTL_UPE);
1582 if (dev->data->all_multicast == 1)
1583 rctl |= E1000_RCTL_MPE;
1585 rctl &= (~E1000_RCTL_MPE);
1586 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1590 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1592 struct e1000_hw *hw =
1593 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596 rctl = E1000_READ_REG(hw, E1000_RCTL);
1597 rctl |= E1000_RCTL_MPE;
1598 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1602 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1604 struct e1000_hw *hw =
1605 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608 if (dev->data->promiscuous == 1)
1609 return; /* must remain in all_multicast mode */
1610 rctl = E1000_READ_REG(hw, E1000_RCTL);
1611 rctl &= (~E1000_RCTL_MPE);
1612 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1616 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1618 struct e1000_hw *hw =
1619 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620 struct e1000_vfta * shadow_vfta =
1621 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1626 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1627 E1000_VFTA_ENTRY_MASK);
1628 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1629 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1634 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1636 /* update local VFTA copy */
1637 shadow_vfta->vfta[vid_idx] = vfta;
1643 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1645 struct e1000_hw *hw =
1646 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647 uint32_t reg = ETHER_TYPE_VLAN ;
1649 reg |= (tpid << 16);
1650 E1000_WRITE_REG(hw, E1000_VET, reg);
1654 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1656 struct e1000_hw *hw =
1657 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660 /* Filter Table Disable */
1661 reg = E1000_READ_REG(hw, E1000_RCTL);
1662 reg &= ~E1000_RCTL_CFIEN;
1663 reg &= ~E1000_RCTL_VFE;
1664 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1668 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1670 struct e1000_hw *hw =
1671 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1672 struct e1000_vfta * shadow_vfta =
1673 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1677 /* Filter Table Enable, CFI not used for packet acceptance */
1678 reg = E1000_READ_REG(hw, E1000_RCTL);
1679 reg &= ~E1000_RCTL_CFIEN;
1680 reg |= E1000_RCTL_VFE;
1681 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1683 /* restore VFTA table */
1684 for (i = 0; i < IGB_VFTA_SIZE; i++)
1685 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1689 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1691 struct e1000_hw *hw =
1692 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695 /* VLAN Mode Disable */
1696 reg = E1000_READ_REG(hw, E1000_CTRL);
1697 reg &= ~E1000_CTRL_VME;
1698 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1702 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1704 struct e1000_hw *hw =
1705 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1708 /* VLAN Mode Enable */
1709 reg = E1000_READ_REG(hw, E1000_CTRL);
1710 reg |= E1000_CTRL_VME;
1711 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1715 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1717 struct e1000_hw *hw =
1718 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721 /* CTRL_EXT: Extended VLAN */
1722 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1723 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1724 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1726 /* Update maximum packet length */
1727 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1728 E1000_WRITE_REG(hw, E1000_RLPML,
1729 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1734 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1736 struct e1000_hw *hw =
1737 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740 /* CTRL_EXT: Extended VLAN */
1741 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1742 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1743 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1745 /* Update maximum packet length */
1746 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1747 E1000_WRITE_REG(hw, E1000_RLPML,
1748 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1753 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1755 if(mask & ETH_VLAN_STRIP_MASK){
1756 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1757 igb_vlan_hw_strip_enable(dev);
1759 igb_vlan_hw_strip_disable(dev);
1762 if(mask & ETH_VLAN_FILTER_MASK){
1763 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1764 igb_vlan_hw_filter_enable(dev);
1766 igb_vlan_hw_filter_disable(dev);
1769 if(mask & ETH_VLAN_EXTEND_MASK){
1770 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1771 igb_vlan_hw_extend_enable(dev);
1773 igb_vlan_hw_extend_disable(dev);
1779 * It enables the interrupt mask and then enable the interrupt.
1782 * Pointer to struct rte_eth_dev.
1785 * - On success, zero.
1786 * - On failure, a negative value.
1789 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1791 struct e1000_interrupt *intr =
1792 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1794 intr->mask |= E1000_ICR_LSC;
1800 * It reads ICR and gets interrupt causes, check it and set a bit flag
1801 * to update link status.
1804 * Pointer to struct rte_eth_dev.
1807 * - On success, zero.
1808 * - On failure, a negative value.
1811 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1814 struct e1000_hw *hw =
1815 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816 struct e1000_interrupt *intr =
1817 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1819 igb_intr_disable(hw);
1821 /* read-on-clear nic registers here */
1822 icr = E1000_READ_REG(hw, E1000_ICR);
1825 if (icr & E1000_ICR_LSC) {
1826 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1829 if (icr & E1000_ICR_VMMB)
1830 intr->flags |= E1000_FLAG_MAILBOX;
1836 * It executes link_update after knowing an interrupt is prsent.
1839 * Pointer to struct rte_eth_dev.
1842 * - On success, zero.
1843 * - On failure, a negative value.
1846 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1848 struct e1000_hw *hw =
1849 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850 struct e1000_interrupt *intr =
1851 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1852 uint32_t tctl, rctl;
1853 struct rte_eth_link link;
1856 if (intr->flags & E1000_FLAG_MAILBOX) {
1857 igb_pf_mbx_process(dev);
1858 intr->flags &= ~E1000_FLAG_MAILBOX;
1861 igb_intr_enable(dev);
1862 rte_intr_enable(&(dev->pci_dev->intr_handle));
1864 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1865 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1867 /* set get_link_status to check register later */
1868 hw->mac.get_link_status = 1;
1869 ret = eth_igb_link_update(dev, 0);
1871 /* check if link has changed */
1875 memset(&link, 0, sizeof(link));
1876 rte_igb_dev_atomic_read_link_status(dev, &link);
1877 if (link.link_status) {
1879 " Port %d: Link Up - speed %u Mbps - %s",
1881 (unsigned)link.link_speed,
1882 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1883 "full-duplex" : "half-duplex");
1885 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1886 dev->data->port_id);
1888 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1889 dev->pci_dev->addr.domain,
1890 dev->pci_dev->addr.bus,
1891 dev->pci_dev->addr.devid,
1892 dev->pci_dev->addr.function);
1893 tctl = E1000_READ_REG(hw, E1000_TCTL);
1894 rctl = E1000_READ_REG(hw, E1000_RCTL);
1895 if (link.link_status) {
1897 tctl |= E1000_TCTL_EN;
1898 rctl |= E1000_RCTL_EN;
1901 tctl &= ~E1000_TCTL_EN;
1902 rctl &= ~E1000_RCTL_EN;
1904 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1905 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1906 E1000_WRITE_FLUSH(hw);
1907 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1914 * Interrupt handler which shall be registered at first.
1917 * Pointer to interrupt handle.
1919 * The address of parameter (struct rte_eth_dev *) regsitered before.
1925 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1928 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1930 eth_igb_interrupt_get_status(dev);
1931 eth_igb_interrupt_action(dev);
1935 eth_igb_led_on(struct rte_eth_dev *dev)
1937 struct e1000_hw *hw;
1939 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1944 eth_igb_led_off(struct rte_eth_dev *dev)
1946 struct e1000_hw *hw;
1948 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1953 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1955 struct e1000_hw *hw;
1960 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961 fc_conf->pause_time = hw->fc.pause_time;
1962 fc_conf->high_water = hw->fc.high_water;
1963 fc_conf->low_water = hw->fc.low_water;
1964 fc_conf->send_xon = hw->fc.send_xon;
1965 fc_conf->autoneg = hw->mac.autoneg;
1968 * Return rx_pause and tx_pause status according to actual setting of
1969 * the TFCE and RFCE bits in the CTRL register.
1971 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1972 if (ctrl & E1000_CTRL_TFCE)
1977 if (ctrl & E1000_CTRL_RFCE)
1982 if (rx_pause && tx_pause)
1983 fc_conf->mode = RTE_FC_FULL;
1985 fc_conf->mode = RTE_FC_RX_PAUSE;
1987 fc_conf->mode = RTE_FC_TX_PAUSE;
1989 fc_conf->mode = RTE_FC_NONE;
1995 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1997 struct e1000_hw *hw;
1999 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2005 uint32_t rx_buf_size;
2006 uint32_t max_high_water;
2009 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010 if (fc_conf->autoneg != hw->mac.autoneg)
2012 rx_buf_size = igb_get_rx_buffer_size(hw);
2013 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2015 /* At least reserve one Ethernet frame for watermark */
2016 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2017 if ((fc_conf->high_water > max_high_water) ||
2018 (fc_conf->high_water < fc_conf->low_water)) {
2019 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2020 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2024 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2025 hw->fc.pause_time = fc_conf->pause_time;
2026 hw->fc.high_water = fc_conf->high_water;
2027 hw->fc.low_water = fc_conf->low_water;
2028 hw->fc.send_xon = fc_conf->send_xon;
2030 err = e1000_setup_link_generic(hw);
2031 if (err == E1000_SUCCESS) {
2033 /* check if we want to forward MAC frames - driver doesn't have native
2034 * capability to do that, so we'll write the registers ourselves */
2036 rctl = E1000_READ_REG(hw, E1000_RCTL);
2038 /* set or clear MFLCN.PMCF bit depending on configuration */
2039 if (fc_conf->mac_ctrl_frame_fwd != 0)
2040 rctl |= E1000_RCTL_PMCF;
2042 rctl &= ~E1000_RCTL_PMCF;
2044 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2045 E1000_WRITE_FLUSH(hw);
2050 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2054 #define E1000_RAH_POOLSEL_SHIFT (18)
2056 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2057 uint32_t index, __rte_unused uint32_t pool)
2059 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2063 rah = E1000_READ_REG(hw, E1000_RAH(index));
2064 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2065 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2069 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2071 uint8_t addr[ETHER_ADDR_LEN];
2072 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2074 memset(addr, 0, sizeof(addr));
2076 e1000_rar_set(hw, addr, index);
2080 * Virtual Function operations
2083 igbvf_intr_disable(struct e1000_hw *hw)
2085 PMD_INIT_FUNC_TRACE();
2087 /* Clear interrupt mask to stop from interrupts being generated */
2088 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2090 E1000_WRITE_FLUSH(hw);
2094 igbvf_stop_adapter(struct rte_eth_dev *dev)
2098 struct rte_eth_dev_info dev_info;
2099 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101 memset(&dev_info, 0, sizeof(dev_info));
2102 eth_igbvf_infos_get(dev, &dev_info);
2104 /* Clear interrupt mask to stop from interrupts being generated */
2105 igbvf_intr_disable(hw);
2107 /* Clear any pending interrupts, flush previous writes */
2108 E1000_READ_REG(hw, E1000_EICR);
2110 /* Disable the transmit unit. Each queue must be disabled. */
2111 for (i = 0; i < dev_info.max_tx_queues; i++)
2112 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2114 /* Disable the receive unit by stopping each queue */
2115 for (i = 0; i < dev_info.max_rx_queues; i++) {
2116 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2117 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2118 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2119 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2123 /* flush all queues disables */
2124 E1000_WRITE_FLUSH(hw);
2128 static int eth_igbvf_link_update(struct e1000_hw *hw)
2130 struct e1000_mbx_info *mbx = &hw->mbx;
2131 struct e1000_mac_info *mac = &hw->mac;
2132 int ret_val = E1000_SUCCESS;
2134 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2137 * We only want to run this if there has been a rst asserted.
2138 * in this case that could mean a link change, device reset,
2139 * or a virtual function reset
2142 /* If we were hit with a reset or timeout drop the link */
2143 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2144 mac->get_link_status = TRUE;
2146 if (!mac->get_link_status)
2149 /* if link status is down no point in checking to see if pf is up */
2150 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2153 /* if we passed all the tests above then the link is up and we no
2154 * longer need to check for link */
2155 mac->get_link_status = FALSE;
2163 igbvf_dev_configure(struct rte_eth_dev *dev)
2165 struct rte_eth_conf* conf = &dev->data->dev_conf;
2167 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2168 dev->data->port_id);
2171 * VF has no ability to enable/disable HW CRC
2172 * Keep the persistent behavior the same as Host PF
2174 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2175 if (!conf->rxmode.hw_strip_crc) {
2176 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2177 conf->rxmode.hw_strip_crc = 1;
2180 if (conf->rxmode.hw_strip_crc) {
2181 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2182 conf->rxmode.hw_strip_crc = 0;
2190 igbvf_dev_start(struct rte_eth_dev *dev)
2192 struct e1000_hw *hw =
2193 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196 PMD_INIT_FUNC_TRACE();
2198 hw->mac.ops.reset_hw(hw);
2201 igbvf_set_vfta_all(dev,1);
2203 eth_igbvf_tx_init(dev);
2205 /* This can fail when allocating mbufs for descriptor rings */
2206 ret = eth_igbvf_rx_init(dev);
2208 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2209 igb_dev_clear_queues(dev);
2217 igbvf_dev_stop(struct rte_eth_dev *dev)
2219 PMD_INIT_FUNC_TRACE();
2221 igbvf_stop_adapter(dev);
2224 * Clear what we set, but we still keep shadow_vfta to
2225 * restore after device starts
2227 igbvf_set_vfta_all(dev,0);
2229 igb_dev_clear_queues(dev);
2233 igbvf_dev_close(struct rte_eth_dev *dev)
2235 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237 PMD_INIT_FUNC_TRACE();
2241 igbvf_dev_stop(dev);
2244 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2246 struct e1000_mbx_info *mbx = &hw->mbx;
2249 /* After set vlan, vlan strip will also be enabled in igb driver*/
2250 msgbuf[0] = E1000_VF_SET_VLAN;
2252 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2254 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2256 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2259 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2261 struct e1000_hw *hw =
2262 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263 struct e1000_vfta * shadow_vfta =
2264 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2265 int i = 0, j = 0, vfta = 0, mask = 1;
2267 for (i = 0; i < IGB_VFTA_SIZE; i++){
2268 vfta = shadow_vfta->vfta[i];
2271 for (j = 0; j < 32; j++){
2274 (uint16_t)((i<<5)+j), on);
2283 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2285 struct e1000_hw *hw =
2286 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287 struct e1000_vfta * shadow_vfta =
2288 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2289 uint32_t vid_idx = 0;
2290 uint32_t vid_bit = 0;
2293 PMD_INIT_FUNC_TRACE();
2295 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2296 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2298 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2301 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2302 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2304 /*Save what we set and retore it after device reset*/
2306 shadow_vfta->vfta[vid_idx] |= vid_bit;
2308 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2314 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2315 struct rte_eth_rss_reta_entry64 *reta_conf,
2320 uint16_t idx, shift;
2321 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2324 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2325 "(%d) doesn't match the number hardware can supported "
2326 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2330 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2331 idx = i / RTE_RETA_GROUP_SIZE;
2332 shift = i % RTE_RETA_GROUP_SIZE;
2333 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2337 if (mask == IGB_4_BIT_MASK)
2340 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2341 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2342 if (mask & (0x1 << j))
2343 reta |= reta_conf[idx].reta[shift + j] <<
2346 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2348 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2355 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2356 struct rte_eth_rss_reta_entry64 *reta_conf,
2361 uint16_t idx, shift;
2362 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2365 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2366 "(%d) doesn't match the number hardware can supported "
2367 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2371 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2372 idx = i / RTE_RETA_GROUP_SIZE;
2373 shift = i % RTE_RETA_GROUP_SIZE;
2374 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2378 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2379 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2380 if (mask & (0x1 << j))
2381 reta_conf[idx].reta[shift + j] =
2382 ((reta >> (CHAR_BIT * j)) &
2390 #define MAC_TYPE_FILTER_SUP(type) do {\
2391 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2392 (type) != e1000_82576)\
2397 * add the syn filter
2400 * dev: Pointer to struct rte_eth_dev.
2401 * filter: ponter to the filter that will be added.
2402 * rx_queue: the queue id the filter assigned to.
2405 * - On success, zero.
2406 * - On failure, a negative value.
2409 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2410 struct rte_syn_filter *filter, uint16_t rx_queue)
2412 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413 uint32_t synqf, rfctl;
2415 MAC_TYPE_FILTER_SUP(hw->mac.type);
2417 if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2420 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2421 if (synqf & E1000_SYN_FILTER_ENABLE)
2424 synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2425 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2427 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2428 if (filter->hig_pri)
2429 rfctl |= E1000_RFCTL_SYNQFP;
2431 rfctl &= ~E1000_RFCTL_SYNQFP;
2433 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2434 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2439 * remove the syn filter
2442 * dev: Pointer to struct rte_eth_dev.
2445 * - On success, zero.
2446 * - On failure, a negative value.
2449 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2451 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2453 MAC_TYPE_FILTER_SUP(hw->mac.type);
2455 E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2460 * get the syn filter's info
2463 * dev: Pointer to struct rte_eth_dev.
2464 * filter: ponter to the filter that returns.
2465 * *rx_queue: pointer to the queue id the filter assigned to.
2468 * - On success, zero.
2469 * - On failure, a negative value.
2472 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2473 struct rte_syn_filter *filter, uint16_t *rx_queue)
2475 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476 uint32_t synqf, rfctl;
2478 MAC_TYPE_FILTER_SUP(hw->mac.type);
2479 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2480 if (synqf & E1000_SYN_FILTER_ENABLE) {
2481 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2482 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2483 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2484 E1000_SYN_FILTER_QUEUE_SHIFT);
2490 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2491 if ((type) != e1000_82580 && (type) != e1000_i350)\
2496 * add a 2tuple filter
2499 * dev: Pointer to struct rte_eth_dev.
2500 * index: the index the filter allocates.
2501 * filter: ponter to the filter that will be added.
2502 * rx_queue: the queue id the filter assigned to.
2505 * - On success, zero.
2506 * - On failure, a negative value.
2509 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2510 struct rte_2tuple_filter *filter, uint16_t rx_queue)
2512 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513 uint32_t ttqf, imir = 0;
2514 uint32_t imir_ext = 0;
2516 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2518 if (index >= E1000_MAX_TTQF_FILTERS ||
2519 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2520 filter->priority > E1000_2TUPLE_MAX_PRI)
2521 return -EINVAL; /* filter index is out of range. */
2522 if (filter->tcp_flags > TCP_FLAG_ALL)
2523 return -EINVAL; /* flags is invalid. */
2525 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2526 if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2527 return -EINVAL; /* filter index is in use. */
2529 imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2530 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2531 imir |= E1000_IMIR_PORT_BP;
2533 imir &= ~E1000_IMIR_PORT_BP;
2535 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2538 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2539 ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2540 ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2541 if (filter->protocol_mask == 1)
2542 ttqf |= E1000_TTQF_MASK_ENABLE;
2544 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2546 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2547 /* tcp flags bits setting. */
2548 if (filter->tcp_flags & TCP_FLAG_ALL) {
2549 if (filter->tcp_flags & TCP_UGR_FLAG)
2550 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2551 if (filter->tcp_flags & TCP_ACK_FLAG)
2552 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2553 if (filter->tcp_flags & TCP_PSH_FLAG)
2554 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2555 if (filter->tcp_flags & TCP_RST_FLAG)
2556 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2557 if (filter->tcp_flags & TCP_SYN_FLAG)
2558 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2559 if (filter->tcp_flags & TCP_FIN_FLAG)
2560 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2561 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2563 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2564 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2565 E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2566 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2571 * remove a 2tuple filter
2574 * dev: Pointer to struct rte_eth_dev.
2575 * index: the index the filter allocates.
2578 * - On success, zero.
2579 * - On failure, a negative value.
2582 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2585 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2589 if (index >= E1000_MAX_TTQF_FILTERS)
2590 return -EINVAL; /* filter index is out of range */
2592 E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2593 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2594 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2599 * get a 2tuple filter
2602 * dev: Pointer to struct rte_eth_dev.
2603 * index: the index the filter allocates.
2604 * filter: ponter to the filter that returns.
2605 * *rx_queue: pointer of the queue id the filter assigned to.
2608 * - On success, zero.
2609 * - On failure, a negative value.
2612 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2613 struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2615 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 uint32_t imir, ttqf, imir_ext;
2618 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2620 if (index >= E1000_MAX_TTQF_FILTERS)
2621 return -EINVAL; /* filter index is out of range. */
2623 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2624 if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2625 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2626 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2627 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2628 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2629 E1000_TTQF_QUEUE_SHIFT;
2630 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2631 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2632 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2633 E1000_IMIR_PRIORITY_SHIFT;
2635 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2636 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2637 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2638 filter->tcp_flags |= TCP_UGR_FLAG;
2639 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2640 filter->tcp_flags |= TCP_ACK_FLAG;
2641 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2642 filter->tcp_flags |= TCP_PSH_FLAG;
2643 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2644 filter->tcp_flags |= TCP_RST_FLAG;
2645 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2646 filter->tcp_flags |= TCP_SYN_FLAG;
2647 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2648 filter->tcp_flags |= TCP_FIN_FLAG;
2650 filter->tcp_flags = 0;
2660 * dev: Pointer to struct rte_eth_dev.
2661 * index: the index the filter allocates.
2662 * filter: ponter to the filter that will be added.
2663 * rx_queue: the queue id the filter assigned to.
2666 * - On success, zero.
2667 * - On failure, a negative value.
2670 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2671 struct rte_flex_filter *filter, uint16_t rx_queue)
2673 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674 uint32_t wufc, en_bits = 0;
2675 uint32_t queueing = 0;
2676 uint32_t reg_off = 0;
2679 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2681 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2682 return -EINVAL; /* filter index is out of range. */
2684 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2685 filter->len % 8 != 0 ||
2686 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2689 wufc = E1000_READ_REG(hw, E1000_WUFC);
2690 en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2691 if ((wufc & en_bits) == en_bits)
2692 return -EINVAL; /* the filter is in use. */
2694 E1000_WRITE_REG(hw, E1000_WUFC,
2695 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2698 if (index < E1000_MAX_FHFT)
2699 reg_off = E1000_FHFT(index);
2701 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2703 for (i = 0; i < 16; i++) {
2704 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2705 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2706 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2707 (uint32_t)filter->mask[i]);
2710 queueing |= filter->len |
2711 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2712 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2713 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2718 * remove a flex filter
2721 * dev: Pointer to struct rte_eth_dev.
2722 * index: the index the filter allocates.
2725 * - On success, zero.
2726 * - On failure, a negative value.
2729 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2732 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733 uint32_t wufc, reg_off = 0;
2736 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2738 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2739 return -EINVAL; /* filter index is out of range. */
2741 wufc = E1000_READ_REG(hw, E1000_WUFC);
2742 E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2744 if (index < E1000_MAX_FHFT)
2745 reg_off = E1000_FHFT(index);
2747 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2749 for (i = 0; i < 64; i++)
2750 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2758 * dev: Pointer to struct rte_eth_dev.
2759 * index: the index the filter allocates.
2760 * filter: ponter to the filter that returns.
2761 * *rx_queue: the pointer of the queue id the filter assigned to.
2764 * - On success, zero.
2765 * - On failure, a negative value.
2768 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2769 struct rte_flex_filter *filter, uint16_t *rx_queue)
2771 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772 uint32_t wufc, queueing, wufc_en = 0;
2775 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2777 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2778 return -EINVAL; /* filter index is out of range. */
2780 wufc = E1000_READ_REG(hw, E1000_WUFC);
2781 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2783 if ((wufc & wufc_en) == wufc_en) {
2784 uint32_t reg_off = 0;
2786 if (index < E1000_MAX_FHFT)
2787 reg_off = E1000_FHFT(index);
2789 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2791 for (i = 0; i < 16; i++, j = i * 2) {
2793 E1000_READ_REG(hw, reg_off + i*4*4);
2794 filter->dwords[j+1] =
2795 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2797 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2799 queueing = E1000_READ_REG(hw,
2800 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2801 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2802 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2803 E1000_FHFT_QUEUEING_PRIO_SHIFT;
2804 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2805 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2812 * add a 5tuple filter
2815 * dev: Pointer to struct rte_eth_dev.
2816 * index: the index the filter allocates.
2817 * filter: ponter to the filter that will be added.
2818 * rx_queue: the queue id the filter assigned to.
2821 * - On success, zero.
2822 * - On failure, a negative value.
2825 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2826 struct rte_5tuple_filter *filter, uint16_t rx_queue)
2828 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829 uint32_t ftqf, spqf = 0;
2831 uint32_t imir_ext = 0;
2833 if (hw->mac.type != e1000_82576)
2836 if (index >= E1000_MAX_FTQF_FILTERS ||
2837 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2838 return -EINVAL; /* filter index is out of range. */
2840 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2841 if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2842 return -EINVAL; /* filter index is in use. */
2845 ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2846 if (filter->src_ip_mask == 1) /* 1b means not compare. */
2847 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2848 if (filter->dst_ip_mask == 1)
2849 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2850 if (filter->src_port_mask == 1)
2851 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2852 if (filter->protocol_mask == 1)
2853 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2854 ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2855 ftqf |= E1000_FTQF_VF_MASK_EN;
2856 ftqf |= E1000_FTQF_QUEUE_ENABLE;
2857 E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2858 E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2859 E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2861 spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2862 E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2864 imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2865 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2866 imir |= E1000_IMIR_PORT_BP;
2868 imir &= ~E1000_IMIR_PORT_BP;
2869 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2871 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2872 /* tcp flags bits setting. */
2873 if (filter->tcp_flags & TCP_FLAG_ALL) {
2874 if (filter->tcp_flags & TCP_UGR_FLAG)
2875 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2876 if (filter->tcp_flags & TCP_ACK_FLAG)
2877 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2878 if (filter->tcp_flags & TCP_PSH_FLAG)
2879 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2880 if (filter->tcp_flags & TCP_RST_FLAG)
2881 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2882 if (filter->tcp_flags & TCP_SYN_FLAG)
2883 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2884 if (filter->tcp_flags & TCP_FIN_FLAG)
2885 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2887 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2888 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2889 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2894 * remove a 5tuple filter
2897 * dev: Pointer to struct rte_eth_dev.
2898 * index: the index the filter allocates
2901 * - On success, zero.
2902 * - On failure, a negative value.
2905 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2908 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910 if (hw->mac.type != e1000_82576)
2913 if (index >= E1000_MAX_FTQF_FILTERS)
2914 return -EINVAL; /* filter index is out of range. */
2916 E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2917 E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2918 E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2919 E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2920 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2921 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2926 * get a 5tuple filter
2929 * dev: Pointer to struct rte_eth_dev.
2930 * index: the index the filter allocates
2931 * filter: ponter to the filter that returns
2932 * *rx_queue: pointer of the queue id the filter assigned to
2935 * - On success, zero.
2936 * - On failure, a negative value.
2939 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2940 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2942 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943 uint32_t spqf, ftqf, imir, imir_ext;
2945 if (hw->mac.type != e1000_82576)
2948 if (index >= E1000_MAX_FTQF_FILTERS)
2949 return -EINVAL; /* filter index is out of range. */
2951 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2952 if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2953 filter->src_ip_mask =
2954 (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2955 filter->dst_ip_mask =
2956 (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2957 filter->src_port_mask =
2958 (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2959 filter->protocol_mask =
2960 (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2962 (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2963 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2964 E1000_FTQF_QUEUE_SHIFT);
2966 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2967 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2969 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2970 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2972 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2973 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2974 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2975 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2976 E1000_IMIR_PRIORITY_SHIFT;
2978 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2979 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2980 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2981 filter->tcp_flags |= TCP_UGR_FLAG;
2982 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2983 filter->tcp_flags |= TCP_ACK_FLAG;
2984 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2985 filter->tcp_flags |= TCP_PSH_FLAG;
2986 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2987 filter->tcp_flags |= TCP_RST_FLAG;
2988 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2989 filter->tcp_flags |= TCP_SYN_FLAG;
2990 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2991 filter->tcp_flags |= TCP_FIN_FLAG;
2993 filter->tcp_flags = 0;
3000 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3003 struct e1000_hw *hw;
3004 struct rte_eth_dev_info dev_info;
3005 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3008 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010 #ifdef RTE_LIBRTE_82571_SUPPORT
3011 /* XXX: not bigger than max_rx_pktlen */
3012 if (hw->mac.type == e1000_82571)
3015 eth_igb_infos_get(dev, &dev_info);
3017 /* check that mtu is within the allowed range */
3018 if ((mtu < ETHER_MIN_MTU) ||
3019 (frame_size > dev_info.max_rx_pktlen))
3022 /* refuse mtu that requires the support of scattered packets when this
3023 * feature has not been enabled before. */
3024 if (!dev->data->scattered_rx &&
3025 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3028 rctl = E1000_READ_REG(hw, E1000_RCTL);
3030 /* switch to jumbo mode if needed */
3031 if (frame_size > ETHER_MAX_LEN) {
3032 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3033 rctl |= E1000_RCTL_LPE;
3035 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3036 rctl &= ~E1000_RCTL_LPE;
3038 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3040 /* update max frame size */
3041 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3043 E1000_WRITE_REG(hw, E1000_RLPML,
3044 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3050 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3055 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3056 if (filter_info->ethertype_filters[i] == ethertype &&
3057 (filter_info->ethertype_mask & (1 << i)))
3064 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3069 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3070 if (!(filter_info->ethertype_mask & (1 << i))) {
3071 filter_info->ethertype_mask |= 1 << i;
3072 filter_info->ethertype_filters[i] = ethertype;
3080 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3083 if (idx >= E1000_MAX_ETQF_FILTERS)
3085 filter_info->ethertype_mask &= ~(1 << idx);
3086 filter_info->ethertype_filters[idx] = 0;
3092 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3093 struct rte_eth_ethertype_filter *filter,
3096 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097 struct e1000_filter_info *filter_info =
3098 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3102 if (filter->ether_type == ETHER_TYPE_IPv4 ||
3103 filter->ether_type == ETHER_TYPE_IPv6) {
3104 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3105 " ethertype filter.", filter->ether_type);
3109 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3110 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3113 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3114 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3118 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3119 if (ret >= 0 && add) {
3120 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3121 filter->ether_type);
3124 if (ret < 0 && !add) {
3125 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3126 filter->ether_type);
3131 ret = igb_ethertype_filter_insert(filter_info,
3132 filter->ether_type);
3134 PMD_DRV_LOG(ERR, "ethertype filters are full.");
3138 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3139 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3140 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3142 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3146 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3147 E1000_WRITE_FLUSH(hw);
3153 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3154 struct rte_eth_ethertype_filter *filter)
3156 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3157 struct e1000_filter_info *filter_info =
3158 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3162 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3164 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3165 filter->ether_type);
3169 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3170 if (etqf & E1000_ETQF_FILTER_ENABLE) {
3171 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3173 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3174 E1000_ETQF_QUEUE_SHIFT;
3182 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3183 * @dev: pointer to rte_eth_dev structure
3184 * @filter_op:operation will be taken.
3185 * @arg: a pointer to specific structure corresponding to the filter_op
3188 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3189 enum rte_filter_op filter_op,
3192 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195 MAC_TYPE_FILTER_SUP(hw->mac.type);
3197 if (filter_op == RTE_ETH_FILTER_NOP)
3201 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3206 switch (filter_op) {
3207 case RTE_ETH_FILTER_ADD:
3208 ret = igb_add_del_ethertype_filter(dev,
3209 (struct rte_eth_ethertype_filter *)arg,
3212 case RTE_ETH_FILTER_DELETE:
3213 ret = igb_add_del_ethertype_filter(dev,
3214 (struct rte_eth_ethertype_filter *)arg,
3217 case RTE_ETH_FILTER_GET:
3218 ret = igb_get_ethertype_filter(dev,
3219 (struct rte_eth_ethertype_filter *)arg);
3222 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3230 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3231 enum rte_filter_type filter_type,
3232 enum rte_filter_op filter_op,
3237 switch (filter_type) {
3238 case RTE_ETH_FILTER_ETHERTYPE:
3239 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3242 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3250 static struct rte_driver pmd_igb_drv = {
3252 .init = rte_igb_pmd_init,
3255 static struct rte_driver pmd_igbvf_drv = {
3257 .init = rte_igbvf_pmd_init,
3260 PMD_REGISTER_DRIVER(pmd_igb_drv);
3261 PMD_REGISTER_DRIVER(pmd_igbvf_drv);