lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 static int  eth_igb_configure(struct rte_eth_dev *dev);
  73 static int  eth_igb_start(struct rte_eth_dev *dev);
  74 static void eth_igb_stop(struct rte_eth_dev *dev);
  75 static void eth_igb_close(struct rte_eth_dev *dev);
  76 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  77 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  78 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  79 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  80 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  81                                 int wait_to_complete);
  82 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  83                                 struct rte_eth_stats *rte_stats);
  84 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  85 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  86                                 struct rte_eth_dev_info *dev_info);
  87 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  88                                 struct rte_eth_fc_conf *fc_conf);
  89 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  90                                 struct rte_eth_fc_conf *fc_conf);
  91 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  92 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  93 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  94 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  95                                                         void *param);
  96 static int  igb_hardware_init(struct e1000_hw *hw);
  97 static void igb_hw_control_acquire(struct e1000_hw *hw);
  98 static void igb_hw_control_release(struct e1000_hw *hw);
  99 static void igb_init_manageability(struct e1000_hw *hw);
 100 static void igb_release_manageability(struct e1000_hw *hw);
 101
 102 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 103
 104 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 105                 uint16_t vlan_id, int on);
 106 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 107 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 108
 109 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 110 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 111 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 112 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 113 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 114 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 115
 116 static int eth_igb_led_on(struct rte_eth_dev *dev);
 117 static int eth_igb_led_off(struct rte_eth_dev *dev);
 118
 119 static void igb_intr_disable(struct e1000_hw *hw);
 120 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 121 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 122                 struct ether_addr *mac_addr,
 123                 uint32_t index, uint32_t pool);
 124 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 125
 126 static void igbvf_intr_disable(struct e1000_hw *hw);
 127 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 128 static int igbvf_dev_start(struct rte_eth_dev *dev);
 129 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 130 static void igbvf_dev_close(struct rte_eth_dev *dev);
 131 static int eth_igbvf_link_update(struct e1000_hw *hw);
 132 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 133 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 134 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 135                 uint16_t vlan_id, int on);
 136 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 137 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 138 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 139                  struct rte_eth_rss_reta *reta_conf);
 140 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 141                 struct rte_eth_rss_reta *reta_conf);
 142
 143 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 144                         struct rte_syn_filter *filter, uint16_t rx_queue);
 145 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 146 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 147                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 148 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
 149                         uint16_t index,
 150                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 151 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
 152                         uint16_t index);
 153 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
 154                         uint16_t index,
 155                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 156 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 157                         uint16_t index,
 158                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 159 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 160                         uint16_t index);
 161 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 162                         uint16_t index,
 163                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 164 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 165                         uint16_t index,
 166                         struct rte_flex_filter *filter, uint16_t rx_queue);
 167 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 168                         uint16_t index);
 169 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 170                         uint16_t index,
 171                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 172 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 173                         uint16_t index,
 174                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 175 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 176                         uint16_t index);
 177 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 178                         uint16_t index,
 179                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 180
 181 /*
 182  * Define VF Stats MACRO for Non "cleared on read" register
 183  */
 184 #define UPDATE_VF_STAT(reg, last, cur)            \
 185 {                                                 \
 186         u32 latest = E1000_READ_REG(hw, reg);     \
 187         cur += latest - last;                     \
 188         last = latest;                            \
 189 }
 190
 191
 192 #define IGB_FC_PAUSE_TIME 0x0680
 193 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 194 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 195
 196 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 197
 198 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 199
 200 /*
 201  * The set of PCI devices this driver supports
 202  */
 203 static struct rte_pci_id pci_id_igb_map[] = {
 204
 205 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 206 #include "rte_pci_dev_ids.h"
 207
 208 {.device_id = 0},
 209 };
 210
 211 /*
 212  * The set of PCI devices this driver supports (for 82576&I350 VF)
 213  */
 214 static struct rte_pci_id pci_id_igbvf_map[] = {
 215
 216 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 217 #include "rte_pci_dev_ids.h"
 218
 219 {.device_id = 0},
 220 };
 221
 222 static struct eth_dev_ops eth_igb_ops = {
 223         .dev_configure        = eth_igb_configure,
 224         .dev_start            = eth_igb_start,
 225         .dev_stop             = eth_igb_stop,
 226         .dev_close            = eth_igb_close,
 227         .promiscuous_enable   = eth_igb_promiscuous_enable,
 228         .promiscuous_disable  = eth_igb_promiscuous_disable,
 229         .allmulticast_enable  = eth_igb_allmulticast_enable,
 230         .allmulticast_disable = eth_igb_allmulticast_disable,
 231         .link_update          = eth_igb_link_update,
 232         .stats_get            = eth_igb_stats_get,
 233         .stats_reset          = eth_igb_stats_reset,
 234         .dev_infos_get        = eth_igb_infos_get,
 235         .mtu_set              = eth_igb_mtu_set,
 236         .vlan_filter_set      = eth_igb_vlan_filter_set,
 237         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 238         .vlan_offload_set     = eth_igb_vlan_offload_set,
 239         .rx_queue_setup       = eth_igb_rx_queue_setup,
 240         .rx_queue_release     = eth_igb_rx_queue_release,
 241         .rx_queue_count       = eth_igb_rx_queue_count,
 242         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 243         .tx_queue_setup       = eth_igb_tx_queue_setup,
 244         .tx_queue_release     = eth_igb_tx_queue_release,
 245         .dev_led_on           = eth_igb_led_on,
 246         .dev_led_off          = eth_igb_led_off,
 247         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 248         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 249         .mac_addr_add         = eth_igb_rar_set,
 250         .mac_addr_remove      = eth_igb_rar_clear,
 251         .reta_update          = eth_igb_rss_reta_update,
 252         .reta_query           = eth_igb_rss_reta_query,
 253         .rss_hash_update      = eth_igb_rss_hash_update,
 254         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 255         .add_syn_filter          = eth_igb_add_syn_filter,
 256         .remove_syn_filter       = eth_igb_remove_syn_filter,
 257         .get_syn_filter          = eth_igb_get_syn_filter,
 258         .add_ethertype_filter    = eth_igb_add_ethertype_filter,
 259         .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
 260         .get_ethertype_filter    = eth_igb_get_ethertype_filter,
 261         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 262         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 263         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 264         .add_flex_filter         = eth_igb_add_flex_filter,
 265         .remove_flex_filter      = eth_igb_remove_flex_filter,
 266         .get_flex_filter         = eth_igb_get_flex_filter,
 267         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 268         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 269         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 270 };
 271
 272 /*
 273  * dev_ops for virtual function, bare necessities for basic vf
 274  * operation have been implemented
 275  */
 276 static struct eth_dev_ops igbvf_eth_dev_ops = {
 277         .dev_configure        = igbvf_dev_configure,
 278         .dev_start            = igbvf_dev_start,
 279         .dev_stop             = igbvf_dev_stop,
 280         .dev_close            = igbvf_dev_close,
 281         .link_update          = eth_igb_link_update,
 282         .stats_get            = eth_igbvf_stats_get,
 283         .stats_reset          = eth_igbvf_stats_reset,
 284         .vlan_filter_set      = igbvf_vlan_filter_set,
 285         .dev_infos_get        = eth_igb_infos_get,
 286         .rx_queue_setup       = eth_igb_rx_queue_setup,
 287         .rx_queue_release     = eth_igb_rx_queue_release,
 288         .tx_queue_setup       = eth_igb_tx_queue_setup,
 289         .tx_queue_release     = eth_igb_tx_queue_release,
 290 };
 291
 292 /**
 293  * Atomically reads the link status information from global
 294  * structure rte_eth_dev.
 295  *
 296  * @param dev
 297  *   - Pointer to the structure rte_eth_dev to read from.
 298  *   - Pointer to the buffer to be saved with the link status.
 299  *
 300  * @return
 301  *   - On success, zero.
 302  *   - On failure, negative value.
 303  */
 304 static inline int
 305 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 306                                 struct rte_eth_link *link)
 307 {
 308         struct rte_eth_link *dst = link;
 309         struct rte_eth_link *src = &(dev->data->dev_link);
 310
 311         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 312                                         *(uint64_t *)src) == 0)
 313                 return -1;
 314
 315         return 0;
 316 }
 317
 318 /**
 319  * Atomically writes the link status information into global
 320  * structure rte_eth_dev.
 321  *
 322  * @param dev
 323  *   - Pointer to the structure rte_eth_dev to read from.
 324  *   - Pointer to the buffer to be saved with the link status.
 325  *
 326  * @return
 327  *   - On success, zero.
 328  *   - On failure, negative value.
 329  */
 330 static inline int
 331 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 332                                 struct rte_eth_link *link)
 333 {
 334         struct rte_eth_link *dst = &(dev->data->dev_link);
 335         struct rte_eth_link *src = link;
 336
 337         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 338                                         *(uint64_t *)src) == 0)
 339                 return -1;
 340
 341         return 0;
 342 }
 343
 344 static inline void
 345 igb_intr_enable(struct rte_eth_dev *dev)
 346 {
 347         struct e1000_interrupt *intr =
 348                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 349         struct e1000_hw *hw =
 350                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 351
 352         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 353         E1000_WRITE_FLUSH(hw);
 354 }
 355
 356 static void
 357 igb_intr_disable(struct e1000_hw *hw)
 358 {
 359         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 360         E1000_WRITE_FLUSH(hw);
 361 }
 362
 363 static inline int32_t
 364 igb_pf_reset_hw(struct e1000_hw *hw)
 365 {
 366         uint32_t ctrl_ext;
 367         int32_t status;
 368
 369         status = e1000_reset_hw(hw);
 370
 371         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 372         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 373         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 374         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 375         E1000_WRITE_FLUSH(hw);
 376
 377         return status;
 378 }
 379
 380 static void
 381 igb_identify_hardware(struct rte_eth_dev *dev)
 382 {
 383         struct e1000_hw *hw =
 384                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 385
 386         hw->vendor_id = dev->pci_dev->id.vendor_id;
 387         hw->device_id = dev->pci_dev->id.device_id;
 388         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 389         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 390
 391         e1000_set_mac_type(hw);
 392
 393         /* need to check if it is a vf device below */
 394 }
 395
 396 static int
 397 igb_reset_swfw_lock(struct e1000_hw *hw)
 398 {
 399         int ret_val;
 400
 401         /*
 402          * Do mac ops initialization manually here, since we will need
 403          * some function pointers set by this call.
 404          */
 405         ret_val = e1000_init_mac_params(hw);
 406         if (ret_val)
 407                 return ret_val;
 408
 409         /*
 410          * SMBI lock should not fail in this early stage. If this is the case,
 411          * it is due to an improper exit of the application.
 412          * So force the release of the faulty lock.
 413          */
 414         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 415                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 416         }
 417         e1000_put_hw_semaphore_generic(hw);
 418
 419         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 420                 uint16_t mask;
 421
 422                 /*
 423                  * Phy lock should not fail in this early stage. If this is the case,
 424                  * it is due to an improper exit of the application.
 425                  * So force the release of the faulty lock.
 426                  */
 427                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 428                 if (hw->bus.func > E1000_FUNC_1)
 429                         mask <<= 2;
 430                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 431                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 432                                     hw->bus.func);
 433                 }
 434                 hw->mac.ops.release_swfw_sync(hw, mask);
 435
 436                 /*
 437                  * This one is more tricky since it is common to all ports; but
 438                  * swfw_sync retries last long enough (1s) to be almost sure that if
 439                  * lock can not be taken it is due to an improper lock of the
 440                  * semaphore.
 441                  */
 442                 mask = E1000_SWFW_EEP_SM;
 443                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 444                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 445                 }
 446                 hw->mac.ops.release_swfw_sync(hw, mask);
 447         }
 448
 449         return E1000_SUCCESS;
 450 }
 451
 452 static int
 453 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 454                    struct rte_eth_dev *eth_dev)
 455 {
 456         int error = 0;
 457         struct rte_pci_device *pci_dev;
 458         struct e1000_hw *hw =
 459                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 460         struct e1000_vfta * shadow_vfta =
 461                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 462         uint32_t ctrl_ext;
 463
 464         pci_dev = eth_dev->pci_dev;
 465         eth_dev->dev_ops = &eth_igb_ops;
 466         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 467         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 468
 469         /* for secondary processes, we don't initialise any further as primary
 470          * has already done this work. Only check we don't need a different
 471          * RX function */
 472         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 473                 if (eth_dev->data->scattered_rx)
 474                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 475                 return 0;
 476         }
 477
 478         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 479
 480         igb_identify_hardware(eth_dev);
 481         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 482                 error = -EIO;
 483                 goto err_late;
 484         }
 485
 486         e1000_get_bus_info(hw);
 487
 488         /* Reset any pending lock */
 489         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 490                 error = -EIO;
 491                 goto err_late;
 492         }
 493
 494         /* Finish initialization */
 495         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 496                 error = -EIO;
 497                 goto err_late;
 498         }
 499
 500         hw->mac.autoneg = 1;
 501         hw->phy.autoneg_wait_to_complete = 0;
 502         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 503
 504         /* Copper options */
 505         if (hw->phy.media_type == e1000_media_type_copper) {
 506                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 507                 hw->phy.disable_polarity_correction = 0;
 508                 hw->phy.ms_type = e1000_ms_hw_default;
 509         }
 510
 511         /*
 512          * Start from a known state, this is important in reading the nvm
 513          * and mac from that.
 514          */
 515         igb_pf_reset_hw(hw);
 516
 517         /* Make sure we have a good EEPROM before we read from it */
 518         if (e1000_validate_nvm_checksum(hw) < 0) {
 519                 /*
 520                  * Some PCI-E parts fail the first check due to
 521                  * the link being in sleep state, call it again,
 522                  * if it fails a second time its a real issue.
 523                  */
 524                 if (e1000_validate_nvm_checksum(hw) < 0) {
 525                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 526                         error = -EIO;
 527                         goto err_late;
 528                 }
 529         }
 530
 531         /* Read the permanent MAC address out of the EEPROM */
 532         if (e1000_read_mac_addr(hw) != 0) {
 533                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 534                 error = -EIO;
 535                 goto err_late;
 536         }
 537
 538         /* Allocate memory for storing MAC addresses */
 539         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 540                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 541         if (eth_dev->data->mac_addrs == NULL) {
 542                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 543                                                 "store MAC addresses",
 544                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 545                 error = -ENOMEM;
 546                 goto err_late;
 547         }
 548
 549         /* Copy the permanent MAC address */
 550         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 551
 552         /* initialize the vfta */
 553         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 554
 555         /* Now initialize the hardware */
 556         if (igb_hardware_init(hw) != 0) {
 557                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 558                 rte_free(eth_dev->data->mac_addrs);
 559                 eth_dev->data->mac_addrs = NULL;
 560                 error = -ENODEV;
 561                 goto err_late;
 562         }
 563         hw->mac.get_link_status = 1;
 564
 565         /* Indicate SOL/IDER usage */
 566         if (e1000_check_reset_block(hw) < 0) {
 567                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 568                                         "SOL/IDER session");
 569         }
 570
 571         /* initialize PF if max_vfs not zero */
 572         igb_pf_host_init(eth_dev);
 573
 574         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 575         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 576         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 577         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 578         E1000_WRITE_FLUSH(hw);
 579
 580         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 581                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 582                      pci_dev->id.device_id);
 583
 584         rte_intr_callback_register(&(pci_dev->intr_handle),
 585                 eth_igb_interrupt_handler, (void *)eth_dev);
 586
 587         /* enable uio intr after callback register */
 588         rte_intr_enable(&(pci_dev->intr_handle));
 589
 590         /* enable support intr */
 591         igb_intr_enable(eth_dev);
 592
 593         return 0;
 594
 595 err_late:
 596         igb_hw_control_release(hw);
 597
 598         return (error);
 599 }
 600
 601 /*
 602  * Virtual Function device init
 603  */
 604 static int
 605 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 606                 struct rte_eth_dev *eth_dev)
 607 {
 608         struct rte_pci_device *pci_dev;
 609         struct e1000_hw *hw =
 610                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 611         int diag;
 612
 613         PMD_INIT_FUNC_TRACE();
 614
 615         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 616         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 617         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 618
 619         /* for secondary processes, we don't initialise any further as primary
 620          * has already done this work. Only check we don't need a different
 621          * RX function */
 622         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 623                 if (eth_dev->data->scattered_rx)
 624                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 625                 return 0;
 626         }
 627
 628         pci_dev = eth_dev->pci_dev;
 629
 630         hw->device_id = pci_dev->id.device_id;
 631         hw->vendor_id = pci_dev->id.vendor_id;
 632         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 633
 634         /* Initialize the shared code (base driver) */
 635         diag = e1000_setup_init_funcs(hw, TRUE);
 636         if (diag != 0) {
 637                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 638                         diag);
 639                 return -EIO;
 640         }
 641
 642         /* init_mailbox_params */
 643         hw->mbx.ops.init_params(hw);
 644
 645         /* Disable the interrupts for VF */
 646         igbvf_intr_disable(hw);
 647
 648         diag = hw->mac.ops.reset_hw(hw);
 649
 650         /* Allocate memory for storing MAC addresses */
 651         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 652                 hw->mac.rar_entry_count, 0);
 653         if (eth_dev->data->mac_addrs == NULL) {
 654                 PMD_INIT_LOG(ERR,
 655                         "Failed to allocate %d bytes needed to store MAC "
 656                         "addresses",
 657                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 658                 return -ENOMEM;
 659         }
 660
 661         /* Copy the permanent MAC address */
 662         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 663                         &eth_dev->data->mac_addrs[0]);
 664
 665         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 666                      "mac.type=%s",
 667                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 668                      pci_dev->id.device_id, "igb_mac_82576_vf");
 669
 670         return 0;
 671 }
 672
 673 static struct eth_driver rte_igb_pmd = {
 674         {
 675                 .name = "rte_igb_pmd",
 676                 .id_table = pci_id_igb_map,
 677                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 678         },
 679         .eth_dev_init = eth_igb_dev_init,
 680         .dev_private_size = sizeof(struct e1000_adapter),
 681 };
 682
 683 /*
 684  * virtual function driver struct
 685  */
 686 static struct eth_driver rte_igbvf_pmd = {
 687         {
 688                 .name = "rte_igbvf_pmd",
 689                 .id_table = pci_id_igbvf_map,
 690                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 691         },
 692         .eth_dev_init = eth_igbvf_dev_init,
 693         .dev_private_size = sizeof(struct e1000_adapter),
 694 };
 695
 696 static int
 697 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 698 {
 699         rte_eth_driver_register(&rte_igb_pmd);
 700         return 0;
 701 }
 702
 703 static void
 704 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 705 {
 706         struct e1000_hw *hw =
 707                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 708         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 709         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 710         rctl |= E1000_RCTL_VFE;
 711         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 712 }
 713
 714 /*
 715  * VF Driver initialization routine.
 716  * Invoked one at EAL init time.
 717  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 718  */
 719 static int
 720 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 721 {
 722         PMD_INIT_FUNC_TRACE();
 723
 724         rte_eth_driver_register(&rte_igbvf_pmd);
 725         return (0);
 726 }
 727
 728 static int
 729 eth_igb_configure(struct rte_eth_dev *dev)
 730 {
 731         struct e1000_interrupt *intr =
 732                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 733
 734         PMD_INIT_FUNC_TRACE();
 735         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 736         PMD_INIT_FUNC_TRACE();
 737
 738         return (0);
 739 }
 740
 741 static int
 742 eth_igb_start(struct rte_eth_dev *dev)
 743 {
 744         struct e1000_hw *hw =
 745                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 746         int ret, i, mask;
 747         uint32_t ctrl_ext;
 748
 749         PMD_INIT_FUNC_TRACE();
 750
 751         /* Power up the phy. Needed to make the link go Up */
 752         e1000_power_up_phy(hw);
 753
 754         /*
 755          * Packet Buffer Allocation (PBA)
 756          * Writing PBA sets the receive portion of the buffer
 757          * the remainder is used for the transmit buffer.
 758          */
 759         if (hw->mac.type == e1000_82575) {
 760                 uint32_t pba;
 761
 762                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 763                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 764         }
 765
 766         /* Put the address into the Receive Address Array */
 767         e1000_rar_set(hw, hw->mac.addr, 0);
 768
 769         /* Initialize the hardware */
 770         if (igb_hardware_init(hw)) {
 771                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 772                 return (-EIO);
 773         }
 774
 775         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 776
 777         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 778         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 779         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 780         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 781         E1000_WRITE_FLUSH(hw);
 782
 783         /* configure PF module if SRIOV enabled */
 784         igb_pf_host_configure(dev);
 785
 786         /* Configure for OS presence */
 787         igb_init_manageability(hw);
 788
 789         eth_igb_tx_init(dev);
 790
 791         /* This can fail when allocating mbufs for descriptor rings */
 792         ret = eth_igb_rx_init(dev);
 793         if (ret) {
 794                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 795                 igb_dev_clear_queues(dev);
 796                 return ret;
 797         }
 798
 799         e1000_clear_hw_cntrs_base_generic(hw);
 800
 801         /*
 802          * VLAN Offload Settings
 803          */
 804         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 805                         ETH_VLAN_EXTEND_MASK;
 806         eth_igb_vlan_offload_set(dev, mask);
 807
 808         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 809                 /* Enable VLAN filter since VMDq always use VLAN filter */
 810                 igb_vmdq_vlan_hw_filter_enable(dev);
 811         }
 812
 813         /*
 814          * Configure the Interrupt Moderation register (EITR) with the maximum
 815          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 816          * spurious [DMA] memory updates of RX and TX ring descriptors.
 817          *
 818          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 819          * spurious memory updates per second should be expected.
 820          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 821          *
 822          * Because interrupts are not used at all, the MSI-X is not activated
 823          * and interrupt moderation is controlled by EITR[0].
 824          *
 825          * Note that having [almost] disabled memory updates of RX and TX ring
 826          * descriptors through the Interrupt Moderation mechanism, memory
 827          * updates of ring descriptors are now moderated by the configurable
 828          * value of Write-Back Threshold registers.
 829          */
 830         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 831                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 832                 (hw->mac.type == e1000_i211)) {
 833                 uint32_t ivar;
 834
 835                 /* Enable all RX & TX queues in the IVAR registers */
 836                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 837                 for (i = 0; i < 8; i++)
 838                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 839
 840                 /* Configure EITR with the maximum possible value (0xFFFF) */
 841                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 842         }
 843
 844         /* Setup link speed and duplex */
 845         switch (dev->data->dev_conf.link_speed) {
 846         case ETH_LINK_SPEED_AUTONEG:
 847                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 848                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 849                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 850                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 851                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 852                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 853                 else
 854                         goto error_invalid_config;
 855                 break;
 856         case ETH_LINK_SPEED_10:
 857                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 858                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 859                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 860                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 861                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 862                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 863                 else
 864                         goto error_invalid_config;
 865                 break;
 866         case ETH_LINK_SPEED_100:
 867                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 868                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 869                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 870                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 871                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 872                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 873                 else
 874                         goto error_invalid_config;
 875                 break;
 876         case ETH_LINK_SPEED_1000:
 877                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 878                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 879                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 880                 else
 881                         goto error_invalid_config;
 882                 break;
 883         case ETH_LINK_SPEED_10000:
 884         default:
 885                 goto error_invalid_config;
 886         }
 887         e1000_setup_link(hw);
 888
 889         /* check if lsc interrupt feature is enabled */
 890         if (dev->data->dev_conf.intr_conf.lsc != 0)
 891                 ret = eth_igb_lsc_interrupt_setup(dev);
 892
 893         /* resume enabled intr since hw reset */
 894         igb_intr_enable(dev);
 895
 896         PMD_INIT_LOG(DEBUG, "<<");
 897
 898         return (0);
 899
 900 error_invalid_config:
 901         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 902                      dev->data->dev_conf.link_speed,
 903                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 904         igb_dev_clear_queues(dev);
 905         return (-EINVAL);
 906 }
 907
 908 /*********************************************************************
 909  *
 910  *  This routine disables all traffic on the adapter by issuing a
 911  *  global reset on the MAC.
 912  *
 913  **********************************************************************/
 914 static void
 915 eth_igb_stop(struct rte_eth_dev *dev)
 916 {
 917         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 918         struct rte_eth_link link;
 919
 920         igb_intr_disable(hw);
 921         igb_pf_reset_hw(hw);
 922         E1000_WRITE_REG(hw, E1000_WUC, 0);
 923
 924         /* Set bit for Go Link disconnect */
 925         if (hw->mac.type >= e1000_82580) {
 926                 uint32_t phpm_reg;
 927
 928                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 929                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 930                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 931         }
 932
 933         /* Power down the phy. Needed to make the link go Down */
 934         e1000_power_down_phy(hw);
 935
 936         igb_dev_clear_queues(dev);
 937
 938         /* clear the recorded link status */
 939         memset(&link, 0, sizeof(link));
 940         rte_igb_dev_atomic_write_link_status(dev, &link);
 941 }
 942
 943 static void
 944 eth_igb_close(struct rte_eth_dev *dev)
 945 {
 946         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947         struct rte_eth_link link;
 948
 949         eth_igb_stop(dev);
 950         e1000_phy_hw_reset(hw);
 951         igb_release_manageability(hw);
 952         igb_hw_control_release(hw);
 953
 954         /* Clear bit for Go Link disconnect */
 955         if (hw->mac.type >= e1000_82580) {
 956                 uint32_t phpm_reg;
 957
 958                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 959                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 960                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 961         }
 962
 963         igb_dev_clear_queues(dev);
 964
 965         memset(&link, 0, sizeof(link));
 966         rte_igb_dev_atomic_write_link_status(dev, &link);
 967 }
 968
 969 static int
 970 igb_get_rx_buffer_size(struct e1000_hw *hw)
 971 {
 972         uint32_t rx_buf_size;
 973         if (hw->mac.type == e1000_82576) {
 974                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 975         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 976                 /* PBS needs to be translated according to a lookup table */
 977                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 978                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 979                 rx_buf_size = (rx_buf_size << 10);
 980         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
 981                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 982         } else {
 983                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 984         }
 985
 986         return rx_buf_size;
 987 }
 988
 989 /*********************************************************************
 990  *
 991  *  Initialize the hardware
 992  *
 993  **********************************************************************/
 994 static int
 995 igb_hardware_init(struct e1000_hw *hw)
 996 {
 997         uint32_t rx_buf_size;
 998         int diag;
 999
1000         /* Let the firmware know the OS is in control */
1001         igb_hw_control_acquire(hw);
1002
1003         /*
1004          * These parameters control the automatic generation (Tx) and
1005          * response (Rx) to Ethernet PAUSE frames.
1006          * - High water mark should allow for at least two standard size (1518)
1007          *   frames to be received after sending an XOFF.
1008          * - Low water mark works best when it is very near the high water mark.
1009          *   This allows the receiver to restart by sending XON when it has
1010          *   drained a bit. Here we use an arbitrary value of 1500 which will
1011          *   restart after one full frame is pulled from the buffer. There
1012          *   could be several smaller frames in the buffer and if so they will
1013          *   not trigger the XON until their total number reduces the buffer
1014          *   by 1500.
1015          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1016          */
1017         rx_buf_size = igb_get_rx_buffer_size(hw);
1018
1019         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1020         hw->fc.low_water = hw->fc.high_water - 1500;
1021         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1022         hw->fc.send_xon = 1;
1023
1024         /* Set Flow control, use the tunable location if sane */
1025         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1026                 hw->fc.requested_mode = igb_fc_setting;
1027         else
1028                 hw->fc.requested_mode = e1000_fc_none;
1029
1030         /* Issue a global reset */
1031         igb_pf_reset_hw(hw);
1032         E1000_WRITE_REG(hw, E1000_WUC, 0);
1033
1034         diag = e1000_init_hw(hw);
1035         if (diag < 0)
1036                 return (diag);
1037
1038         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1039         e1000_get_phy_info(hw);
1040         e1000_check_for_link(hw);
1041
1042         return (0);
1043 }
1044
1045 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1046 static void
1047 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1048 {
1049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050         struct e1000_hw_stats *stats =
1051                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1052         int pause_frames;
1053
1054         if(hw->phy.media_type == e1000_media_type_copper ||
1055             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1056                 stats->symerrs +=
1057                     E1000_READ_REG(hw,E1000_SYMERRS);
1058                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1059         }
1060
1061         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1062         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1063         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1064         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1065
1066         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1067         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1068         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1069         stats->dc += E1000_READ_REG(hw, E1000_DC);
1070         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1071         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1072         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1073         /*
1074         ** For watchdog management we need to know if we have been
1075         ** paused during the last interval, so capture that here.
1076         */
1077         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1078         stats->xoffrxc += pause_frames;
1079         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1080         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1081         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1082         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1083         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1084         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1085         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1086         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1087         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1088         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1089         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1090         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1091
1092         /* For the 64-bit byte counters the low dword must be read first. */
1093         /* Both registers clear on the read of the high dword */
1094
1095         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1096         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1097         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1098         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1099
1100         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1101         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1102         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1103         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1104         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1105
1106         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1107         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1108
1109         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1110         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1111         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1112         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1113         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1114         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1115         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1116         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1117         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1118         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1119
1120         /* Interrupt Counts */
1121
1122         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1123         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1124         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1125         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1126         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1127         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1128         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1129         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1130         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1131
1132         /* Host to Card Statistics */
1133
1134         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1135         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1136         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1137         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1138         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1139         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1140         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1141         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1142         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1143         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1144         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1145         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1146         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1147         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1148
1149         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1150         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1151         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1152         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1153         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1154         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1155
1156         if (rte_stats == NULL)
1157                 return;
1158
1159         /* Rx Errors */
1160         rte_stats->ibadcrc = stats->crcerrs;
1161         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1162         rte_stats->imissed = stats->mpc;
1163         rte_stats->ierrors = rte_stats->ibadcrc +
1164                              rte_stats->ibadlen +
1165                              rte_stats->imissed +
1166                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1167
1168         /* Tx Errors */
1169         rte_stats->oerrors = stats->ecol + stats->latecol;
1170
1171         /* XON/XOFF pause frames */
1172         rte_stats->tx_pause_xon  = stats->xontxc;
1173         rte_stats->rx_pause_xon  = stats->xonrxc;
1174         rte_stats->tx_pause_xoff = stats->xofftxc;
1175         rte_stats->rx_pause_xoff = stats->xoffrxc;
1176
1177         rte_stats->ipackets = stats->gprc;
1178         rte_stats->opackets = stats->gptc;
1179         rte_stats->ibytes   = stats->gorc;
1180         rte_stats->obytes   = stats->gotc;
1181 }
1182
1183 static void
1184 eth_igb_stats_reset(struct rte_eth_dev *dev)
1185 {
1186         struct e1000_hw_stats *hw_stats =
1187                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1188
1189         /* HW registers are cleared on read */
1190         eth_igb_stats_get(dev, NULL);
1191
1192         /* Reset software totals */
1193         memset(hw_stats, 0, sizeof(*hw_stats));
1194 }
1195
1196 static void
1197 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1198 {
1199         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1201                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1202
1203         /* Good Rx packets, include VF loopback */
1204         UPDATE_VF_STAT(E1000_VFGPRC,
1205             hw_stats->last_gprc, hw_stats->gprc);
1206
1207         /* Good Rx octets, include VF loopback */
1208         UPDATE_VF_STAT(E1000_VFGORC,
1209             hw_stats->last_gorc, hw_stats->gorc);
1210
1211         /* Good Tx packets, include VF loopback */
1212         UPDATE_VF_STAT(E1000_VFGPTC,
1213             hw_stats->last_gptc, hw_stats->gptc);
1214
1215         /* Good Tx octets, include VF loopback */
1216         UPDATE_VF_STAT(E1000_VFGOTC,
1217             hw_stats->last_gotc, hw_stats->gotc);
1218
1219         /* Rx Multicst packets */
1220         UPDATE_VF_STAT(E1000_VFMPRC,
1221             hw_stats->last_mprc, hw_stats->mprc);
1222
1223         /* Good Rx loopback packets */
1224         UPDATE_VF_STAT(E1000_VFGPRLBC,
1225             hw_stats->last_gprlbc, hw_stats->gprlbc);
1226
1227         /* Good Rx loopback octets */
1228         UPDATE_VF_STAT(E1000_VFGORLBC,
1229             hw_stats->last_gorlbc, hw_stats->gorlbc);
1230
1231         /* Good Tx loopback packets */
1232         UPDATE_VF_STAT(E1000_VFGPTLBC,
1233             hw_stats->last_gptlbc, hw_stats->gptlbc);
1234
1235         /* Good Tx loopback octets */
1236         UPDATE_VF_STAT(E1000_VFGOTLBC,
1237             hw_stats->last_gotlbc, hw_stats->gotlbc);
1238
1239         if (rte_stats == NULL)
1240                 return;
1241
1242         memset(rte_stats, 0, sizeof(*rte_stats));
1243         rte_stats->ipackets = hw_stats->gprc;
1244         rte_stats->ibytes = hw_stats->gorc;
1245         rte_stats->opackets = hw_stats->gptc;
1246         rte_stats->obytes = hw_stats->gotc;
1247         rte_stats->imcasts = hw_stats->mprc;
1248         rte_stats->ilbpackets = hw_stats->gprlbc;
1249         rte_stats->ilbbytes = hw_stats->gorlbc;
1250         rte_stats->olbpackets = hw_stats->gptlbc;
1251         rte_stats->olbbytes = hw_stats->gotlbc;
1252
1253 }
1254
1255 static void
1256 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1257 {
1258         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1259                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1260
1261         /* Sync HW register to the last stats */
1262         eth_igbvf_stats_get(dev, NULL);
1263
1264         /* reset HW current stats*/
1265         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1266                offsetof(struct e1000_vf_stats, gprc));
1267
1268 }
1269
1270 static void
1271 eth_igb_infos_get(struct rte_eth_dev *dev,
1272                     struct rte_eth_dev_info *dev_info)
1273 {
1274         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275
1276         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1277         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1278         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1279         dev_info->rx_offload_capa =
1280                 DEV_RX_OFFLOAD_VLAN_STRIP |
1281                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1282                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1283                 DEV_RX_OFFLOAD_TCP_CKSUM;
1284         dev_info->tx_offload_capa =
1285                 DEV_TX_OFFLOAD_VLAN_INSERT |
1286                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1287                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1288                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1289                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1290
1291         switch (hw->mac.type) {
1292         case e1000_82575:
1293                 dev_info->max_rx_queues = 4;
1294                 dev_info->max_tx_queues = 4;
1295                 dev_info->max_vmdq_pools = 0;
1296                 break;
1297
1298         case e1000_82576:
1299                 dev_info->max_rx_queues = 16;
1300                 dev_info->max_tx_queues = 16;
1301                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1302                 break;
1303
1304         case e1000_82580:
1305                 dev_info->max_rx_queues = 8;
1306                 dev_info->max_tx_queues = 8;
1307                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1308                 break;
1309
1310         case e1000_i350:
1311                 dev_info->max_rx_queues = 8;
1312                 dev_info->max_tx_queues = 8;
1313                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1314                 break;
1315
1316         case e1000_i354:
1317                 dev_info->max_rx_queues = 8;
1318                 dev_info->max_tx_queues = 8;
1319                 break;
1320
1321         case e1000_i210:
1322                 dev_info->max_rx_queues = 4;
1323                 dev_info->max_tx_queues = 4;
1324                 dev_info->max_vmdq_pools = 0;
1325                 break;
1326
1327         case e1000_i211:
1328                 dev_info->max_rx_queues = 2;
1329                 dev_info->max_tx_queues = 2;
1330                 dev_info->max_vmdq_pools = 0;
1331                 break;
1332
1333         case e1000_vfadapt:
1334                 dev_info->max_rx_queues = 2;
1335                 dev_info->max_tx_queues = 2;
1336                 dev_info->max_vmdq_pools = 0;
1337                 break;
1338
1339         case e1000_vfadapt_i350:
1340                 dev_info->max_rx_queues = 1;
1341                 dev_info->max_tx_queues = 1;
1342                 dev_info->max_vmdq_pools = 0;
1343                 break;
1344
1345         default:
1346                 /* Should not happen */
1347                 dev_info->max_rx_queues = 0;
1348                 dev_info->max_tx_queues = 0;
1349                 dev_info->max_vmdq_pools = 0;
1350         }
1351
1352         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1353                 .rx_thresh = {
1354                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1355                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1356                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1357                 },
1358                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1359                 .rx_drop_en = 0,
1360         };
1361
1362         dev_info->default_txconf = (struct rte_eth_txconf) {
1363                 .tx_thresh = {
1364                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1365                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1366                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1367                 },
1368                 .txq_flags = 0,
1369         };
1370 }
1371
1372 /* return 0 means link status changed, -1 means not changed */
1373 static int
1374 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1375 {
1376         struct e1000_hw *hw =
1377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         struct rte_eth_link link, old;
1379         int link_check, count;
1380
1381         link_check = 0;
1382         hw->mac.get_link_status = 1;
1383
1384         /* possible wait-to-complete in up to 9 seconds */
1385         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1386                 /* Read the real link status */
1387                 switch (hw->phy.media_type) {
1388                 case e1000_media_type_copper:
1389                         /* Do the work to read phy */
1390                         e1000_check_for_link(hw);
1391                         link_check = !hw->mac.get_link_status;
1392                         break;
1393
1394                 case e1000_media_type_fiber:
1395                         e1000_check_for_link(hw);
1396                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1397                                       E1000_STATUS_LU);
1398                         break;
1399
1400                 case e1000_media_type_internal_serdes:
1401                         e1000_check_for_link(hw);
1402                         link_check = hw->mac.serdes_has_link;
1403                         break;
1404
1405                 /* VF device is type_unknown */
1406                 case e1000_media_type_unknown:
1407                         eth_igbvf_link_update(hw);
1408                         link_check = !hw->mac.get_link_status;
1409                         break;
1410
1411                 default:
1412                         break;
1413                 }
1414                 if (link_check || wait_to_complete == 0)
1415                         break;
1416                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1417         }
1418         memset(&link, 0, sizeof(link));
1419         rte_igb_dev_atomic_read_link_status(dev, &link);
1420         old = link;
1421
1422         /* Now we check if a transition has happened */
1423         if (link_check) {
1424                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1425                                           &link.link_duplex);
1426                 link.link_status = 1;
1427         } else if (!link_check) {
1428                 link.link_speed = 0;
1429                 link.link_duplex = 0;
1430                 link.link_status = 0;
1431         }
1432         rte_igb_dev_atomic_write_link_status(dev, &link);
1433
1434         /* not changed */
1435         if (old.link_status == link.link_status)
1436                 return -1;
1437
1438         /* changed */
1439         return 0;
1440 }
1441
1442 /*
1443  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1444  * For ASF and Pass Through versions of f/w this means
1445  * that the driver is loaded.
1446  */
1447 static void
1448 igb_hw_control_acquire(struct e1000_hw *hw)
1449 {
1450         uint32_t ctrl_ext;
1451
1452         /* Let firmware know the driver has taken over */
1453         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1454         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1455 }
1456
1457 /*
1458  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1459  * For ASF and Pass Through versions of f/w this means that the
1460  * driver is no longer loaded.
1461  */
1462 static void
1463 igb_hw_control_release(struct e1000_hw *hw)
1464 {
1465         uint32_t ctrl_ext;
1466
1467         /* Let firmware taken over control of h/w */
1468         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1469         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1470                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1471 }
1472
1473 /*
1474  * Bit of a misnomer, what this really means is
1475  * to enable OS management of the system... aka
1476  * to disable special hardware management features.
1477  */
1478 static void
1479 igb_init_manageability(struct e1000_hw *hw)
1480 {
1481         if (e1000_enable_mng_pass_thru(hw)) {
1482                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1483                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1484
1485                 /* disable hardware interception of ARP */
1486                 manc &= ~(E1000_MANC_ARP_EN);
1487
1488                 /* enable receiving management packets to the host */
1489                 manc |= E1000_MANC_EN_MNG2HOST;
1490                 manc2h |= 1 << 5;  /* Mng Port 623 */
1491                 manc2h |= 1 << 6;  /* Mng Port 664 */
1492                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1493                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1494         }
1495 }
1496
1497 static void
1498 igb_release_manageability(struct e1000_hw *hw)
1499 {
1500         if (e1000_enable_mng_pass_thru(hw)) {
1501                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1502
1503                 manc |= E1000_MANC_ARP_EN;
1504                 manc &= ~E1000_MANC_EN_MNG2HOST;
1505
1506                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1507         }
1508 }
1509
1510 static void
1511 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1512 {
1513         struct e1000_hw *hw =
1514                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515         uint32_t rctl;
1516
1517         rctl = E1000_READ_REG(hw, E1000_RCTL);
1518         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1519         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1520 }
1521
1522 static void
1523 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1524 {
1525         struct e1000_hw *hw =
1526                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1527         uint32_t rctl;
1528
1529         rctl = E1000_READ_REG(hw, E1000_RCTL);
1530         rctl &= (~E1000_RCTL_UPE);
1531         if (dev->data->all_multicast == 1)
1532                 rctl |= E1000_RCTL_MPE;
1533         else
1534                 rctl &= (~E1000_RCTL_MPE);
1535         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1536 }
1537
1538 static void
1539 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1540 {
1541         struct e1000_hw *hw =
1542                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543         uint32_t rctl;
1544
1545         rctl = E1000_READ_REG(hw, E1000_RCTL);
1546         rctl |= E1000_RCTL_MPE;
1547         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1548 }
1549
1550 static void
1551 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1552 {
1553         struct e1000_hw *hw =
1554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555         uint32_t rctl;
1556
1557         if (dev->data->promiscuous == 1)
1558                 return; /* must remain in all_multicast mode */
1559         rctl = E1000_READ_REG(hw, E1000_RCTL);
1560         rctl &= (~E1000_RCTL_MPE);
1561         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1562 }
1563
1564 static int
1565 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1566 {
1567         struct e1000_hw *hw =
1568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569         struct e1000_vfta * shadow_vfta =
1570                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1571         uint32_t vfta;
1572         uint32_t vid_idx;
1573         uint32_t vid_bit;
1574
1575         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1576                               E1000_VFTA_ENTRY_MASK);
1577         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1578         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1579         if (on)
1580                 vfta |= vid_bit;
1581         else
1582                 vfta &= ~vid_bit;
1583         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1584
1585         /* update local VFTA copy */
1586         shadow_vfta->vfta[vid_idx] = vfta;
1587
1588         return 0;
1589 }
1590
1591 static void
1592 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1593 {
1594         struct e1000_hw *hw =
1595                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         uint32_t reg = ETHER_TYPE_VLAN ;
1597
1598         reg |= (tpid << 16);
1599         E1000_WRITE_REG(hw, E1000_VET, reg);
1600 }
1601
1602 static void
1603 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1604 {
1605         struct e1000_hw *hw =
1606                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607         uint32_t reg;
1608
1609         /* Filter Table Disable */
1610         reg = E1000_READ_REG(hw, E1000_RCTL);
1611         reg &= ~E1000_RCTL_CFIEN;
1612         reg &= ~E1000_RCTL_VFE;
1613         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1614 }
1615
1616 static void
1617 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1618 {
1619         struct e1000_hw *hw =
1620                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621         struct e1000_vfta * shadow_vfta =
1622                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1623         uint32_t reg;
1624         int i;
1625
1626         /* Filter Table Enable, CFI not used for packet acceptance */
1627         reg = E1000_READ_REG(hw, E1000_RCTL);
1628         reg &= ~E1000_RCTL_CFIEN;
1629         reg |= E1000_RCTL_VFE;
1630         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1631
1632         /* restore VFTA table */
1633         for (i = 0; i < IGB_VFTA_SIZE; i++)
1634                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1635 }
1636
1637 static void
1638 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1639 {
1640         struct e1000_hw *hw =
1641                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642         uint32_t reg;
1643
1644         /* VLAN Mode Disable */
1645         reg = E1000_READ_REG(hw, E1000_CTRL);
1646         reg &= ~E1000_CTRL_VME;
1647         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1648 }
1649
1650 static void
1651 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1652 {
1653         struct e1000_hw *hw =
1654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         uint32_t reg;
1656
1657         /* VLAN Mode Enable */
1658         reg = E1000_READ_REG(hw, E1000_CTRL);
1659         reg |= E1000_CTRL_VME;
1660         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1661 }
1662
1663 static void
1664 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1665 {
1666         struct e1000_hw *hw =
1667                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668         uint32_t reg;
1669
1670         /* CTRL_EXT: Extended VLAN */
1671         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1672         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1673         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1674
1675         /* Update maximum packet length */
1676         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1677                 E1000_WRITE_REG(hw, E1000_RLPML,
1678                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1679                                                 VLAN_TAG_SIZE);
1680 }
1681
1682 static void
1683 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1684 {
1685         struct e1000_hw *hw =
1686                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         uint32_t reg;
1688
1689         /* CTRL_EXT: Extended VLAN */
1690         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1691         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1692         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1693
1694         /* Update maximum packet length */
1695         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1696                 E1000_WRITE_REG(hw, E1000_RLPML,
1697                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1698                                                 2 * VLAN_TAG_SIZE);
1699 }
1700
1701 static void
1702 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1703 {
1704         if(mask & ETH_VLAN_STRIP_MASK){
1705                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1706                         igb_vlan_hw_strip_enable(dev);
1707                 else
1708                         igb_vlan_hw_strip_disable(dev);
1709         }
1710
1711         if(mask & ETH_VLAN_FILTER_MASK){
1712                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1713                         igb_vlan_hw_filter_enable(dev);
1714                 else
1715                         igb_vlan_hw_filter_disable(dev);
1716         }
1717
1718         if(mask & ETH_VLAN_EXTEND_MASK){
1719                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1720                         igb_vlan_hw_extend_enable(dev);
1721                 else
1722                         igb_vlan_hw_extend_disable(dev);
1723         }
1724 }
1725
1726
1727 /**
1728  * It enables the interrupt mask and then enable the interrupt.
1729  *
1730  * @param dev
1731  *  Pointer to struct rte_eth_dev.
1732  *
1733  * @return
1734  *  - On success, zero.
1735  *  - On failure, a negative value.
1736  */
1737 static int
1738 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1739 {
1740         struct e1000_interrupt *intr =
1741                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1742
1743         intr->mask |= E1000_ICR_LSC;
1744
1745         return 0;
1746 }
1747
1748 /*
1749  * It reads ICR and gets interrupt causes, check it and set a bit flag
1750  * to update link status.
1751  *
1752  * @param dev
1753  *  Pointer to struct rte_eth_dev.
1754  *
1755  * @return
1756  *  - On success, zero.
1757  *  - On failure, a negative value.
1758  */
1759 static int
1760 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1761 {
1762         uint32_t icr;
1763         struct e1000_hw *hw =
1764                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1765         struct e1000_interrupt *intr =
1766                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1767
1768         igb_intr_disable(hw);
1769
1770         /* read-on-clear nic registers here */
1771         icr = E1000_READ_REG(hw, E1000_ICR);
1772
1773         intr->flags = 0;
1774         if (icr & E1000_ICR_LSC) {
1775                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1776         }
1777
1778         if (icr & E1000_ICR_VMMB)
1779                 intr->flags |= E1000_FLAG_MAILBOX;
1780
1781         return 0;
1782 }
1783
1784 /*
1785  * It executes link_update after knowing an interrupt is prsent.
1786  *
1787  * @param dev
1788  *  Pointer to struct rte_eth_dev.
1789  *
1790  * @return
1791  *  - On success, zero.
1792  *  - On failure, a negative value.
1793  */
1794 static int
1795 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1796 {
1797         struct e1000_hw *hw =
1798                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799         struct e1000_interrupt *intr =
1800                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1801         uint32_t tctl, rctl;
1802         struct rte_eth_link link;
1803         int ret;
1804
1805         if (intr->flags & E1000_FLAG_MAILBOX) {
1806                 igb_pf_mbx_process(dev);
1807                 intr->flags &= ~E1000_FLAG_MAILBOX;
1808         }
1809
1810         igb_intr_enable(dev);
1811         rte_intr_enable(&(dev->pci_dev->intr_handle));
1812
1813         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1814                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1815
1816                 /* set get_link_status to check register later */
1817                 hw->mac.get_link_status = 1;
1818                 ret = eth_igb_link_update(dev, 0);
1819
1820                 /* check if link has changed */
1821                 if (ret < 0)
1822                         return 0;
1823
1824                 memset(&link, 0, sizeof(link));
1825                 rte_igb_dev_atomic_read_link_status(dev, &link);
1826                 if (link.link_status) {
1827                         PMD_INIT_LOG(INFO,
1828                                      " Port %d: Link Up - speed %u Mbps - %s",
1829                                      dev->data->port_id,
1830                                      (unsigned)link.link_speed,
1831                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1832                                      "full-duplex" : "half-duplex");
1833                 } else {
1834                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1835                                      dev->data->port_id);
1836                 }
1837                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1838                              dev->pci_dev->addr.domain,
1839                              dev->pci_dev->addr.bus,
1840                              dev->pci_dev->addr.devid,
1841                              dev->pci_dev->addr.function);
1842                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1843                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1844                 if (link.link_status) {
1845                         /* enable Tx/Rx */
1846                         tctl |= E1000_TCTL_EN;
1847                         rctl |= E1000_RCTL_EN;
1848                 } else {
1849                         /* disable Tx/Rx */
1850                         tctl &= ~E1000_TCTL_EN;
1851                         rctl &= ~E1000_RCTL_EN;
1852                 }
1853                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1854                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1855                 E1000_WRITE_FLUSH(hw);
1856                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1857         }
1858
1859         return 0;
1860 }
1861
1862 /**
1863  * Interrupt handler which shall be registered at first.
1864  *
1865  * @param handle
1866  *  Pointer to interrupt handle.
1867  * @param param
1868  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1869  *
1870  * @return
1871  *  void
1872  */
1873 static void
1874 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1875                                                         void *param)
1876 {
1877         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1878
1879         eth_igb_interrupt_get_status(dev);
1880         eth_igb_interrupt_action(dev);
1881 }
1882
1883 static int
1884 eth_igb_led_on(struct rte_eth_dev *dev)
1885 {
1886         struct e1000_hw *hw;
1887
1888         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1890 }
1891
1892 static int
1893 eth_igb_led_off(struct rte_eth_dev *dev)
1894 {
1895         struct e1000_hw *hw;
1896
1897         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1899 }
1900
1901 static int
1902 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1903 {
1904         struct e1000_hw *hw;
1905         uint32_t ctrl;
1906         int tx_pause;
1907         int rx_pause;
1908
1909         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         fc_conf->pause_time = hw->fc.pause_time;
1911         fc_conf->high_water = hw->fc.high_water;
1912         fc_conf->low_water = hw->fc.low_water;
1913         fc_conf->send_xon = hw->fc.send_xon;
1914         fc_conf->autoneg = hw->mac.autoneg;
1915
1916         /*
1917          * Return rx_pause and tx_pause status according to actual setting of
1918          * the TFCE and RFCE bits in the CTRL register.
1919          */
1920         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1921         if (ctrl & E1000_CTRL_TFCE)
1922                 tx_pause = 1;
1923         else
1924                 tx_pause = 0;
1925
1926         if (ctrl & E1000_CTRL_RFCE)
1927                 rx_pause = 1;
1928         else
1929                 rx_pause = 0;
1930
1931         if (rx_pause && tx_pause)
1932                 fc_conf->mode = RTE_FC_FULL;
1933         else if (rx_pause)
1934                 fc_conf->mode = RTE_FC_RX_PAUSE;
1935         else if (tx_pause)
1936                 fc_conf->mode = RTE_FC_TX_PAUSE;
1937         else
1938                 fc_conf->mode = RTE_FC_NONE;
1939
1940         return 0;
1941 }
1942
1943 static int
1944 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1945 {
1946         struct e1000_hw *hw;
1947         int err;
1948         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1949                 e1000_fc_none,
1950                 e1000_fc_rx_pause,
1951                 e1000_fc_tx_pause,
1952                 e1000_fc_full
1953         };
1954         uint32_t rx_buf_size;
1955         uint32_t max_high_water;
1956         uint32_t rctl;
1957
1958         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         if (fc_conf->autoneg != hw->mac.autoneg)
1960                 return -ENOTSUP;
1961         rx_buf_size = igb_get_rx_buffer_size(hw);
1962         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1963
1964         /* At least reserve one Ethernet frame for watermark */
1965         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1966         if ((fc_conf->high_water > max_high_water) ||
1967             (fc_conf->high_water < fc_conf->low_water)) {
1968                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1969                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
1970                 return (-EINVAL);
1971         }
1972
1973         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1974         hw->fc.pause_time     = fc_conf->pause_time;
1975         hw->fc.high_water     = fc_conf->high_water;
1976         hw->fc.low_water      = fc_conf->low_water;
1977         hw->fc.send_xon       = fc_conf->send_xon;
1978
1979         err = e1000_setup_link_generic(hw);
1980         if (err == E1000_SUCCESS) {
1981
1982                 /* check if we want to forward MAC frames - driver doesn't have native
1983                  * capability to do that, so we'll write the registers ourselves */
1984
1985                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1986
1987                 /* set or clear MFLCN.PMCF bit depending on configuration */
1988                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1989                         rctl |= E1000_RCTL_PMCF;
1990                 else
1991                         rctl &= ~E1000_RCTL_PMCF;
1992
1993                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1994                 E1000_WRITE_FLUSH(hw);
1995
1996                 return 0;
1997         }
1998
1999         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2000         return (-EIO);
2001 }
2002
2003 #define E1000_RAH_POOLSEL_SHIFT      (18)
2004 static void
2005 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2006                 uint32_t index, __rte_unused uint32_t pool)
2007 {
2008         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009         uint32_t rah;
2010
2011         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2012         rah = E1000_READ_REG(hw, E1000_RAH(index));
2013         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2014         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2015 }
2016
2017 static void
2018 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2019 {
2020         uint8_t addr[ETHER_ADDR_LEN];
2021         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022
2023         memset(addr, 0, sizeof(addr));
2024
2025         e1000_rar_set(hw, addr, index);
2026 }
2027
2028 /*
2029  * Virtual Function operations
2030  */
2031 static void
2032 igbvf_intr_disable(struct e1000_hw *hw)
2033 {
2034         PMD_INIT_FUNC_TRACE();
2035
2036         /* Clear interrupt mask to stop from interrupts being generated */
2037         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2038
2039         E1000_WRITE_FLUSH(hw);
2040 }
2041
2042 static void
2043 igbvf_stop_adapter(struct rte_eth_dev *dev)
2044 {
2045         u32 reg_val;
2046         u16 i;
2047         struct rte_eth_dev_info dev_info;
2048         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049
2050         memset(&dev_info, 0, sizeof(dev_info));
2051         eth_igb_infos_get(dev, &dev_info);
2052
2053         /* Clear interrupt mask to stop from interrupts being generated */
2054         igbvf_intr_disable(hw);
2055
2056         /* Clear any pending interrupts, flush previous writes */
2057         E1000_READ_REG(hw, E1000_EICR);
2058
2059         /* Disable the transmit unit.  Each queue must be disabled. */
2060         for (i = 0; i < dev_info.max_tx_queues; i++)
2061                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2062
2063         /* Disable the receive unit by stopping each queue */
2064         for (i = 0; i < dev_info.max_rx_queues; i++) {
2065                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2066                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2067                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2068                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2069                         ;
2070         }
2071
2072         /* flush all queues disables */
2073         E1000_WRITE_FLUSH(hw);
2074         msec_delay(2);
2075 }
2076
2077 static int eth_igbvf_link_update(struct e1000_hw *hw)
2078 {
2079         struct e1000_mbx_info *mbx = &hw->mbx;
2080         struct e1000_mac_info *mac = &hw->mac;
2081         int ret_val = E1000_SUCCESS;
2082
2083         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2084
2085         /*
2086          * We only want to run this if there has been a rst asserted.
2087          * in this case that could mean a link change, device reset,
2088          * or a virtual function reset
2089          */
2090
2091         /* If we were hit with a reset or timeout drop the link */
2092         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2093                 mac->get_link_status = TRUE;
2094
2095         if (!mac->get_link_status)
2096                 goto out;
2097
2098         /* if link status is down no point in checking to see if pf is up */
2099         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2100                 goto out;
2101
2102         /* if we passed all the tests above then the link is up and we no
2103          * longer need to check for link */
2104         mac->get_link_status = FALSE;
2105
2106 out:
2107         return ret_val;
2108 }
2109
2110
2111 static int
2112 igbvf_dev_configure(struct rte_eth_dev *dev)
2113 {
2114         struct rte_eth_conf* conf = &dev->data->dev_conf;
2115
2116         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2117                      dev->data->port_id);
2118
2119         /*
2120          * VF has no ability to enable/disable HW CRC
2121          * Keep the persistent behavior the same as Host PF
2122          */
2123 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2124         if (!conf->rxmode.hw_strip_crc) {
2125                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2126                 conf->rxmode.hw_strip_crc = 1;
2127         }
2128 #else
2129         if (conf->rxmode.hw_strip_crc) {
2130                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2131                 conf->rxmode.hw_strip_crc = 0;
2132         }
2133 #endif
2134
2135         return 0;
2136 }
2137
2138 static int
2139 igbvf_dev_start(struct rte_eth_dev *dev)
2140 {
2141         struct e1000_hw *hw =
2142                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143         int ret;
2144
2145         PMD_INIT_FUNC_TRACE();
2146
2147         hw->mac.ops.reset_hw(hw);
2148
2149         /* Set all vfta */
2150         igbvf_set_vfta_all(dev,1);
2151
2152         eth_igbvf_tx_init(dev);
2153
2154         /* This can fail when allocating mbufs for descriptor rings */
2155         ret = eth_igbvf_rx_init(dev);
2156         if (ret) {
2157                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2158                 igb_dev_clear_queues(dev);
2159                 return ret;
2160         }
2161
2162         return 0;
2163 }
2164
2165 static void
2166 igbvf_dev_stop(struct rte_eth_dev *dev)
2167 {
2168         PMD_INIT_FUNC_TRACE();
2169
2170         igbvf_stop_adapter(dev);
2171
2172         /*
2173           * Clear what we set, but we still keep shadow_vfta to
2174           * restore after device starts
2175           */
2176         igbvf_set_vfta_all(dev,0);
2177
2178         igb_dev_clear_queues(dev);
2179 }
2180
2181 static void
2182 igbvf_dev_close(struct rte_eth_dev *dev)
2183 {
2184         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185
2186         PMD_INIT_FUNC_TRACE();
2187
2188         e1000_reset_hw(hw);
2189
2190         igbvf_dev_stop(dev);
2191 }
2192
2193 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2194 {
2195         struct e1000_mbx_info *mbx = &hw->mbx;
2196         uint32_t msgbuf[2];
2197
2198         /* After set vlan, vlan strip will also be enabled in igb driver*/
2199         msgbuf[0] = E1000_VF_SET_VLAN;
2200         msgbuf[1] = vid;
2201         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2202         if (on)
2203                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2204
2205         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2206 }
2207
2208 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2209 {
2210         struct e1000_hw *hw =
2211                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         struct e1000_vfta * shadow_vfta =
2213                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2214         int i = 0, j = 0, vfta = 0, mask = 1;
2215
2216         for (i = 0; i < IGB_VFTA_SIZE; i++){
2217                 vfta = shadow_vfta->vfta[i];
2218                 if(vfta){
2219                         mask = 1;
2220                         for (j = 0; j < 32; j++){
2221                                 if(vfta & mask)
2222                                         igbvf_set_vfta(hw,
2223                                                 (uint16_t)((i<<5)+j), on);
2224                                 mask<<=1;
2225                         }
2226                 }
2227         }
2228
2229 }
2230
2231 static int
2232 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2233 {
2234         struct e1000_hw *hw =
2235                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236         struct e1000_vfta * shadow_vfta =
2237                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2238         uint32_t vid_idx = 0;
2239         uint32_t vid_bit = 0;
2240         int ret = 0;
2241
2242         PMD_INIT_FUNC_TRACE();
2243
2244         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2245         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2246         if(ret){
2247                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2248                 return ret;
2249         }
2250         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2251         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2252
2253         /*Save what we set and retore it after device reset*/
2254         if (on)
2255                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2256         else
2257                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2258
2259         return 0;
2260 }
2261
2262 static int
2263 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2264                                 struct rte_eth_rss_reta *reta_conf)
2265 {
2266         uint8_t i,j,mask;
2267         uint32_t reta;
2268         struct e1000_hw *hw =
2269                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270
2271         /*
2272          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2273          * 128-entries in 32 registers
2274          */
2275         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2276                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2277                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2278                 else
2279                         mask = (uint8_t)((reta_conf->mask_hi >>
2280                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2281                 if (mask != 0) {
2282                         reta = 0;
2283                         /* If all 4 entries were set,don't need read RETA register */
2284                         if (mask != 0xF)
2285                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2286
2287                         for (j = 0; j < 4; j++) {
2288                                 if (mask & (0x1 << j)) {
2289                                         if (mask != 0xF)
2290                                                 reta &= ~(0xFF << 8 * j);
2291                                         reta |= reta_conf->reta[i + j] << 8 * j;
2292                                 }
2293                         }
2294                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2295                 }
2296         }
2297
2298         return 0;
2299 }
2300
2301 static int
2302 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2303                                 struct rte_eth_rss_reta *reta_conf)
2304 {
2305         uint8_t i,j,mask;
2306         uint32_t reta;
2307         struct e1000_hw *hw =
2308                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309
2310         /*
2311          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2312          * 128-entries in 32 registers
2313          */
2314         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2315                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2316                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2317                 else
2318                         mask = (uint8_t)((reta_conf->mask_hi >>
2319                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2320
2321                 if (mask != 0) {
2322                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2323                         for (j = 0; j < 4; j++) {
2324                                 if (mask & (0x1 << j))
2325                                         reta_conf->reta[i + j] =
2326                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2327                         }
2328                 }
2329         }
2330
2331         return 0;
2332 }
2333
2334 #define MAC_TYPE_FILTER_SUP(type)    do {\
2335         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2336                 (type) != e1000_82576)\
2337                 return -ENOSYS;\
2338 } while (0)
2339
2340 /*
2341  * add the syn filter
2342  *
2343  * @param
2344  * dev: Pointer to struct rte_eth_dev.
2345  * filter: ponter to the filter that will be added.
2346  * rx_queue: the queue id the filter assigned to.
2347  *
2348  * @return
2349  *    - On success, zero.
2350  *    - On failure, a negative value.
2351  */
2352 static int
2353 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2354                         struct rte_syn_filter *filter, uint16_t rx_queue)
2355 {
2356         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357         uint32_t synqf, rfctl;
2358
2359         MAC_TYPE_FILTER_SUP(hw->mac.type);
2360
2361         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2362                 return -EINVAL;
2363
2364         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2365         if (synqf & E1000_SYN_FILTER_ENABLE)
2366                 return -EINVAL;
2367
2368         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2369                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2370
2371         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2372         if (filter->hig_pri)
2373                 rfctl |= E1000_RFCTL_SYNQFP;
2374         else
2375                 rfctl &= ~E1000_RFCTL_SYNQFP;
2376
2377         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2378         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2379         return 0;
2380 }
2381
2382 /*
2383  * remove the syn filter
2384  *
2385  * @param
2386  * dev: Pointer to struct rte_eth_dev.
2387  *
2388  * @return
2389  *    - On success, zero.
2390  *    - On failure, a negative value.
2391  */
2392 static int
2393 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2394 {
2395         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396
2397         MAC_TYPE_FILTER_SUP(hw->mac.type);
2398
2399         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2400         return 0;
2401 }
2402
2403 /*
2404  * get the syn filter's info
2405  *
2406  * @param
2407  * dev: Pointer to struct rte_eth_dev.
2408  * filter: ponter to the filter that returns.
2409  * *rx_queue: pointer to the queue id the filter assigned to.
2410  *
2411  * @return
2412  *    - On success, zero.
2413  *    - On failure, a negative value.
2414  */
2415 static int
2416 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2417                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2418 {
2419         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420         uint32_t synqf, rfctl;
2421
2422         MAC_TYPE_FILTER_SUP(hw->mac.type);
2423         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2424         if (synqf & E1000_SYN_FILTER_ENABLE) {
2425                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2426                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2427                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2428                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2429                 return 0;
2430         }
2431         return -ENOENT;
2432 }
2433
2434 /*
2435  * add an ethertype filter
2436  *
2437  * @param
2438  * dev: Pointer to struct rte_eth_dev.
2439  * index: the index the filter allocates.
2440  * filter: ponter to the filter that will be added.
2441  * rx_queue: the queue id the filter assigned to.
2442  *
2443  * @return
2444  *    - On success, zero.
2445  *    - On failure, a negative value.
2446  */
2447 static int
2448 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2449                         struct rte_ethertype_filter *filter, uint16_t rx_queue)
2450 {
2451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452         uint32_t etqf;
2453
2454         MAC_TYPE_FILTER_SUP(hw->mac.type);
2455
2456         if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2457                 return -EINVAL;
2458
2459         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2460         if (etqf & E1000_ETQF_FILTER_ENABLE)
2461                 return -EINVAL;  /* filter index is in use. */
2462         else
2463                 etqf = 0;
2464
2465         etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2466         etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2467         etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2468
2469         if (filter->priority_en) {
2470                 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2471                         " in E1000.", filter->priority);
2472                 return -EINVAL;
2473         }
2474
2475         E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2476         return 0;
2477 }
2478
2479 /*
2480  * remove an ethertype filter
2481  *
2482  * @param
2483  * dev: Pointer to struct rte_eth_dev.
2484  * index: the index the filter allocates.
2485  *
2486  * @return
2487  *    - On success, zero.
2488  *    - On failure, a negative value.
2489  */
2490 static int
2491 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2492 {
2493         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494
2495         MAC_TYPE_FILTER_SUP(hw->mac.type);
2496
2497         if (index >= E1000_MAX_ETQF_FILTERS)
2498                 return -EINVAL;
2499
2500         E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2501         return 0;
2502 }
2503
2504 /*
2505  * get an ethertype filter
2506  *
2507  * @param
2508  * dev: Pointer to struct rte_eth_dev.
2509  * index: the index the filter allocates.
2510  * filter: ponter to the filter that will be gotten.
2511  * *rx_queue: the ponited of the queue id the filter assigned to.
2512  *
2513  * @return
2514  *    - On success, zero.
2515  *    - On failure, a negative value.
2516  */
2517 static int
2518 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2519                         struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2520 {
2521         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522         uint32_t etqf;
2523
2524         MAC_TYPE_FILTER_SUP(hw->mac.type);
2525
2526         if (index >= E1000_MAX_ETQF_FILTERS)
2527                 return -EINVAL;
2528
2529         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2530         if (etqf & E1000_ETQF_FILTER_ENABLE) {
2531                 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2532                 filter->priority_en = 0;
2533                 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2534                 return 0;
2535         }
2536         return -ENOENT;
2537 }
2538
2539 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2540         if ((type) != e1000_82580 && (type) != e1000_i350)\
2541                 return -ENOSYS; \
2542 } while (0)
2543
2544 /*
2545  * add a 2tuple filter
2546  *
2547  * @param
2548  * dev: Pointer to struct rte_eth_dev.
2549  * index: the index the filter allocates.
2550  * filter: ponter to the filter that will be added.
2551  * rx_queue: the queue id the filter assigned to.
2552  *
2553  * @return
2554  *    - On success, zero.
2555  *    - On failure, a negative value.
2556  */
2557 static int
2558 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2559                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2560 {
2561         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562         uint32_t ttqf, imir = 0;
2563         uint32_t imir_ext = 0;
2564
2565         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2566
2567         if (index >= E1000_MAX_TTQF_FILTERS ||
2568                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2569                 filter->priority > E1000_2TUPLE_MAX_PRI)
2570                 return -EINVAL;  /* filter index is out of range. */
2571         if  (filter->tcp_flags > TCP_FLAG_ALL)
2572                 return -EINVAL;  /* flags is invalid. */
2573
2574         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2575         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2576                 return -EINVAL;  /* filter index is in use. */
2577
2578         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2579         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2580                 imir |= E1000_IMIR_PORT_BP;
2581         else
2582                 imir &= ~E1000_IMIR_PORT_BP;
2583
2584         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2585
2586         ttqf = 0;
2587         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2588         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2589         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2590         if (filter->protocol_mask == 1)
2591                 ttqf |= E1000_TTQF_MASK_ENABLE;
2592         else
2593                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2594
2595         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2596         /* tcp flags bits setting. */
2597         if (filter->tcp_flags & TCP_FLAG_ALL) {
2598                 if (filter->tcp_flags & TCP_UGR_FLAG)
2599                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2600                 if (filter->tcp_flags & TCP_ACK_FLAG)
2601                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2602                 if (filter->tcp_flags & TCP_PSH_FLAG)
2603                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2604                 if (filter->tcp_flags & TCP_RST_FLAG)
2605                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2606                 if (filter->tcp_flags & TCP_SYN_FLAG)
2607                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2608                 if (filter->tcp_flags & TCP_FIN_FLAG)
2609                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2610                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2611         } else
2612                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2613         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2614         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2615         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2616         return 0;
2617 }
2618
2619 /*
2620  * remove a 2tuple filter
2621  *
2622  * @param
2623  * dev: Pointer to struct rte_eth_dev.
2624  * index: the index the filter allocates.
2625  *
2626  * @return
2627  *    - On success, zero.
2628  *    - On failure, a negative value.
2629  */
2630 static int
2631 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2632                         uint16_t index)
2633 {
2634         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2635
2636         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2637
2638         if (index >= E1000_MAX_TTQF_FILTERS)
2639                 return -EINVAL;  /* filter index is out of range */
2640
2641         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2642         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2643         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2644         return 0;
2645 }
2646
2647 /*
2648  * get a 2tuple filter
2649  *
2650  * @param
2651  * dev: Pointer to struct rte_eth_dev.
2652  * index: the index the filter allocates.
2653  * filter: ponter to the filter that returns.
2654  * *rx_queue: pointer of the queue id the filter assigned to.
2655  *
2656  * @return
2657  *    - On success, zero.
2658  *    - On failure, a negative value.
2659  */
2660 static int
2661 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2662                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2663 {
2664         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2665         uint32_t imir, ttqf, imir_ext;
2666
2667         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2668
2669         if (index >= E1000_MAX_TTQF_FILTERS)
2670                 return -EINVAL;  /* filter index is out of range. */
2671
2672         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2673         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2674                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2675                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2676                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2677                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2678                                 E1000_TTQF_QUEUE_SHIFT;
2679                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2680                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2681                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2682                         E1000_IMIR_PRIORITY_SHIFT;
2683
2684                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2685                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2686                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2687                                 filter->tcp_flags |= TCP_UGR_FLAG;
2688                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2689                                 filter->tcp_flags |= TCP_ACK_FLAG;
2690                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2691                                 filter->tcp_flags |= TCP_PSH_FLAG;
2692                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2693                                 filter->tcp_flags |= TCP_RST_FLAG;
2694                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2695                                 filter->tcp_flags |= TCP_SYN_FLAG;
2696                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2697                                 filter->tcp_flags |= TCP_FIN_FLAG;
2698                 } else
2699                         filter->tcp_flags = 0;
2700                 return 0;
2701         }
2702         return -ENOENT;
2703 }
2704
2705 /*
2706  * add a flex filter
2707  *
2708  * @param
2709  * dev: Pointer to struct rte_eth_dev.
2710  * index: the index the filter allocates.
2711  * filter: ponter to the filter that will be added.
2712  * rx_queue: the queue id the filter assigned to.
2713  *
2714  * @return
2715  *    - On success, zero.
2716  *     - On failure, a negative value.
2717  */
2718 static int
2719 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2720                         struct rte_flex_filter *filter, uint16_t rx_queue)
2721 {
2722         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2723         uint32_t wufc, en_bits = 0;
2724         uint32_t queueing = 0;
2725         uint32_t reg_off = 0;
2726         uint8_t i, j = 0;
2727
2728         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2729
2730         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2731                 return -EINVAL;  /* filter index is out of range. */
2732
2733         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2734                 filter->len % 8 != 0 ||
2735                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2736                 return -EINVAL;
2737
2738         wufc = E1000_READ_REG(hw, E1000_WUFC);
2739         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2740         if ((wufc & en_bits) == en_bits)
2741                 return -EINVAL;  /* the filter is in use. */
2742
2743         E1000_WRITE_REG(hw, E1000_WUFC,
2744                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2745
2746         j = 0;
2747         if (index < E1000_MAX_FHFT)
2748                 reg_off = E1000_FHFT(index);
2749         else
2750                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2751
2752         for (i = 0; i < 16; i++) {
2753                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2754                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2755                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2756                                 (uint32_t)filter->mask[i]);
2757                 ++j;
2758         }
2759         queueing |= filter->len |
2760                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2761                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2762         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2763         return 0;
2764 }
2765
2766 /*
2767  * remove a flex filter
2768  *
2769  * @param
2770  * dev: Pointer to struct rte_eth_dev.
2771  * index: the index the filter allocates.
2772  *
2773  * @return
2774  *    - On success, zero.
2775  *    - On failure, a negative value.
2776  */
2777 static int
2778 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2779                                 uint16_t index)
2780 {
2781         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         uint32_t wufc, reg_off = 0;
2783         uint8_t i;
2784
2785         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2786
2787         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2788                 return -EINVAL;  /* filter index is out of range. */
2789
2790         wufc = E1000_READ_REG(hw, E1000_WUFC);
2791         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2792
2793         if (index < E1000_MAX_FHFT)
2794                 reg_off = E1000_FHFT(index);
2795         else
2796                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2797
2798         for (i = 0; i < 64; i++)
2799                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2800         return 0;
2801 }
2802
2803 /*
2804  * get a flex filter
2805  *
2806  * @param
2807  * dev: Pointer to struct rte_eth_dev.
2808  * index: the index the filter allocates.
2809  * filter: ponter to the filter that returns.
2810  * *rx_queue: the pointer of the queue id the filter assigned to.
2811  *
2812  * @return
2813  *    - On success, zero.
2814  *    - On failure, a negative value.
2815  */
2816 static int
2817 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2818                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2819 {
2820         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821         uint32_t wufc, queueing, wufc_en = 0;
2822         uint8_t i, j;
2823
2824         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2825
2826         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2827                 return -EINVAL;  /* filter index is out of range. */
2828
2829         wufc = E1000_READ_REG(hw, E1000_WUFC);
2830         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2831
2832         if ((wufc & wufc_en) == wufc_en) {
2833                 uint32_t reg_off = 0;
2834                 j = 0;
2835                 if (index < E1000_MAX_FHFT)
2836                         reg_off = E1000_FHFT(index);
2837                 else
2838                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2839
2840                 for (i = 0; i < 16; i++, j = i * 2) {
2841                         filter->dwords[j] =
2842                                 E1000_READ_REG(hw, reg_off + i*4*4);
2843                         filter->dwords[j+1] =
2844                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2845                         filter->mask[i] =
2846                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2847                 }
2848                 queueing = E1000_READ_REG(hw,
2849                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2850                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2851                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2852                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2853                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2854                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2855                 return 0;
2856         }
2857         return -ENOENT;
2858 }
2859
2860 /*
2861  * add a 5tuple filter
2862  *
2863  * @param
2864  * dev: Pointer to struct rte_eth_dev.
2865  * index: the index the filter allocates.
2866  * filter: ponter to the filter that will be added.
2867  * rx_queue: the queue id the filter assigned to.
2868  *
2869  * @return
2870  *    - On success, zero.
2871  *    - On failure, a negative value.
2872  */
2873 static int
2874 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2875                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2876 {
2877         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878         uint32_t ftqf, spqf = 0;
2879         uint32_t imir = 0;
2880         uint32_t imir_ext = 0;
2881
2882         if (hw->mac.type != e1000_82576)
2883                 return -ENOSYS;
2884
2885         if (index >= E1000_MAX_FTQF_FILTERS ||
2886                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2887                 return -EINVAL;  /* filter index is out of range. */
2888
2889         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2890         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2891                 return -EINVAL;  /* filter index is in use. */
2892
2893         ftqf = 0;
2894         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2895         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2896                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2897         if (filter->dst_ip_mask == 1)
2898                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2899         if (filter->src_port_mask == 1)
2900                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2901         if (filter->protocol_mask == 1)
2902                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2903         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2904         ftqf |= E1000_FTQF_VF_MASK_EN;
2905         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2906         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2907         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2908         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2909
2910         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2911         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2912
2913         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2914         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2915                 imir |= E1000_IMIR_PORT_BP;
2916         else
2917                 imir &= ~E1000_IMIR_PORT_BP;
2918         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2919
2920         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2921         /* tcp flags bits setting. */
2922         if (filter->tcp_flags & TCP_FLAG_ALL) {
2923                 if (filter->tcp_flags & TCP_UGR_FLAG)
2924                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2925                 if (filter->tcp_flags & TCP_ACK_FLAG)
2926                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2927                 if (filter->tcp_flags & TCP_PSH_FLAG)
2928                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2929                 if (filter->tcp_flags & TCP_RST_FLAG)
2930                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2931                 if (filter->tcp_flags & TCP_SYN_FLAG)
2932                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2933                 if (filter->tcp_flags & TCP_FIN_FLAG)
2934                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2935         } else
2936                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2937         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2938         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2939         return 0;
2940 }
2941
2942 /*
2943  * remove a 5tuple filter
2944  *
2945  * @param
2946  * dev: Pointer to struct rte_eth_dev.
2947  * index: the index the filter allocates
2948  *
2949  * @return
2950  *    - On success, zero.
2951  *    - On failure, a negative value.
2952  */
2953 static int
2954 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2955                                 uint16_t index)
2956 {
2957         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958
2959         if (hw->mac.type != e1000_82576)
2960                 return -ENOSYS;
2961
2962         if (index >= E1000_MAX_FTQF_FILTERS)
2963                 return -EINVAL;  /* filter index is out of range. */
2964
2965         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2966         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2967         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2968         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2969         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2970         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2971         return 0;
2972 }
2973
2974 /*
2975  * get a 5tuple filter
2976  *
2977  * @param
2978  * dev: Pointer to struct rte_eth_dev.
2979  * index: the index the filter allocates
2980  * filter: ponter to the filter that returns
2981  * *rx_queue: pointer of the queue id the filter assigned to
2982  *
2983  * @return
2984  *    - On success, zero.
2985  *    - On failure, a negative value.
2986  */
2987 static int
2988 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2989                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2990 {
2991         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992         uint32_t spqf, ftqf, imir, imir_ext;
2993
2994         if (hw->mac.type != e1000_82576)
2995                 return -ENOSYS;
2996
2997         if (index >= E1000_MAX_FTQF_FILTERS)
2998                 return -EINVAL;  /* filter index is out of range. */
2999
3000         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
3001         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
3002                 filter->src_ip_mask =
3003                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3004                 filter->dst_ip_mask =
3005                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3006                 filter->src_port_mask =
3007                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3008                 filter->protocol_mask =
3009                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3010                 filter->protocol =
3011                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
3012                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
3013                                 E1000_FTQF_QUEUE_SHIFT);
3014
3015                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
3016                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
3017
3018                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
3019                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
3020
3021                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
3022                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
3023                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
3024                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
3025                         E1000_IMIR_PRIORITY_SHIFT;
3026
3027                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
3028                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
3029                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
3030                                 filter->tcp_flags |= TCP_UGR_FLAG;
3031                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
3032                                 filter->tcp_flags |= TCP_ACK_FLAG;
3033                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
3034                                 filter->tcp_flags |= TCP_PSH_FLAG;
3035                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
3036                                 filter->tcp_flags |= TCP_RST_FLAG;
3037                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3038                                 filter->tcp_flags |= TCP_SYN_FLAG;
3039                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3040                                 filter->tcp_flags |= TCP_FIN_FLAG;
3041                 } else
3042                         filter->tcp_flags = 0;
3043                 return 0;
3044         }
3045         return -ENOENT;
3046 }
3047
3048 static int
3049 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3050 {
3051         uint32_t rctl;
3052         struct e1000_hw *hw;
3053         struct rte_eth_dev_info dev_info;
3054         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3055                                      VLAN_TAG_SIZE);
3056
3057         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058
3059 #ifdef RTE_LIBRTE_82571_SUPPORT
3060         /* XXX: not bigger than max_rx_pktlen */
3061         if (hw->mac.type == e1000_82571)
3062                 return -ENOTSUP;
3063 #endif
3064         eth_igb_infos_get(dev, &dev_info);
3065
3066         /* check that mtu is within the allowed range */
3067         if ((mtu < ETHER_MIN_MTU) ||
3068             (frame_size > dev_info.max_rx_pktlen))
3069                 return -EINVAL;
3070
3071         /* refuse mtu that requires the support of scattered packets when this
3072          * feature has not been enabled before. */
3073         if (!dev->data->scattered_rx &&
3074             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3075                 return -EINVAL;
3076
3077         rctl = E1000_READ_REG(hw, E1000_RCTL);
3078
3079         /* switch to jumbo mode if needed */
3080         if (frame_size > ETHER_MAX_LEN) {
3081                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3082                 rctl |= E1000_RCTL_LPE;
3083         } else {
3084                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3085                 rctl &= ~E1000_RCTL_LPE;
3086         }
3087         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3088
3089         /* update max frame size */
3090         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3091
3092         E1000_WRITE_REG(hw, E1000_RLPML,
3093                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3094
3095         return 0;
3096 }
3097
3098 static struct rte_driver pmd_igb_drv = {
3099         .type = PMD_PDEV,
3100         .init = rte_igb_pmd_init,
3101 };
3102
3103 static struct rte_driver pmd_igbvf_drv = {
3104         .type = PMD_PDEV,
3105         .init = rte_igbvf_pmd_init,
3106 };
3107
3108 PMD_REGISTER_DRIVER(pmd_igb_drv);
3109 PMD_REGISTER_DRIVER(pmd_igbvf_drv);