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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "e1000/e1000_api.h"
57 #include "e1000_ethdev.h"
59 static int eth_igb_configure(struct rte_eth_dev *dev);
60 static int eth_igb_start(struct rte_eth_dev *dev);
61 static void eth_igb_stop(struct rte_eth_dev *dev);
62 static void eth_igb_close(struct rte_eth_dev *dev);
63 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
64 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
65 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
66 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
67 static int eth_igb_link_update(struct rte_eth_dev *dev,
68 int wait_to_complete);
69 static void eth_igb_stats_get(struct rte_eth_dev *dev,
70 struct rte_eth_stats *rte_stats);
71 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
72 static void eth_igb_infos_get(struct rte_eth_dev *dev,
73 struct rte_eth_dev_info *dev_info);
74 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
75 struct rte_eth_fc_conf *fc_conf);
76 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
77 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
78 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
79 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
81 static int igb_hardware_init(struct e1000_hw *hw);
82 static void igb_hw_control_acquire(struct e1000_hw *hw);
83 static void igb_hw_control_release(struct e1000_hw *hw);
84 static void igb_init_manageability(struct e1000_hw *hw);
85 static void igb_release_manageability(struct e1000_hw *hw);
87 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
88 uint16_t vlan_id, int on);
89 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
90 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
92 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
93 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
94 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
95 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
96 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
97 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
99 static int eth_igb_led_on(struct rte_eth_dev *dev);
100 static int eth_igb_led_off(struct rte_eth_dev *dev);
102 static void igb_intr_disable(struct e1000_hw *hw);
103 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
104 static void eth_igb_rar_set(struct rte_eth_dev *dev,
105 struct ether_addr *mac_addr,
106 uint32_t index, uint32_t pool);
107 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
109 static void igbvf_intr_disable(struct e1000_hw *hw);
110 static int igbvf_dev_configure(struct rte_eth_dev *dev);
111 static int igbvf_dev_start(struct rte_eth_dev *dev);
112 static void igbvf_dev_stop(struct rte_eth_dev *dev);
113 static void igbvf_dev_close(struct rte_eth_dev *dev);
114 static int eth_igbvf_link_update(struct e1000_hw *hw);
115 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
116 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
117 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
118 uint16_t vlan_id, int on);
119 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
120 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
121 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
122 struct rte_eth_rss_reta *reta_conf);
123 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
124 struct rte_eth_rss_reta *reta_conf);
127 * Define VF Stats MACRO for Non "cleared on read" register
129 #define UPDATE_VF_STAT(reg, last, cur) \
131 u32 latest = E1000_READ_REG(hw, reg); \
132 cur += latest - last; \
137 #define IGB_FC_PAUSE_TIME 0x0680
138 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
139 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
141 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
143 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
146 * The set of PCI devices this driver supports
148 static struct rte_pci_id pci_id_igb_map[] = {
150 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
151 #include "rte_pci_dev_ids.h"
157 * The set of PCI devices this driver supports (for 82576&I350 VF)
159 static struct rte_pci_id pci_id_igbvf_map[] = {
161 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
162 #include "rte_pci_dev_ids.h"
167 static struct eth_dev_ops eth_igb_ops = {
168 .dev_configure = eth_igb_configure,
169 .dev_start = eth_igb_start,
170 .dev_stop = eth_igb_stop,
171 .dev_close = eth_igb_close,
172 .promiscuous_enable = eth_igb_promiscuous_enable,
173 .promiscuous_disable = eth_igb_promiscuous_disable,
174 .allmulticast_enable = eth_igb_allmulticast_enable,
175 .allmulticast_disable = eth_igb_allmulticast_disable,
176 .link_update = eth_igb_link_update,
177 .stats_get = eth_igb_stats_get,
178 .stats_reset = eth_igb_stats_reset,
179 .dev_infos_get = eth_igb_infos_get,
180 .vlan_filter_set = eth_igb_vlan_filter_set,
181 .vlan_tpid_set = eth_igb_vlan_tpid_set,
182 .vlan_offload_set = eth_igb_vlan_offload_set,
183 .rx_queue_setup = eth_igb_rx_queue_setup,
184 .rx_queue_release = eth_igb_rx_queue_release,
185 .rx_queue_count = eth_igb_rx_queue_count,
186 .rx_descriptor_done = eth_igb_rx_descriptor_done,
187 .tx_queue_setup = eth_igb_tx_queue_setup,
188 .tx_queue_release = eth_igb_tx_queue_release,
189 .dev_led_on = eth_igb_led_on,
190 .dev_led_off = eth_igb_led_off,
191 .flow_ctrl_set = eth_igb_flow_ctrl_set,
192 .mac_addr_add = eth_igb_rar_set,
193 .mac_addr_remove = eth_igb_rar_clear,
194 .reta_update = eth_igb_rss_reta_update,
195 .reta_query = eth_igb_rss_reta_query,
199 * dev_ops for virtual function, bare necessities for basic vf
200 * operation have been implemented
202 static struct eth_dev_ops igbvf_eth_dev_ops = {
203 .dev_configure = igbvf_dev_configure,
204 .dev_start = igbvf_dev_start,
205 .dev_stop = igbvf_dev_stop,
206 .dev_close = igbvf_dev_close,
207 .link_update = eth_igb_link_update,
208 .stats_get = eth_igbvf_stats_get,
209 .stats_reset = eth_igbvf_stats_reset,
210 .vlan_filter_set = igbvf_vlan_filter_set,
211 .dev_infos_get = eth_igb_infos_get,
212 .rx_queue_setup = eth_igb_rx_queue_setup,
213 .rx_queue_release = eth_igb_rx_queue_release,
214 .tx_queue_setup = eth_igb_tx_queue_setup,
215 .tx_queue_release = eth_igb_tx_queue_release,
219 * Atomically reads the link status information from global
220 * structure rte_eth_dev.
223 * - Pointer to the structure rte_eth_dev to read from.
224 * - Pointer to the buffer to be saved with the link status.
227 * - On success, zero.
228 * - On failure, negative value.
231 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
232 struct rte_eth_link *link)
234 struct rte_eth_link *dst = link;
235 struct rte_eth_link *src = &(dev->data->dev_link);
237 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
238 *(uint64_t *)src) == 0)
245 * Atomically writes the link status information into global
246 * structure rte_eth_dev.
249 * - Pointer to the structure rte_eth_dev to read from.
250 * - Pointer to the buffer to be saved with the link status.
253 * - On success, zero.
254 * - On failure, negative value.
257 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
258 struct rte_eth_link *link)
260 struct rte_eth_link *dst = &(dev->data->dev_link);
261 struct rte_eth_link *src = link;
263 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
264 *(uint64_t *)src) == 0)
271 igb_intr_enable(struct rte_eth_dev *dev)
273 struct e1000_interrupt *intr =
274 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
275 struct e1000_hw *hw =
276 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
278 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
279 E1000_WRITE_FLUSH(hw);
283 igb_intr_disable(struct e1000_hw *hw)
285 E1000_WRITE_REG(hw, E1000_IMC, ~0);
286 E1000_WRITE_FLUSH(hw);
289 static inline int32_t
290 igb_pf_reset_hw(struct e1000_hw *hw)
295 status = e1000_reset_hw(hw);
297 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
298 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
299 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
300 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
301 E1000_WRITE_FLUSH(hw);
307 igb_identify_hardware(struct rte_eth_dev *dev)
309 struct e1000_hw *hw =
310 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
312 hw->vendor_id = dev->pci_dev->id.vendor_id;
313 hw->device_id = dev->pci_dev->id.device_id;
314 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
315 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
317 e1000_set_mac_type(hw);
319 /* need to check if it is a vf device below */
323 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
324 struct rte_eth_dev *eth_dev)
327 struct rte_pci_device *pci_dev;
328 struct e1000_hw *hw =
329 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
330 struct e1000_vfta * shadow_vfta =
331 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
334 pci_dev = eth_dev->pci_dev;
335 eth_dev->dev_ops = ð_igb_ops;
336 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
337 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
339 /* for secondary processes, we don't initialise any further as primary
340 * has already done this work. Only check we don't need a different
342 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
343 if (eth_dev->data->scattered_rx)
344 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
348 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
350 igb_identify_hardware(eth_dev);
351 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
356 e1000_get_bus_info(hw);
359 hw->phy.autoneg_wait_to_complete = 0;
360 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
363 if (hw->phy.media_type == e1000_media_type_copper) {
364 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
365 hw->phy.disable_polarity_correction = 0;
366 hw->phy.ms_type = e1000_ms_hw_default;
370 * Start from a known state, this is important in reading the nvm
375 /* Make sure we have a good EEPROM before we read from it */
376 if (e1000_validate_nvm_checksum(hw) < 0) {
378 * Some PCI-E parts fail the first check due to
379 * the link being in sleep state, call it again,
380 * if it fails a second time its a real issue.
382 if (e1000_validate_nvm_checksum(hw) < 0) {
383 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
389 /* Read the permanent MAC address out of the EEPROM */
390 if (e1000_read_mac_addr(hw) != 0) {
391 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
396 /* Allocate memory for storing MAC addresses */
397 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
398 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
399 if (eth_dev->data->mac_addrs == NULL) {
400 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
401 "store MAC addresses",
402 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
407 /* Copy the permanent MAC address */
408 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
410 /* initialize the vfta */
411 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
413 /* Now initialize the hardware */
414 if (igb_hardware_init(hw) != 0) {
415 PMD_INIT_LOG(ERR, "Hardware initialization failed");
416 rte_free(eth_dev->data->mac_addrs);
417 eth_dev->data->mac_addrs = NULL;
421 hw->mac.get_link_status = 1;
423 /* Indicate SOL/IDER usage */
424 if (e1000_check_reset_block(hw) < 0) {
425 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
429 /* initialize PF if max_vfs not zero */
430 igb_pf_host_init(eth_dev);
432 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
433 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
434 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
435 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
436 E1000_WRITE_FLUSH(hw);
438 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
439 eth_dev->data->port_id, pci_dev->id.vendor_id,
440 pci_dev->id.device_id);
442 rte_intr_callback_register(&(pci_dev->intr_handle),
443 eth_igb_interrupt_handler, (void *)eth_dev);
445 /* enable uio intr after callback register */
446 rte_intr_enable(&(pci_dev->intr_handle));
448 /* enable support intr */
449 igb_intr_enable(eth_dev);
454 igb_hw_control_release(hw);
460 * Virtual Function device init
463 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
464 struct rte_eth_dev *eth_dev)
466 struct rte_pci_device *pci_dev;
467 struct e1000_hw *hw =
468 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
471 PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
473 eth_dev->dev_ops = &igbvf_eth_dev_ops;
474 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
475 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
477 /* for secondary processes, we don't initialise any further as primary
478 * has already done this work. Only check we don't need a different
480 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
481 if (eth_dev->data->scattered_rx)
482 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
486 pci_dev = eth_dev->pci_dev;
488 hw->device_id = pci_dev->id.device_id;
489 hw->vendor_id = pci_dev->id.vendor_id;
490 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
492 /* Initialize the shared code */
493 diag = e1000_setup_init_funcs(hw, TRUE);
495 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
500 /* init_mailbox_params */
501 hw->mbx.ops.init_params(hw);
503 /* Disable the interrupts for VF */
504 igbvf_intr_disable(hw);
506 diag = hw->mac.ops.reset_hw(hw);
508 /* Allocate memory for storing MAC addresses */
509 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
510 hw->mac.rar_entry_count, 0);
511 if (eth_dev->data->mac_addrs == NULL) {
513 "Failed to allocate %d bytes needed to store MAC "
515 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
519 /* Copy the permanent MAC address */
520 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
521 ð_dev->data->mac_addrs[0]);
523 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
525 eth_dev->data->port_id, pci_dev->id.vendor_id,
526 pci_dev->id.device_id,
532 static struct eth_driver rte_igb_pmd = {
534 .name = "rte_igb_pmd",
535 .id_table = pci_id_igb_map,
536 #ifdef RTE_EAL_UNBIND_PORTS
537 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
540 .eth_dev_init = eth_igb_dev_init,
541 .dev_private_size = sizeof(struct e1000_adapter),
545 * virtual function driver struct
547 static struct eth_driver rte_igbvf_pmd = {
549 .name = "rte_igbvf_pmd",
550 .id_table = pci_id_igbvf_map,
551 #ifdef RTE_EAL_UNBIND_PORTS
552 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
555 .eth_dev_init = eth_igbvf_dev_init,
556 .dev_private_size = sizeof(struct e1000_adapter),
560 rte_igb_pmd_init(void)
562 rte_eth_driver_register(&rte_igb_pmd);
567 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
569 struct e1000_hw *hw =
570 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
571 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
572 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
573 rctl |= E1000_RCTL_VFE;
574 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
578 * VF Driver initialization routine.
579 * Invoked one at EAL init time.
580 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
583 rte_igbvf_pmd_init(void)
585 DEBUGFUNC("rte_igbvf_pmd_init");
587 rte_eth_driver_register(&rte_igbvf_pmd);
592 eth_igb_configure(struct rte_eth_dev *dev)
594 struct e1000_interrupt *intr =
595 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
597 PMD_INIT_LOG(DEBUG, ">>");
599 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
601 PMD_INIT_LOG(DEBUG, "<<");
607 eth_igb_start(struct rte_eth_dev *dev)
609 struct e1000_hw *hw =
610 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
614 PMD_INIT_LOG(DEBUG, ">>");
616 /* Power up the phy. Needed to make the link go Up */
617 e1000_power_up_phy(hw);
620 * Packet Buffer Allocation (PBA)
621 * Writing PBA sets the receive portion of the buffer
622 * the remainder is used for the transmit buffer.
624 if (hw->mac.type == e1000_82575) {
627 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
628 E1000_WRITE_REG(hw, E1000_PBA, pba);
631 /* Put the address into the Receive Address Array */
632 e1000_rar_set(hw, hw->mac.addr, 0);
634 /* Initialize the hardware */
635 if (igb_hardware_init(hw)) {
636 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
640 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
642 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
643 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
644 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
645 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
646 E1000_WRITE_FLUSH(hw);
648 /* configure PF module if SRIOV enabled */
649 igb_pf_host_configure(dev);
651 /* Configure for OS presence */
652 igb_init_manageability(hw);
654 eth_igb_tx_init(dev);
656 /* This can fail when allocating mbufs for descriptor rings */
657 ret = eth_igb_rx_init(dev);
659 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
660 igb_dev_clear_queues(dev);
664 e1000_clear_hw_cntrs_base_generic(hw);
667 * VLAN Offload Settings
669 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
670 ETH_VLAN_EXTEND_MASK;
671 eth_igb_vlan_offload_set(dev, mask);
673 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
674 /* Enable VLAN filter since VMDq always use VLAN filter */
675 igb_vmdq_vlan_hw_filter_enable(dev);
679 * Configure the Interrupt Moderation register (EITR) with the maximum
680 * possible value (0xFFFF) to minimize "System Partial Write" issued by
681 * spurious [DMA] memory updates of RX and TX ring descriptors.
683 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
684 * spurious memory updates per second should be expected.
685 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
687 * Because interrupts are not used at all, the MSI-X is not activated
688 * and interrupt moderation is controlled by EITR[0].
690 * Note that having [almost] disabled memory updates of RX and TX ring
691 * descriptors through the Interrupt Moderation mechanism, memory
692 * updates of ring descriptors are now moderated by the configurable
693 * value of Write-Back Threshold registers.
695 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
696 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
699 /* Enable all RX & TX queues in the IVAR registers */
700 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
701 for (i = 0; i < 8; i++)
702 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
704 /* Configure EITR with the maximum possible value (0xFFFF) */
705 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
708 /* Setup link speed and duplex */
709 switch (dev->data->dev_conf.link_speed) {
710 case ETH_LINK_SPEED_AUTONEG:
711 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
712 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
713 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
714 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
715 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
716 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
718 goto error_invalid_config;
720 case ETH_LINK_SPEED_10:
721 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
722 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
723 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
724 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
725 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
726 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
728 goto error_invalid_config;
730 case ETH_LINK_SPEED_100:
731 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
732 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
733 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
734 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
735 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
736 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
738 goto error_invalid_config;
740 case ETH_LINK_SPEED_1000:
741 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
742 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
743 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
745 goto error_invalid_config;
747 case ETH_LINK_SPEED_10000:
749 goto error_invalid_config;
751 e1000_setup_link(hw);
753 /* check if lsc interrupt feature is enabled */
754 if (dev->data->dev_conf.intr_conf.lsc != 0)
755 ret = eth_igb_lsc_interrupt_setup(dev);
757 /* resume enabled intr since hw reset */
758 igb_intr_enable(dev);
760 PMD_INIT_LOG(DEBUG, "<<");
764 error_invalid_config:
765 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
766 dev->data->dev_conf.link_speed,
767 dev->data->dev_conf.link_duplex, dev->data->port_id);
768 igb_dev_clear_queues(dev);
772 /*********************************************************************
774 * This routine disables all traffic on the adapter by issuing a
775 * global reset on the MAC.
777 **********************************************************************/
779 eth_igb_stop(struct rte_eth_dev *dev)
781 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
782 struct rte_eth_link link;
784 igb_intr_disable(hw);
786 E1000_WRITE_REG(hw, E1000_WUC, 0);
788 /* Set bit for Go Link disconnect */
789 if (hw->mac.type >= e1000_82580) {
792 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
793 phpm_reg |= E1000_82580_PM_GO_LINKD;
794 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
797 /* Power down the phy. Needed to make the link go Down */
798 e1000_power_down_phy(hw);
800 igb_dev_clear_queues(dev);
802 /* clear the recorded link status */
803 memset(&link, 0, sizeof(link));
804 rte_igb_dev_atomic_write_link_status(dev, &link);
808 eth_igb_close(struct rte_eth_dev *dev)
810 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
811 struct rte_eth_link link;
814 e1000_phy_hw_reset(hw);
815 igb_release_manageability(hw);
816 igb_hw_control_release(hw);
818 /* Clear bit for Go Link disconnect */
819 if (hw->mac.type >= e1000_82580) {
822 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
823 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
824 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
827 igb_dev_clear_queues(dev);
829 memset(&link, 0, sizeof(link));
830 rte_igb_dev_atomic_write_link_status(dev, &link);
834 igb_get_rx_buffer_size(struct e1000_hw *hw)
836 uint32_t rx_buf_size;
837 if (hw->mac.type == e1000_82576) {
838 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
839 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
840 /* PBS needs to be translated according to a lookup table */
841 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
842 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
843 rx_buf_size = (rx_buf_size << 10);
844 } else if (hw->mac.type == e1000_i210) {
845 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
847 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
853 /*********************************************************************
855 * Initialize the hardware
857 **********************************************************************/
859 igb_hardware_init(struct e1000_hw *hw)
861 uint32_t rx_buf_size;
864 /* Let the firmware know the OS is in control */
865 igb_hw_control_acquire(hw);
868 * These parameters control the automatic generation (Tx) and
869 * response (Rx) to Ethernet PAUSE frames.
870 * - High water mark should allow for at least two standard size (1518)
871 * frames to be received after sending an XOFF.
872 * - Low water mark works best when it is very near the high water mark.
873 * This allows the receiver to restart by sending XON when it has
874 * drained a bit. Here we use an arbitary value of 1500 which will
875 * restart after one full frame is pulled from the buffer. There
876 * could be several smaller frames in the buffer and if so they will
877 * not trigger the XON until their total number reduces the buffer
879 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
881 rx_buf_size = igb_get_rx_buffer_size(hw);
883 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
884 hw->fc.low_water = hw->fc.high_water - 1500;
885 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
888 /* Set Flow control, use the tunable location if sane */
889 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
890 hw->fc.requested_mode = igb_fc_setting;
892 hw->fc.requested_mode = e1000_fc_none;
894 /* Issue a global reset */
896 E1000_WRITE_REG(hw, E1000_WUC, 0);
898 diag = e1000_init_hw(hw);
902 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
903 e1000_get_phy_info(hw);
904 e1000_check_for_link(hw);
909 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
911 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
913 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
914 struct e1000_hw_stats *stats =
915 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
918 if(hw->phy.media_type == e1000_media_type_copper ||
919 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
921 E1000_READ_REG(hw,E1000_SYMERRS);
922 stats->sec += E1000_READ_REG(hw, E1000_SEC);
925 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
926 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
927 stats->scc += E1000_READ_REG(hw, E1000_SCC);
928 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
930 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
931 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
932 stats->colc += E1000_READ_REG(hw, E1000_COLC);
933 stats->dc += E1000_READ_REG(hw, E1000_DC);
934 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
935 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
936 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
938 ** For watchdog management we need to know if we have been
939 ** paused during the last interval, so capture that here.
941 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
942 stats->xoffrxc += pause_frames;
943 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
944 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
945 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
946 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
947 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
948 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
949 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
950 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
951 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
952 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
953 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
954 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
956 /* For the 64-bit byte counters the low dword must be read first. */
957 /* Both registers clear on the read of the high dword */
959 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
960 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
961 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
962 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
964 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
965 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
966 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
967 stats->roc += E1000_READ_REG(hw, E1000_ROC);
968 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
970 stats->tor += E1000_READ_REG(hw, E1000_TORH);
971 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
973 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
974 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
975 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
976 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
977 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
978 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
979 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
980 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
981 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
982 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
984 /* Interrupt Counts */
986 stats->iac += E1000_READ_REG(hw, E1000_IAC);
987 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
988 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
989 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
990 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
991 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
992 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
993 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
994 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
996 /* Host to Card Statistics */
998 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
999 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1000 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1001 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1002 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1003 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1004 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1005 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1006 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1007 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1008 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1009 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1010 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1011 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1013 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1014 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1015 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1016 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1017 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1018 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1020 if (rte_stats == NULL)
1024 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
1025 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
1028 rte_stats->oerrors = stats->ecol + stats->latecol;
1030 rte_stats->ipackets = stats->gprc;
1031 rte_stats->opackets = stats->gptc;
1032 rte_stats->ibytes = stats->gorc;
1033 rte_stats->obytes = stats->gotc;
1037 eth_igb_stats_reset(struct rte_eth_dev *dev)
1039 struct e1000_hw_stats *hw_stats =
1040 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1042 /* HW registers are cleared on read */
1043 eth_igb_stats_get(dev, NULL);
1045 /* Reset software totals */
1046 memset(hw_stats, 0, sizeof(*hw_stats));
1050 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1052 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1053 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1054 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1056 /* Good Rx packets, include VF loopback */
1057 UPDATE_VF_STAT(E1000_VFGPRC,
1058 hw_stats->last_gprc, hw_stats->gprc);
1060 /* Good Rx octets, include VF loopback */
1061 UPDATE_VF_STAT(E1000_VFGORC,
1062 hw_stats->last_gorc, hw_stats->gorc);
1064 /* Good Tx packets, include VF loopback */
1065 UPDATE_VF_STAT(E1000_VFGPTC,
1066 hw_stats->last_gptc, hw_stats->gptc);
1068 /* Good Tx octets, include VF loopback */
1069 UPDATE_VF_STAT(E1000_VFGOTC,
1070 hw_stats->last_gotc, hw_stats->gotc);
1072 /* Rx Multicst packets */
1073 UPDATE_VF_STAT(E1000_VFMPRC,
1074 hw_stats->last_mprc, hw_stats->mprc);
1076 /* Good Rx loopback packets */
1077 UPDATE_VF_STAT(E1000_VFGPRLBC,
1078 hw_stats->last_gprlbc, hw_stats->gprlbc);
1080 /* Good Rx loopback octets */
1081 UPDATE_VF_STAT(E1000_VFGORLBC,
1082 hw_stats->last_gorlbc, hw_stats->gorlbc);
1084 /* Good Tx loopback packets */
1085 UPDATE_VF_STAT(E1000_VFGPTLBC,
1086 hw_stats->last_gptlbc, hw_stats->gptlbc);
1088 /* Good Tx loopback octets */
1089 UPDATE_VF_STAT(E1000_VFGOTLBC,
1090 hw_stats->last_gotlbc, hw_stats->gotlbc);
1092 if (rte_stats == NULL)
1095 memset(rte_stats, 0, sizeof(*rte_stats));
1096 rte_stats->ipackets = hw_stats->gprc;
1097 rte_stats->ibytes = hw_stats->gorc;
1098 rte_stats->opackets = hw_stats->gptc;
1099 rte_stats->obytes = hw_stats->gotc;
1100 rte_stats->imcasts = hw_stats->mprc;
1101 rte_stats->ilbpackets = hw_stats->gprlbc;
1102 rte_stats->ilbbytes = hw_stats->gorlbc;
1103 rte_stats->olbpackets = hw_stats->gptlbc;
1104 rte_stats->olbbytes = hw_stats->gotlbc;
1109 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1111 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1112 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1114 /* Sync HW register to the last stats */
1115 eth_igbvf_stats_get(dev, NULL);
1117 /* reset HW current stats*/
1118 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1119 offsetof(struct e1000_vf_stats, gprc));
1124 eth_igb_infos_get(struct rte_eth_dev *dev,
1125 struct rte_eth_dev_info *dev_info)
1127 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1130 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1131 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1133 switch (hw->mac.type) {
1135 dev_info->max_rx_queues = 4;
1136 dev_info->max_tx_queues = 4;
1137 dev_info->max_vmdq_pools = 0;
1141 dev_info->max_rx_queues = 16;
1142 dev_info->max_tx_queues = 16;
1143 dev_info->max_vmdq_pools = ETH_8_POOLS;
1147 dev_info->max_rx_queues = 8;
1148 dev_info->max_tx_queues = 8;
1149 dev_info->max_vmdq_pools = ETH_8_POOLS;
1153 dev_info->max_rx_queues = 8;
1154 dev_info->max_tx_queues = 8;
1155 dev_info->max_vmdq_pools = ETH_8_POOLS;
1159 dev_info->max_rx_queues = 8;
1160 dev_info->max_tx_queues = 8;
1164 dev_info->max_rx_queues = 4;
1165 dev_info->max_tx_queues = 4;
1166 dev_info->max_vmdq_pools = 0;
1170 dev_info->max_rx_queues = 2;
1171 dev_info->max_tx_queues = 2;
1172 dev_info->max_vmdq_pools = 0;
1175 case e1000_vfadapt_i350:
1176 dev_info->max_rx_queues = 1;
1177 dev_info->max_tx_queues = 1;
1178 dev_info->max_vmdq_pools = 0;
1182 /* Should not happen */
1183 dev_info->max_rx_queues = 0;
1184 dev_info->max_tx_queues = 0;
1185 dev_info->max_vmdq_pools = 0;
1189 /* return 0 means link status changed, -1 means not changed */
1191 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1193 struct e1000_hw *hw =
1194 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1195 struct rte_eth_link link, old;
1196 int link_check, count;
1199 hw->mac.get_link_status = 1;
1201 /* possible wait-to-complete in up to 9 seconds */
1202 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1203 /* Read the real link status */
1204 switch (hw->phy.media_type) {
1205 case e1000_media_type_copper:
1206 /* Do the work to read phy */
1207 e1000_check_for_link(hw);
1208 link_check = !hw->mac.get_link_status;
1211 case e1000_media_type_fiber:
1212 e1000_check_for_link(hw);
1213 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1217 case e1000_media_type_internal_serdes:
1218 e1000_check_for_link(hw);
1219 link_check = hw->mac.serdes_has_link;
1222 /* VF device is type_unknown */
1223 case e1000_media_type_unknown:
1224 eth_igbvf_link_update(hw);
1225 link_check = !hw->mac.get_link_status;
1231 if (link_check || wait_to_complete == 0)
1233 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1235 memset(&link, 0, sizeof(link));
1236 rte_igb_dev_atomic_read_link_status(dev, &link);
1239 /* Now we check if a transition has happened */
1241 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1243 link.link_status = 1;
1244 } else if (!link_check) {
1245 link.link_speed = 0;
1246 link.link_duplex = 0;
1247 link.link_status = 0;
1249 rte_igb_dev_atomic_write_link_status(dev, &link);
1252 if (old.link_status == link.link_status)
1260 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1261 * For ASF and Pass Through versions of f/w this means
1262 * that the driver is loaded.
1265 igb_hw_control_acquire(struct e1000_hw *hw)
1269 /* Let firmware know the driver has taken over */
1270 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1271 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1275 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1276 * For ASF and Pass Through versions of f/w this means that the
1277 * driver is no longer loaded.
1280 igb_hw_control_release(struct e1000_hw *hw)
1284 /* Let firmware taken over control of h/w */
1285 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1286 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1287 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1291 * Bit of a misnomer, what this really means is
1292 * to enable OS management of the system... aka
1293 * to disable special hardware management features.
1296 igb_init_manageability(struct e1000_hw *hw)
1298 if (e1000_enable_mng_pass_thru(hw)) {
1299 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1300 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1302 /* disable hardware interception of ARP */
1303 manc &= ~(E1000_MANC_ARP_EN);
1305 /* enable receiving management packets to the host */
1306 manc |= E1000_MANC_EN_MNG2HOST;
1307 manc2h |= 1 << 5; /* Mng Port 623 */
1308 manc2h |= 1 << 6; /* Mng Port 664 */
1309 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1310 E1000_WRITE_REG(hw, E1000_MANC, manc);
1315 igb_release_manageability(struct e1000_hw *hw)
1317 if (e1000_enable_mng_pass_thru(hw)) {
1318 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1320 manc |= E1000_MANC_ARP_EN;
1321 manc &= ~E1000_MANC_EN_MNG2HOST;
1323 E1000_WRITE_REG(hw, E1000_MANC, manc);
1328 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1330 struct e1000_hw *hw =
1331 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334 rctl = E1000_READ_REG(hw, E1000_RCTL);
1335 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1336 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1340 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1342 struct e1000_hw *hw =
1343 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1346 rctl = E1000_READ_REG(hw, E1000_RCTL);
1347 rctl &= (~E1000_RCTL_UPE);
1348 if (dev->data->all_multicast == 1)
1349 rctl |= E1000_RCTL_MPE;
1351 rctl &= (~E1000_RCTL_MPE);
1352 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1356 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1358 struct e1000_hw *hw =
1359 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362 rctl = E1000_READ_REG(hw, E1000_RCTL);
1363 rctl |= E1000_RCTL_MPE;
1364 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1368 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1370 struct e1000_hw *hw =
1371 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1374 if (dev->data->promiscuous == 1)
1375 return; /* must remain in all_multicast mode */
1376 rctl = E1000_READ_REG(hw, E1000_RCTL);
1377 rctl &= (~E1000_RCTL_MPE);
1378 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1382 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1384 struct e1000_hw *hw =
1385 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386 struct e1000_vfta * shadow_vfta =
1387 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1392 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1393 E1000_VFTA_ENTRY_MASK);
1394 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1395 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1400 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1402 /* update local VFTA copy */
1403 shadow_vfta->vfta[vid_idx] = vfta;
1409 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1411 struct e1000_hw *hw =
1412 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413 uint32_t reg = ETHER_TYPE_VLAN ;
1415 reg |= (tpid << 16);
1416 E1000_WRITE_REG(hw, E1000_VET, reg);
1420 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1422 struct e1000_hw *hw =
1423 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 /* Filter Table Disable */
1427 reg = E1000_READ_REG(hw, E1000_RCTL);
1428 reg &= ~E1000_RCTL_CFIEN;
1429 reg &= ~E1000_RCTL_VFE;
1430 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1434 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1436 struct e1000_hw *hw =
1437 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438 struct e1000_vfta * shadow_vfta =
1439 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1443 /* Filter Table Enable, CFI not used for packet acceptance */
1444 reg = E1000_READ_REG(hw, E1000_RCTL);
1445 reg &= ~E1000_RCTL_CFIEN;
1446 reg |= E1000_RCTL_VFE;
1447 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1449 /* restore VFTA table */
1450 for (i = 0; i < IGB_VFTA_SIZE; i++)
1451 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1455 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1457 struct e1000_hw *hw =
1458 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461 /* VLAN Mode Disable */
1462 reg = E1000_READ_REG(hw, E1000_CTRL);
1463 reg &= ~E1000_CTRL_VME;
1464 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1468 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1470 struct e1000_hw *hw =
1471 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1474 /* VLAN Mode Enable */
1475 reg = E1000_READ_REG(hw, E1000_CTRL);
1476 reg |= E1000_CTRL_VME;
1477 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1481 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1483 struct e1000_hw *hw =
1484 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1487 /* CTRL_EXT: Extended VLAN */
1488 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1489 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1490 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1492 /* Update maximum packet length */
1493 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1494 E1000_WRITE_REG(hw, E1000_RLPML,
1495 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1500 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1502 struct e1000_hw *hw =
1503 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 /* CTRL_EXT: Extended VLAN */
1507 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1508 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1509 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1511 /* Update maximum packet length */
1512 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1513 E1000_WRITE_REG(hw, E1000_RLPML,
1514 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1519 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1521 if(mask & ETH_VLAN_STRIP_MASK){
1522 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1523 igb_vlan_hw_strip_enable(dev);
1525 igb_vlan_hw_strip_disable(dev);
1528 if(mask & ETH_VLAN_FILTER_MASK){
1529 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1530 igb_vlan_hw_filter_enable(dev);
1532 igb_vlan_hw_filter_disable(dev);
1535 if(mask & ETH_VLAN_EXTEND_MASK){
1536 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1537 igb_vlan_hw_extend_enable(dev);
1539 igb_vlan_hw_extend_disable(dev);
1545 * It enables the interrupt mask and then enable the interrupt.
1548 * Pointer to struct rte_eth_dev.
1551 * - On success, zero.
1552 * - On failure, a negative value.
1555 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1557 struct e1000_interrupt *intr =
1558 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1560 intr->mask |= E1000_ICR_LSC;
1566 * It reads ICR and gets interrupt causes, check it and set a bit flag
1567 * to update link status.
1570 * Pointer to struct rte_eth_dev.
1573 * - On success, zero.
1574 * - On failure, a negative value.
1577 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1580 struct e1000_hw *hw =
1581 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582 struct e1000_interrupt *intr =
1583 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1585 igb_intr_disable(hw);
1587 /* read-on-clear nic registers here */
1588 icr = E1000_READ_REG(hw, E1000_ICR);
1591 if (icr & E1000_ICR_LSC) {
1592 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1595 if (icr & E1000_ICR_VMMB)
1596 intr->flags |= E1000_FLAG_MAILBOX;
1602 * It executes link_update after knowing an interrupt is prsent.
1605 * Pointer to struct rte_eth_dev.
1608 * - On success, zero.
1609 * - On failure, a negative value.
1612 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1614 struct e1000_hw *hw =
1615 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616 struct e1000_interrupt *intr =
1617 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1618 uint32_t tctl, rctl;
1619 struct rte_eth_link link;
1622 if (intr->flags & E1000_FLAG_MAILBOX) {
1623 igb_pf_mbx_process(dev);
1624 intr->flags &= ~E1000_FLAG_MAILBOX;
1627 igb_intr_enable(dev);
1628 rte_intr_enable(&(dev->pci_dev->intr_handle));
1630 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1631 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1633 /* set get_link_status to check register later */
1634 hw->mac.get_link_status = 1;
1635 ret = eth_igb_link_update(dev, 0);
1637 /* check if link has changed */
1641 memset(&link, 0, sizeof(link));
1642 rte_igb_dev_atomic_read_link_status(dev, &link);
1643 if (link.link_status) {
1645 " Port %d: Link Up - speed %u Mbps - %s\n",
1646 dev->data->port_id, (unsigned)link.link_speed,
1647 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1648 "full-duplex" : "half-duplex");
1650 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1651 dev->data->port_id);
1653 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1654 dev->pci_dev->addr.domain,
1655 dev->pci_dev->addr.bus,
1656 dev->pci_dev->addr.devid,
1657 dev->pci_dev->addr.function);
1658 tctl = E1000_READ_REG(hw, E1000_TCTL);
1659 rctl = E1000_READ_REG(hw, E1000_RCTL);
1660 if (link.link_status) {
1662 tctl |= E1000_TCTL_EN;
1663 rctl |= E1000_RCTL_EN;
1666 tctl &= ~E1000_TCTL_EN;
1667 rctl &= ~E1000_RCTL_EN;
1669 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1670 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1671 E1000_WRITE_FLUSH(hw);
1672 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1679 * Interrupt handler which shall be registered at first.
1682 * Pointer to interrupt handle.
1684 * The address of parameter (struct rte_eth_dev *) regsitered before.
1690 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1693 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1695 eth_igb_interrupt_get_status(dev);
1696 eth_igb_interrupt_action(dev);
1700 eth_igb_led_on(struct rte_eth_dev *dev)
1702 struct e1000_hw *hw;
1704 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1705 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1709 eth_igb_led_off(struct rte_eth_dev *dev)
1711 struct e1000_hw *hw;
1713 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1714 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1718 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1720 struct e1000_hw *hw;
1722 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1728 uint32_t rx_buf_size;
1729 uint32_t max_high_water;
1732 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1733 rx_buf_size = igb_get_rx_buffer_size(hw);
1734 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1736 /* At least reserve one Ethernet frame for watermark */
1737 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1738 if ((fc_conf->high_water > max_high_water) ||
1739 (fc_conf->high_water < fc_conf->low_water)) {
1740 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1741 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1745 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1746 hw->fc.pause_time = fc_conf->pause_time;
1747 hw->fc.high_water = fc_conf->high_water;
1748 hw->fc.low_water = fc_conf->low_water;
1749 hw->fc.send_xon = fc_conf->send_xon;
1751 err = e1000_setup_link_generic(hw);
1752 if (err == E1000_SUCCESS) {
1754 /* check if we want to forward MAC frames - driver doesn't have native
1755 * capability to do that, so we'll write the registers ourselves */
1757 rctl = E1000_READ_REG(hw, E1000_RCTL);
1759 /* set or clear MFLCN.PMCF bit depending on configuration */
1760 if (fc_conf->mac_ctrl_frame_fwd != 0)
1761 rctl |= E1000_RCTL_PMCF;
1763 rctl &= ~E1000_RCTL_PMCF;
1765 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1766 E1000_WRITE_FLUSH(hw);
1771 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1775 #define E1000_RAH_POOLSEL_SHIFT (18)
1777 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1778 uint32_t index, __rte_unused uint32_t pool)
1780 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1784 rah = E1000_READ_REG(hw, E1000_RAH(index));
1785 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1786 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1790 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1792 uint8_t addr[ETHER_ADDR_LEN];
1793 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795 memset(addr, 0, sizeof(addr));
1797 e1000_rar_set(hw, addr, index);
1801 * Virtual Function operations
1804 igbvf_intr_disable(struct e1000_hw *hw)
1806 PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1808 /* Clear interrupt mask to stop from interrupts being generated */
1809 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1811 E1000_WRITE_FLUSH(hw);
1815 igbvf_stop_adapter(struct rte_eth_dev *dev)
1819 struct rte_eth_dev_info dev_info;
1820 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822 memset(&dev_info, 0, sizeof(dev_info));
1823 eth_igb_infos_get(dev, &dev_info);
1825 /* Clear interrupt mask to stop from interrupts being generated */
1826 igbvf_intr_disable(hw);
1828 /* Clear any pending interrupts, flush previous writes */
1829 E1000_READ_REG(hw, E1000_EICR);
1831 /* Disable the transmit unit. Each queue must be disabled. */
1832 for (i = 0; i < dev_info.max_tx_queues; i++)
1833 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1835 /* Disable the receive unit by stopping each queue */
1836 for (i = 0; i < dev_info.max_rx_queues; i++) {
1837 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1838 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1839 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1840 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1844 /* flush all queues disables */
1845 E1000_WRITE_FLUSH(hw);
1849 static int eth_igbvf_link_update(struct e1000_hw *hw)
1851 struct e1000_mbx_info *mbx = &hw->mbx;
1852 struct e1000_mac_info *mac = &hw->mac;
1853 int ret_val = E1000_SUCCESS;
1855 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1858 * We only want to run this if there has been a rst asserted.
1859 * in this case that could mean a link change, device reset,
1860 * or a virtual function reset
1863 /* If we were hit with a reset or timeout drop the link */
1864 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1865 mac->get_link_status = TRUE;
1867 if (!mac->get_link_status)
1870 /* if link status is down no point in checking to see if pf is up */
1871 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1874 /* if we passed all the tests above then the link is up and we no
1875 * longer need to check for link */
1876 mac->get_link_status = FALSE;
1884 igbvf_dev_configure(struct rte_eth_dev *dev)
1886 struct rte_eth_conf* conf = &dev->data->dev_conf;
1888 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1889 dev->data->port_id);
1892 * VF has no ability to enable/disable HW CRC
1893 * Keep the persistent behavior the same as Host PF
1895 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1896 if (!conf->rxmode.hw_strip_crc) {
1897 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1898 conf->rxmode.hw_strip_crc = 1;
1901 if (conf->rxmode.hw_strip_crc) {
1902 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1903 conf->rxmode.hw_strip_crc = 0;
1911 igbvf_dev_start(struct rte_eth_dev *dev)
1913 struct e1000_hw *hw =
1914 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1919 hw->mac.ops.reset_hw(hw);
1922 igbvf_set_vfta_all(dev,1);
1924 eth_igbvf_tx_init(dev);
1926 /* This can fail when allocating mbufs for descriptor rings */
1927 ret = eth_igbvf_rx_init(dev);
1929 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1930 igb_dev_clear_queues(dev);
1938 igbvf_dev_stop(struct rte_eth_dev *dev)
1940 PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1942 igbvf_stop_adapter(dev);
1945 * Clear what we set, but we still keep shadow_vfta to
1946 * restore after device starts
1948 igbvf_set_vfta_all(dev,0);
1950 igb_dev_clear_queues(dev);
1954 igbvf_dev_close(struct rte_eth_dev *dev)
1956 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958 PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1962 igbvf_dev_stop(dev);
1965 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1967 struct e1000_mbx_info *mbx = &hw->mbx;
1970 /* After set vlan, vlan strip will also be enabled in igb driver*/
1971 msgbuf[0] = E1000_VF_SET_VLAN;
1973 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1975 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1977 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1980 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1982 struct e1000_hw *hw =
1983 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984 struct e1000_vfta * shadow_vfta =
1985 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1986 int i = 0, j = 0, vfta = 0, mask = 1;
1988 for (i = 0; i < IGB_VFTA_SIZE; i++){
1989 vfta = shadow_vfta->vfta[i];
1992 for (j = 0; j < 32; j++){
1995 (uint16_t)((i<<5)+j), on);
2004 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2006 struct e1000_hw *hw =
2007 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008 struct e1000_vfta * shadow_vfta =
2009 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2010 uint32_t vid_idx = 0;
2011 uint32_t vid_bit = 0;
2014 PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2016 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2017 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2019 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2022 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2023 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2025 /*Save what we set and retore it after device reset*/
2027 shadow_vfta->vfta[vid_idx] |= vid_bit;
2029 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2035 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2036 struct rte_eth_rss_reta *reta_conf)
2040 struct e1000_hw *hw =
2041 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2044 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2045 * 128-entries in 32 registers
2047 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2048 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2049 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2051 mask = (uint8_t)((reta_conf->mask_hi >>
2052 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2055 /* If all 4 entries were set,don't need read RETA register */
2057 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2059 for (j = 0; j < 4; j++) {
2060 if (mask & (0x1 << j)) {
2062 reta &= ~(0xFF << 8 * j);
2063 reta |= reta_conf->reta[i + j] << 8 * j;
2066 E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2074 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2075 struct rte_eth_rss_reta *reta_conf)
2079 struct e1000_hw *hw =
2080 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2084 * 128-entries in 32 registers
2086 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2087 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2088 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2090 mask = (uint8_t)((reta_conf->mask_hi >>
2091 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2094 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2095 for (j = 0; j < 4; j++) {
2096 if (mask & (0x1 << j))
2097 reta_conf->reta[i + j] =
2098 (uint8_t)((reta >> 8 * j) & 0xFF);