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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
64 #define IGB_DEFAULT_RX_PTHRESH 8
65 #define IGB_DEFAULT_RX_HTHRESH 8
66 #define IGB_DEFAULT_RX_WTHRESH 0
68 #define IGB_DEFAULT_TX_PTHRESH 32
69 #define IGB_DEFAULT_TX_HTHRESH 0
70 #define IGB_DEFAULT_TX_WTHRESH 0
72 static int eth_igb_configure(struct rte_eth_dev *dev);
73 static int eth_igb_start(struct rte_eth_dev *dev);
74 static void eth_igb_stop(struct rte_eth_dev *dev);
75 static void eth_igb_close(struct rte_eth_dev *dev);
76 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
77 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
78 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
79 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
80 static int eth_igb_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static void eth_igb_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *rte_stats);
84 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
85 static void eth_igb_infos_get(struct rte_eth_dev *dev,
86 struct rte_eth_dev_info *dev_info);
87 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
88 struct rte_eth_fc_conf *fc_conf);
89 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
90 struct rte_eth_fc_conf *fc_conf);
91 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
92 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
93 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
94 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
96 static int igb_hardware_init(struct e1000_hw *hw);
97 static void igb_hw_control_acquire(struct e1000_hw *hw);
98 static void igb_hw_control_release(struct e1000_hw *hw);
99 static void igb_init_manageability(struct e1000_hw *hw);
100 static void igb_release_manageability(struct e1000_hw *hw);
102 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
104 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
105 uint16_t vlan_id, int on);
106 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
107 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
109 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
110 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
111 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
112 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
113 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
114 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
116 static int eth_igb_led_on(struct rte_eth_dev *dev);
117 static int eth_igb_led_off(struct rte_eth_dev *dev);
119 static void igb_intr_disable(struct e1000_hw *hw);
120 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
121 static void eth_igb_rar_set(struct rte_eth_dev *dev,
122 struct ether_addr *mac_addr,
123 uint32_t index, uint32_t pool);
124 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
126 static void igbvf_intr_disable(struct e1000_hw *hw);
127 static int igbvf_dev_configure(struct rte_eth_dev *dev);
128 static int igbvf_dev_start(struct rte_eth_dev *dev);
129 static void igbvf_dev_stop(struct rte_eth_dev *dev);
130 static void igbvf_dev_close(struct rte_eth_dev *dev);
131 static int eth_igbvf_link_update(struct e1000_hw *hw);
132 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
133 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
134 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
135 uint16_t vlan_id, int on);
136 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
137 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
138 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
139 struct rte_eth_rss_reta *reta_conf);
140 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
141 struct rte_eth_rss_reta *reta_conf);
143 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
144 struct rte_syn_filter *filter, uint16_t rx_queue);
145 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
146 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
147 struct rte_syn_filter *filter, uint16_t *rx_queue);
148 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
150 struct rte_ethertype_filter *filter, uint16_t rx_queue);
151 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
153 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
155 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
156 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
158 struct rte_2tuple_filter *filter, uint16_t rx_queue);
159 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
161 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
163 struct rte_2tuple_filter *filter, uint16_t *rx_queue);
164 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
166 struct rte_flex_filter *filter, uint16_t rx_queue);
167 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
169 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
171 struct rte_flex_filter *filter, uint16_t *rx_queue);
172 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
174 struct rte_5tuple_filter *filter, uint16_t rx_queue);
175 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
177 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
179 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
182 * Define VF Stats MACRO for Non "cleared on read" register
184 #define UPDATE_VF_STAT(reg, last, cur) \
186 u32 latest = E1000_READ_REG(hw, reg); \
187 cur += latest - last; \
192 #define IGB_FC_PAUSE_TIME 0x0680
193 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
194 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
196 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
198 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
201 * The set of PCI devices this driver supports
203 static struct rte_pci_id pci_id_igb_map[] = {
205 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
206 #include "rte_pci_dev_ids.h"
212 * The set of PCI devices this driver supports (for 82576&I350 VF)
214 static struct rte_pci_id pci_id_igbvf_map[] = {
216 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
217 #include "rte_pci_dev_ids.h"
222 static struct eth_dev_ops eth_igb_ops = {
223 .dev_configure = eth_igb_configure,
224 .dev_start = eth_igb_start,
225 .dev_stop = eth_igb_stop,
226 .dev_close = eth_igb_close,
227 .promiscuous_enable = eth_igb_promiscuous_enable,
228 .promiscuous_disable = eth_igb_promiscuous_disable,
229 .allmulticast_enable = eth_igb_allmulticast_enable,
230 .allmulticast_disable = eth_igb_allmulticast_disable,
231 .link_update = eth_igb_link_update,
232 .stats_get = eth_igb_stats_get,
233 .stats_reset = eth_igb_stats_reset,
234 .dev_infos_get = eth_igb_infos_get,
235 .mtu_set = eth_igb_mtu_set,
236 .vlan_filter_set = eth_igb_vlan_filter_set,
237 .vlan_tpid_set = eth_igb_vlan_tpid_set,
238 .vlan_offload_set = eth_igb_vlan_offload_set,
239 .rx_queue_setup = eth_igb_rx_queue_setup,
240 .rx_queue_release = eth_igb_rx_queue_release,
241 .rx_queue_count = eth_igb_rx_queue_count,
242 .rx_descriptor_done = eth_igb_rx_descriptor_done,
243 .tx_queue_setup = eth_igb_tx_queue_setup,
244 .tx_queue_release = eth_igb_tx_queue_release,
245 .dev_led_on = eth_igb_led_on,
246 .dev_led_off = eth_igb_led_off,
247 .flow_ctrl_get = eth_igb_flow_ctrl_get,
248 .flow_ctrl_set = eth_igb_flow_ctrl_set,
249 .mac_addr_add = eth_igb_rar_set,
250 .mac_addr_remove = eth_igb_rar_clear,
251 .reta_update = eth_igb_rss_reta_update,
252 .reta_query = eth_igb_rss_reta_query,
253 .rss_hash_update = eth_igb_rss_hash_update,
254 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
255 .add_syn_filter = eth_igb_add_syn_filter,
256 .remove_syn_filter = eth_igb_remove_syn_filter,
257 .get_syn_filter = eth_igb_get_syn_filter,
258 .add_ethertype_filter = eth_igb_add_ethertype_filter,
259 .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
260 .get_ethertype_filter = eth_igb_get_ethertype_filter,
261 .add_2tuple_filter = eth_igb_add_2tuple_filter,
262 .remove_2tuple_filter = eth_igb_remove_2tuple_filter,
263 .get_2tuple_filter = eth_igb_get_2tuple_filter,
264 .add_flex_filter = eth_igb_add_flex_filter,
265 .remove_flex_filter = eth_igb_remove_flex_filter,
266 .get_flex_filter = eth_igb_get_flex_filter,
267 .add_5tuple_filter = eth_igb_add_5tuple_filter,
268 .remove_5tuple_filter = eth_igb_remove_5tuple_filter,
269 .get_5tuple_filter = eth_igb_get_5tuple_filter,
273 * dev_ops for virtual function, bare necessities for basic vf
274 * operation have been implemented
276 static struct eth_dev_ops igbvf_eth_dev_ops = {
277 .dev_configure = igbvf_dev_configure,
278 .dev_start = igbvf_dev_start,
279 .dev_stop = igbvf_dev_stop,
280 .dev_close = igbvf_dev_close,
281 .link_update = eth_igb_link_update,
282 .stats_get = eth_igbvf_stats_get,
283 .stats_reset = eth_igbvf_stats_reset,
284 .vlan_filter_set = igbvf_vlan_filter_set,
285 .dev_infos_get = eth_igb_infos_get,
286 .rx_queue_setup = eth_igb_rx_queue_setup,
287 .rx_queue_release = eth_igb_rx_queue_release,
288 .tx_queue_setup = eth_igb_tx_queue_setup,
289 .tx_queue_release = eth_igb_tx_queue_release,
293 * Atomically reads the link status information from global
294 * structure rte_eth_dev.
297 * - Pointer to the structure rte_eth_dev to read from.
298 * - Pointer to the buffer to be saved with the link status.
301 * - On success, zero.
302 * - On failure, negative value.
305 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
306 struct rte_eth_link *link)
308 struct rte_eth_link *dst = link;
309 struct rte_eth_link *src = &(dev->data->dev_link);
311 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
312 *(uint64_t *)src) == 0)
319 * Atomically writes the link status information into global
320 * structure rte_eth_dev.
323 * - Pointer to the structure rte_eth_dev to read from.
324 * - Pointer to the buffer to be saved with the link status.
327 * - On success, zero.
328 * - On failure, negative value.
331 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
332 struct rte_eth_link *link)
334 struct rte_eth_link *dst = &(dev->data->dev_link);
335 struct rte_eth_link *src = link;
337 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
338 *(uint64_t *)src) == 0)
345 igb_intr_enable(struct rte_eth_dev *dev)
347 struct e1000_interrupt *intr =
348 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
349 struct e1000_hw *hw =
350 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
352 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
353 E1000_WRITE_FLUSH(hw);
357 igb_intr_disable(struct e1000_hw *hw)
359 E1000_WRITE_REG(hw, E1000_IMC, ~0);
360 E1000_WRITE_FLUSH(hw);
363 static inline int32_t
364 igb_pf_reset_hw(struct e1000_hw *hw)
369 status = e1000_reset_hw(hw);
371 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
372 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
373 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
374 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
375 E1000_WRITE_FLUSH(hw);
381 igb_identify_hardware(struct rte_eth_dev *dev)
383 struct e1000_hw *hw =
384 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
386 hw->vendor_id = dev->pci_dev->id.vendor_id;
387 hw->device_id = dev->pci_dev->id.device_id;
388 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
389 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
391 e1000_set_mac_type(hw);
393 /* need to check if it is a vf device below */
397 igb_reset_swfw_lock(struct e1000_hw *hw)
402 * Do mac ops initialization manually here, since we will need
403 * some function pointers set by this call.
405 ret_val = e1000_init_mac_params(hw);
410 * SMBI lock should not fail in this early stage. If this is the case,
411 * it is due to an improper exit of the application.
412 * So force the release of the faulty lock.
414 if (e1000_get_hw_semaphore_generic(hw) < 0) {
415 PMD_DRV_LOG(DEBUG, "SMBI lock released");
417 e1000_put_hw_semaphore_generic(hw);
419 if (hw->mac.ops.acquire_swfw_sync != NULL) {
423 * Phy lock should not fail in this early stage. If this is the case,
424 * it is due to an improper exit of the application.
425 * So force the release of the faulty lock.
427 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
428 if (hw->bus.func > E1000_FUNC_1)
430 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
431 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
434 hw->mac.ops.release_swfw_sync(hw, mask);
437 * This one is more tricky since it is common to all ports; but
438 * swfw_sync retries last long enough (1s) to be almost sure that if
439 * lock can not be taken it is due to an improper lock of the
442 mask = E1000_SWFW_EEP_SM;
443 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
444 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
446 hw->mac.ops.release_swfw_sync(hw, mask);
449 return E1000_SUCCESS;
453 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
454 struct rte_eth_dev *eth_dev)
457 struct rte_pci_device *pci_dev;
458 struct e1000_hw *hw =
459 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
460 struct e1000_vfta * shadow_vfta =
461 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
464 pci_dev = eth_dev->pci_dev;
465 eth_dev->dev_ops = ð_igb_ops;
466 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
467 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
469 /* for secondary processes, we don't initialise any further as primary
470 * has already done this work. Only check we don't need a different
472 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
473 if (eth_dev->data->scattered_rx)
474 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
478 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
480 igb_identify_hardware(eth_dev);
481 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
486 e1000_get_bus_info(hw);
488 /* Reset any pending lock */
489 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
494 /* Finish initialization */
495 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
501 hw->phy.autoneg_wait_to_complete = 0;
502 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
505 if (hw->phy.media_type == e1000_media_type_copper) {
506 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
507 hw->phy.disable_polarity_correction = 0;
508 hw->phy.ms_type = e1000_ms_hw_default;
512 * Start from a known state, this is important in reading the nvm
517 /* Make sure we have a good EEPROM before we read from it */
518 if (e1000_validate_nvm_checksum(hw) < 0) {
520 * Some PCI-E parts fail the first check due to
521 * the link being in sleep state, call it again,
522 * if it fails a second time its a real issue.
524 if (e1000_validate_nvm_checksum(hw) < 0) {
525 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
531 /* Read the permanent MAC address out of the EEPROM */
532 if (e1000_read_mac_addr(hw) != 0) {
533 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
538 /* Allocate memory for storing MAC addresses */
539 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
540 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
541 if (eth_dev->data->mac_addrs == NULL) {
542 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
543 "store MAC addresses",
544 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
549 /* Copy the permanent MAC address */
550 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
552 /* initialize the vfta */
553 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
555 /* Now initialize the hardware */
556 if (igb_hardware_init(hw) != 0) {
557 PMD_INIT_LOG(ERR, "Hardware initialization failed");
558 rte_free(eth_dev->data->mac_addrs);
559 eth_dev->data->mac_addrs = NULL;
563 hw->mac.get_link_status = 1;
565 /* Indicate SOL/IDER usage */
566 if (e1000_check_reset_block(hw) < 0) {
567 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
571 /* initialize PF if max_vfs not zero */
572 igb_pf_host_init(eth_dev);
574 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
575 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
576 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
577 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
578 E1000_WRITE_FLUSH(hw);
580 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
581 eth_dev->data->port_id, pci_dev->id.vendor_id,
582 pci_dev->id.device_id);
584 rte_intr_callback_register(&(pci_dev->intr_handle),
585 eth_igb_interrupt_handler, (void *)eth_dev);
587 /* enable uio intr after callback register */
588 rte_intr_enable(&(pci_dev->intr_handle));
590 /* enable support intr */
591 igb_intr_enable(eth_dev);
596 igb_hw_control_release(hw);
602 * Virtual Function device init
605 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
606 struct rte_eth_dev *eth_dev)
608 struct rte_pci_device *pci_dev;
609 struct e1000_hw *hw =
610 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
613 PMD_INIT_FUNC_TRACE();
615 eth_dev->dev_ops = &igbvf_eth_dev_ops;
616 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
617 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
619 /* for secondary processes, we don't initialise any further as primary
620 * has already done this work. Only check we don't need a different
622 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
623 if (eth_dev->data->scattered_rx)
624 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
628 pci_dev = eth_dev->pci_dev;
630 hw->device_id = pci_dev->id.device_id;
631 hw->vendor_id = pci_dev->id.vendor_id;
632 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
634 /* Initialize the shared code (base driver) */
635 diag = e1000_setup_init_funcs(hw, TRUE);
637 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
642 /* init_mailbox_params */
643 hw->mbx.ops.init_params(hw);
645 /* Disable the interrupts for VF */
646 igbvf_intr_disable(hw);
648 diag = hw->mac.ops.reset_hw(hw);
650 /* Allocate memory for storing MAC addresses */
651 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
652 hw->mac.rar_entry_count, 0);
653 if (eth_dev->data->mac_addrs == NULL) {
655 "Failed to allocate %d bytes needed to store MAC "
657 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
661 /* Copy the permanent MAC address */
662 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
663 ð_dev->data->mac_addrs[0]);
665 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
667 eth_dev->data->port_id, pci_dev->id.vendor_id,
668 pci_dev->id.device_id, "igb_mac_82576_vf");
673 static struct eth_driver rte_igb_pmd = {
675 .name = "rte_igb_pmd",
676 .id_table = pci_id_igb_map,
677 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
679 .eth_dev_init = eth_igb_dev_init,
680 .dev_private_size = sizeof(struct e1000_adapter),
684 * virtual function driver struct
686 static struct eth_driver rte_igbvf_pmd = {
688 .name = "rte_igbvf_pmd",
689 .id_table = pci_id_igbvf_map,
690 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
692 .eth_dev_init = eth_igbvf_dev_init,
693 .dev_private_size = sizeof(struct e1000_adapter),
697 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
699 rte_eth_driver_register(&rte_igb_pmd);
704 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
706 struct e1000_hw *hw =
707 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
708 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
709 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
710 rctl |= E1000_RCTL_VFE;
711 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
715 * VF Driver initialization routine.
716 * Invoked one at EAL init time.
717 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
720 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
722 PMD_INIT_FUNC_TRACE();
724 rte_eth_driver_register(&rte_igbvf_pmd);
729 eth_igb_configure(struct rte_eth_dev *dev)
731 struct e1000_interrupt *intr =
732 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
734 PMD_INIT_FUNC_TRACE();
735 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
736 PMD_INIT_FUNC_TRACE();
742 eth_igb_start(struct rte_eth_dev *dev)
744 struct e1000_hw *hw =
745 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
749 PMD_INIT_FUNC_TRACE();
751 /* Power up the phy. Needed to make the link go Up */
752 e1000_power_up_phy(hw);
755 * Packet Buffer Allocation (PBA)
756 * Writing PBA sets the receive portion of the buffer
757 * the remainder is used for the transmit buffer.
759 if (hw->mac.type == e1000_82575) {
762 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
763 E1000_WRITE_REG(hw, E1000_PBA, pba);
766 /* Put the address into the Receive Address Array */
767 e1000_rar_set(hw, hw->mac.addr, 0);
769 /* Initialize the hardware */
770 if (igb_hardware_init(hw)) {
771 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
775 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
777 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
778 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
779 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
780 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
781 E1000_WRITE_FLUSH(hw);
783 /* configure PF module if SRIOV enabled */
784 igb_pf_host_configure(dev);
786 /* Configure for OS presence */
787 igb_init_manageability(hw);
789 eth_igb_tx_init(dev);
791 /* This can fail when allocating mbufs for descriptor rings */
792 ret = eth_igb_rx_init(dev);
794 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
795 igb_dev_clear_queues(dev);
799 e1000_clear_hw_cntrs_base_generic(hw);
802 * VLAN Offload Settings
804 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
805 ETH_VLAN_EXTEND_MASK;
806 eth_igb_vlan_offload_set(dev, mask);
808 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
809 /* Enable VLAN filter since VMDq always use VLAN filter */
810 igb_vmdq_vlan_hw_filter_enable(dev);
814 * Configure the Interrupt Moderation register (EITR) with the maximum
815 * possible value (0xFFFF) to minimize "System Partial Write" issued by
816 * spurious [DMA] memory updates of RX and TX ring descriptors.
818 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
819 * spurious memory updates per second should be expected.
820 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
822 * Because interrupts are not used at all, the MSI-X is not activated
823 * and interrupt moderation is controlled by EITR[0].
825 * Note that having [almost] disabled memory updates of RX and TX ring
826 * descriptors through the Interrupt Moderation mechanism, memory
827 * updates of ring descriptors are now moderated by the configurable
828 * value of Write-Back Threshold registers.
830 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
831 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
832 (hw->mac.type == e1000_i211)) {
835 /* Enable all RX & TX queues in the IVAR registers */
836 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
837 for (i = 0; i < 8; i++)
838 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
840 /* Configure EITR with the maximum possible value (0xFFFF) */
841 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
844 /* Setup link speed and duplex */
845 switch (dev->data->dev_conf.link_speed) {
846 case ETH_LINK_SPEED_AUTONEG:
847 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
848 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
849 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
850 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
851 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
852 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
854 goto error_invalid_config;
856 case ETH_LINK_SPEED_10:
857 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
858 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
859 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
860 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
861 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
862 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
864 goto error_invalid_config;
866 case ETH_LINK_SPEED_100:
867 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
868 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
869 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
870 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
871 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
872 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
874 goto error_invalid_config;
876 case ETH_LINK_SPEED_1000:
877 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
878 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
879 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
881 goto error_invalid_config;
883 case ETH_LINK_SPEED_10000:
885 goto error_invalid_config;
887 e1000_setup_link(hw);
889 /* check if lsc interrupt feature is enabled */
890 if (dev->data->dev_conf.intr_conf.lsc != 0)
891 ret = eth_igb_lsc_interrupt_setup(dev);
893 /* resume enabled intr since hw reset */
894 igb_intr_enable(dev);
896 PMD_INIT_LOG(DEBUG, "<<");
900 error_invalid_config:
901 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
902 dev->data->dev_conf.link_speed,
903 dev->data->dev_conf.link_duplex, dev->data->port_id);
904 igb_dev_clear_queues(dev);
908 /*********************************************************************
910 * This routine disables all traffic on the adapter by issuing a
911 * global reset on the MAC.
913 **********************************************************************/
915 eth_igb_stop(struct rte_eth_dev *dev)
917 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
918 struct rte_eth_link link;
920 igb_intr_disable(hw);
922 E1000_WRITE_REG(hw, E1000_WUC, 0);
924 /* Set bit for Go Link disconnect */
925 if (hw->mac.type >= e1000_82580) {
928 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
929 phpm_reg |= E1000_82580_PM_GO_LINKD;
930 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
933 /* Power down the phy. Needed to make the link go Down */
934 e1000_power_down_phy(hw);
936 igb_dev_clear_queues(dev);
938 /* clear the recorded link status */
939 memset(&link, 0, sizeof(link));
940 rte_igb_dev_atomic_write_link_status(dev, &link);
944 eth_igb_close(struct rte_eth_dev *dev)
946 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
947 struct rte_eth_link link;
950 e1000_phy_hw_reset(hw);
951 igb_release_manageability(hw);
952 igb_hw_control_release(hw);
954 /* Clear bit for Go Link disconnect */
955 if (hw->mac.type >= e1000_82580) {
958 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
959 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
960 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
963 igb_dev_clear_queues(dev);
965 memset(&link, 0, sizeof(link));
966 rte_igb_dev_atomic_write_link_status(dev, &link);
970 igb_get_rx_buffer_size(struct e1000_hw *hw)
972 uint32_t rx_buf_size;
973 if (hw->mac.type == e1000_82576) {
974 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
975 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
976 /* PBS needs to be translated according to a lookup table */
977 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
978 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
979 rx_buf_size = (rx_buf_size << 10);
980 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
981 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
983 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
989 /*********************************************************************
991 * Initialize the hardware
993 **********************************************************************/
995 igb_hardware_init(struct e1000_hw *hw)
997 uint32_t rx_buf_size;
1000 /* Let the firmware know the OS is in control */
1001 igb_hw_control_acquire(hw);
1004 * These parameters control the automatic generation (Tx) and
1005 * response (Rx) to Ethernet PAUSE frames.
1006 * - High water mark should allow for at least two standard size (1518)
1007 * frames to be received after sending an XOFF.
1008 * - Low water mark works best when it is very near the high water mark.
1009 * This allows the receiver to restart by sending XON when it has
1010 * drained a bit. Here we use an arbitrary value of 1500 which will
1011 * restart after one full frame is pulled from the buffer. There
1012 * could be several smaller frames in the buffer and if so they will
1013 * not trigger the XON until their total number reduces the buffer
1015 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1017 rx_buf_size = igb_get_rx_buffer_size(hw);
1019 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1020 hw->fc.low_water = hw->fc.high_water - 1500;
1021 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1022 hw->fc.send_xon = 1;
1024 /* Set Flow control, use the tunable location if sane */
1025 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1026 hw->fc.requested_mode = igb_fc_setting;
1028 hw->fc.requested_mode = e1000_fc_none;
1030 /* Issue a global reset */
1031 igb_pf_reset_hw(hw);
1032 E1000_WRITE_REG(hw, E1000_WUC, 0);
1034 diag = e1000_init_hw(hw);
1038 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1039 e1000_get_phy_info(hw);
1040 e1000_check_for_link(hw);
1045 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1047 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1049 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050 struct e1000_hw_stats *stats =
1051 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1054 if(hw->phy.media_type == e1000_media_type_copper ||
1055 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1057 E1000_READ_REG(hw,E1000_SYMERRS);
1058 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1061 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1062 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1063 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1064 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1066 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1067 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1068 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1069 stats->dc += E1000_READ_REG(hw, E1000_DC);
1070 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1071 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1072 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1074 ** For watchdog management we need to know if we have been
1075 ** paused during the last interval, so capture that here.
1077 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1078 stats->xoffrxc += pause_frames;
1079 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1080 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1081 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1082 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1083 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1084 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1085 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1086 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1087 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1088 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1089 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1090 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1092 /* For the 64-bit byte counters the low dword must be read first. */
1093 /* Both registers clear on the read of the high dword */
1095 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1096 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1097 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1098 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1100 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1101 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1102 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1103 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1104 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1106 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1107 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1109 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1110 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1111 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1112 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1113 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1114 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1115 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1116 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1117 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1118 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1120 /* Interrupt Counts */
1122 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1123 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1124 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1125 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1126 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1127 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1128 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1129 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1130 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1132 /* Host to Card Statistics */
1134 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1135 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1136 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1137 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1138 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1139 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1140 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1141 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1142 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1143 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1144 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1145 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1146 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1147 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1149 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1150 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1151 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1152 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1153 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1154 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1156 if (rte_stats == NULL)
1160 rte_stats->ibadcrc = stats->crcerrs;
1161 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1162 rte_stats->imissed = stats->mpc;
1163 rte_stats->ierrors = rte_stats->ibadcrc +
1164 rte_stats->ibadlen +
1165 rte_stats->imissed +
1166 stats->rxerrc + stats->algnerrc + stats->cexterr;
1169 rte_stats->oerrors = stats->ecol + stats->latecol;
1171 /* XON/XOFF pause frames */
1172 rte_stats->tx_pause_xon = stats->xontxc;
1173 rte_stats->rx_pause_xon = stats->xonrxc;
1174 rte_stats->tx_pause_xoff = stats->xofftxc;
1175 rte_stats->rx_pause_xoff = stats->xoffrxc;
1177 rte_stats->ipackets = stats->gprc;
1178 rte_stats->opackets = stats->gptc;
1179 rte_stats->ibytes = stats->gorc;
1180 rte_stats->obytes = stats->gotc;
1184 eth_igb_stats_reset(struct rte_eth_dev *dev)
1186 struct e1000_hw_stats *hw_stats =
1187 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1189 /* HW registers are cleared on read */
1190 eth_igb_stats_get(dev, NULL);
1192 /* Reset software totals */
1193 memset(hw_stats, 0, sizeof(*hw_stats));
1197 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1199 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1201 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1203 /* Good Rx packets, include VF loopback */
1204 UPDATE_VF_STAT(E1000_VFGPRC,
1205 hw_stats->last_gprc, hw_stats->gprc);
1207 /* Good Rx octets, include VF loopback */
1208 UPDATE_VF_STAT(E1000_VFGORC,
1209 hw_stats->last_gorc, hw_stats->gorc);
1211 /* Good Tx packets, include VF loopback */
1212 UPDATE_VF_STAT(E1000_VFGPTC,
1213 hw_stats->last_gptc, hw_stats->gptc);
1215 /* Good Tx octets, include VF loopback */
1216 UPDATE_VF_STAT(E1000_VFGOTC,
1217 hw_stats->last_gotc, hw_stats->gotc);
1219 /* Rx Multicst packets */
1220 UPDATE_VF_STAT(E1000_VFMPRC,
1221 hw_stats->last_mprc, hw_stats->mprc);
1223 /* Good Rx loopback packets */
1224 UPDATE_VF_STAT(E1000_VFGPRLBC,
1225 hw_stats->last_gprlbc, hw_stats->gprlbc);
1227 /* Good Rx loopback octets */
1228 UPDATE_VF_STAT(E1000_VFGORLBC,
1229 hw_stats->last_gorlbc, hw_stats->gorlbc);
1231 /* Good Tx loopback packets */
1232 UPDATE_VF_STAT(E1000_VFGPTLBC,
1233 hw_stats->last_gptlbc, hw_stats->gptlbc);
1235 /* Good Tx loopback octets */
1236 UPDATE_VF_STAT(E1000_VFGOTLBC,
1237 hw_stats->last_gotlbc, hw_stats->gotlbc);
1239 if (rte_stats == NULL)
1242 memset(rte_stats, 0, sizeof(*rte_stats));
1243 rte_stats->ipackets = hw_stats->gprc;
1244 rte_stats->ibytes = hw_stats->gorc;
1245 rte_stats->opackets = hw_stats->gptc;
1246 rte_stats->obytes = hw_stats->gotc;
1247 rte_stats->imcasts = hw_stats->mprc;
1248 rte_stats->ilbpackets = hw_stats->gprlbc;
1249 rte_stats->ilbbytes = hw_stats->gorlbc;
1250 rte_stats->olbpackets = hw_stats->gptlbc;
1251 rte_stats->olbbytes = hw_stats->gotlbc;
1256 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1258 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1259 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1261 /* Sync HW register to the last stats */
1262 eth_igbvf_stats_get(dev, NULL);
1264 /* reset HW current stats*/
1265 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1266 offsetof(struct e1000_vf_stats, gprc));
1271 eth_igb_infos_get(struct rte_eth_dev *dev,
1272 struct rte_eth_dev_info *dev_info)
1274 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1277 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1278 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1279 dev_info->rx_offload_capa =
1280 DEV_RX_OFFLOAD_VLAN_STRIP |
1281 DEV_RX_OFFLOAD_IPV4_CKSUM |
1282 DEV_RX_OFFLOAD_UDP_CKSUM |
1283 DEV_RX_OFFLOAD_TCP_CKSUM;
1284 dev_info->tx_offload_capa =
1285 DEV_TX_OFFLOAD_VLAN_INSERT |
1286 DEV_TX_OFFLOAD_IPV4_CKSUM |
1287 DEV_TX_OFFLOAD_UDP_CKSUM |
1288 DEV_TX_OFFLOAD_TCP_CKSUM |
1289 DEV_TX_OFFLOAD_SCTP_CKSUM;
1291 switch (hw->mac.type) {
1293 dev_info->max_rx_queues = 4;
1294 dev_info->max_tx_queues = 4;
1295 dev_info->max_vmdq_pools = 0;
1299 dev_info->max_rx_queues = 16;
1300 dev_info->max_tx_queues = 16;
1301 dev_info->max_vmdq_pools = ETH_8_POOLS;
1302 dev_info->vmdq_queue_num = 16;
1306 dev_info->max_rx_queues = 8;
1307 dev_info->max_tx_queues = 8;
1308 dev_info->max_vmdq_pools = ETH_8_POOLS;
1309 dev_info->vmdq_queue_num = 8;
1313 dev_info->max_rx_queues = 8;
1314 dev_info->max_tx_queues = 8;
1315 dev_info->max_vmdq_pools = ETH_8_POOLS;
1316 dev_info->vmdq_queue_num = 8;
1320 dev_info->max_rx_queues = 8;
1321 dev_info->max_tx_queues = 8;
1325 dev_info->max_rx_queues = 4;
1326 dev_info->max_tx_queues = 4;
1327 dev_info->max_vmdq_pools = 0;
1331 dev_info->max_rx_queues = 2;
1332 dev_info->max_tx_queues = 2;
1333 dev_info->max_vmdq_pools = 0;
1337 dev_info->max_rx_queues = 2;
1338 dev_info->max_tx_queues = 2;
1339 dev_info->max_vmdq_pools = 0;
1342 case e1000_vfadapt_i350:
1343 dev_info->max_rx_queues = 1;
1344 dev_info->max_tx_queues = 1;
1345 dev_info->max_vmdq_pools = 0;
1349 /* Should not happen */
1350 dev_info->max_rx_queues = 0;
1351 dev_info->max_tx_queues = 0;
1352 dev_info->max_vmdq_pools = 0;
1355 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1357 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1358 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1359 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1361 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1365 dev_info->default_txconf = (struct rte_eth_txconf) {
1367 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1368 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1369 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1375 /* return 0 means link status changed, -1 means not changed */
1377 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1379 struct e1000_hw *hw =
1380 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1381 struct rte_eth_link link, old;
1382 int link_check, count;
1385 hw->mac.get_link_status = 1;
1387 /* possible wait-to-complete in up to 9 seconds */
1388 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1389 /* Read the real link status */
1390 switch (hw->phy.media_type) {
1391 case e1000_media_type_copper:
1392 /* Do the work to read phy */
1393 e1000_check_for_link(hw);
1394 link_check = !hw->mac.get_link_status;
1397 case e1000_media_type_fiber:
1398 e1000_check_for_link(hw);
1399 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1403 case e1000_media_type_internal_serdes:
1404 e1000_check_for_link(hw);
1405 link_check = hw->mac.serdes_has_link;
1408 /* VF device is type_unknown */
1409 case e1000_media_type_unknown:
1410 eth_igbvf_link_update(hw);
1411 link_check = !hw->mac.get_link_status;
1417 if (link_check || wait_to_complete == 0)
1419 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1421 memset(&link, 0, sizeof(link));
1422 rte_igb_dev_atomic_read_link_status(dev, &link);
1425 /* Now we check if a transition has happened */
1427 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1429 link.link_status = 1;
1430 } else if (!link_check) {
1431 link.link_speed = 0;
1432 link.link_duplex = 0;
1433 link.link_status = 0;
1435 rte_igb_dev_atomic_write_link_status(dev, &link);
1438 if (old.link_status == link.link_status)
1446 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1447 * For ASF and Pass Through versions of f/w this means
1448 * that the driver is loaded.
1451 igb_hw_control_acquire(struct e1000_hw *hw)
1455 /* Let firmware know the driver has taken over */
1456 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1457 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1461 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1462 * For ASF and Pass Through versions of f/w this means that the
1463 * driver is no longer loaded.
1466 igb_hw_control_release(struct e1000_hw *hw)
1470 /* Let firmware taken over control of h/w */
1471 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1472 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1473 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1477 * Bit of a misnomer, what this really means is
1478 * to enable OS management of the system... aka
1479 * to disable special hardware management features.
1482 igb_init_manageability(struct e1000_hw *hw)
1484 if (e1000_enable_mng_pass_thru(hw)) {
1485 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1486 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1488 /* disable hardware interception of ARP */
1489 manc &= ~(E1000_MANC_ARP_EN);
1491 /* enable receiving management packets to the host */
1492 manc |= E1000_MANC_EN_MNG2HOST;
1493 manc2h |= 1 << 5; /* Mng Port 623 */
1494 manc2h |= 1 << 6; /* Mng Port 664 */
1495 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1496 E1000_WRITE_REG(hw, E1000_MANC, manc);
1501 igb_release_manageability(struct e1000_hw *hw)
1503 if (e1000_enable_mng_pass_thru(hw)) {
1504 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1506 manc |= E1000_MANC_ARP_EN;
1507 manc &= ~E1000_MANC_EN_MNG2HOST;
1509 E1000_WRITE_REG(hw, E1000_MANC, manc);
1514 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1516 struct e1000_hw *hw =
1517 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520 rctl = E1000_READ_REG(hw, E1000_RCTL);
1521 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1522 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1526 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1528 struct e1000_hw *hw =
1529 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532 rctl = E1000_READ_REG(hw, E1000_RCTL);
1533 rctl &= (~E1000_RCTL_UPE);
1534 if (dev->data->all_multicast == 1)
1535 rctl |= E1000_RCTL_MPE;
1537 rctl &= (~E1000_RCTL_MPE);
1538 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1542 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1544 struct e1000_hw *hw =
1545 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1548 rctl = E1000_READ_REG(hw, E1000_RCTL);
1549 rctl |= E1000_RCTL_MPE;
1550 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1554 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1556 struct e1000_hw *hw =
1557 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560 if (dev->data->promiscuous == 1)
1561 return; /* must remain in all_multicast mode */
1562 rctl = E1000_READ_REG(hw, E1000_RCTL);
1563 rctl &= (~E1000_RCTL_MPE);
1564 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1568 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1570 struct e1000_hw *hw =
1571 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1572 struct e1000_vfta * shadow_vfta =
1573 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1578 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1579 E1000_VFTA_ENTRY_MASK);
1580 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1581 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1586 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1588 /* update local VFTA copy */
1589 shadow_vfta->vfta[vid_idx] = vfta;
1595 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1597 struct e1000_hw *hw =
1598 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599 uint32_t reg = ETHER_TYPE_VLAN ;
1601 reg |= (tpid << 16);
1602 E1000_WRITE_REG(hw, E1000_VET, reg);
1606 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1608 struct e1000_hw *hw =
1609 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612 /* Filter Table Disable */
1613 reg = E1000_READ_REG(hw, E1000_RCTL);
1614 reg &= ~E1000_RCTL_CFIEN;
1615 reg &= ~E1000_RCTL_VFE;
1616 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1620 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1622 struct e1000_hw *hw =
1623 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624 struct e1000_vfta * shadow_vfta =
1625 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1629 /* Filter Table Enable, CFI not used for packet acceptance */
1630 reg = E1000_READ_REG(hw, E1000_RCTL);
1631 reg &= ~E1000_RCTL_CFIEN;
1632 reg |= E1000_RCTL_VFE;
1633 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1635 /* restore VFTA table */
1636 for (i = 0; i < IGB_VFTA_SIZE; i++)
1637 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1641 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1643 struct e1000_hw *hw =
1644 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647 /* VLAN Mode Disable */
1648 reg = E1000_READ_REG(hw, E1000_CTRL);
1649 reg &= ~E1000_CTRL_VME;
1650 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1654 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1656 struct e1000_hw *hw =
1657 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660 /* VLAN Mode Enable */
1661 reg = E1000_READ_REG(hw, E1000_CTRL);
1662 reg |= E1000_CTRL_VME;
1663 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1667 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1669 struct e1000_hw *hw =
1670 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673 /* CTRL_EXT: Extended VLAN */
1674 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1675 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1676 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1678 /* Update maximum packet length */
1679 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1680 E1000_WRITE_REG(hw, E1000_RLPML,
1681 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1686 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1688 struct e1000_hw *hw =
1689 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692 /* CTRL_EXT: Extended VLAN */
1693 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1694 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1695 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1697 /* Update maximum packet length */
1698 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1699 E1000_WRITE_REG(hw, E1000_RLPML,
1700 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1705 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1707 if(mask & ETH_VLAN_STRIP_MASK){
1708 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1709 igb_vlan_hw_strip_enable(dev);
1711 igb_vlan_hw_strip_disable(dev);
1714 if(mask & ETH_VLAN_FILTER_MASK){
1715 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1716 igb_vlan_hw_filter_enable(dev);
1718 igb_vlan_hw_filter_disable(dev);
1721 if(mask & ETH_VLAN_EXTEND_MASK){
1722 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1723 igb_vlan_hw_extend_enable(dev);
1725 igb_vlan_hw_extend_disable(dev);
1731 * It enables the interrupt mask and then enable the interrupt.
1734 * Pointer to struct rte_eth_dev.
1737 * - On success, zero.
1738 * - On failure, a negative value.
1741 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1743 struct e1000_interrupt *intr =
1744 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1746 intr->mask |= E1000_ICR_LSC;
1752 * It reads ICR and gets interrupt causes, check it and set a bit flag
1753 * to update link status.
1756 * Pointer to struct rte_eth_dev.
1759 * - On success, zero.
1760 * - On failure, a negative value.
1763 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1766 struct e1000_hw *hw =
1767 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768 struct e1000_interrupt *intr =
1769 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1771 igb_intr_disable(hw);
1773 /* read-on-clear nic registers here */
1774 icr = E1000_READ_REG(hw, E1000_ICR);
1777 if (icr & E1000_ICR_LSC) {
1778 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1781 if (icr & E1000_ICR_VMMB)
1782 intr->flags |= E1000_FLAG_MAILBOX;
1788 * It executes link_update after knowing an interrupt is prsent.
1791 * Pointer to struct rte_eth_dev.
1794 * - On success, zero.
1795 * - On failure, a negative value.
1798 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1800 struct e1000_hw *hw =
1801 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802 struct e1000_interrupt *intr =
1803 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1804 uint32_t tctl, rctl;
1805 struct rte_eth_link link;
1808 if (intr->flags & E1000_FLAG_MAILBOX) {
1809 igb_pf_mbx_process(dev);
1810 intr->flags &= ~E1000_FLAG_MAILBOX;
1813 igb_intr_enable(dev);
1814 rte_intr_enable(&(dev->pci_dev->intr_handle));
1816 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1817 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1819 /* set get_link_status to check register later */
1820 hw->mac.get_link_status = 1;
1821 ret = eth_igb_link_update(dev, 0);
1823 /* check if link has changed */
1827 memset(&link, 0, sizeof(link));
1828 rte_igb_dev_atomic_read_link_status(dev, &link);
1829 if (link.link_status) {
1831 " Port %d: Link Up - speed %u Mbps - %s",
1833 (unsigned)link.link_speed,
1834 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1835 "full-duplex" : "half-duplex");
1837 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1838 dev->data->port_id);
1840 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1841 dev->pci_dev->addr.domain,
1842 dev->pci_dev->addr.bus,
1843 dev->pci_dev->addr.devid,
1844 dev->pci_dev->addr.function);
1845 tctl = E1000_READ_REG(hw, E1000_TCTL);
1846 rctl = E1000_READ_REG(hw, E1000_RCTL);
1847 if (link.link_status) {
1849 tctl |= E1000_TCTL_EN;
1850 rctl |= E1000_RCTL_EN;
1853 tctl &= ~E1000_TCTL_EN;
1854 rctl &= ~E1000_RCTL_EN;
1856 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1857 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1858 E1000_WRITE_FLUSH(hw);
1859 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1866 * Interrupt handler which shall be registered at first.
1869 * Pointer to interrupt handle.
1871 * The address of parameter (struct rte_eth_dev *) regsitered before.
1877 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1880 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1882 eth_igb_interrupt_get_status(dev);
1883 eth_igb_interrupt_action(dev);
1887 eth_igb_led_on(struct rte_eth_dev *dev)
1889 struct e1000_hw *hw;
1891 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1896 eth_igb_led_off(struct rte_eth_dev *dev)
1898 struct e1000_hw *hw;
1900 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1905 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1907 struct e1000_hw *hw;
1912 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 fc_conf->pause_time = hw->fc.pause_time;
1914 fc_conf->high_water = hw->fc.high_water;
1915 fc_conf->low_water = hw->fc.low_water;
1916 fc_conf->send_xon = hw->fc.send_xon;
1917 fc_conf->autoneg = hw->mac.autoneg;
1920 * Return rx_pause and tx_pause status according to actual setting of
1921 * the TFCE and RFCE bits in the CTRL register.
1923 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1924 if (ctrl & E1000_CTRL_TFCE)
1929 if (ctrl & E1000_CTRL_RFCE)
1934 if (rx_pause && tx_pause)
1935 fc_conf->mode = RTE_FC_FULL;
1937 fc_conf->mode = RTE_FC_RX_PAUSE;
1939 fc_conf->mode = RTE_FC_TX_PAUSE;
1941 fc_conf->mode = RTE_FC_NONE;
1947 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1949 struct e1000_hw *hw;
1951 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1957 uint32_t rx_buf_size;
1958 uint32_t max_high_water;
1961 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962 if (fc_conf->autoneg != hw->mac.autoneg)
1964 rx_buf_size = igb_get_rx_buffer_size(hw);
1965 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1967 /* At least reserve one Ethernet frame for watermark */
1968 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1969 if ((fc_conf->high_water > max_high_water) ||
1970 (fc_conf->high_water < fc_conf->low_water)) {
1971 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1972 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1976 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1977 hw->fc.pause_time = fc_conf->pause_time;
1978 hw->fc.high_water = fc_conf->high_water;
1979 hw->fc.low_water = fc_conf->low_water;
1980 hw->fc.send_xon = fc_conf->send_xon;
1982 err = e1000_setup_link_generic(hw);
1983 if (err == E1000_SUCCESS) {
1985 /* check if we want to forward MAC frames - driver doesn't have native
1986 * capability to do that, so we'll write the registers ourselves */
1988 rctl = E1000_READ_REG(hw, E1000_RCTL);
1990 /* set or clear MFLCN.PMCF bit depending on configuration */
1991 if (fc_conf->mac_ctrl_frame_fwd != 0)
1992 rctl |= E1000_RCTL_PMCF;
1994 rctl &= ~E1000_RCTL_PMCF;
1996 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1997 E1000_WRITE_FLUSH(hw);
2002 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2006 #define E1000_RAH_POOLSEL_SHIFT (18)
2008 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2009 uint32_t index, __rte_unused uint32_t pool)
2011 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2015 rah = E1000_READ_REG(hw, E1000_RAH(index));
2016 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2017 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2021 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2023 uint8_t addr[ETHER_ADDR_LEN];
2024 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026 memset(addr, 0, sizeof(addr));
2028 e1000_rar_set(hw, addr, index);
2032 * Virtual Function operations
2035 igbvf_intr_disable(struct e1000_hw *hw)
2037 PMD_INIT_FUNC_TRACE();
2039 /* Clear interrupt mask to stop from interrupts being generated */
2040 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2042 E1000_WRITE_FLUSH(hw);
2046 igbvf_stop_adapter(struct rte_eth_dev *dev)
2050 struct rte_eth_dev_info dev_info;
2051 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 memset(&dev_info, 0, sizeof(dev_info));
2054 eth_igb_infos_get(dev, &dev_info);
2056 /* Clear interrupt mask to stop from interrupts being generated */
2057 igbvf_intr_disable(hw);
2059 /* Clear any pending interrupts, flush previous writes */
2060 E1000_READ_REG(hw, E1000_EICR);
2062 /* Disable the transmit unit. Each queue must be disabled. */
2063 for (i = 0; i < dev_info.max_tx_queues; i++)
2064 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2066 /* Disable the receive unit by stopping each queue */
2067 for (i = 0; i < dev_info.max_rx_queues; i++) {
2068 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2069 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2070 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2071 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2075 /* flush all queues disables */
2076 E1000_WRITE_FLUSH(hw);
2080 static int eth_igbvf_link_update(struct e1000_hw *hw)
2082 struct e1000_mbx_info *mbx = &hw->mbx;
2083 struct e1000_mac_info *mac = &hw->mac;
2084 int ret_val = E1000_SUCCESS;
2086 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2089 * We only want to run this if there has been a rst asserted.
2090 * in this case that could mean a link change, device reset,
2091 * or a virtual function reset
2094 /* If we were hit with a reset or timeout drop the link */
2095 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2096 mac->get_link_status = TRUE;
2098 if (!mac->get_link_status)
2101 /* if link status is down no point in checking to see if pf is up */
2102 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2105 /* if we passed all the tests above then the link is up and we no
2106 * longer need to check for link */
2107 mac->get_link_status = FALSE;
2115 igbvf_dev_configure(struct rte_eth_dev *dev)
2117 struct rte_eth_conf* conf = &dev->data->dev_conf;
2119 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2120 dev->data->port_id);
2123 * VF has no ability to enable/disable HW CRC
2124 * Keep the persistent behavior the same as Host PF
2126 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2127 if (!conf->rxmode.hw_strip_crc) {
2128 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2129 conf->rxmode.hw_strip_crc = 1;
2132 if (conf->rxmode.hw_strip_crc) {
2133 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2134 conf->rxmode.hw_strip_crc = 0;
2142 igbvf_dev_start(struct rte_eth_dev *dev)
2144 struct e1000_hw *hw =
2145 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148 PMD_INIT_FUNC_TRACE();
2150 hw->mac.ops.reset_hw(hw);
2153 igbvf_set_vfta_all(dev,1);
2155 eth_igbvf_tx_init(dev);
2157 /* This can fail when allocating mbufs for descriptor rings */
2158 ret = eth_igbvf_rx_init(dev);
2160 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2161 igb_dev_clear_queues(dev);
2169 igbvf_dev_stop(struct rte_eth_dev *dev)
2171 PMD_INIT_FUNC_TRACE();
2173 igbvf_stop_adapter(dev);
2176 * Clear what we set, but we still keep shadow_vfta to
2177 * restore after device starts
2179 igbvf_set_vfta_all(dev,0);
2181 igb_dev_clear_queues(dev);
2185 igbvf_dev_close(struct rte_eth_dev *dev)
2187 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189 PMD_INIT_FUNC_TRACE();
2193 igbvf_dev_stop(dev);
2196 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2198 struct e1000_mbx_info *mbx = &hw->mbx;
2201 /* After set vlan, vlan strip will also be enabled in igb driver*/
2202 msgbuf[0] = E1000_VF_SET_VLAN;
2204 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2206 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2208 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2211 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2213 struct e1000_hw *hw =
2214 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2215 struct e1000_vfta * shadow_vfta =
2216 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2217 int i = 0, j = 0, vfta = 0, mask = 1;
2219 for (i = 0; i < IGB_VFTA_SIZE; i++){
2220 vfta = shadow_vfta->vfta[i];
2223 for (j = 0; j < 32; j++){
2226 (uint16_t)((i<<5)+j), on);
2235 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2237 struct e1000_hw *hw =
2238 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct e1000_vfta * shadow_vfta =
2240 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2241 uint32_t vid_idx = 0;
2242 uint32_t vid_bit = 0;
2245 PMD_INIT_FUNC_TRACE();
2247 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2248 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2250 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2253 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2254 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2256 /*Save what we set and retore it after device reset*/
2258 shadow_vfta->vfta[vid_idx] |= vid_bit;
2260 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2266 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2267 struct rte_eth_rss_reta *reta_conf)
2271 struct e1000_hw *hw =
2272 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2276 * 128-entries in 32 registers
2278 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2279 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2280 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2282 mask = (uint8_t)((reta_conf->mask_hi >>
2283 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2286 /* If all 4 entries were set,don't need read RETA register */
2288 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2290 for (j = 0; j < 4; j++) {
2291 if (mask & (0x1 << j)) {
2293 reta &= ~(0xFF << 8 * j);
2294 reta |= reta_conf->reta[i + j] << 8 * j;
2297 E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2305 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2306 struct rte_eth_rss_reta *reta_conf)
2310 struct e1000_hw *hw =
2311 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2315 * 128-entries in 32 registers
2317 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2318 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2319 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2321 mask = (uint8_t)((reta_conf->mask_hi >>
2322 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2325 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2326 for (j = 0; j < 4; j++) {
2327 if (mask & (0x1 << j))
2328 reta_conf->reta[i + j] =
2329 (uint8_t)((reta >> 8 * j) & 0xFF);
2337 #define MAC_TYPE_FILTER_SUP(type) do {\
2338 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2339 (type) != e1000_82576)\
2344 * add the syn filter
2347 * dev: Pointer to struct rte_eth_dev.
2348 * filter: ponter to the filter that will be added.
2349 * rx_queue: the queue id the filter assigned to.
2352 * - On success, zero.
2353 * - On failure, a negative value.
2356 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2357 struct rte_syn_filter *filter, uint16_t rx_queue)
2359 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360 uint32_t synqf, rfctl;
2362 MAC_TYPE_FILTER_SUP(hw->mac.type);
2364 if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2367 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2368 if (synqf & E1000_SYN_FILTER_ENABLE)
2371 synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2372 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2374 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2375 if (filter->hig_pri)
2376 rfctl |= E1000_RFCTL_SYNQFP;
2378 rfctl &= ~E1000_RFCTL_SYNQFP;
2380 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2381 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2386 * remove the syn filter
2389 * dev: Pointer to struct rte_eth_dev.
2392 * - On success, zero.
2393 * - On failure, a negative value.
2396 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2398 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400 MAC_TYPE_FILTER_SUP(hw->mac.type);
2402 E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2407 * get the syn filter's info
2410 * dev: Pointer to struct rte_eth_dev.
2411 * filter: ponter to the filter that returns.
2412 * *rx_queue: pointer to the queue id the filter assigned to.
2415 * - On success, zero.
2416 * - On failure, a negative value.
2419 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2420 struct rte_syn_filter *filter, uint16_t *rx_queue)
2422 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423 uint32_t synqf, rfctl;
2425 MAC_TYPE_FILTER_SUP(hw->mac.type);
2426 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2427 if (synqf & E1000_SYN_FILTER_ENABLE) {
2428 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2429 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2430 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2431 E1000_SYN_FILTER_QUEUE_SHIFT);
2438 * add an ethertype filter
2441 * dev: Pointer to struct rte_eth_dev.
2442 * index: the index the filter allocates.
2443 * filter: ponter to the filter that will be added.
2444 * rx_queue: the queue id the filter assigned to.
2447 * - On success, zero.
2448 * - On failure, a negative value.
2451 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2452 struct rte_ethertype_filter *filter, uint16_t rx_queue)
2454 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457 MAC_TYPE_FILTER_SUP(hw->mac.type);
2459 if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2462 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2463 if (etqf & E1000_ETQF_FILTER_ENABLE)
2464 return -EINVAL; /* filter index is in use. */
2468 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2469 etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2470 etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2472 if (filter->priority_en) {
2473 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2474 " in E1000.", filter->priority);
2478 E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2483 * remove an ethertype filter
2486 * dev: Pointer to struct rte_eth_dev.
2487 * index: the index the filter allocates.
2490 * - On success, zero.
2491 * - On failure, a negative value.
2494 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2496 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498 MAC_TYPE_FILTER_SUP(hw->mac.type);
2500 if (index >= E1000_MAX_ETQF_FILTERS)
2503 E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2508 * get an ethertype filter
2511 * dev: Pointer to struct rte_eth_dev.
2512 * index: the index the filter allocates.
2513 * filter: ponter to the filter that will be gotten.
2514 * *rx_queue: the ponited of the queue id the filter assigned to.
2517 * - On success, zero.
2518 * - On failure, a negative value.
2521 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2522 struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2524 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 MAC_TYPE_FILTER_SUP(hw->mac.type);
2529 if (index >= E1000_MAX_ETQF_FILTERS)
2532 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2533 if (etqf & E1000_ETQF_FILTER_ENABLE) {
2534 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2535 filter->priority_en = 0;
2536 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2542 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2543 if ((type) != e1000_82580 && (type) != e1000_i350)\
2548 * add a 2tuple filter
2551 * dev: Pointer to struct rte_eth_dev.
2552 * index: the index the filter allocates.
2553 * filter: ponter to the filter that will be added.
2554 * rx_queue: the queue id the filter assigned to.
2557 * - On success, zero.
2558 * - On failure, a negative value.
2561 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2562 struct rte_2tuple_filter *filter, uint16_t rx_queue)
2564 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565 uint32_t ttqf, imir = 0;
2566 uint32_t imir_ext = 0;
2568 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2570 if (index >= E1000_MAX_TTQF_FILTERS ||
2571 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2572 filter->priority > E1000_2TUPLE_MAX_PRI)
2573 return -EINVAL; /* filter index is out of range. */
2574 if (filter->tcp_flags > TCP_FLAG_ALL)
2575 return -EINVAL; /* flags is invalid. */
2577 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2578 if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2579 return -EINVAL; /* filter index is in use. */
2581 imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2582 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2583 imir |= E1000_IMIR_PORT_BP;
2585 imir &= ~E1000_IMIR_PORT_BP;
2587 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2590 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2591 ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2592 ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2593 if (filter->protocol_mask == 1)
2594 ttqf |= E1000_TTQF_MASK_ENABLE;
2596 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2598 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2599 /* tcp flags bits setting. */
2600 if (filter->tcp_flags & TCP_FLAG_ALL) {
2601 if (filter->tcp_flags & TCP_UGR_FLAG)
2602 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2603 if (filter->tcp_flags & TCP_ACK_FLAG)
2604 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2605 if (filter->tcp_flags & TCP_PSH_FLAG)
2606 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2607 if (filter->tcp_flags & TCP_RST_FLAG)
2608 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2609 if (filter->tcp_flags & TCP_SYN_FLAG)
2610 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2611 if (filter->tcp_flags & TCP_FIN_FLAG)
2612 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2613 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2615 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2616 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2617 E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2618 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2623 * remove a 2tuple filter
2626 * dev: Pointer to struct rte_eth_dev.
2627 * index: the index the filter allocates.
2630 * - On success, zero.
2631 * - On failure, a negative value.
2634 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2637 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2641 if (index >= E1000_MAX_TTQF_FILTERS)
2642 return -EINVAL; /* filter index is out of range */
2644 E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2645 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2646 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2651 * get a 2tuple filter
2654 * dev: Pointer to struct rte_eth_dev.
2655 * index: the index the filter allocates.
2656 * filter: ponter to the filter that returns.
2657 * *rx_queue: pointer of the queue id the filter assigned to.
2660 * - On success, zero.
2661 * - On failure, a negative value.
2664 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2665 struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2667 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668 uint32_t imir, ttqf, imir_ext;
2670 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2672 if (index >= E1000_MAX_TTQF_FILTERS)
2673 return -EINVAL; /* filter index is out of range. */
2675 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2676 if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2677 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2678 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2679 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2680 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2681 E1000_TTQF_QUEUE_SHIFT;
2682 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2683 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2684 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2685 E1000_IMIR_PRIORITY_SHIFT;
2687 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2688 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2689 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2690 filter->tcp_flags |= TCP_UGR_FLAG;
2691 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2692 filter->tcp_flags |= TCP_ACK_FLAG;
2693 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2694 filter->tcp_flags |= TCP_PSH_FLAG;
2695 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2696 filter->tcp_flags |= TCP_RST_FLAG;
2697 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2698 filter->tcp_flags |= TCP_SYN_FLAG;
2699 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2700 filter->tcp_flags |= TCP_FIN_FLAG;
2702 filter->tcp_flags = 0;
2712 * dev: Pointer to struct rte_eth_dev.
2713 * index: the index the filter allocates.
2714 * filter: ponter to the filter that will be added.
2715 * rx_queue: the queue id the filter assigned to.
2718 * - On success, zero.
2719 * - On failure, a negative value.
2722 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2723 struct rte_flex_filter *filter, uint16_t rx_queue)
2725 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2726 uint32_t wufc, en_bits = 0;
2727 uint32_t queueing = 0;
2728 uint32_t reg_off = 0;
2731 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2733 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2734 return -EINVAL; /* filter index is out of range. */
2736 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2737 filter->len % 8 != 0 ||
2738 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2741 wufc = E1000_READ_REG(hw, E1000_WUFC);
2742 en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2743 if ((wufc & en_bits) == en_bits)
2744 return -EINVAL; /* the filter is in use. */
2746 E1000_WRITE_REG(hw, E1000_WUFC,
2747 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2750 if (index < E1000_MAX_FHFT)
2751 reg_off = E1000_FHFT(index);
2753 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2755 for (i = 0; i < 16; i++) {
2756 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2757 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2758 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2759 (uint32_t)filter->mask[i]);
2762 queueing |= filter->len |
2763 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2764 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2765 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2770 * remove a flex filter
2773 * dev: Pointer to struct rte_eth_dev.
2774 * index: the index the filter allocates.
2777 * - On success, zero.
2778 * - On failure, a negative value.
2781 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2784 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785 uint32_t wufc, reg_off = 0;
2788 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2790 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2791 return -EINVAL; /* filter index is out of range. */
2793 wufc = E1000_READ_REG(hw, E1000_WUFC);
2794 E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2796 if (index < E1000_MAX_FHFT)
2797 reg_off = E1000_FHFT(index);
2799 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2801 for (i = 0; i < 64; i++)
2802 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2810 * dev: Pointer to struct rte_eth_dev.
2811 * index: the index the filter allocates.
2812 * filter: ponter to the filter that returns.
2813 * *rx_queue: the pointer of the queue id the filter assigned to.
2816 * - On success, zero.
2817 * - On failure, a negative value.
2820 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2821 struct rte_flex_filter *filter, uint16_t *rx_queue)
2823 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824 uint32_t wufc, queueing, wufc_en = 0;
2827 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2829 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2830 return -EINVAL; /* filter index is out of range. */
2832 wufc = E1000_READ_REG(hw, E1000_WUFC);
2833 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2835 if ((wufc & wufc_en) == wufc_en) {
2836 uint32_t reg_off = 0;
2838 if (index < E1000_MAX_FHFT)
2839 reg_off = E1000_FHFT(index);
2841 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2843 for (i = 0; i < 16; i++, j = i * 2) {
2845 E1000_READ_REG(hw, reg_off + i*4*4);
2846 filter->dwords[j+1] =
2847 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2849 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2851 queueing = E1000_READ_REG(hw,
2852 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2853 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2854 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2855 E1000_FHFT_QUEUEING_PRIO_SHIFT;
2856 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2857 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2864 * add a 5tuple filter
2867 * dev: Pointer to struct rte_eth_dev.
2868 * index: the index the filter allocates.
2869 * filter: ponter to the filter that will be added.
2870 * rx_queue: the queue id the filter assigned to.
2873 * - On success, zero.
2874 * - On failure, a negative value.
2877 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2878 struct rte_5tuple_filter *filter, uint16_t rx_queue)
2880 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881 uint32_t ftqf, spqf = 0;
2883 uint32_t imir_ext = 0;
2885 if (hw->mac.type != e1000_82576)
2888 if (index >= E1000_MAX_FTQF_FILTERS ||
2889 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2890 return -EINVAL; /* filter index is out of range. */
2892 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2893 if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2894 return -EINVAL; /* filter index is in use. */
2897 ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2898 if (filter->src_ip_mask == 1) /* 1b means not compare. */
2899 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2900 if (filter->dst_ip_mask == 1)
2901 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2902 if (filter->src_port_mask == 1)
2903 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2904 if (filter->protocol_mask == 1)
2905 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2906 ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2907 ftqf |= E1000_FTQF_VF_MASK_EN;
2908 ftqf |= E1000_FTQF_QUEUE_ENABLE;
2909 E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2910 E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2911 E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2913 spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2914 E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2916 imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2917 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2918 imir |= E1000_IMIR_PORT_BP;
2920 imir &= ~E1000_IMIR_PORT_BP;
2921 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2923 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2924 /* tcp flags bits setting. */
2925 if (filter->tcp_flags & TCP_FLAG_ALL) {
2926 if (filter->tcp_flags & TCP_UGR_FLAG)
2927 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2928 if (filter->tcp_flags & TCP_ACK_FLAG)
2929 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2930 if (filter->tcp_flags & TCP_PSH_FLAG)
2931 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2932 if (filter->tcp_flags & TCP_RST_FLAG)
2933 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2934 if (filter->tcp_flags & TCP_SYN_FLAG)
2935 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2936 if (filter->tcp_flags & TCP_FIN_FLAG)
2937 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2939 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2940 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2941 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2946 * remove a 5tuple filter
2949 * dev: Pointer to struct rte_eth_dev.
2950 * index: the index the filter allocates
2953 * - On success, zero.
2954 * - On failure, a negative value.
2957 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2960 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962 if (hw->mac.type != e1000_82576)
2965 if (index >= E1000_MAX_FTQF_FILTERS)
2966 return -EINVAL; /* filter index is out of range. */
2968 E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2969 E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2970 E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2971 E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2972 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2973 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2978 * get a 5tuple filter
2981 * dev: Pointer to struct rte_eth_dev.
2982 * index: the index the filter allocates
2983 * filter: ponter to the filter that returns
2984 * *rx_queue: pointer of the queue id the filter assigned to
2987 * - On success, zero.
2988 * - On failure, a negative value.
2991 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2992 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2994 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995 uint32_t spqf, ftqf, imir, imir_ext;
2997 if (hw->mac.type != e1000_82576)
3000 if (index >= E1000_MAX_FTQF_FILTERS)
3001 return -EINVAL; /* filter index is out of range. */
3003 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
3004 if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
3005 filter->src_ip_mask =
3006 (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3007 filter->dst_ip_mask =
3008 (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3009 filter->src_port_mask =
3010 (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3011 filter->protocol_mask =
3012 (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3014 (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
3015 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
3016 E1000_FTQF_QUEUE_SHIFT);
3018 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
3019 filter->src_port = spqf & E1000_SPQF_SRCPORT;
3021 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
3022 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
3024 imir = E1000_READ_REG(hw, E1000_IMIR(index));
3025 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
3026 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
3027 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
3028 E1000_IMIR_PRIORITY_SHIFT;
3030 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
3031 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
3032 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
3033 filter->tcp_flags |= TCP_UGR_FLAG;
3034 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
3035 filter->tcp_flags |= TCP_ACK_FLAG;
3036 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
3037 filter->tcp_flags |= TCP_PSH_FLAG;
3038 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
3039 filter->tcp_flags |= TCP_RST_FLAG;
3040 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3041 filter->tcp_flags |= TCP_SYN_FLAG;
3042 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3043 filter->tcp_flags |= TCP_FIN_FLAG;
3045 filter->tcp_flags = 0;
3052 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3055 struct e1000_hw *hw;
3056 struct rte_eth_dev_info dev_info;
3057 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3060 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3062 #ifdef RTE_LIBRTE_82571_SUPPORT
3063 /* XXX: not bigger than max_rx_pktlen */
3064 if (hw->mac.type == e1000_82571)
3067 eth_igb_infos_get(dev, &dev_info);
3069 /* check that mtu is within the allowed range */
3070 if ((mtu < ETHER_MIN_MTU) ||
3071 (frame_size > dev_info.max_rx_pktlen))
3074 /* refuse mtu that requires the support of scattered packets when this
3075 * feature has not been enabled before. */
3076 if (!dev->data->scattered_rx &&
3077 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3080 rctl = E1000_READ_REG(hw, E1000_RCTL);
3082 /* switch to jumbo mode if needed */
3083 if (frame_size > ETHER_MAX_LEN) {
3084 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3085 rctl |= E1000_RCTL_LPE;
3087 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3088 rctl &= ~E1000_RCTL_LPE;
3090 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3092 /* update max frame size */
3093 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3095 E1000_WRITE_REG(hw, E1000_RLPML,
3096 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3101 static struct rte_driver pmd_igb_drv = {
3103 .init = rte_igb_pmd_init,
3106 static struct rte_driver pmd_igbvf_drv = {
3108 .init = rte_igbvf_pmd_init,
3111 PMD_REGISTER_DRIVER(pmd_igb_drv);
3112 PMD_REGISTER_DRIVER(pmd_igbvf_drv);