lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 /* Bit shift and mask */
  73 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  74 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  75 #define IGB_8_BIT_WIDTH  CHAR_BIT
  76 #define IGB_8_BIT_MASK   UINT8_MAX
  77
  78 static int  eth_igb_configure(struct rte_eth_dev *dev);
  79 static int  eth_igb_start(struct rte_eth_dev *dev);
  80 static void eth_igb_stop(struct rte_eth_dev *dev);
  81 static void eth_igb_close(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  91 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_dev_info *dev_info);
  93 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
  94                                 struct rte_eth_dev_info *dev_info);
  95 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  96                                 struct rte_eth_fc_conf *fc_conf);
  97 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  98                                 struct rte_eth_fc_conf *fc_conf);
  99 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 100 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 101 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 102 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 103                                                         void *param);
 104 static int  igb_hardware_init(struct e1000_hw *hw);
 105 static void igb_hw_control_acquire(struct e1000_hw *hw);
 106 static void igb_hw_control_release(struct e1000_hw *hw);
 107 static void igb_init_manageability(struct e1000_hw *hw);
 108 static void igb_release_manageability(struct e1000_hw *hw);
 109
 110 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 111
 112 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 113                 uint16_t vlan_id, int on);
 114 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 115 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 116
 117 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 118 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 119 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 120 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 121 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 122 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 123
 124 static int eth_igb_led_on(struct rte_eth_dev *dev);
 125 static int eth_igb_led_off(struct rte_eth_dev *dev);
 126
 127 static void igb_intr_disable(struct e1000_hw *hw);
 128 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 129 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 130                 struct ether_addr *mac_addr,
 131                 uint32_t index, uint32_t pool);
 132 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 133
 134 static void igbvf_intr_disable(struct e1000_hw *hw);
 135 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 136 static int igbvf_dev_start(struct rte_eth_dev *dev);
 137 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 138 static void igbvf_dev_close(struct rte_eth_dev *dev);
 139 static int eth_igbvf_link_update(struct e1000_hw *hw);
 140 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 141 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 142 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 143                 uint16_t vlan_id, int on);
 144 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 145 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 146 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 147                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 148                                    uint16_t reta_size);
 149 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 150                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                   uint16_t reta_size);
 152
 153 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 154                         struct rte_eth_syn_filter *filter,
 155                         bool add);
 156 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 157                         struct rte_eth_syn_filter *filter);
 158 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 159                         enum rte_filter_op filter_op,
 160                         void *arg);
 161 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 162                         uint16_t index,
 163                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 164 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 165                         uint16_t index);
 166 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 167                         uint16_t index,
 168                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 169 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 170                         struct rte_eth_flex_filter *filter,
 171                         bool add);
 172 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 173                         struct rte_eth_flex_filter *filter);
 174 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 175                         enum rte_filter_op filter_op,
 176                         void *arg);
 177 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 178                         uint16_t index,
 179                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 180 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 181                         uint16_t index);
 182 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 183                         uint16_t index,
 184                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 185 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 186                         struct rte_eth_ethertype_filter *filter,
 187                         bool add);
 188 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 189                                 enum rte_filter_op filter_op,
 190                                 void *arg);
 191 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ethertype_filter *filter);
 193 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 194                      enum rte_filter_type filter_type,
 195                      enum rte_filter_op filter_op,
 196                      void *arg);
 197
 198 /*
 199  * Define VF Stats MACRO for Non "cleared on read" register
 200  */
 201 #define UPDATE_VF_STAT(reg, last, cur)            \
 202 {                                                 \
 203         u32 latest = E1000_READ_REG(hw, reg);     \
 204         cur += latest - last;                     \
 205         last = latest;                            \
 206 }
 207
 208
 209 #define IGB_FC_PAUSE_TIME 0x0680
 210 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 211 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 212
 213 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 214
 215 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 216
 217 /*
 218  * The set of PCI devices this driver supports
 219  */
 220 static struct rte_pci_id pci_id_igb_map[] = {
 221
 222 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 223 #include "rte_pci_dev_ids.h"
 224
 225 {.device_id = 0},
 226 };
 227
 228 /*
 229  * The set of PCI devices this driver supports (for 82576&I350 VF)
 230  */
 231 static struct rte_pci_id pci_id_igbvf_map[] = {
 232
 233 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 234 #include "rte_pci_dev_ids.h"
 235
 236 {.device_id = 0},
 237 };
 238
 239 static struct eth_dev_ops eth_igb_ops = {
 240         .dev_configure        = eth_igb_configure,
 241         .dev_start            = eth_igb_start,
 242         .dev_stop             = eth_igb_stop,
 243         .dev_close            = eth_igb_close,
 244         .promiscuous_enable   = eth_igb_promiscuous_enable,
 245         .promiscuous_disable  = eth_igb_promiscuous_disable,
 246         .allmulticast_enable  = eth_igb_allmulticast_enable,
 247         .allmulticast_disable = eth_igb_allmulticast_disable,
 248         .link_update          = eth_igb_link_update,
 249         .stats_get            = eth_igb_stats_get,
 250         .stats_reset          = eth_igb_stats_reset,
 251         .dev_infos_get        = eth_igb_infos_get,
 252         .mtu_set              = eth_igb_mtu_set,
 253         .vlan_filter_set      = eth_igb_vlan_filter_set,
 254         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 255         .vlan_offload_set     = eth_igb_vlan_offload_set,
 256         .rx_queue_setup       = eth_igb_rx_queue_setup,
 257         .rx_queue_release     = eth_igb_rx_queue_release,
 258         .rx_queue_count       = eth_igb_rx_queue_count,
 259         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 260         .tx_queue_setup       = eth_igb_tx_queue_setup,
 261         .tx_queue_release     = eth_igb_tx_queue_release,
 262         .dev_led_on           = eth_igb_led_on,
 263         .dev_led_off          = eth_igb_led_off,
 264         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 265         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 266         .mac_addr_add         = eth_igb_rar_set,
 267         .mac_addr_remove      = eth_igb_rar_clear,
 268         .reta_update          = eth_igb_rss_reta_update,
 269         .reta_query           = eth_igb_rss_reta_query,
 270         .rss_hash_update      = eth_igb_rss_hash_update,
 271         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 272         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 273         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 274         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 275         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 276         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 277         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 278         .filter_ctrl             = eth_igb_filter_ctrl,
 279 };
 280
 281 /*
 282  * dev_ops for virtual function, bare necessities for basic vf
 283  * operation have been implemented
 284  */
 285 static struct eth_dev_ops igbvf_eth_dev_ops = {
 286         .dev_configure        = igbvf_dev_configure,
 287         .dev_start            = igbvf_dev_start,
 288         .dev_stop             = igbvf_dev_stop,
 289         .dev_close            = igbvf_dev_close,
 290         .link_update          = eth_igb_link_update,
 291         .stats_get            = eth_igbvf_stats_get,
 292         .stats_reset          = eth_igbvf_stats_reset,
 293         .vlan_filter_set      = igbvf_vlan_filter_set,
 294         .dev_infos_get        = eth_igbvf_infos_get,
 295         .rx_queue_setup       = eth_igb_rx_queue_setup,
 296         .rx_queue_release     = eth_igb_rx_queue_release,
 297         .tx_queue_setup       = eth_igb_tx_queue_setup,
 298         .tx_queue_release     = eth_igb_tx_queue_release,
 299 };
 300
 301 /**
 302  * Atomically reads the link status information from global
 303  * structure rte_eth_dev.
 304  *
 305  * @param dev
 306  *   - Pointer to the structure rte_eth_dev to read from.
 307  *   - Pointer to the buffer to be saved with the link status.
 308  *
 309  * @return
 310  *   - On success, zero.
 311  *   - On failure, negative value.
 312  */
 313 static inline int
 314 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 315                                 struct rte_eth_link *link)
 316 {
 317         struct rte_eth_link *dst = link;
 318         struct rte_eth_link *src = &(dev->data->dev_link);
 319
 320         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 321                                         *(uint64_t *)src) == 0)
 322                 return -1;
 323
 324         return 0;
 325 }
 326
 327 /**
 328  * Atomically writes the link status information into global
 329  * structure rte_eth_dev.
 330  *
 331  * @param dev
 332  *   - Pointer to the structure rte_eth_dev to read from.
 333  *   - Pointer to the buffer to be saved with the link status.
 334  *
 335  * @return
 336  *   - On success, zero.
 337  *   - On failure, negative value.
 338  */
 339 static inline int
 340 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 341                                 struct rte_eth_link *link)
 342 {
 343         struct rte_eth_link *dst = &(dev->data->dev_link);
 344         struct rte_eth_link *src = link;
 345
 346         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 347                                         *(uint64_t *)src) == 0)
 348                 return -1;
 349
 350         return 0;
 351 }
 352
 353 static inline void
 354 igb_intr_enable(struct rte_eth_dev *dev)
 355 {
 356         struct e1000_interrupt *intr =
 357                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 358         struct e1000_hw *hw =
 359                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 360
 361         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 362         E1000_WRITE_FLUSH(hw);
 363 }
 364
 365 static void
 366 igb_intr_disable(struct e1000_hw *hw)
 367 {
 368         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 369         E1000_WRITE_FLUSH(hw);
 370 }
 371
 372 static inline int32_t
 373 igb_pf_reset_hw(struct e1000_hw *hw)
 374 {
 375         uint32_t ctrl_ext;
 376         int32_t status;
 377
 378         status = e1000_reset_hw(hw);
 379
 380         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 381         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 382         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 383         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 384         E1000_WRITE_FLUSH(hw);
 385
 386         return status;
 387 }
 388
 389 static void
 390 igb_identify_hardware(struct rte_eth_dev *dev)
 391 {
 392         struct e1000_hw *hw =
 393                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 394
 395         hw->vendor_id = dev->pci_dev->id.vendor_id;
 396         hw->device_id = dev->pci_dev->id.device_id;
 397         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 398         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 399
 400         e1000_set_mac_type(hw);
 401
 402         /* need to check if it is a vf device below */
 403 }
 404
 405 static int
 406 igb_reset_swfw_lock(struct e1000_hw *hw)
 407 {
 408         int ret_val;
 409
 410         /*
 411          * Do mac ops initialization manually here, since we will need
 412          * some function pointers set by this call.
 413          */
 414         ret_val = e1000_init_mac_params(hw);
 415         if (ret_val)
 416                 return ret_val;
 417
 418         /*
 419          * SMBI lock should not fail in this early stage. If this is the case,
 420          * it is due to an improper exit of the application.
 421          * So force the release of the faulty lock.
 422          */
 423         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 424                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 425         }
 426         e1000_put_hw_semaphore_generic(hw);
 427
 428         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 429                 uint16_t mask;
 430
 431                 /*
 432                  * Phy lock should not fail in this early stage. If this is the case,
 433                  * it is due to an improper exit of the application.
 434                  * So force the release of the faulty lock.
 435                  */
 436                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 437                 if (hw->bus.func > E1000_FUNC_1)
 438                         mask <<= 2;
 439                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 440                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 441                                     hw->bus.func);
 442                 }
 443                 hw->mac.ops.release_swfw_sync(hw, mask);
 444
 445                 /*
 446                  * This one is more tricky since it is common to all ports; but
 447                  * swfw_sync retries last long enough (1s) to be almost sure that if
 448                  * lock can not be taken it is due to an improper lock of the
 449                  * semaphore.
 450                  */
 451                 mask = E1000_SWFW_EEP_SM;
 452                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 453                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 454                 }
 455                 hw->mac.ops.release_swfw_sync(hw, mask);
 456         }
 457
 458         return E1000_SUCCESS;
 459 }
 460
 461 static int
 462 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 463                    struct rte_eth_dev *eth_dev)
 464 {
 465         int error = 0;
 466         struct rte_pci_device *pci_dev;
 467         struct e1000_hw *hw =
 468                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 469         struct e1000_vfta * shadow_vfta =
 470                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 471         struct e1000_filter_info *filter_info =
 472                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 473         uint32_t ctrl_ext;
 474
 475         pci_dev = eth_dev->pci_dev;
 476         eth_dev->dev_ops = &eth_igb_ops;
 477         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 478         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 479
 480         /* for secondary processes, we don't initialise any further as primary
 481          * has already done this work. Only check we don't need a different
 482          * RX function */
 483         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 484                 if (eth_dev->data->scattered_rx)
 485                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 486                 return 0;
 487         }
 488
 489         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 490
 491         igb_identify_hardware(eth_dev);
 492         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 493                 error = -EIO;
 494                 goto err_late;
 495         }
 496
 497         e1000_get_bus_info(hw);
 498
 499         /* Reset any pending lock */
 500         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 501                 error = -EIO;
 502                 goto err_late;
 503         }
 504
 505         /* Finish initialization */
 506         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 507                 error = -EIO;
 508                 goto err_late;
 509         }
 510
 511         hw->mac.autoneg = 1;
 512         hw->phy.autoneg_wait_to_complete = 0;
 513         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 514
 515         /* Copper options */
 516         if (hw->phy.media_type == e1000_media_type_copper) {
 517                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 518                 hw->phy.disable_polarity_correction = 0;
 519                 hw->phy.ms_type = e1000_ms_hw_default;
 520         }
 521
 522         /*
 523          * Start from a known state, this is important in reading the nvm
 524          * and mac from that.
 525          */
 526         igb_pf_reset_hw(hw);
 527
 528         /* Make sure we have a good EEPROM before we read from it */
 529         if (e1000_validate_nvm_checksum(hw) < 0) {
 530                 /*
 531                  * Some PCI-E parts fail the first check due to
 532                  * the link being in sleep state, call it again,
 533                  * if it fails a second time its a real issue.
 534                  */
 535                 if (e1000_validate_nvm_checksum(hw) < 0) {
 536                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 537                         error = -EIO;
 538                         goto err_late;
 539                 }
 540         }
 541
 542         /* Read the permanent MAC address out of the EEPROM */
 543         if (e1000_read_mac_addr(hw) != 0) {
 544                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 545                 error = -EIO;
 546                 goto err_late;
 547         }
 548
 549         /* Allocate memory for storing MAC addresses */
 550         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 551                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 552         if (eth_dev->data->mac_addrs == NULL) {
 553                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 554                                                 "store MAC addresses",
 555                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 556                 error = -ENOMEM;
 557                 goto err_late;
 558         }
 559
 560         /* Copy the permanent MAC address */
 561         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 562
 563         /* initialize the vfta */
 564         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 565
 566         /* Now initialize the hardware */
 567         if (igb_hardware_init(hw) != 0) {
 568                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 569                 rte_free(eth_dev->data->mac_addrs);
 570                 eth_dev->data->mac_addrs = NULL;
 571                 error = -ENODEV;
 572                 goto err_late;
 573         }
 574         hw->mac.get_link_status = 1;
 575
 576         /* Indicate SOL/IDER usage */
 577         if (e1000_check_reset_block(hw) < 0) {
 578                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 579                                         "SOL/IDER session");
 580         }
 581
 582         /* initialize PF if max_vfs not zero */
 583         igb_pf_host_init(eth_dev);
 584
 585         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 586         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 587         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 588         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 589         E1000_WRITE_FLUSH(hw);
 590
 591         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 592                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 593                      pci_dev->id.device_id);
 594
 595         rte_intr_callback_register(&(pci_dev->intr_handle),
 596                 eth_igb_interrupt_handler, (void *)eth_dev);
 597
 598         /* enable uio intr after callback register */
 599         rte_intr_enable(&(pci_dev->intr_handle));
 600
 601         /* enable support intr */
 602         igb_intr_enable(eth_dev);
 603
 604         TAILQ_INIT(&filter_info->flex_list);
 605         filter_info->flex_mask = 0;
 606
 607         return 0;
 608
 609 err_late:
 610         igb_hw_control_release(hw);
 611
 612         return (error);
 613 }
 614
 615 /*
 616  * Virtual Function device init
 617  */
 618 static int
 619 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 620                 struct rte_eth_dev *eth_dev)
 621 {
 622         struct rte_pci_device *pci_dev;
 623         struct e1000_hw *hw =
 624                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 625         int diag;
 626
 627         PMD_INIT_FUNC_TRACE();
 628
 629         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 630         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 631         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 632
 633         /* for secondary processes, we don't initialise any further as primary
 634          * has already done this work. Only check we don't need a different
 635          * RX function */
 636         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 637                 if (eth_dev->data->scattered_rx)
 638                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 639                 return 0;
 640         }
 641
 642         pci_dev = eth_dev->pci_dev;
 643
 644         hw->device_id = pci_dev->id.device_id;
 645         hw->vendor_id = pci_dev->id.vendor_id;
 646         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 647
 648         /* Initialize the shared code (base driver) */
 649         diag = e1000_setup_init_funcs(hw, TRUE);
 650         if (diag != 0) {
 651                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 652                         diag);
 653                 return -EIO;
 654         }
 655
 656         /* init_mailbox_params */
 657         hw->mbx.ops.init_params(hw);
 658
 659         /* Disable the interrupts for VF */
 660         igbvf_intr_disable(hw);
 661
 662         diag = hw->mac.ops.reset_hw(hw);
 663
 664         /* Allocate memory for storing MAC addresses */
 665         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 666                 hw->mac.rar_entry_count, 0);
 667         if (eth_dev->data->mac_addrs == NULL) {
 668                 PMD_INIT_LOG(ERR,
 669                         "Failed to allocate %d bytes needed to store MAC "
 670                         "addresses",
 671                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 672                 return -ENOMEM;
 673         }
 674
 675         /* Copy the permanent MAC address */
 676         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 677                         &eth_dev->data->mac_addrs[0]);
 678
 679         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 680                      "mac.type=%s",
 681                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 682                      pci_dev->id.device_id, "igb_mac_82576_vf");
 683
 684         return 0;
 685 }
 686
 687 static struct eth_driver rte_igb_pmd = {
 688         {
 689                 .name = "rte_igb_pmd",
 690                 .id_table = pci_id_igb_map,
 691                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 692         },
 693         .eth_dev_init = eth_igb_dev_init,
 694         .dev_private_size = sizeof(struct e1000_adapter),
 695 };
 696
 697 /*
 698  * virtual function driver struct
 699  */
 700 static struct eth_driver rte_igbvf_pmd = {
 701         {
 702                 .name = "rte_igbvf_pmd",
 703                 .id_table = pci_id_igbvf_map,
 704                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 705         },
 706         .eth_dev_init = eth_igbvf_dev_init,
 707         .dev_private_size = sizeof(struct e1000_adapter),
 708 };
 709
 710 static int
 711 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 712 {
 713         rte_eth_driver_register(&rte_igb_pmd);
 714         return 0;
 715 }
 716
 717 static void
 718 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 719 {
 720         struct e1000_hw *hw =
 721                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 722         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 723         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 724         rctl |= E1000_RCTL_VFE;
 725         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 726 }
 727
 728 /*
 729  * VF Driver initialization routine.
 730  * Invoked one at EAL init time.
 731  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 732  */
 733 static int
 734 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 735 {
 736         PMD_INIT_FUNC_TRACE();
 737
 738         rte_eth_driver_register(&rte_igbvf_pmd);
 739         return (0);
 740 }
 741
 742 static int
 743 eth_igb_configure(struct rte_eth_dev *dev)
 744 {
 745         struct e1000_interrupt *intr =
 746                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 747
 748         PMD_INIT_FUNC_TRACE();
 749         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 750         PMD_INIT_FUNC_TRACE();
 751
 752         return (0);
 753 }
 754
 755 static int
 756 eth_igb_start(struct rte_eth_dev *dev)
 757 {
 758         struct e1000_hw *hw =
 759                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 760         int ret, i, mask;
 761         uint32_t ctrl_ext;
 762
 763         PMD_INIT_FUNC_TRACE();
 764
 765         /* Power up the phy. Needed to make the link go Up */
 766         e1000_power_up_phy(hw);
 767
 768         /*
 769          * Packet Buffer Allocation (PBA)
 770          * Writing PBA sets the receive portion of the buffer
 771          * the remainder is used for the transmit buffer.
 772          */
 773         if (hw->mac.type == e1000_82575) {
 774                 uint32_t pba;
 775
 776                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 777                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 778         }
 779
 780         /* Put the address into the Receive Address Array */
 781         e1000_rar_set(hw, hw->mac.addr, 0);
 782
 783         /* Initialize the hardware */
 784         if (igb_hardware_init(hw)) {
 785                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 786                 return (-EIO);
 787         }
 788
 789         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 790
 791         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 792         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 793         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 794         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 795         E1000_WRITE_FLUSH(hw);
 796
 797         /* configure PF module if SRIOV enabled */
 798         igb_pf_host_configure(dev);
 799
 800         /* Configure for OS presence */
 801         igb_init_manageability(hw);
 802
 803         eth_igb_tx_init(dev);
 804
 805         /* This can fail when allocating mbufs for descriptor rings */
 806         ret = eth_igb_rx_init(dev);
 807         if (ret) {
 808                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 809                 igb_dev_clear_queues(dev);
 810                 return ret;
 811         }
 812
 813         e1000_clear_hw_cntrs_base_generic(hw);
 814
 815         /*
 816          * VLAN Offload Settings
 817          */
 818         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 819                         ETH_VLAN_EXTEND_MASK;
 820         eth_igb_vlan_offload_set(dev, mask);
 821
 822         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 823                 /* Enable VLAN filter since VMDq always use VLAN filter */
 824                 igb_vmdq_vlan_hw_filter_enable(dev);
 825         }
 826
 827         /*
 828          * Configure the Interrupt Moderation register (EITR) with the maximum
 829          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 830          * spurious [DMA] memory updates of RX and TX ring descriptors.
 831          *
 832          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 833          * spurious memory updates per second should be expected.
 834          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 835          *
 836          * Because interrupts are not used at all, the MSI-X is not activated
 837          * and interrupt moderation is controlled by EITR[0].
 838          *
 839          * Note that having [almost] disabled memory updates of RX and TX ring
 840          * descriptors through the Interrupt Moderation mechanism, memory
 841          * updates of ring descriptors are now moderated by the configurable
 842          * value of Write-Back Threshold registers.
 843          */
 844         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 845                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 846                 (hw->mac.type == e1000_i211)) {
 847                 uint32_t ivar;
 848
 849                 /* Enable all RX & TX queues in the IVAR registers */
 850                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 851                 for (i = 0; i < 8; i++)
 852                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 853
 854                 /* Configure EITR with the maximum possible value (0xFFFF) */
 855                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 856         }
 857
 858         /* Setup link speed and duplex */
 859         switch (dev->data->dev_conf.link_speed) {
 860         case ETH_LINK_SPEED_AUTONEG:
 861                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 862                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 863                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 864                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 865                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 866                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 867                 else
 868                         goto error_invalid_config;
 869                 break;
 870         case ETH_LINK_SPEED_10:
 871                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 872                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 873                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 874                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 875                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 876                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 877                 else
 878                         goto error_invalid_config;
 879                 break;
 880         case ETH_LINK_SPEED_100:
 881                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 882                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 883                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 884                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 885                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 886                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 887                 else
 888                         goto error_invalid_config;
 889                 break;
 890         case ETH_LINK_SPEED_1000:
 891                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 892                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 893                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 894                 else
 895                         goto error_invalid_config;
 896                 break;
 897         case ETH_LINK_SPEED_10000:
 898         default:
 899                 goto error_invalid_config;
 900         }
 901         e1000_setup_link(hw);
 902
 903         /* check if lsc interrupt feature is enabled */
 904         if (dev->data->dev_conf.intr_conf.lsc != 0)
 905                 ret = eth_igb_lsc_interrupt_setup(dev);
 906
 907         /* resume enabled intr since hw reset */
 908         igb_intr_enable(dev);
 909
 910         PMD_INIT_LOG(DEBUG, "<<");
 911
 912         return (0);
 913
 914 error_invalid_config:
 915         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 916                      dev->data->dev_conf.link_speed,
 917                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 918         igb_dev_clear_queues(dev);
 919         return (-EINVAL);
 920 }
 921
 922 /*********************************************************************
 923  *
 924  *  This routine disables all traffic on the adapter by issuing a
 925  *  global reset on the MAC.
 926  *
 927  **********************************************************************/
 928 static void
 929 eth_igb_stop(struct rte_eth_dev *dev)
 930 {
 931         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932         struct e1000_filter_info *filter_info =
 933                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
 934         struct rte_eth_link link;
 935         struct e1000_flex_filter *p_flex;
 936
 937         igb_intr_disable(hw);
 938         igb_pf_reset_hw(hw);
 939         E1000_WRITE_REG(hw, E1000_WUC, 0);
 940
 941         /* Set bit for Go Link disconnect */
 942         if (hw->mac.type >= e1000_82580) {
 943                 uint32_t phpm_reg;
 944
 945                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 946                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 947                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 948         }
 949
 950         /* Power down the phy. Needed to make the link go Down */
 951         e1000_power_down_phy(hw);
 952
 953         igb_dev_clear_queues(dev);
 954
 955         /* clear the recorded link status */
 956         memset(&link, 0, sizeof(link));
 957         rte_igb_dev_atomic_write_link_status(dev, &link);
 958
 959         /* Remove all flex filters of the device */
 960         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 961                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 962                 rte_free(p_flex);
 963         }
 964         filter_info->flex_mask = 0;
 965 }
 966
 967 static void
 968 eth_igb_close(struct rte_eth_dev *dev)
 969 {
 970         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         struct rte_eth_link link;
 972
 973         eth_igb_stop(dev);
 974         e1000_phy_hw_reset(hw);
 975         igb_release_manageability(hw);
 976         igb_hw_control_release(hw);
 977
 978         /* Clear bit for Go Link disconnect */
 979         if (hw->mac.type >= e1000_82580) {
 980                 uint32_t phpm_reg;
 981
 982                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 983                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 984                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 985         }
 986
 987         igb_dev_clear_queues(dev);
 988
 989         memset(&link, 0, sizeof(link));
 990         rte_igb_dev_atomic_write_link_status(dev, &link);
 991 }
 992
 993 static int
 994 igb_get_rx_buffer_size(struct e1000_hw *hw)
 995 {
 996         uint32_t rx_buf_size;
 997         if (hw->mac.type == e1000_82576) {
 998                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 999         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1000                 /* PBS needs to be translated according to a lookup table */
1001                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1002                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1003                 rx_buf_size = (rx_buf_size << 10);
1004         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1005                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1006         } else {
1007                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1008         }
1009
1010         return rx_buf_size;
1011 }
1012
1013 /*********************************************************************
1014  *
1015  *  Initialize the hardware
1016  *
1017  **********************************************************************/
1018 static int
1019 igb_hardware_init(struct e1000_hw *hw)
1020 {
1021         uint32_t rx_buf_size;
1022         int diag;
1023
1024         /* Let the firmware know the OS is in control */
1025         igb_hw_control_acquire(hw);
1026
1027         /*
1028          * These parameters control the automatic generation (Tx) and
1029          * response (Rx) to Ethernet PAUSE frames.
1030          * - High water mark should allow for at least two standard size (1518)
1031          *   frames to be received after sending an XOFF.
1032          * - Low water mark works best when it is very near the high water mark.
1033          *   This allows the receiver to restart by sending XON when it has
1034          *   drained a bit. Here we use an arbitrary value of 1500 which will
1035          *   restart after one full frame is pulled from the buffer. There
1036          *   could be several smaller frames in the buffer and if so they will
1037          *   not trigger the XON until their total number reduces the buffer
1038          *   by 1500.
1039          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1040          */
1041         rx_buf_size = igb_get_rx_buffer_size(hw);
1042
1043         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1044         hw->fc.low_water = hw->fc.high_water - 1500;
1045         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1046         hw->fc.send_xon = 1;
1047
1048         /* Set Flow control, use the tunable location if sane */
1049         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1050                 hw->fc.requested_mode = igb_fc_setting;
1051         else
1052                 hw->fc.requested_mode = e1000_fc_none;
1053
1054         /* Issue a global reset */
1055         igb_pf_reset_hw(hw);
1056         E1000_WRITE_REG(hw, E1000_WUC, 0);
1057
1058         diag = e1000_init_hw(hw);
1059         if (diag < 0)
1060                 return (diag);
1061
1062         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1063         e1000_get_phy_info(hw);
1064         e1000_check_for_link(hw);
1065
1066         return (0);
1067 }
1068
1069 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1070 static void
1071 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1072 {
1073         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1074         struct e1000_hw_stats *stats =
1075                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1076         int pause_frames;
1077
1078         if(hw->phy.media_type == e1000_media_type_copper ||
1079             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1080                 stats->symerrs +=
1081                     E1000_READ_REG(hw,E1000_SYMERRS);
1082                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1083         }
1084
1085         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1086         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1087         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1088         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1089
1090         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1091         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1092         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1093         stats->dc += E1000_READ_REG(hw, E1000_DC);
1094         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1095         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1096         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1097         /*
1098         ** For watchdog management we need to know if we have been
1099         ** paused during the last interval, so capture that here.
1100         */
1101         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1102         stats->xoffrxc += pause_frames;
1103         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1104         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1105         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1106         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1107         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1108         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1109         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1110         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1111         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1112         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1113         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1114         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1115
1116         /* For the 64-bit byte counters the low dword must be read first. */
1117         /* Both registers clear on the read of the high dword */
1118
1119         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1120         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1121         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1122         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1123
1124         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1125         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1126         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1127         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1128         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1129
1130         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1131         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1132
1133         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1134         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1135         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1136         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1137         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1138         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1139         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1140         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1141         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1142         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1143
1144         /* Interrupt Counts */
1145
1146         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1147         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1148         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1149         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1150         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1151         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1152         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1153         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1154         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1155
1156         /* Host to Card Statistics */
1157
1158         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1159         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1160         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1161         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1162         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1163         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1164         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1165         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1166         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1167         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1168         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1169         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1170         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1171         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1172
1173         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1174         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1175         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1176         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1177         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1178         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1179
1180         if (rte_stats == NULL)
1181                 return;
1182
1183         /* Rx Errors */
1184         rte_stats->ibadcrc = stats->crcerrs;
1185         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1186         rte_stats->imissed = stats->mpc;
1187         rte_stats->ierrors = rte_stats->ibadcrc +
1188                              rte_stats->ibadlen +
1189                              rte_stats->imissed +
1190                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1191
1192         /* Tx Errors */
1193         rte_stats->oerrors = stats->ecol + stats->latecol;
1194
1195         /* XON/XOFF pause frames */
1196         rte_stats->tx_pause_xon  = stats->xontxc;
1197         rte_stats->rx_pause_xon  = stats->xonrxc;
1198         rte_stats->tx_pause_xoff = stats->xofftxc;
1199         rte_stats->rx_pause_xoff = stats->xoffrxc;
1200
1201         rte_stats->ipackets = stats->gprc;
1202         rte_stats->opackets = stats->gptc;
1203         rte_stats->ibytes   = stats->gorc;
1204         rte_stats->obytes   = stats->gotc;
1205 }
1206
1207 static void
1208 eth_igb_stats_reset(struct rte_eth_dev *dev)
1209 {
1210         struct e1000_hw_stats *hw_stats =
1211                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1212
1213         /* HW registers are cleared on read */
1214         eth_igb_stats_get(dev, NULL);
1215
1216         /* Reset software totals */
1217         memset(hw_stats, 0, sizeof(*hw_stats));
1218 }
1219
1220 static void
1221 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1222 {
1223         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1225                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1226
1227         /* Good Rx packets, include VF loopback */
1228         UPDATE_VF_STAT(E1000_VFGPRC,
1229             hw_stats->last_gprc, hw_stats->gprc);
1230
1231         /* Good Rx octets, include VF loopback */
1232         UPDATE_VF_STAT(E1000_VFGORC,
1233             hw_stats->last_gorc, hw_stats->gorc);
1234
1235         /* Good Tx packets, include VF loopback */
1236         UPDATE_VF_STAT(E1000_VFGPTC,
1237             hw_stats->last_gptc, hw_stats->gptc);
1238
1239         /* Good Tx octets, include VF loopback */
1240         UPDATE_VF_STAT(E1000_VFGOTC,
1241             hw_stats->last_gotc, hw_stats->gotc);
1242
1243         /* Rx Multicst packets */
1244         UPDATE_VF_STAT(E1000_VFMPRC,
1245             hw_stats->last_mprc, hw_stats->mprc);
1246
1247         /* Good Rx loopback packets */
1248         UPDATE_VF_STAT(E1000_VFGPRLBC,
1249             hw_stats->last_gprlbc, hw_stats->gprlbc);
1250
1251         /* Good Rx loopback octets */
1252         UPDATE_VF_STAT(E1000_VFGORLBC,
1253             hw_stats->last_gorlbc, hw_stats->gorlbc);
1254
1255         /* Good Tx loopback packets */
1256         UPDATE_VF_STAT(E1000_VFGPTLBC,
1257             hw_stats->last_gptlbc, hw_stats->gptlbc);
1258
1259         /* Good Tx loopback octets */
1260         UPDATE_VF_STAT(E1000_VFGOTLBC,
1261             hw_stats->last_gotlbc, hw_stats->gotlbc);
1262
1263         if (rte_stats == NULL)
1264                 return;
1265
1266         rte_stats->ipackets = hw_stats->gprc;
1267         rte_stats->ibytes = hw_stats->gorc;
1268         rte_stats->opackets = hw_stats->gptc;
1269         rte_stats->obytes = hw_stats->gotc;
1270         rte_stats->imcasts = hw_stats->mprc;
1271         rte_stats->ilbpackets = hw_stats->gprlbc;
1272         rte_stats->ilbbytes = hw_stats->gorlbc;
1273         rte_stats->olbpackets = hw_stats->gptlbc;
1274         rte_stats->olbbytes = hw_stats->gotlbc;
1275
1276 }
1277
1278 static void
1279 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1280 {
1281         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1282                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1283
1284         /* Sync HW register to the last stats */
1285         eth_igbvf_stats_get(dev, NULL);
1286
1287         /* reset HW current stats*/
1288         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1289                offsetof(struct e1000_vf_stats, gprc));
1290
1291 }
1292
1293 static void
1294 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1295 {
1296         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1297
1298         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1299         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1300         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1301         dev_info->rx_offload_capa =
1302                 DEV_RX_OFFLOAD_VLAN_STRIP |
1303                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1304                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1305                 DEV_RX_OFFLOAD_TCP_CKSUM;
1306         dev_info->tx_offload_capa =
1307                 DEV_TX_OFFLOAD_VLAN_INSERT |
1308                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1309                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1310                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1311                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1312
1313         switch (hw->mac.type) {
1314         case e1000_82575:
1315                 dev_info->max_rx_queues = 4;
1316                 dev_info->max_tx_queues = 4;
1317                 dev_info->max_vmdq_pools = 0;
1318                 break;
1319
1320         case e1000_82576:
1321                 dev_info->max_rx_queues = 16;
1322                 dev_info->max_tx_queues = 16;
1323                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1324                 dev_info->vmdq_queue_num = 16;
1325                 break;
1326
1327         case e1000_82580:
1328                 dev_info->max_rx_queues = 8;
1329                 dev_info->max_tx_queues = 8;
1330                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1331                 dev_info->vmdq_queue_num = 8;
1332                 break;
1333
1334         case e1000_i350:
1335                 dev_info->max_rx_queues = 8;
1336                 dev_info->max_tx_queues = 8;
1337                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1338                 dev_info->vmdq_queue_num = 8;
1339                 break;
1340
1341         case e1000_i354:
1342                 dev_info->max_rx_queues = 8;
1343                 dev_info->max_tx_queues = 8;
1344                 break;
1345
1346         case e1000_i210:
1347                 dev_info->max_rx_queues = 4;
1348                 dev_info->max_tx_queues = 4;
1349                 dev_info->max_vmdq_pools = 0;
1350                 break;
1351
1352         case e1000_i211:
1353                 dev_info->max_rx_queues = 2;
1354                 dev_info->max_tx_queues = 2;
1355                 dev_info->max_vmdq_pools = 0;
1356                 break;
1357
1358         default:
1359                 /* Should not happen */
1360                 break;
1361         }
1362         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1363
1364         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1365                 .rx_thresh = {
1366                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1367                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1368                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1369                 },
1370                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1371                 .rx_drop_en = 0,
1372         };
1373
1374         dev_info->default_txconf = (struct rte_eth_txconf) {
1375                 .tx_thresh = {
1376                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1377                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1378                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1379                 },
1380                 .txq_flags = 0,
1381         };
1382 }
1383
1384 static void
1385 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1386 {
1387         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388
1389         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1390         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1391         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1392         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1393                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1394                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1395                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1396         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1397                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1398                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1399                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1400                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1401         switch (hw->mac.type) {
1402         case e1000_vfadapt:
1403                 dev_info->max_rx_queues = 2;
1404                 dev_info->max_tx_queues = 2;
1405                 break;
1406         case e1000_vfadapt_i350:
1407                 dev_info->max_rx_queues = 1;
1408                 dev_info->max_tx_queues = 1;
1409                 break;
1410         default:
1411                 /* Should not happen */
1412                 break;
1413         }
1414
1415         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1416                 .rx_thresh = {
1417                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1418                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1419                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1420                 },
1421                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1422                 .rx_drop_en = 0,
1423         };
1424
1425         dev_info->default_txconf = (struct rte_eth_txconf) {
1426                 .tx_thresh = {
1427                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1428                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1429                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1430                 },
1431                 .txq_flags = 0,
1432         };
1433 }
1434
1435 /* return 0 means link status changed, -1 means not changed */
1436 static int
1437 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1438 {
1439         struct e1000_hw *hw =
1440                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441         struct rte_eth_link link, old;
1442         int link_check, count;
1443
1444         link_check = 0;
1445         hw->mac.get_link_status = 1;
1446
1447         /* possible wait-to-complete in up to 9 seconds */
1448         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1449                 /* Read the real link status */
1450                 switch (hw->phy.media_type) {
1451                 case e1000_media_type_copper:
1452                         /* Do the work to read phy */
1453                         e1000_check_for_link(hw);
1454                         link_check = !hw->mac.get_link_status;
1455                         break;
1456
1457                 case e1000_media_type_fiber:
1458                         e1000_check_for_link(hw);
1459                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1460                                       E1000_STATUS_LU);
1461                         break;
1462
1463                 case e1000_media_type_internal_serdes:
1464                         e1000_check_for_link(hw);
1465                         link_check = hw->mac.serdes_has_link;
1466                         break;
1467
1468                 /* VF device is type_unknown */
1469                 case e1000_media_type_unknown:
1470                         eth_igbvf_link_update(hw);
1471                         link_check = !hw->mac.get_link_status;
1472                         break;
1473
1474                 default:
1475                         break;
1476                 }
1477                 if (link_check || wait_to_complete == 0)
1478                         break;
1479                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1480         }
1481         memset(&link, 0, sizeof(link));
1482         rte_igb_dev_atomic_read_link_status(dev, &link);
1483         old = link;
1484
1485         /* Now we check if a transition has happened */
1486         if (link_check) {
1487                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1488                                           &link.link_duplex);
1489                 link.link_status = 1;
1490         } else if (!link_check) {
1491                 link.link_speed = 0;
1492                 link.link_duplex = 0;
1493                 link.link_status = 0;
1494         }
1495         rte_igb_dev_atomic_write_link_status(dev, &link);
1496
1497         /* not changed */
1498         if (old.link_status == link.link_status)
1499                 return -1;
1500
1501         /* changed */
1502         return 0;
1503 }
1504
1505 /*
1506  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1507  * For ASF and Pass Through versions of f/w this means
1508  * that the driver is loaded.
1509  */
1510 static void
1511 igb_hw_control_acquire(struct e1000_hw *hw)
1512 {
1513         uint32_t ctrl_ext;
1514
1515         /* Let firmware know the driver has taken over */
1516         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1517         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1518 }
1519
1520 /*
1521  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1522  * For ASF and Pass Through versions of f/w this means that the
1523  * driver is no longer loaded.
1524  */
1525 static void
1526 igb_hw_control_release(struct e1000_hw *hw)
1527 {
1528         uint32_t ctrl_ext;
1529
1530         /* Let firmware taken over control of h/w */
1531         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1532         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1533                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1534 }
1535
1536 /*
1537  * Bit of a misnomer, what this really means is
1538  * to enable OS management of the system... aka
1539  * to disable special hardware management features.
1540  */
1541 static void
1542 igb_init_manageability(struct e1000_hw *hw)
1543 {
1544         if (e1000_enable_mng_pass_thru(hw)) {
1545                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1546                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1547
1548                 /* disable hardware interception of ARP */
1549                 manc &= ~(E1000_MANC_ARP_EN);
1550
1551                 /* enable receiving management packets to the host */
1552                 manc |= E1000_MANC_EN_MNG2HOST;
1553                 manc2h |= 1 << 5;  /* Mng Port 623 */
1554                 manc2h |= 1 << 6;  /* Mng Port 664 */
1555                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1556                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1557         }
1558 }
1559
1560 static void
1561 igb_release_manageability(struct e1000_hw *hw)
1562 {
1563         if (e1000_enable_mng_pass_thru(hw)) {
1564                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1565
1566                 manc |= E1000_MANC_ARP_EN;
1567                 manc &= ~E1000_MANC_EN_MNG2HOST;
1568
1569                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1570         }
1571 }
1572
1573 static void
1574 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1575 {
1576         struct e1000_hw *hw =
1577                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578         uint32_t rctl;
1579
1580         rctl = E1000_READ_REG(hw, E1000_RCTL);
1581         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1582         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1583 }
1584
1585 static void
1586 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1587 {
1588         struct e1000_hw *hw =
1589                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590         uint32_t rctl;
1591
1592         rctl = E1000_READ_REG(hw, E1000_RCTL);
1593         rctl &= (~E1000_RCTL_UPE);
1594         if (dev->data->all_multicast == 1)
1595                 rctl |= E1000_RCTL_MPE;
1596         else
1597                 rctl &= (~E1000_RCTL_MPE);
1598         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1599 }
1600
1601 static void
1602 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1603 {
1604         struct e1000_hw *hw =
1605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         uint32_t rctl;
1607
1608         rctl = E1000_READ_REG(hw, E1000_RCTL);
1609         rctl |= E1000_RCTL_MPE;
1610         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1611 }
1612
1613 static void
1614 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1615 {
1616         struct e1000_hw *hw =
1617                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618         uint32_t rctl;
1619
1620         if (dev->data->promiscuous == 1)
1621                 return; /* must remain in all_multicast mode */
1622         rctl = E1000_READ_REG(hw, E1000_RCTL);
1623         rctl &= (~E1000_RCTL_MPE);
1624         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1625 }
1626
1627 static int
1628 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1629 {
1630         struct e1000_hw *hw =
1631                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632         struct e1000_vfta * shadow_vfta =
1633                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1634         uint32_t vfta;
1635         uint32_t vid_idx;
1636         uint32_t vid_bit;
1637
1638         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1639                               E1000_VFTA_ENTRY_MASK);
1640         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1641         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1642         if (on)
1643                 vfta |= vid_bit;
1644         else
1645                 vfta &= ~vid_bit;
1646         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1647
1648         /* update local VFTA copy */
1649         shadow_vfta->vfta[vid_idx] = vfta;
1650
1651         return 0;
1652 }
1653
1654 static void
1655 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1656 {
1657         struct e1000_hw *hw =
1658                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         uint32_t reg = ETHER_TYPE_VLAN ;
1660
1661         reg |= (tpid << 16);
1662         E1000_WRITE_REG(hw, E1000_VET, reg);
1663 }
1664
1665 static void
1666 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1667 {
1668         struct e1000_hw *hw =
1669                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670         uint32_t reg;
1671
1672         /* Filter Table Disable */
1673         reg = E1000_READ_REG(hw, E1000_RCTL);
1674         reg &= ~E1000_RCTL_CFIEN;
1675         reg &= ~E1000_RCTL_VFE;
1676         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1677 }
1678
1679 static void
1680 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1681 {
1682         struct e1000_hw *hw =
1683                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         struct e1000_vfta * shadow_vfta =
1685                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1686         uint32_t reg;
1687         int i;
1688
1689         /* Filter Table Enable, CFI not used for packet acceptance */
1690         reg = E1000_READ_REG(hw, E1000_RCTL);
1691         reg &= ~E1000_RCTL_CFIEN;
1692         reg |= E1000_RCTL_VFE;
1693         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1694
1695         /* restore VFTA table */
1696         for (i = 0; i < IGB_VFTA_SIZE; i++)
1697                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1698 }
1699
1700 static void
1701 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1702 {
1703         struct e1000_hw *hw =
1704                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1705         uint32_t reg;
1706
1707         /* VLAN Mode Disable */
1708         reg = E1000_READ_REG(hw, E1000_CTRL);
1709         reg &= ~E1000_CTRL_VME;
1710         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1711 }
1712
1713 static void
1714 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1715 {
1716         struct e1000_hw *hw =
1717                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718         uint32_t reg;
1719
1720         /* VLAN Mode Enable */
1721         reg = E1000_READ_REG(hw, E1000_CTRL);
1722         reg |= E1000_CTRL_VME;
1723         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1724 }
1725
1726 static void
1727 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1728 {
1729         struct e1000_hw *hw =
1730                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1731         uint32_t reg;
1732
1733         /* CTRL_EXT: Extended VLAN */
1734         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1735         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1736         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1737
1738         /* Update maximum packet length */
1739         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1740                 E1000_WRITE_REG(hw, E1000_RLPML,
1741                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1742                                                 VLAN_TAG_SIZE);
1743 }
1744
1745 static void
1746 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1747 {
1748         struct e1000_hw *hw =
1749                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         uint32_t reg;
1751
1752         /* CTRL_EXT: Extended VLAN */
1753         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1754         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1755         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1756
1757         /* Update maximum packet length */
1758         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1759                 E1000_WRITE_REG(hw, E1000_RLPML,
1760                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1761                                                 2 * VLAN_TAG_SIZE);
1762 }
1763
1764 static void
1765 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1766 {
1767         if(mask & ETH_VLAN_STRIP_MASK){
1768                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1769                         igb_vlan_hw_strip_enable(dev);
1770                 else
1771                         igb_vlan_hw_strip_disable(dev);
1772         }
1773
1774         if(mask & ETH_VLAN_FILTER_MASK){
1775                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1776                         igb_vlan_hw_filter_enable(dev);
1777                 else
1778                         igb_vlan_hw_filter_disable(dev);
1779         }
1780
1781         if(mask & ETH_VLAN_EXTEND_MASK){
1782                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1783                         igb_vlan_hw_extend_enable(dev);
1784                 else
1785                         igb_vlan_hw_extend_disable(dev);
1786         }
1787 }
1788
1789
1790 /**
1791  * It enables the interrupt mask and then enable the interrupt.
1792  *
1793  * @param dev
1794  *  Pointer to struct rte_eth_dev.
1795  *
1796  * @return
1797  *  - On success, zero.
1798  *  - On failure, a negative value.
1799  */
1800 static int
1801 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1802 {
1803         struct e1000_interrupt *intr =
1804                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1805
1806         intr->mask |= E1000_ICR_LSC;
1807
1808         return 0;
1809 }
1810
1811 /*
1812  * It reads ICR and gets interrupt causes, check it and set a bit flag
1813  * to update link status.
1814  *
1815  * @param dev
1816  *  Pointer to struct rte_eth_dev.
1817  *
1818  * @return
1819  *  - On success, zero.
1820  *  - On failure, a negative value.
1821  */
1822 static int
1823 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1824 {
1825         uint32_t icr;
1826         struct e1000_hw *hw =
1827                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828         struct e1000_interrupt *intr =
1829                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1830
1831         igb_intr_disable(hw);
1832
1833         /* read-on-clear nic registers here */
1834         icr = E1000_READ_REG(hw, E1000_ICR);
1835
1836         intr->flags = 0;
1837         if (icr & E1000_ICR_LSC) {
1838                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1839         }
1840
1841         if (icr & E1000_ICR_VMMB)
1842                 intr->flags |= E1000_FLAG_MAILBOX;
1843
1844         return 0;
1845 }
1846
1847 /*
1848  * It executes link_update after knowing an interrupt is prsent.
1849  *
1850  * @param dev
1851  *  Pointer to struct rte_eth_dev.
1852  *
1853  * @return
1854  *  - On success, zero.
1855  *  - On failure, a negative value.
1856  */
1857 static int
1858 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1859 {
1860         struct e1000_hw *hw =
1861                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         struct e1000_interrupt *intr =
1863                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1864         uint32_t tctl, rctl;
1865         struct rte_eth_link link;
1866         int ret;
1867
1868         if (intr->flags & E1000_FLAG_MAILBOX) {
1869                 igb_pf_mbx_process(dev);
1870                 intr->flags &= ~E1000_FLAG_MAILBOX;
1871         }
1872
1873         igb_intr_enable(dev);
1874         rte_intr_enable(&(dev->pci_dev->intr_handle));
1875
1876         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1877                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1878
1879                 /* set get_link_status to check register later */
1880                 hw->mac.get_link_status = 1;
1881                 ret = eth_igb_link_update(dev, 0);
1882
1883                 /* check if link has changed */
1884                 if (ret < 0)
1885                         return 0;
1886
1887                 memset(&link, 0, sizeof(link));
1888                 rte_igb_dev_atomic_read_link_status(dev, &link);
1889                 if (link.link_status) {
1890                         PMD_INIT_LOG(INFO,
1891                                      " Port %d: Link Up - speed %u Mbps - %s",
1892                                      dev->data->port_id,
1893                                      (unsigned)link.link_speed,
1894                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1895                                      "full-duplex" : "half-duplex");
1896                 } else {
1897                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1898                                      dev->data->port_id);
1899                 }
1900                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1901                              dev->pci_dev->addr.domain,
1902                              dev->pci_dev->addr.bus,
1903                              dev->pci_dev->addr.devid,
1904                              dev->pci_dev->addr.function);
1905                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1906                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1907                 if (link.link_status) {
1908                         /* enable Tx/Rx */
1909                         tctl |= E1000_TCTL_EN;
1910                         rctl |= E1000_RCTL_EN;
1911                 } else {
1912                         /* disable Tx/Rx */
1913                         tctl &= ~E1000_TCTL_EN;
1914                         rctl &= ~E1000_RCTL_EN;
1915                 }
1916                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1917                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1918                 E1000_WRITE_FLUSH(hw);
1919                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1920         }
1921
1922         return 0;
1923 }
1924
1925 /**
1926  * Interrupt handler which shall be registered at first.
1927  *
1928  * @param handle
1929  *  Pointer to interrupt handle.
1930  * @param param
1931  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1932  *
1933  * @return
1934  *  void
1935  */
1936 static void
1937 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1938                                                         void *param)
1939 {
1940         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1941
1942         eth_igb_interrupt_get_status(dev);
1943         eth_igb_interrupt_action(dev);
1944 }
1945
1946 static int
1947 eth_igb_led_on(struct rte_eth_dev *dev)
1948 {
1949         struct e1000_hw *hw;
1950
1951         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1953 }
1954
1955 static int
1956 eth_igb_led_off(struct rte_eth_dev *dev)
1957 {
1958         struct e1000_hw *hw;
1959
1960         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1962 }
1963
1964 static int
1965 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1966 {
1967         struct e1000_hw *hw;
1968         uint32_t ctrl;
1969         int tx_pause;
1970         int rx_pause;
1971
1972         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         fc_conf->pause_time = hw->fc.pause_time;
1974         fc_conf->high_water = hw->fc.high_water;
1975         fc_conf->low_water = hw->fc.low_water;
1976         fc_conf->send_xon = hw->fc.send_xon;
1977         fc_conf->autoneg = hw->mac.autoneg;
1978
1979         /*
1980          * Return rx_pause and tx_pause status according to actual setting of
1981          * the TFCE and RFCE bits in the CTRL register.
1982          */
1983         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1984         if (ctrl & E1000_CTRL_TFCE)
1985                 tx_pause = 1;
1986         else
1987                 tx_pause = 0;
1988
1989         if (ctrl & E1000_CTRL_RFCE)
1990                 rx_pause = 1;
1991         else
1992                 rx_pause = 0;
1993
1994         if (rx_pause && tx_pause)
1995                 fc_conf->mode = RTE_FC_FULL;
1996         else if (rx_pause)
1997                 fc_conf->mode = RTE_FC_RX_PAUSE;
1998         else if (tx_pause)
1999                 fc_conf->mode = RTE_FC_TX_PAUSE;
2000         else
2001                 fc_conf->mode = RTE_FC_NONE;
2002
2003         return 0;
2004 }
2005
2006 static int
2007 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2008 {
2009         struct e1000_hw *hw;
2010         int err;
2011         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2012                 e1000_fc_none,
2013                 e1000_fc_rx_pause,
2014                 e1000_fc_tx_pause,
2015                 e1000_fc_full
2016         };
2017         uint32_t rx_buf_size;
2018         uint32_t max_high_water;
2019         uint32_t rctl;
2020
2021         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         if (fc_conf->autoneg != hw->mac.autoneg)
2023                 return -ENOTSUP;
2024         rx_buf_size = igb_get_rx_buffer_size(hw);
2025         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2026
2027         /* At least reserve one Ethernet frame for watermark */
2028         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2029         if ((fc_conf->high_water > max_high_water) ||
2030             (fc_conf->high_water < fc_conf->low_water)) {
2031                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2032                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2033                 return (-EINVAL);
2034         }
2035
2036         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2037         hw->fc.pause_time     = fc_conf->pause_time;
2038         hw->fc.high_water     = fc_conf->high_water;
2039         hw->fc.low_water      = fc_conf->low_water;
2040         hw->fc.send_xon       = fc_conf->send_xon;
2041
2042         err = e1000_setup_link_generic(hw);
2043         if (err == E1000_SUCCESS) {
2044
2045                 /* check if we want to forward MAC frames - driver doesn't have native
2046                  * capability to do that, so we'll write the registers ourselves */
2047
2048                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2049
2050                 /* set or clear MFLCN.PMCF bit depending on configuration */
2051                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2052                         rctl |= E1000_RCTL_PMCF;
2053                 else
2054                         rctl &= ~E1000_RCTL_PMCF;
2055
2056                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2057                 E1000_WRITE_FLUSH(hw);
2058
2059                 return 0;
2060         }
2061
2062         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2063         return (-EIO);
2064 }
2065
2066 #define E1000_RAH_POOLSEL_SHIFT      (18)
2067 static void
2068 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2069                 uint32_t index, __rte_unused uint32_t pool)
2070 {
2071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072         uint32_t rah;
2073
2074         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2075         rah = E1000_READ_REG(hw, E1000_RAH(index));
2076         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2077         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2078 }
2079
2080 static void
2081 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2082 {
2083         uint8_t addr[ETHER_ADDR_LEN];
2084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085
2086         memset(addr, 0, sizeof(addr));
2087
2088         e1000_rar_set(hw, addr, index);
2089 }
2090
2091 /*
2092  * Virtual Function operations
2093  */
2094 static void
2095 igbvf_intr_disable(struct e1000_hw *hw)
2096 {
2097         PMD_INIT_FUNC_TRACE();
2098
2099         /* Clear interrupt mask to stop from interrupts being generated */
2100         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2101
2102         E1000_WRITE_FLUSH(hw);
2103 }
2104
2105 static void
2106 igbvf_stop_adapter(struct rte_eth_dev *dev)
2107 {
2108         u32 reg_val;
2109         u16 i;
2110         struct rte_eth_dev_info dev_info;
2111         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112
2113         memset(&dev_info, 0, sizeof(dev_info));
2114         eth_igbvf_infos_get(dev, &dev_info);
2115
2116         /* Clear interrupt mask to stop from interrupts being generated */
2117         igbvf_intr_disable(hw);
2118
2119         /* Clear any pending interrupts, flush previous writes */
2120         E1000_READ_REG(hw, E1000_EICR);
2121
2122         /* Disable the transmit unit.  Each queue must be disabled. */
2123         for (i = 0; i < dev_info.max_tx_queues; i++)
2124                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2125
2126         /* Disable the receive unit by stopping each queue */
2127         for (i = 0; i < dev_info.max_rx_queues; i++) {
2128                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2129                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2130                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2131                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2132                         ;
2133         }
2134
2135         /* flush all queues disables */
2136         E1000_WRITE_FLUSH(hw);
2137         msec_delay(2);
2138 }
2139
2140 static int eth_igbvf_link_update(struct e1000_hw *hw)
2141 {
2142         struct e1000_mbx_info *mbx = &hw->mbx;
2143         struct e1000_mac_info *mac = &hw->mac;
2144         int ret_val = E1000_SUCCESS;
2145
2146         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2147
2148         /*
2149          * We only want to run this if there has been a rst asserted.
2150          * in this case that could mean a link change, device reset,
2151          * or a virtual function reset
2152          */
2153
2154         /* If we were hit with a reset or timeout drop the link */
2155         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2156                 mac->get_link_status = TRUE;
2157
2158         if (!mac->get_link_status)
2159                 goto out;
2160
2161         /* if link status is down no point in checking to see if pf is up */
2162         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2163                 goto out;
2164
2165         /* if we passed all the tests above then the link is up and we no
2166          * longer need to check for link */
2167         mac->get_link_status = FALSE;
2168
2169 out:
2170         return ret_val;
2171 }
2172
2173
2174 static int
2175 igbvf_dev_configure(struct rte_eth_dev *dev)
2176 {
2177         struct rte_eth_conf* conf = &dev->data->dev_conf;
2178
2179         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2180                      dev->data->port_id);
2181
2182         /*
2183          * VF has no ability to enable/disable HW CRC
2184          * Keep the persistent behavior the same as Host PF
2185          */
2186 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2187         if (!conf->rxmode.hw_strip_crc) {
2188                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2189                 conf->rxmode.hw_strip_crc = 1;
2190         }
2191 #else
2192         if (conf->rxmode.hw_strip_crc) {
2193                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2194                 conf->rxmode.hw_strip_crc = 0;
2195         }
2196 #endif
2197
2198         return 0;
2199 }
2200
2201 static int
2202 igbvf_dev_start(struct rte_eth_dev *dev)
2203 {
2204         struct e1000_hw *hw =
2205                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2206         int ret;
2207
2208         PMD_INIT_FUNC_TRACE();
2209
2210         hw->mac.ops.reset_hw(hw);
2211
2212         /* Set all vfta */
2213         igbvf_set_vfta_all(dev,1);
2214
2215         eth_igbvf_tx_init(dev);
2216
2217         /* This can fail when allocating mbufs for descriptor rings */
2218         ret = eth_igbvf_rx_init(dev);
2219         if (ret) {
2220                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2221                 igb_dev_clear_queues(dev);
2222                 return ret;
2223         }
2224
2225         return 0;
2226 }
2227
2228 static void
2229 igbvf_dev_stop(struct rte_eth_dev *dev)
2230 {
2231         PMD_INIT_FUNC_TRACE();
2232
2233         igbvf_stop_adapter(dev);
2234
2235         /*
2236           * Clear what we set, but we still keep shadow_vfta to
2237           * restore after device starts
2238           */
2239         igbvf_set_vfta_all(dev,0);
2240
2241         igb_dev_clear_queues(dev);
2242 }
2243
2244 static void
2245 igbvf_dev_close(struct rte_eth_dev *dev)
2246 {
2247         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248
2249         PMD_INIT_FUNC_TRACE();
2250
2251         e1000_reset_hw(hw);
2252
2253         igbvf_dev_stop(dev);
2254 }
2255
2256 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2257 {
2258         struct e1000_mbx_info *mbx = &hw->mbx;
2259         uint32_t msgbuf[2];
2260
2261         /* After set vlan, vlan strip will also be enabled in igb driver*/
2262         msgbuf[0] = E1000_VF_SET_VLAN;
2263         msgbuf[1] = vid;
2264         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2265         if (on)
2266                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2267
2268         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2269 }
2270
2271 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2272 {
2273         struct e1000_hw *hw =
2274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275         struct e1000_vfta * shadow_vfta =
2276                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2277         int i = 0, j = 0, vfta = 0, mask = 1;
2278
2279         for (i = 0; i < IGB_VFTA_SIZE; i++){
2280                 vfta = shadow_vfta->vfta[i];
2281                 if(vfta){
2282                         mask = 1;
2283                         for (j = 0; j < 32; j++){
2284                                 if(vfta & mask)
2285                                         igbvf_set_vfta(hw,
2286                                                 (uint16_t)((i<<5)+j), on);
2287                                 mask<<=1;
2288                         }
2289                 }
2290         }
2291
2292 }
2293
2294 static int
2295 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2296 {
2297         struct e1000_hw *hw =
2298                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2299         struct e1000_vfta * shadow_vfta =
2300                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2301         uint32_t vid_idx = 0;
2302         uint32_t vid_bit = 0;
2303         int ret = 0;
2304
2305         PMD_INIT_FUNC_TRACE();
2306
2307         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2308         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2309         if(ret){
2310                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2311                 return ret;
2312         }
2313         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2314         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2315
2316         /*Save what we set and retore it after device reset*/
2317         if (on)
2318                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2319         else
2320                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2321
2322         return 0;
2323 }
2324
2325 static int
2326 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2327                         struct rte_eth_rss_reta_entry64 *reta_conf,
2328                         uint16_t reta_size)
2329 {
2330         uint8_t i, j, mask;
2331         uint32_t reta, r;
2332         uint16_t idx, shift;
2333         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334
2335         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2336                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2337                         "(%d) doesn't match the number hardware can supported "
2338                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2339                 return -EINVAL;
2340         }
2341
2342         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2343                 idx = i / RTE_RETA_GROUP_SIZE;
2344                 shift = i % RTE_RETA_GROUP_SIZE;
2345                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2346                                                 IGB_4_BIT_MASK);
2347                 if (!mask)
2348                         continue;
2349                 if (mask == IGB_4_BIT_MASK)
2350                         r = 0;
2351                 else
2352                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2353                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2354                         if (mask & (0x1 << j))
2355                                 reta |= reta_conf[idx].reta[shift + j] <<
2356                                                         (CHAR_BIT * j);
2357                         else
2358                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2359                 }
2360                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2361         }
2362
2363         return 0;
2364 }
2365
2366 static int
2367 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2368                        struct rte_eth_rss_reta_entry64 *reta_conf,
2369                        uint16_t reta_size)
2370 {
2371         uint8_t i, j, mask;
2372         uint32_t reta;
2373         uint16_t idx, shift;
2374         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375
2376         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2377                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2378                         "(%d) doesn't match the number hardware can supported "
2379                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2380                 return -EINVAL;
2381         }
2382
2383         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2384                 idx = i / RTE_RETA_GROUP_SIZE;
2385                 shift = i % RTE_RETA_GROUP_SIZE;
2386                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2387                                                 IGB_4_BIT_MASK);
2388                 if (!mask)
2389                         continue;
2390                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2391                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2392                         if (mask & (0x1 << j))
2393                                 reta_conf[idx].reta[shift + j] =
2394                                         ((reta >> (CHAR_BIT * j)) &
2395                                                 IGB_8_BIT_MASK);
2396                 }
2397         }
2398
2399         return 0;
2400 }
2401
2402 #define MAC_TYPE_FILTER_SUP(type)    do {\
2403         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2404                 (type) != e1000_82576)\
2405                 return -ENOTSUP;\
2406 } while (0)
2407
2408 static int
2409 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2410                         struct rte_eth_syn_filter *filter,
2411                         bool add)
2412 {
2413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         uint32_t synqf, rfctl;
2415
2416         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2417                 return -EINVAL;
2418
2419         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2420
2421         if (add) {
2422                 if (synqf & E1000_SYN_FILTER_ENABLE)
2423                         return -EINVAL;
2424
2425                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2426                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2427
2428                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2429                 if (filter->hig_pri)
2430                         rfctl |= E1000_RFCTL_SYNQFP;
2431                 else
2432                         rfctl &= ~E1000_RFCTL_SYNQFP;
2433
2434                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2435         } else {
2436                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2437                         return -ENOENT;
2438                 synqf = 0;
2439         }
2440
2441         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2442         E1000_WRITE_FLUSH(hw);
2443         return 0;
2444 }
2445
2446 static int
2447 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2448                         struct rte_eth_syn_filter *filter)
2449 {
2450         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451         uint32_t synqf, rfctl;
2452
2453         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2454         if (synqf & E1000_SYN_FILTER_ENABLE) {
2455                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2456                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2457                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2458                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2459                 return 0;
2460         }
2461
2462         return -ENOENT;
2463 }
2464
2465 static int
2466 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2467                         enum rte_filter_op filter_op,
2468                         void *arg)
2469 {
2470         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         int ret;
2472
2473         MAC_TYPE_FILTER_SUP(hw->mac.type);
2474
2475         if (filter_op == RTE_ETH_FILTER_NOP)
2476                 return 0;
2477
2478         if (arg == NULL) {
2479                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2480                             filter_op);
2481                 return -EINVAL;
2482         }
2483
2484         switch (filter_op) {
2485         case RTE_ETH_FILTER_ADD:
2486                 ret = eth_igb_syn_filter_set(dev,
2487                                 (struct rte_eth_syn_filter *)arg,
2488                                 TRUE);
2489                 break;
2490         case RTE_ETH_FILTER_DELETE:
2491                 ret = eth_igb_syn_filter_set(dev,
2492                                 (struct rte_eth_syn_filter *)arg,
2493                                 FALSE);
2494                 break;
2495         case RTE_ETH_FILTER_GET:
2496                 ret = eth_igb_syn_filter_get(dev,
2497                                 (struct rte_eth_syn_filter *)arg);
2498                 break;
2499         default:
2500                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2501                 ret = -EINVAL;
2502                 break;
2503         }
2504
2505         return ret;
2506 }
2507
2508 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2509         if ((type) != e1000_82580 && (type) != e1000_i350)\
2510                 return -ENOSYS; \
2511 } while (0)
2512
2513 /*
2514  * add a 2tuple filter
2515  *
2516  * @param
2517  * dev: Pointer to struct rte_eth_dev.
2518  * index: the index the filter allocates.
2519  * filter: ponter to the filter that will be added.
2520  * rx_queue: the queue id the filter assigned to.
2521  *
2522  * @return
2523  *    - On success, zero.
2524  *    - On failure, a negative value.
2525  */
2526 static int
2527 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2528                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2529 {
2530         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         uint32_t ttqf, imir = 0;
2532         uint32_t imir_ext = 0;
2533
2534         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2535
2536         if (index >= E1000_MAX_TTQF_FILTERS ||
2537                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2538                 filter->priority > E1000_2TUPLE_MAX_PRI)
2539                 return -EINVAL;  /* filter index is out of range. */
2540         if  (filter->tcp_flags > TCP_FLAG_ALL)
2541                 return -EINVAL;  /* flags is invalid. */
2542
2543         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2544         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2545                 return -EINVAL;  /* filter index is in use. */
2546
2547         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2548         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2549                 imir |= E1000_IMIR_PORT_BP;
2550         else
2551                 imir &= ~E1000_IMIR_PORT_BP;
2552
2553         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2554
2555         ttqf = 0;
2556         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2557         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2558         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2559         if (filter->protocol_mask == 1)
2560                 ttqf |= E1000_TTQF_MASK_ENABLE;
2561         else
2562                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2563
2564         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2565         /* tcp flags bits setting. */
2566         if (filter->tcp_flags & TCP_FLAG_ALL) {
2567                 if (filter->tcp_flags & TCP_UGR_FLAG)
2568                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2569                 if (filter->tcp_flags & TCP_ACK_FLAG)
2570                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2571                 if (filter->tcp_flags & TCP_PSH_FLAG)
2572                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2573                 if (filter->tcp_flags & TCP_RST_FLAG)
2574                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2575                 if (filter->tcp_flags & TCP_SYN_FLAG)
2576                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2577                 if (filter->tcp_flags & TCP_FIN_FLAG)
2578                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2579                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2580         } else
2581                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2582         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2583         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2584         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2585         return 0;
2586 }
2587
2588 /*
2589  * remove a 2tuple filter
2590  *
2591  * @param
2592  * dev: Pointer to struct rte_eth_dev.
2593  * index: the index the filter allocates.
2594  *
2595  * @return
2596  *    - On success, zero.
2597  *    - On failure, a negative value.
2598  */
2599 static int
2600 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2601                         uint16_t index)
2602 {
2603         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604
2605         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2606
2607         if (index >= E1000_MAX_TTQF_FILTERS)
2608                 return -EINVAL;  /* filter index is out of range */
2609
2610         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2611         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2612         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2613         return 0;
2614 }
2615
2616 /*
2617  * get a 2tuple filter
2618  *
2619  * @param
2620  * dev: Pointer to struct rte_eth_dev.
2621  * index: the index the filter allocates.
2622  * filter: ponter to the filter that returns.
2623  * *rx_queue: pointer of the queue id the filter assigned to.
2624  *
2625  * @return
2626  *    - On success, zero.
2627  *    - On failure, a negative value.
2628  */
2629 static int
2630 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2631                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2632 {
2633         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634         uint32_t imir, ttqf, imir_ext;
2635
2636         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2637
2638         if (index >= E1000_MAX_TTQF_FILTERS)
2639                 return -EINVAL;  /* filter index is out of range. */
2640
2641         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2642         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2643                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2644                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2645                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2646                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2647                                 E1000_TTQF_QUEUE_SHIFT;
2648                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2649                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2650                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2651                         E1000_IMIR_PRIORITY_SHIFT;
2652
2653                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2654                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2655                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2656                                 filter->tcp_flags |= TCP_UGR_FLAG;
2657                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2658                                 filter->tcp_flags |= TCP_ACK_FLAG;
2659                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2660                                 filter->tcp_flags |= TCP_PSH_FLAG;
2661                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2662                                 filter->tcp_flags |= TCP_RST_FLAG;
2663                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2664                                 filter->tcp_flags |= TCP_SYN_FLAG;
2665                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2666                                 filter->tcp_flags |= TCP_FIN_FLAG;
2667                 } else
2668                         filter->tcp_flags = 0;
2669                 return 0;
2670         }
2671         return -ENOENT;
2672 }
2673
2674 static inline struct e1000_flex_filter *
2675 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2676                         struct e1000_flex_filter_info *key)
2677 {
2678         struct e1000_flex_filter *it;
2679
2680         TAILQ_FOREACH(it, filter_list, entries) {
2681                 if (memcmp(key, &it->filter_info,
2682                         sizeof(struct e1000_flex_filter_info)) == 0)
2683                         return it;
2684         }
2685
2686         return NULL;
2687 }
2688
2689 static int
2690 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2691                         struct rte_eth_flex_filter *filter,
2692                         bool add)
2693 {
2694         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2695         struct e1000_filter_info *filter_info =
2696                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2697         struct e1000_flex_filter *flex_filter, *it;
2698         uint32_t wufc, queueing, mask;
2699         uint32_t reg_off;
2700         uint8_t shift, i, j = 0;
2701
2702         flex_filter = rte_zmalloc("e1000_flex_filter",
2703                         sizeof(struct e1000_flex_filter), 0);
2704         if (flex_filter == NULL)
2705                 return -ENOMEM;
2706
2707         flex_filter->filter_info.len = filter->len;
2708         flex_filter->filter_info.priority = filter->priority;
2709         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2710         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2711                 mask = 0;
2712                 /* reverse bits in flex filter's mask*/
2713                 for (shift = 0; shift < CHAR_BIT; shift++) {
2714                         if (filter->mask[i] & (0x01 << shift))
2715                                 mask |= (0x80 >> shift);
2716                 }
2717                 flex_filter->filter_info.mask[i] = mask;
2718         }
2719
2720         wufc = E1000_READ_REG(hw, E1000_WUFC);
2721         if (flex_filter->index < E1000_MAX_FHFT)
2722                 reg_off = E1000_FHFT(flex_filter->index);
2723         else
2724                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2725
2726         if (add) {
2727                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2728                                 &flex_filter->filter_info) != NULL) {
2729                         PMD_DRV_LOG(ERR, "filter exists.");
2730                         rte_free(flex_filter);
2731                         return -EEXIST;
2732                 }
2733                 flex_filter->queue = filter->queue;
2734                 /*
2735                  * look for an unused flex filter index
2736                  * and insert the filter into the list.
2737                  */
2738                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2739                         if (!(filter_info->flex_mask & (1 << i))) {
2740                                 filter_info->flex_mask |= 1 << i;
2741                                 flex_filter->index = i;
2742                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2743                                         flex_filter,
2744                                         entries);
2745                                 break;
2746                         }
2747                 }
2748                 if (i >= E1000_MAX_FLEX_FILTERS) {
2749                         PMD_DRV_LOG(ERR, "flex filters are full.");
2750                         rte_free(flex_filter);
2751                         return -ENOSYS;
2752                 }
2753
2754                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2755                                 (E1000_WUFC_FLX0 << flex_filter->index));
2756                 queueing = filter->len |
2757                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2758                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2759                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2760                                 queueing);
2761                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2762                         E1000_WRITE_REG(hw, reg_off,
2763                                         flex_filter->filter_info.dwords[j]);
2764                         reg_off += sizeof(uint32_t);
2765                         E1000_WRITE_REG(hw, reg_off,
2766                                         flex_filter->filter_info.dwords[++j]);
2767                         reg_off += sizeof(uint32_t);
2768                         E1000_WRITE_REG(hw, reg_off,
2769                                 (uint32_t)flex_filter->filter_info.mask[i]);
2770                         reg_off += sizeof(uint32_t) * 2;
2771                         ++j;
2772                 }
2773         } else {
2774                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2775                                 &flex_filter->filter_info);
2776                 if (it == NULL) {
2777                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
2778                         rte_free(flex_filter);
2779                         return -ENOENT;
2780                 }
2781
2782                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
2783                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
2784                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
2785                         (~(E1000_WUFC_FLX0 << it->index)));
2786
2787                 filter_info->flex_mask &= ~(1 << it->index);
2788                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
2789                 rte_free(it);
2790                 rte_free(flex_filter);
2791         }
2792
2793         return 0;
2794 }
2795
2796 static int
2797 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
2798                         struct rte_eth_flex_filter *filter)
2799 {
2800         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801         struct e1000_filter_info *filter_info =
2802                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2803         struct e1000_flex_filter flex_filter, *it;
2804         uint32_t wufc, queueing, wufc_en = 0;
2805
2806         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
2807         flex_filter.filter_info.len = filter->len;
2808         flex_filter.filter_info.priority = filter->priority;
2809         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
2810         memcpy(flex_filter.filter_info.mask, filter->mask,
2811                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
2812
2813         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2814                                 &flex_filter.filter_info);
2815         if (it == NULL) {
2816                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2817                 return -ENOENT;
2818         }
2819
2820         wufc = E1000_READ_REG(hw, E1000_WUFC);
2821         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
2822
2823         if ((wufc & wufc_en) == wufc_en) {
2824                 uint32_t reg_off = 0;
2825                 if (it->index < E1000_MAX_FHFT)
2826                         reg_off = E1000_FHFT(it->index);
2827                 else
2828                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
2829
2830                 queueing = E1000_READ_REG(hw,
2831                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2832                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2833                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2834                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2835                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2836                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2837                 return 0;
2838         }
2839         return -ENOENT;
2840 }
2841
2842 static int
2843 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
2844                         enum rte_filter_op filter_op,
2845                         void *arg)
2846 {
2847         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848         struct rte_eth_flex_filter *filter;
2849         int ret = 0;
2850
2851         MAC_TYPE_FILTER_SUP(hw->mac.type);
2852
2853         if (filter_op == RTE_ETH_FILTER_NOP)
2854                 return ret;
2855
2856         if (arg == NULL) {
2857                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2858                             filter_op);
2859                 return -EINVAL;
2860         }
2861
2862         filter = (struct rte_eth_flex_filter *)arg;
2863         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
2864             || filter->len % sizeof(uint64_t) != 0) {
2865                 PMD_DRV_LOG(ERR, "filter's length is out of range");
2866                 return -EINVAL;
2867         }
2868         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
2869                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
2870                 return -EINVAL;
2871         }
2872
2873         switch (filter_op) {
2874         case RTE_ETH_FILTER_ADD:
2875                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
2876                 break;
2877         case RTE_ETH_FILTER_DELETE:
2878                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
2879                 break;
2880         case RTE_ETH_FILTER_GET:
2881                 ret = eth_igb_get_flex_filter(dev, filter);
2882                 break;
2883         default:
2884                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
2885                 ret = -EINVAL;
2886                 break;
2887         }
2888
2889         return ret;
2890 }
2891
2892 /*
2893  * add a 5tuple filter
2894  *
2895  * @param
2896  * dev: Pointer to struct rte_eth_dev.
2897  * index: the index the filter allocates.
2898  * filter: ponter to the filter that will be added.
2899  * rx_queue: the queue id the filter assigned to.
2900  *
2901  * @return
2902  *    - On success, zero.
2903  *    - On failure, a negative value.
2904  */
2905 static int
2906 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2907                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2908 {
2909         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910         uint32_t ftqf, spqf = 0;
2911         uint32_t imir = 0;
2912         uint32_t imir_ext = 0;
2913
2914         if (hw->mac.type != e1000_82576)
2915                 return -ENOSYS;
2916
2917         if (index >= E1000_MAX_FTQF_FILTERS ||
2918                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2919                 return -EINVAL;  /* filter index is out of range. */
2920
2921         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2922         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2923                 return -EINVAL;  /* filter index is in use. */
2924
2925         ftqf = 0;
2926         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2927         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2928                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2929         if (filter->dst_ip_mask == 1)
2930                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2931         if (filter->src_port_mask == 1)
2932                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2933         if (filter->protocol_mask == 1)
2934                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2935         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2936         ftqf |= E1000_FTQF_VF_MASK_EN;
2937         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2938         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2939         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2940         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2941
2942         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2943         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2944
2945         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2946         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2947                 imir |= E1000_IMIR_PORT_BP;
2948         else
2949                 imir &= ~E1000_IMIR_PORT_BP;
2950         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2951
2952         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2953         /* tcp flags bits setting. */
2954         if (filter->tcp_flags & TCP_FLAG_ALL) {
2955                 if (filter->tcp_flags & TCP_UGR_FLAG)
2956                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2957                 if (filter->tcp_flags & TCP_ACK_FLAG)
2958                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2959                 if (filter->tcp_flags & TCP_PSH_FLAG)
2960                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2961                 if (filter->tcp_flags & TCP_RST_FLAG)
2962                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2963                 if (filter->tcp_flags & TCP_SYN_FLAG)
2964                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2965                 if (filter->tcp_flags & TCP_FIN_FLAG)
2966                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2967         } else
2968                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2969         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2970         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2971         return 0;
2972 }
2973
2974 /*
2975  * remove a 5tuple filter
2976  *
2977  * @param
2978  * dev: Pointer to struct rte_eth_dev.
2979  * index: the index the filter allocates
2980  *
2981  * @return
2982  *    - On success, zero.
2983  *    - On failure, a negative value.
2984  */
2985 static int
2986 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2987                                 uint16_t index)
2988 {
2989         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2990
2991         if (hw->mac.type != e1000_82576)
2992                 return -ENOSYS;
2993
2994         if (index >= E1000_MAX_FTQF_FILTERS)
2995                 return -EINVAL;  /* filter index is out of range. */
2996
2997         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2998         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2999         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
3000         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
3001         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
3002         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
3003         return 0;
3004 }
3005
3006 /*
3007  * get a 5tuple filter
3008  *
3009  * @param
3010  * dev: Pointer to struct rte_eth_dev.
3011  * index: the index the filter allocates
3012  * filter: ponter to the filter that returns
3013  * *rx_queue: pointer of the queue id the filter assigned to
3014  *
3015  * @return
3016  *    - On success, zero.
3017  *    - On failure, a negative value.
3018  */
3019 static int
3020 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3021                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3022 {
3023         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3024         uint32_t spqf, ftqf, imir, imir_ext;
3025
3026         if (hw->mac.type != e1000_82576)
3027                 return -ENOSYS;
3028
3029         if (index >= E1000_MAX_FTQF_FILTERS)
3030                 return -EINVAL;  /* filter index is out of range. */
3031
3032         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
3033         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
3034                 filter->src_ip_mask =
3035                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3036                 filter->dst_ip_mask =
3037                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3038                 filter->src_port_mask =
3039                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3040                 filter->protocol_mask =
3041                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3042                 filter->protocol =
3043                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
3044                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
3045                                 E1000_FTQF_QUEUE_SHIFT);
3046
3047                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
3048                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
3049
3050                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
3051                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
3052
3053                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
3054                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
3055                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
3056                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
3057                         E1000_IMIR_PRIORITY_SHIFT;
3058
3059                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
3060                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
3061                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
3062                                 filter->tcp_flags |= TCP_UGR_FLAG;
3063                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
3064                                 filter->tcp_flags |= TCP_ACK_FLAG;
3065                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
3066                                 filter->tcp_flags |= TCP_PSH_FLAG;
3067                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
3068                                 filter->tcp_flags |= TCP_RST_FLAG;
3069                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3070                                 filter->tcp_flags |= TCP_SYN_FLAG;
3071                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3072                                 filter->tcp_flags |= TCP_FIN_FLAG;
3073                 } else
3074                         filter->tcp_flags = 0;
3075                 return 0;
3076         }
3077         return -ENOENT;
3078 }
3079
3080 static int
3081 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3082 {
3083         uint32_t rctl;
3084         struct e1000_hw *hw;
3085         struct rte_eth_dev_info dev_info;
3086         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3087                                      VLAN_TAG_SIZE);
3088
3089         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3090
3091 #ifdef RTE_LIBRTE_82571_SUPPORT
3092         /* XXX: not bigger than max_rx_pktlen */
3093         if (hw->mac.type == e1000_82571)
3094                 return -ENOTSUP;
3095 #endif
3096         eth_igb_infos_get(dev, &dev_info);
3097
3098         /* check that mtu is within the allowed range */
3099         if ((mtu < ETHER_MIN_MTU) ||
3100             (frame_size > dev_info.max_rx_pktlen))
3101                 return -EINVAL;
3102
3103         /* refuse mtu that requires the support of scattered packets when this
3104          * feature has not been enabled before. */
3105         if (!dev->data->scattered_rx &&
3106             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3107                 return -EINVAL;
3108
3109         rctl = E1000_READ_REG(hw, E1000_RCTL);
3110
3111         /* switch to jumbo mode if needed */
3112         if (frame_size > ETHER_MAX_LEN) {
3113                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3114                 rctl |= E1000_RCTL_LPE;
3115         } else {
3116                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3117                 rctl &= ~E1000_RCTL_LPE;
3118         }
3119         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3120
3121         /* update max frame size */
3122         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3123
3124         E1000_WRITE_REG(hw, E1000_RLPML,
3125                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3126
3127         return 0;
3128 }
3129
3130 static inline int
3131 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3132                         uint16_t ethertype)
3133 {
3134         int i;
3135
3136         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3137                 if (filter_info->ethertype_filters[i] == ethertype &&
3138                     (filter_info->ethertype_mask & (1 << i)))
3139                         return i;
3140         }
3141         return -1;
3142 }
3143
3144 static inline int
3145 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3146                         uint16_t ethertype)
3147 {
3148         int i;
3149
3150         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3151                 if (!(filter_info->ethertype_mask & (1 << i))) {
3152                         filter_info->ethertype_mask |= 1 << i;
3153                         filter_info->ethertype_filters[i] = ethertype;
3154                         return i;
3155                 }
3156         }
3157         return -1;
3158 }
3159
3160 static inline int
3161 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3162                         uint8_t idx)
3163 {
3164         if (idx >= E1000_MAX_ETQF_FILTERS)
3165                 return -1;
3166         filter_info->ethertype_mask &= ~(1 << idx);
3167         filter_info->ethertype_filters[idx] = 0;
3168         return idx;
3169 }
3170
3171
3172 static int
3173 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3174                         struct rte_eth_ethertype_filter *filter,
3175                         bool add)
3176 {
3177         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178         struct e1000_filter_info *filter_info =
3179                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3180         uint32_t etqf = 0;
3181         int ret;
3182
3183         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3184                 filter->ether_type == ETHER_TYPE_IPv6) {
3185                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3186                         " ethertype filter.", filter->ether_type);
3187                 return -EINVAL;
3188         }
3189
3190         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3191                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3192                 return -EINVAL;
3193         }
3194         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3195                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3196                 return -EINVAL;
3197         }
3198
3199         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3200         if (ret >= 0 && add) {
3201                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3202                             filter->ether_type);
3203                 return -EEXIST;
3204         }
3205         if (ret < 0 && !add) {
3206                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3207                             filter->ether_type);
3208                 return -ENOENT;
3209         }
3210
3211         if (add) {
3212                 ret = igb_ethertype_filter_insert(filter_info,
3213                         filter->ether_type);
3214                 if (ret < 0) {
3215                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3216                         return -ENOSYS;
3217                 }
3218
3219                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3220                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3221                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3222         } else {
3223                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3224                 if (ret < 0)
3225                         return -ENOSYS;
3226         }
3227         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3228         E1000_WRITE_FLUSH(hw);
3229
3230         return 0;
3231 }
3232
3233 static int
3234 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3235                         struct rte_eth_ethertype_filter *filter)
3236 {
3237         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238         struct e1000_filter_info *filter_info =
3239                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3240         uint32_t etqf;
3241         int ret;
3242
3243         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3244         if (ret < 0) {
3245                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3246                             filter->ether_type);
3247                 return -ENOENT;
3248         }
3249
3250         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3251         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3252                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3253                 filter->flags = 0;
3254                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3255                                 E1000_ETQF_QUEUE_SHIFT;
3256                 return 0;
3257         }
3258
3259         return -ENOENT;
3260 }
3261
3262 /*
3263  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3264  * @dev: pointer to rte_eth_dev structure
3265  * @filter_op:operation will be taken.
3266  * @arg: a pointer to specific structure corresponding to the filter_op
3267  */
3268 static int
3269 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3270                                 enum rte_filter_op filter_op,
3271                                 void *arg)
3272 {
3273         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274         int ret;
3275
3276         MAC_TYPE_FILTER_SUP(hw->mac.type);
3277
3278         if (filter_op == RTE_ETH_FILTER_NOP)
3279                 return 0;
3280
3281         if (arg == NULL) {
3282                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3283                             filter_op);
3284                 return -EINVAL;
3285         }
3286
3287         switch (filter_op) {
3288         case RTE_ETH_FILTER_ADD:
3289                 ret = igb_add_del_ethertype_filter(dev,
3290                         (struct rte_eth_ethertype_filter *)arg,
3291                         TRUE);
3292                 break;
3293         case RTE_ETH_FILTER_DELETE:
3294                 ret = igb_add_del_ethertype_filter(dev,
3295                         (struct rte_eth_ethertype_filter *)arg,
3296                         FALSE);
3297                 break;
3298         case RTE_ETH_FILTER_GET:
3299                 ret = igb_get_ethertype_filter(dev,
3300                         (struct rte_eth_ethertype_filter *)arg);
3301                 break;
3302         default:
3303                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3304                 ret = -EINVAL;
3305                 break;
3306         }
3307         return ret;
3308 }
3309
3310 static int
3311 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3312                      enum rte_filter_type filter_type,
3313                      enum rte_filter_op filter_op,
3314                      void *arg)
3315 {
3316         int ret = -EINVAL;
3317
3318         switch (filter_type) {
3319         case RTE_ETH_FILTER_ETHERTYPE:
3320                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3321                 break;
3322         case RTE_ETH_FILTER_SYN:
3323                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3324                 break;
3325         case RTE_ETH_FILTER_FLEXIBLE:
3326                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3327                 break;
3328         default:
3329                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3330                                                         filter_type);
3331                 break;
3332         }
3333
3334         return ret;
3335 }
3336
3337 static struct rte_driver pmd_igb_drv = {
3338         .type = PMD_PDEV,
3339         .init = rte_igb_pmd_init,
3340 };
3341
3342 static struct rte_driver pmd_igbvf_drv = {
3343         .type = PMD_PDEV,
3344         .init = rte_igbvf_pmd_init,
3345 };
3346
3347 PMD_REGISTER_DRIVER(pmd_igb_drv);
3348 PMD_REGISTER_DRIVER(pmd_igbvf_drv);