4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
41 #include <rte_common.h>
42 #include <rte_interrupts.h>
43 #include <rte_byteorder.h>
45 #include <rte_debug.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
51 #include <rte_tailq.h>
53 #include <rte_atomic.h>
54 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
60 static int eth_igb_configure(struct rte_eth_dev *dev);
61 static int eth_igb_start(struct rte_eth_dev *dev);
62 static void eth_igb_stop(struct rte_eth_dev *dev);
63 static void eth_igb_close(struct rte_eth_dev *dev);
64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
68 static int eth_igb_link_update(struct rte_eth_dev *dev,
69 int wait_to_complete);
70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
71 struct rte_eth_stats *rte_stats);
72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
74 struct rte_eth_dev_info *dev_info);
75 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
76 struct rte_eth_fc_conf *fc_conf);
77 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
82 static int igb_hardware_init(struct e1000_hw *hw);
83 static void igb_hw_control_acquire(struct e1000_hw *hw);
84 static void igb_hw_control_release(struct e1000_hw *hw);
85 static void igb_init_manageability(struct e1000_hw *hw);
86 static void igb_release_manageability(struct e1000_hw *hw);
88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
89 uint16_t vlan_id, int on);
90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
100 static int eth_igb_led_on(struct rte_eth_dev *dev);
101 static int eth_igb_led_off(struct rte_eth_dev *dev);
103 static void igb_intr_disable(struct e1000_hw *hw);
104 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
106 struct ether_addr *mac_addr,
107 uint32_t index, uint32_t pool);
108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
110 static void igbvf_intr_disable(struct e1000_hw *hw);
111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
112 static int igbvf_dev_start(struct rte_eth_dev *dev);
113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
114 static void igbvf_dev_close(struct rte_eth_dev *dev);
115 static int eth_igbvf_link_update(struct e1000_hw *hw);
116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
119 uint16_t vlan_id, int on);
120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
124 * Define VF Stats MACRO for Non "cleared on read" register
126 #define UPDATE_VF_STAT(reg, last, cur) \
128 u32 latest = E1000_READ_REG(hw, reg); \
129 cur += latest - last; \
134 #define IGB_FC_PAUSE_TIME 0x0680
135 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
136 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
138 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
141 * The set of PCI devices this driver supports
143 static struct rte_pci_id pci_id_igb_map[] = {
145 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
146 #include "rte_pci_dev_ids.h"
152 * The set of PCI devices this driver supports (for 82576&I350 VF)
154 static struct rte_pci_id pci_id_igbvf_map[] = {
156 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
157 #include "rte_pci_dev_ids.h"
162 static struct eth_dev_ops eth_igb_ops = {
163 .dev_configure = eth_igb_configure,
164 .dev_start = eth_igb_start,
165 .dev_stop = eth_igb_stop,
166 .dev_close = eth_igb_close,
167 .promiscuous_enable = eth_igb_promiscuous_enable,
168 .promiscuous_disable = eth_igb_promiscuous_disable,
169 .allmulticast_enable = eth_igb_allmulticast_enable,
170 .allmulticast_disable = eth_igb_allmulticast_disable,
171 .link_update = eth_igb_link_update,
172 .stats_get = eth_igb_stats_get,
173 .stats_reset = eth_igb_stats_reset,
174 .dev_infos_get = eth_igb_infos_get,
175 .vlan_filter_set = eth_igb_vlan_filter_set,
176 .vlan_tpid_set = eth_igb_vlan_tpid_set,
177 .vlan_offload_set = eth_igb_vlan_offload_set,
178 .rx_queue_setup = eth_igb_rx_queue_setup,
179 .rx_queue_release = eth_igb_rx_queue_release,
180 .tx_queue_setup = eth_igb_tx_queue_setup,
181 .tx_queue_release = eth_igb_tx_queue_release,
182 .dev_led_on = eth_igb_led_on,
183 .dev_led_off = eth_igb_led_off,
184 .flow_ctrl_set = eth_igb_flow_ctrl_set,
185 .mac_addr_add = eth_igb_rar_set,
186 .mac_addr_remove = eth_igb_rar_clear,
190 * dev_ops for virtual function, bare necessities for basic vf
191 * operation have been implemented
193 static struct eth_dev_ops igbvf_eth_dev_ops = {
194 .dev_configure = igbvf_dev_configure,
195 .dev_start = igbvf_dev_start,
196 .dev_stop = igbvf_dev_stop,
197 .dev_close = igbvf_dev_close,
198 .link_update = eth_igb_link_update,
199 .stats_get = eth_igbvf_stats_get,
200 .stats_reset = eth_igbvf_stats_reset,
201 .vlan_filter_set = igbvf_vlan_filter_set,
202 .dev_infos_get = eth_igb_infos_get,
203 .rx_queue_setup = eth_igb_rx_queue_setup,
204 .rx_queue_release = eth_igb_rx_queue_release,
205 .tx_queue_setup = eth_igb_tx_queue_setup,
206 .tx_queue_release = eth_igb_tx_queue_release,
210 * Atomically reads the link status information from global
211 * structure rte_eth_dev.
214 * - Pointer to the structure rte_eth_dev to read from.
215 * - Pointer to the buffer to be saved with the link status.
218 * - On success, zero.
219 * - On failure, negative value.
222 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
223 struct rte_eth_link *link)
225 struct rte_eth_link *dst = link;
226 struct rte_eth_link *src = &(dev->data->dev_link);
228 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
229 *(uint64_t *)src) == 0)
236 * Atomically writes the link status information into global
237 * structure rte_eth_dev.
240 * - Pointer to the structure rte_eth_dev to read from.
241 * - Pointer to the buffer to be saved with the link status.
244 * - On success, zero.
245 * - On failure, negative value.
248 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
249 struct rte_eth_link *link)
251 struct rte_eth_link *dst = &(dev->data->dev_link);
252 struct rte_eth_link *src = link;
254 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
255 *(uint64_t *)src) == 0)
262 igb_identify_hardware(struct rte_eth_dev *dev)
264 struct e1000_hw *hw =
265 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
267 hw->vendor_id = dev->pci_dev->id.vendor_id;
268 hw->device_id = dev->pci_dev->id.device_id;
269 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
270 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
272 e1000_set_mac_type(hw);
274 /* need to check if it is a vf device below */
278 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
279 struct rte_eth_dev *eth_dev)
282 struct rte_pci_device *pci_dev;
283 struct e1000_hw *hw =
284 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
285 struct e1000_vfta * shadow_vfta =
286 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
288 pci_dev = eth_dev->pci_dev;
289 eth_dev->dev_ops = ð_igb_ops;
290 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
291 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
293 /* for secondary processes, we don't initialise any further as primary
294 * has already done this work. Only check we don't need a different
296 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
297 if (eth_dev->data->scattered_rx)
298 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
302 hw->hw_addr= (void *)pci_dev->mem_resource.addr;
304 igb_identify_hardware(eth_dev);
306 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
311 e1000_get_bus_info(hw);
314 hw->phy.autoneg_wait_to_complete = 0;
315 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
318 if (hw->phy.media_type == e1000_media_type_copper) {
319 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
320 hw->phy.disable_polarity_correction = 0;
321 hw->phy.ms_type = e1000_ms_hw_default;
325 * Start from a known state, this is important in reading the nvm
330 /* Make sure we have a good EEPROM before we read from it */
331 if (e1000_validate_nvm_checksum(hw) < 0) {
333 * Some PCI-E parts fail the first check due to
334 * the link being in sleep state, call it again,
335 * if it fails a second time its a real issue.
337 if (e1000_validate_nvm_checksum(hw) < 0) {
338 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
344 /* Read the permanent MAC address out of the EEPROM */
345 if (e1000_read_mac_addr(hw) != 0) {
346 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
351 /* Allocate memory for storing MAC addresses */
352 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
353 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
354 if (eth_dev->data->mac_addrs == NULL) {
355 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
356 "store MAC addresses",
357 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
362 /* Copy the permanent MAC address */
363 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
365 /* initialize the vfta */
366 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
368 /* Now initialize the hardware */
369 if (igb_hardware_init(hw) != 0) {
370 PMD_INIT_LOG(ERR, "Hardware initialization failed");
371 rte_free(eth_dev->data->mac_addrs);
372 eth_dev->data->mac_addrs = NULL;
376 hw->mac.get_link_status = 1;
378 /* Indicate SOL/IDER usage */
379 if (e1000_check_reset_block(hw) < 0) {
380 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
384 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
385 eth_dev->data->port_id, pci_dev->id.vendor_id,
386 pci_dev->id.device_id);
388 rte_intr_callback_register(&(pci_dev->intr_handle),
389 eth_igb_interrupt_handler, (void *)eth_dev);
394 igb_hw_control_release(hw);
400 * Virtual Function device init
403 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
404 struct rte_eth_dev *eth_dev)
406 struct rte_pci_device *pci_dev;
407 struct e1000_hw *hw =
408 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
411 PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
413 eth_dev->dev_ops = &igbvf_eth_dev_ops;
414 pci_dev = eth_dev->pci_dev;
416 hw->device_id = pci_dev->id.device_id;
417 hw->vendor_id = pci_dev->id.vendor_id;
418 hw->hw_addr = (void *)pci_dev->mem_resource.addr;
420 /* Initialize the shared code */
421 diag = e1000_setup_init_funcs(hw, TRUE);
423 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
428 /* init_mailbox_params */
429 hw->mbx.ops.init_params(hw);
431 /* Disable the interrupts for VF */
432 igbvf_intr_disable(hw);
434 diag = hw->mac.ops.reset_hw(hw);
436 /* Allocate memory for storing MAC addresses */
437 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
438 hw->mac.rar_entry_count, 0);
439 if (eth_dev->data->mac_addrs == NULL) {
441 "Failed to allocate %d bytes needed to store MAC "
443 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
446 /* Copy the permanent MAC address */
447 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
448 ð_dev->data->mac_addrs[0]);
450 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
452 eth_dev->data->port_id, pci_dev->id.vendor_id,
453 pci_dev->id.device_id,
459 static struct eth_driver rte_igb_pmd = {
461 .name = "rte_igb_pmd",
462 .id_table = pci_id_igb_map,
463 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
465 .eth_dev_init = eth_igb_dev_init,
466 .dev_private_size = sizeof(struct e1000_adapter),
470 * virtual function driver struct
472 static struct eth_driver rte_igbvf_pmd = {
474 .name = "rte_igbvf_pmd",
475 .id_table = pci_id_igbvf_map,
476 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
478 .eth_dev_init = eth_igbvf_dev_init,
479 .dev_private_size = sizeof(struct e1000_adapter),
483 rte_igb_pmd_init(void)
485 rte_eth_driver_register(&rte_igb_pmd);
490 * VF Driver initialization routine.
491 * Invoked one at EAL init time.
492 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
495 rte_igbvf_pmd_init(void)
497 DEBUGFUNC("rte_igbvf_pmd_init");
499 rte_eth_driver_register(&rte_igbvf_pmd);
504 eth_igb_configure(struct rte_eth_dev *dev)
506 struct e1000_interrupt *intr =
507 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
509 PMD_INIT_LOG(DEBUG, ">>");
511 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
513 PMD_INIT_LOG(DEBUG, "<<");
519 eth_igb_start(struct rte_eth_dev *dev)
521 struct e1000_hw *hw =
522 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
525 PMD_INIT_LOG(DEBUG, ">>");
527 igb_intr_disable(hw);
529 /* Power up the phy. Needed to make the link go Up */
530 e1000_power_up_phy(hw);
533 * Packet Buffer Allocation (PBA)
534 * Writing PBA sets the receive portion of the buffer
535 * the remainder is used for the transmit buffer.
537 if (hw->mac.type == e1000_82575) {
540 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
541 E1000_WRITE_REG(hw, E1000_PBA, pba);
544 /* Put the address into the Receive Address Array */
545 e1000_rar_set(hw, hw->mac.addr, 0);
547 /* Initialize the hardware */
548 if (igb_hardware_init(hw)) {
549 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
553 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
555 /* Configure for OS presence */
556 igb_init_manageability(hw);
558 eth_igb_tx_init(dev);
560 /* This can fail when allocating mbufs for descriptor rings */
561 ret = eth_igb_rx_init(dev);
563 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
564 igb_dev_clear_queues(dev);
568 e1000_clear_hw_cntrs_base_generic(hw);
571 * VLAN Offload Settings
573 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
574 ETH_VLAN_EXTEND_MASK;
575 eth_igb_vlan_offload_set(dev, mask);
578 * Configure the Interrupt Moderation register (EITR) with the maximum
579 * possible value (0xFFFF) to minimize "System Partial Write" issued by
580 * spurious [DMA] memory updates of RX and TX ring descriptors.
582 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
583 * spurious memory updates per second should be expected.
584 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
586 * Because interrupts are not used at all, the MSI-X is not activated
587 * and interrupt moderation is controlled by EITR[0].
589 * Note that having [almost] disabled memory updates of RX and TX ring
590 * descriptors through the Interrupt Moderation mechanism, memory
591 * updates of ring descriptors are now moderated by the configurable
592 * value of Write-Back Threshold registers.
594 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
595 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
598 /* Enable all RX & TX queues in the IVAR registers */
599 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
600 for (i = 0; i < 8; i++)
601 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
603 /* Configure EITR with the maximum possible value (0xFFFF) */
604 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
607 /* Setup link speed and duplex */
608 switch (dev->data->dev_conf.link_speed) {
609 case ETH_LINK_SPEED_AUTONEG:
610 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
611 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
612 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
613 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
614 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
615 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
617 goto error_invalid_config;
619 case ETH_LINK_SPEED_10:
620 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
621 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
622 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
623 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
624 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
625 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
627 goto error_invalid_config;
629 case ETH_LINK_SPEED_100:
630 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
631 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
632 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
633 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
634 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
635 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
637 goto error_invalid_config;
639 case ETH_LINK_SPEED_1000:
640 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
641 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
642 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
644 goto error_invalid_config;
646 case ETH_LINK_SPEED_10000:
648 goto error_invalid_config;
650 e1000_setup_link(hw);
652 /* check if lsc interrupt feature is enabled */
653 if (dev->data->dev_conf.intr_conf.lsc != 0) {
654 ret = eth_igb_interrupt_setup(dev);
656 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
657 igb_dev_clear_queues(dev);
662 PMD_INIT_LOG(DEBUG, "<<");
666 error_invalid_config:
667 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
668 dev->data->dev_conf.link_speed,
669 dev->data->dev_conf.link_duplex, dev->data->port_id);
670 igb_dev_clear_queues(dev);
674 /*********************************************************************
676 * This routine disables all traffic on the adapter by issuing a
677 * global reset on the MAC.
679 **********************************************************************/
681 eth_igb_stop(struct rte_eth_dev *dev)
683 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
684 struct rte_eth_link link;
686 igb_intr_disable(hw);
688 E1000_WRITE_REG(hw, E1000_WUC, 0);
690 /* Power down the phy. Needed to make the link go Down */
691 e1000_power_down_phy(hw);
693 igb_dev_clear_queues(dev);
695 /* clear the recorded link status */
696 memset(&link, 0, sizeof(link));
697 rte_igb_dev_atomic_write_link_status(dev, &link);
701 eth_igb_close(struct rte_eth_dev *dev)
703 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
704 struct rte_eth_link link;
707 e1000_phy_hw_reset(hw);
708 igb_release_manageability(hw);
709 igb_hw_control_release(hw);
711 igb_dev_clear_queues(dev);
713 memset(&link, 0, sizeof(link));
714 rte_igb_dev_atomic_write_link_status(dev, &link);
718 igb_get_rx_buffer_size(struct e1000_hw *hw)
720 uint32_t rx_buf_size;
721 if (hw->mac.type == e1000_82576) {
722 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
723 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
724 /* PBS needs to be translated according to a lookup table */
725 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
726 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
727 rx_buf_size = (rx_buf_size << 10);
728 } else if (hw->mac.type == e1000_i210) {
729 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
731 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
737 /*********************************************************************
739 * Initialize the hardware
741 **********************************************************************/
743 igb_hardware_init(struct e1000_hw *hw)
745 uint32_t rx_buf_size;
748 /* Let the firmware know the OS is in control */
749 igb_hw_control_acquire(hw);
752 * These parameters control the automatic generation (Tx) and
753 * response (Rx) to Ethernet PAUSE frames.
754 * - High water mark should allow for at least two standard size (1518)
755 * frames to be received after sending an XOFF.
756 * - Low water mark works best when it is very near the high water mark.
757 * This allows the receiver to restart by sending XON when it has
758 * drained a bit. Here we use an arbitary value of 1500 which will
759 * restart after one full frame is pulled from the buffer. There
760 * could be several smaller frames in the buffer and if so they will
761 * not trigger the XON until their total number reduces the buffer
763 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
765 rx_buf_size = igb_get_rx_buffer_size(hw);
767 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
768 hw->fc.low_water = hw->fc.high_water - 1500;
769 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
772 /* Set Flow control, use the tunable location if sane */
773 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
774 hw->fc.requested_mode = igb_fc_setting;
776 hw->fc.requested_mode = e1000_fc_none;
778 /* Issue a global reset */
780 E1000_WRITE_REG(hw, E1000_WUC, 0);
782 diag = e1000_init_hw(hw);
786 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
787 e1000_get_phy_info(hw);
788 e1000_check_for_link(hw);
793 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
795 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
797 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
798 struct e1000_hw_stats *stats =
799 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
802 if(hw->phy.media_type == e1000_media_type_copper ||
803 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
805 E1000_READ_REG(hw,E1000_SYMERRS);
806 stats->sec += E1000_READ_REG(hw, E1000_SEC);
809 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
810 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
811 stats->scc += E1000_READ_REG(hw, E1000_SCC);
812 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
814 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
815 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
816 stats->colc += E1000_READ_REG(hw, E1000_COLC);
817 stats->dc += E1000_READ_REG(hw, E1000_DC);
818 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
819 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
820 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
822 ** For watchdog management we need to know if we have been
823 ** paused during the last interval, so capture that here.
825 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
826 stats->xoffrxc += pause_frames;
827 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
828 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
829 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
830 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
831 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
832 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
833 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
834 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
835 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
836 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
837 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
838 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
840 /* For the 64-bit byte counters the low dword must be read first. */
841 /* Both registers clear on the read of the high dword */
843 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
844 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
845 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
846 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
848 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
849 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
850 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
851 stats->roc += E1000_READ_REG(hw, E1000_ROC);
852 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
854 stats->tor += E1000_READ_REG(hw, E1000_TORH);
855 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
857 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
858 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
859 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
860 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
861 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
862 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
863 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
864 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
865 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
866 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
868 /* Interrupt Counts */
870 stats->iac += E1000_READ_REG(hw, E1000_IAC);
871 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
872 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
873 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
874 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
875 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
876 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
877 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
878 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
880 /* Host to Card Statistics */
882 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
883 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
884 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
885 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
886 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
887 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
888 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
889 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
890 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
891 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
892 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
893 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
894 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
895 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
897 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
898 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
899 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
900 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
901 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
902 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
904 if (rte_stats == NULL)
908 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
909 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
912 rte_stats->oerrors = stats->ecol + stats->latecol;
914 rte_stats->ipackets = stats->gprc;
915 rte_stats->opackets = stats->gptc;
916 rte_stats->ibytes = stats->gorc;
917 rte_stats->obytes = stats->gotc;
921 eth_igb_stats_reset(struct rte_eth_dev *dev)
923 struct e1000_hw_stats *hw_stats =
924 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
926 /* HW registers are cleared on read */
927 eth_igb_stats_get(dev, NULL);
929 /* Reset software totals */
930 memset(hw_stats, 0, sizeof(*hw_stats));
934 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
936 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
937 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
938 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
940 /* Good Rx packets, include VF loopback */
941 UPDATE_VF_STAT(E1000_VFGPRC,
942 hw_stats->last_gprc, hw_stats->gprc);
944 /* Good Rx octets, include VF loopback */
945 UPDATE_VF_STAT(E1000_VFGORC,
946 hw_stats->last_gorc, hw_stats->gorc);
948 /* Good Tx packets, include VF loopback */
949 UPDATE_VF_STAT(E1000_VFGPTC,
950 hw_stats->last_gptc, hw_stats->gptc);
952 /* Good Tx octets, include VF loopback */
953 UPDATE_VF_STAT(E1000_VFGOTC,
954 hw_stats->last_gotc, hw_stats->gotc);
956 /* Rx Multicst packets */
957 UPDATE_VF_STAT(E1000_VFMPRC,
958 hw_stats->last_mprc, hw_stats->mprc);
960 /* Good Rx loopback packets */
961 UPDATE_VF_STAT(E1000_VFGPRLBC,
962 hw_stats->last_gprlbc, hw_stats->gprlbc);
964 /* Good Rx loopback octets */
965 UPDATE_VF_STAT(E1000_VFGORLBC,
966 hw_stats->last_gorlbc, hw_stats->gorlbc);
968 /* Good Tx loopback packets */
969 UPDATE_VF_STAT(E1000_VFGPTLBC,
970 hw_stats->last_gptlbc, hw_stats->gptlbc);
972 /* Good Tx loopback octets */
973 UPDATE_VF_STAT(E1000_VFGOTLBC,
974 hw_stats->last_gotlbc, hw_stats->gotlbc);
976 if (rte_stats == NULL)
979 memset(rte_stats, 0, sizeof(*rte_stats));
980 rte_stats->ipackets = hw_stats->gprc;
981 rte_stats->ibytes = hw_stats->gorc;
982 rte_stats->opackets = hw_stats->gptc;
983 rte_stats->obytes = hw_stats->gotc;
984 rte_stats->imcasts = hw_stats->mprc;
985 rte_stats->ilbpackets = hw_stats->gprlbc;
986 rte_stats->ilbbytes = hw_stats->gorlbc;
987 rte_stats->olbpackets = hw_stats->gptlbc;
988 rte_stats->olbbytes = hw_stats->gotlbc;
993 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
995 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
996 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
998 /* Sync HW register to the last stats */
999 eth_igbvf_stats_get(dev, NULL);
1001 /* reset HW current stats*/
1002 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1003 offsetof(struct e1000_vf_stats, gprc));
1008 eth_igb_infos_get(struct rte_eth_dev *dev,
1009 struct rte_eth_dev_info *dev_info)
1011 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1013 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1014 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1015 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1017 switch (hw->mac.type) {
1019 dev_info->max_rx_queues = 4;
1020 dev_info->max_tx_queues = 4;
1024 dev_info->max_rx_queues = 16;
1025 dev_info->max_tx_queues = 16;
1029 dev_info->max_rx_queues = 8;
1030 dev_info->max_tx_queues = 8;
1034 dev_info->max_rx_queues = 8;
1035 dev_info->max_tx_queues = 8;
1039 dev_info->max_rx_queues = 4;
1040 dev_info->max_tx_queues = 4;
1044 dev_info->max_rx_queues = 2;
1045 dev_info->max_tx_queues = 2;
1048 case e1000_vfadapt_i350:
1049 dev_info->max_rx_queues = 1;
1050 dev_info->max_tx_queues = 1;
1054 /* Should not happen */
1055 dev_info->max_rx_queues = 0;
1056 dev_info->max_tx_queues = 0;
1060 /* return 0 means link status changed, -1 means not changed */
1062 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1064 struct e1000_hw *hw =
1065 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1066 struct rte_eth_link link, old;
1067 int link_check, count;
1070 hw->mac.get_link_status = 1;
1072 /* possible wait-to-complete in up to 9 seconds */
1073 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1074 /* Read the real link status */
1075 switch (hw->phy.media_type) {
1076 case e1000_media_type_copper:
1077 /* Do the work to read phy */
1078 e1000_check_for_link(hw);
1079 link_check = !hw->mac.get_link_status;
1082 case e1000_media_type_fiber:
1083 e1000_check_for_link(hw);
1084 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1088 case e1000_media_type_internal_serdes:
1089 e1000_check_for_link(hw);
1090 link_check = hw->mac.serdes_has_link;
1093 /* VF device is type_unknown */
1094 case e1000_media_type_unknown:
1095 eth_igbvf_link_update(hw);
1096 link_check = !hw->mac.get_link_status;
1102 if (link_check || wait_to_complete == 0)
1104 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1106 memset(&link, 0, sizeof(link));
1107 rte_igb_dev_atomic_read_link_status(dev, &link);
1110 /* Now we check if a transition has happened */
1112 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1114 link.link_status = 1;
1115 } else if (!link_check) {
1116 link.link_speed = 0;
1117 link.link_duplex = 0;
1118 link.link_status = 0;
1120 rte_igb_dev_atomic_write_link_status(dev, &link);
1123 if (old.link_status == link.link_status)
1131 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1132 * For ASF and Pass Through versions of f/w this means
1133 * that the driver is loaded.
1136 igb_hw_control_acquire(struct e1000_hw *hw)
1140 /* Let firmware know the driver has taken over */
1141 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1142 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1146 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1147 * For ASF and Pass Through versions of f/w this means that the
1148 * driver is no longer loaded.
1151 igb_hw_control_release(struct e1000_hw *hw)
1155 /* Let firmware taken over control of h/w */
1156 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1157 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1158 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1162 * Bit of a misnomer, what this really means is
1163 * to enable OS management of the system... aka
1164 * to disable special hardware management features.
1167 igb_init_manageability(struct e1000_hw *hw)
1169 if (e1000_enable_mng_pass_thru(hw)) {
1170 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1171 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1173 /* disable hardware interception of ARP */
1174 manc &= ~(E1000_MANC_ARP_EN);
1176 /* enable receiving management packets to the host */
1177 manc |= E1000_MANC_EN_MNG2HOST;
1178 manc2h |= 1 << 5; /* Mng Port 623 */
1179 manc2h |= 1 << 6; /* Mng Port 664 */
1180 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1181 E1000_WRITE_REG(hw, E1000_MANC, manc);
1186 igb_release_manageability(struct e1000_hw *hw)
1188 if (e1000_enable_mng_pass_thru(hw)) {
1189 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1191 manc |= E1000_MANC_ARP_EN;
1192 manc &= ~E1000_MANC_EN_MNG2HOST;
1194 E1000_WRITE_REG(hw, E1000_MANC, manc);
1199 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1201 struct e1000_hw *hw =
1202 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 rctl = E1000_READ_REG(hw, E1000_RCTL);
1206 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1207 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1211 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1213 struct e1000_hw *hw =
1214 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217 rctl = E1000_READ_REG(hw, E1000_RCTL);
1218 rctl &= (~E1000_RCTL_UPE);
1219 if (dev->data->all_multicast == 1)
1220 rctl |= E1000_RCTL_MPE;
1222 rctl &= (~E1000_RCTL_MPE);
1223 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1227 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1229 struct e1000_hw *hw =
1230 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1233 rctl = E1000_READ_REG(hw, E1000_RCTL);
1234 rctl |= E1000_RCTL_MPE;
1235 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1239 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1241 struct e1000_hw *hw =
1242 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245 if (dev->data->promiscuous == 1)
1246 return; /* must remain in all_multicast mode */
1247 rctl = E1000_READ_REG(hw, E1000_RCTL);
1248 rctl &= (~E1000_RCTL_MPE);
1249 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1253 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1255 struct e1000_hw *hw =
1256 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1257 struct e1000_vfta * shadow_vfta =
1258 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1263 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1264 E1000_VFTA_ENTRY_MASK);
1265 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1266 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1271 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1273 /* update local VFTA copy */
1274 shadow_vfta->vfta[vid_idx] = vfta;
1280 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1282 struct e1000_hw *hw =
1283 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284 uint32_t reg = ETHER_TYPE_VLAN ;
1286 reg |= (tpid << 16);
1287 E1000_WRITE_REG(hw, E1000_VET, reg);
1291 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1293 struct e1000_hw *hw =
1294 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1297 /* Filter Table Disable */
1298 reg = E1000_READ_REG(hw, E1000_RCTL);
1299 reg &= ~E1000_RCTL_CFIEN;
1300 reg &= ~E1000_RCTL_VFE;
1301 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1305 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1307 struct e1000_hw *hw =
1308 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309 struct e1000_vfta * shadow_vfta =
1310 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1314 /* Filter Table Enable, CFI not used for packet acceptance */
1315 reg = E1000_READ_REG(hw, E1000_RCTL);
1316 reg &= ~E1000_RCTL_CFIEN;
1317 reg |= E1000_RCTL_VFE;
1318 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1320 /* restore VFTA table */
1321 for (i = 0; i < IGB_VFTA_SIZE; i++)
1322 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1326 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1328 struct e1000_hw *hw =
1329 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332 /* VLAN Mode Disable */
1333 reg = E1000_READ_REG(hw, E1000_CTRL);
1334 reg &= ~E1000_CTRL_VME;
1335 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1337 /* Update maximum frame size */
1338 E1000_WRITE_REG(hw, E1000_RLPML,
1339 dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE);
1343 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1345 struct e1000_hw *hw =
1346 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 /* VLAN Mode Enable */
1350 reg = E1000_READ_REG(hw, E1000_CTRL);
1351 reg |= E1000_CTRL_VME;
1352 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1354 /* Update maximum frame size */
1355 E1000_WRITE_REG(hw, E1000_RLPML,
1356 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1361 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1363 struct e1000_hw *hw =
1364 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367 /* CTRL_EXT: Extended VLAN */
1368 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1369 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1370 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1375 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1377 struct e1000_hw *hw =
1378 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1381 /* CTRL_EXT: Extended VLAN */
1382 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1383 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1384 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1388 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1390 if(mask & ETH_VLAN_STRIP_MASK){
1391 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1392 igb_vlan_hw_strip_enable(dev);
1394 igb_vlan_hw_strip_disable(dev);
1397 if(mask & ETH_VLAN_FILTER_MASK){
1398 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1399 igb_vlan_hw_filter_enable(dev);
1401 igb_vlan_hw_filter_disable(dev);
1404 if(mask & ETH_VLAN_EXTEND_MASK){
1405 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1406 igb_vlan_hw_extend_enable(dev);
1408 igb_vlan_hw_extend_disable(dev);
1413 igb_intr_disable(struct e1000_hw *hw)
1415 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1416 E1000_WRITE_FLUSH(hw);
1420 * It enables the interrupt mask and then enable the interrupt.
1423 * Pointer to struct rte_eth_dev.
1426 * - On success, zero.
1427 * - On failure, a negative value.
1430 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1432 struct e1000_hw *hw =
1433 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1436 E1000_WRITE_FLUSH(hw);
1437 rte_intr_enable(&(dev->pci_dev->intr_handle));
1443 * It reads ICR and gets interrupt causes, check it and set a bit flag
1444 * to update link status.
1447 * Pointer to struct rte_eth_dev.
1450 * - On success, zero.
1451 * - On failure, a negative value.
1454 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1457 struct e1000_hw *hw =
1458 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459 struct e1000_interrupt *intr =
1460 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1462 /* read-on-clear nic registers here */
1463 icr = E1000_READ_REG(hw, E1000_ICR);
1464 if (icr & E1000_ICR_LSC) {
1465 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1472 * It executes link_update after knowing an interrupt is prsent.
1475 * Pointer to struct rte_eth_dev.
1478 * - On success, zero.
1479 * - On failure, a negative value.
1482 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1484 struct e1000_hw *hw =
1485 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486 struct e1000_interrupt *intr =
1487 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1488 uint32_t tctl, rctl;
1489 struct rte_eth_link link;
1492 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1495 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1496 rte_intr_enable(&(dev->pci_dev->intr_handle));
1498 /* set get_link_status to check register later */
1499 hw->mac.get_link_status = 1;
1500 ret = eth_igb_link_update(dev, 0);
1502 /* check if link has changed */
1506 memset(&link, 0, sizeof(link));
1507 rte_igb_dev_atomic_read_link_status(dev, &link);
1508 if (link.link_status) {
1510 " Port %d: Link Up - speed %u Mbps - %s\n",
1511 dev->data->port_id, (unsigned)link.link_speed,
1512 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1513 "full-duplex" : "half-duplex");
1515 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1516 dev->data->port_id);
1518 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1519 dev->pci_dev->addr.domain,
1520 dev->pci_dev->addr.bus,
1521 dev->pci_dev->addr.devid,
1522 dev->pci_dev->addr.function);
1523 tctl = E1000_READ_REG(hw, E1000_TCTL);
1524 rctl = E1000_READ_REG(hw, E1000_RCTL);
1525 if (link.link_status) {
1527 tctl |= E1000_TCTL_EN;
1528 rctl |= E1000_RCTL_EN;
1531 tctl &= ~E1000_TCTL_EN;
1532 rctl &= ~E1000_RCTL_EN;
1534 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1535 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1536 E1000_WRITE_FLUSH(hw);
1542 * Interrupt handler which shall be registered at first.
1545 * Pointer to interrupt handle.
1547 * The address of parameter (struct rte_eth_dev *) regsitered before.
1553 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1556 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1558 eth_igb_interrupt_get_status(dev);
1559 eth_igb_interrupt_action(dev);
1560 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1564 eth_igb_led_on(struct rte_eth_dev *dev)
1566 struct e1000_hw *hw;
1568 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1573 eth_igb_led_off(struct rte_eth_dev *dev)
1575 struct e1000_hw *hw;
1577 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1582 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1584 struct e1000_hw *hw;
1586 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1592 uint32_t rx_buf_size;
1593 uint32_t max_high_water;
1595 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596 rx_buf_size = igb_get_rx_buffer_size(hw);
1597 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1599 /* At least reserve one Ethernet frame for watermark */
1600 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1601 if ((fc_conf->high_water > max_high_water) ||
1602 (fc_conf->high_water < fc_conf->low_water)) {
1603 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1604 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1608 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1609 hw->fc.pause_time = fc_conf->pause_time;
1610 hw->fc.high_water = fc_conf->high_water;
1611 hw->fc.low_water = fc_conf->low_water;
1612 hw->fc.send_xon = fc_conf->send_xon;
1614 err = e1000_setup_link_generic(hw);
1615 if (err == E1000_SUCCESS) {
1619 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1624 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1625 uint32_t index, __rte_unused uint32_t pool)
1627 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1629 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1633 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1635 uint8_t addr[ETHER_ADDR_LEN];
1636 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638 memset(addr, 0, sizeof(addr));
1640 e1000_rar_set(hw, addr, index);
1644 * Virtual Function operations
1647 igbvf_intr_disable(struct e1000_hw *hw)
1649 PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1651 /* Clear interrupt mask to stop from interrupts being generated */
1652 E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1654 E1000_WRITE_FLUSH(hw);
1658 igbvf_stop_adapter(struct rte_eth_dev *dev)
1662 struct rte_eth_dev_info dev_info;
1663 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665 memset(&dev_info, 0, sizeof(dev_info));
1666 eth_igb_infos_get(dev, &dev_info);
1668 /* Clear interrupt mask to stop from interrupts being generated */
1669 E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1671 /* Clear any pending interrupts, flush previous writes */
1672 E1000_READ_REG(hw, E1000_EICR);
1674 /* Disable the transmit unit. Each queue must be disabled. */
1675 for (i = 0; i < dev_info.max_tx_queues; i++)
1676 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1678 /* Disable the receive unit by stopping each queue */
1679 for (i = 0; i < dev_info.max_rx_queues; i++) {
1680 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1681 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1682 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1683 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1687 /* flush all queues disables */
1688 E1000_WRITE_FLUSH(hw);
1692 static int eth_igbvf_link_update(struct e1000_hw *hw)
1694 struct e1000_mbx_info *mbx = &hw->mbx;
1695 struct e1000_mac_info *mac = &hw->mac;
1696 int ret_val = E1000_SUCCESS;
1698 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1701 * We only want to run this if there has been a rst asserted.
1702 * in this case that could mean a link change, device reset,
1703 * or a virtual function reset
1706 /* If we were hit with a reset or timeout drop the link */
1707 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1708 mac->get_link_status = TRUE;
1710 if (!mac->get_link_status)
1713 /* if link status is down no point in checking to see if pf is up */
1714 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1717 /* if we passed all the tests above then the link is up and we no
1718 * longer need to check for link */
1719 mac->get_link_status = FALSE;
1727 igbvf_dev_configure(struct rte_eth_dev *dev)
1729 struct rte_eth_conf* conf = &dev->data->dev_conf;
1731 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1732 dev->data->port_id);
1735 * VF has no ability to enable/disable HW CRC
1736 * Keep the persistent behavior the same as Host PF
1738 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1739 if (!conf->rxmode.hw_strip_crc) {
1740 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1741 conf->rxmode.hw_strip_crc = 1;
1744 if (conf->rxmode.hw_strip_crc) {
1745 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1746 conf->rxmode.hw_strip_crc = 0;
1754 igbvf_dev_start(struct rte_eth_dev *dev)
1758 PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1761 igbvf_set_vfta_all(dev,1);
1763 eth_igbvf_tx_init(dev);
1765 /* This can fail when allocating mbufs for descriptor rings */
1766 ret = eth_igbvf_rx_init(dev);
1768 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1769 igb_dev_clear_queues(dev);
1777 igbvf_dev_stop(struct rte_eth_dev *dev)
1779 PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1781 igbvf_stop_adapter(dev);
1784 * Clear what we set, but we still keep shadow_vfta to
1785 * restore after device starts
1787 igbvf_set_vfta_all(dev,0);
1789 igb_dev_clear_queues(dev);
1793 igbvf_dev_close(struct rte_eth_dev *dev)
1795 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797 PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1801 igbvf_dev_stop(dev);
1804 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1806 struct e1000_mbx_info *mbx = &hw->mbx;
1809 /* After set vlan, vlan strip will also be enabled in igb driver*/
1810 msgbuf[0] = E1000_VF_SET_VLAN;
1812 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1814 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1816 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1819 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1821 struct e1000_hw *hw =
1822 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823 struct e1000_vfta * shadow_vfta =
1824 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1825 int i = 0, j = 0, vfta = 0, mask = 1;
1827 for (i = 0; i < IGB_VFTA_SIZE; i++){
1828 vfta = shadow_vfta->vfta[i];
1831 for (j = 0; j < 32; j++){
1834 (uint16_t)((i<<5)+j), on);
1843 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1845 struct e1000_hw *hw =
1846 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 struct e1000_vfta * shadow_vfta =
1848 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1849 uint32_t vid_idx = 0;
1850 uint32_t vid_bit = 0;
1853 PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1855 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1856 ret = igbvf_set_vfta(hw, vlan_id, !!on);
1858 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1861 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1862 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1864 /*Save what we set and retore it after device reset*/
1866 shadow_vfta->vfta[vid_idx] |= vid_bit;
1868 shadow_vfta->vfta[vid_idx] &= ~vid_bit;