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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
41 #include <rte_common.h>
42 #include <rte_interrupts.h>
43 #include <rte_byteorder.h>
45 #include <rte_debug.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
51 #include <rte_tailq.h>
53 #include <rte_atomic.h>
54 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
60 static int eth_igb_configure(struct rte_eth_dev *dev);
61 static int eth_igb_start(struct rte_eth_dev *dev);
62 static void eth_igb_stop(struct rte_eth_dev *dev);
63 static void eth_igb_close(struct rte_eth_dev *dev);
64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
68 static int eth_igb_link_update(struct rte_eth_dev *dev,
69 int wait_to_complete);
70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
71 struct rte_eth_stats *rte_stats);
72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
74 struct rte_eth_dev_info *dev_info);
75 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
76 struct rte_eth_fc_conf *fc_conf);
77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
82 static int igb_hardware_init(struct e1000_hw *hw);
83 static void igb_hw_control_acquire(struct e1000_hw *hw);
84 static void igb_hw_control_release(struct e1000_hw *hw);
85 static void igb_init_manageability(struct e1000_hw *hw);
86 static void igb_release_manageability(struct e1000_hw *hw);
88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
89 uint16_t vlan_id, int on);
90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
100 static int eth_igb_led_on(struct rte_eth_dev *dev);
101 static int eth_igb_led_off(struct rte_eth_dev *dev);
103 static void igb_intr_disable(struct e1000_hw *hw);
104 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
106 struct ether_addr *mac_addr,
107 uint32_t index, uint32_t pool);
108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
110 static void igbvf_intr_disable(struct e1000_hw *hw);
111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
112 static int igbvf_dev_start(struct rte_eth_dev *dev);
113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
114 static void igbvf_dev_close(struct rte_eth_dev *dev);
115 static int eth_igbvf_link_update(struct e1000_hw *hw);
116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
119 uint16_t vlan_id, int on);
120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
122 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
123 struct rte_eth_rss_reta *reta_conf);
124 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
125 struct rte_eth_rss_reta *reta_conf);
128 * Define VF Stats MACRO for Non "cleared on read" register
130 #define UPDATE_VF_STAT(reg, last, cur) \
132 u32 latest = E1000_READ_REG(hw, reg); \
133 cur += latest - last; \
138 #define IGB_FC_PAUSE_TIME 0x0680
139 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
140 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
142 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
145 * The set of PCI devices this driver supports
147 static struct rte_pci_id pci_id_igb_map[] = {
149 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
150 #include "rte_pci_dev_ids.h"
156 * The set of PCI devices this driver supports (for 82576&I350 VF)
158 static struct rte_pci_id pci_id_igbvf_map[] = {
160 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
161 #include "rte_pci_dev_ids.h"
166 static struct eth_dev_ops eth_igb_ops = {
167 .dev_configure = eth_igb_configure,
168 .dev_start = eth_igb_start,
169 .dev_stop = eth_igb_stop,
170 .dev_close = eth_igb_close,
171 .promiscuous_enable = eth_igb_promiscuous_enable,
172 .promiscuous_disable = eth_igb_promiscuous_disable,
173 .allmulticast_enable = eth_igb_allmulticast_enable,
174 .allmulticast_disable = eth_igb_allmulticast_disable,
175 .link_update = eth_igb_link_update,
176 .stats_get = eth_igb_stats_get,
177 .stats_reset = eth_igb_stats_reset,
178 .dev_infos_get = eth_igb_infos_get,
179 .vlan_filter_set = eth_igb_vlan_filter_set,
180 .vlan_tpid_set = eth_igb_vlan_tpid_set,
181 .vlan_offload_set = eth_igb_vlan_offload_set,
182 .rx_queue_setup = eth_igb_rx_queue_setup,
183 .rx_queue_release = eth_igb_rx_queue_release,
184 .rx_queue_count = eth_igb_rx_queue_count,
185 .tx_queue_setup = eth_igb_tx_queue_setup,
186 .tx_queue_release = eth_igb_tx_queue_release,
187 .dev_led_on = eth_igb_led_on,
188 .dev_led_off = eth_igb_led_off,
189 .flow_ctrl_set = eth_igb_flow_ctrl_set,
190 .mac_addr_add = eth_igb_rar_set,
191 .mac_addr_remove = eth_igb_rar_clear,
192 .reta_update = eth_igb_rss_reta_update,
193 .reta_query = eth_igb_rss_reta_query,
197 * dev_ops for virtual function, bare necessities for basic vf
198 * operation have been implemented
200 static struct eth_dev_ops igbvf_eth_dev_ops = {
201 .dev_configure = igbvf_dev_configure,
202 .dev_start = igbvf_dev_start,
203 .dev_stop = igbvf_dev_stop,
204 .dev_close = igbvf_dev_close,
205 .link_update = eth_igb_link_update,
206 .stats_get = eth_igbvf_stats_get,
207 .stats_reset = eth_igbvf_stats_reset,
208 .vlan_filter_set = igbvf_vlan_filter_set,
209 .dev_infos_get = eth_igb_infos_get,
210 .rx_queue_setup = eth_igb_rx_queue_setup,
211 .rx_queue_release = eth_igb_rx_queue_release,
212 .tx_queue_setup = eth_igb_tx_queue_setup,
213 .tx_queue_release = eth_igb_tx_queue_release,
217 * Atomically reads the link status information from global
218 * structure rte_eth_dev.
221 * - Pointer to the structure rte_eth_dev to read from.
222 * - Pointer to the buffer to be saved with the link status.
225 * - On success, zero.
226 * - On failure, negative value.
229 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
230 struct rte_eth_link *link)
232 struct rte_eth_link *dst = link;
233 struct rte_eth_link *src = &(dev->data->dev_link);
235 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
236 *(uint64_t *)src) == 0)
243 * Atomically writes the link status information into global
244 * structure rte_eth_dev.
247 * - Pointer to the structure rte_eth_dev to read from.
248 * - Pointer to the buffer to be saved with the link status.
251 * - On success, zero.
252 * - On failure, negative value.
255 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
256 struct rte_eth_link *link)
258 struct rte_eth_link *dst = &(dev->data->dev_link);
259 struct rte_eth_link *src = link;
261 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
262 *(uint64_t *)src) == 0)
269 igb_intr_enable(struct rte_eth_dev *dev)
271 struct e1000_interrupt *intr =
272 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
273 struct e1000_hw *hw =
274 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
276 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
277 E1000_WRITE_FLUSH(hw);
281 igb_intr_disable(struct e1000_hw *hw)
283 E1000_WRITE_REG(hw, E1000_IMC, ~0);
284 E1000_WRITE_FLUSH(hw);
288 igb_identify_hardware(struct rte_eth_dev *dev)
290 struct e1000_hw *hw =
291 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
293 hw->vendor_id = dev->pci_dev->id.vendor_id;
294 hw->device_id = dev->pci_dev->id.device_id;
295 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
296 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
298 e1000_set_mac_type(hw);
300 /* need to check if it is a vf device below */
304 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
305 struct rte_eth_dev *eth_dev)
308 struct rte_pci_device *pci_dev;
309 struct e1000_hw *hw =
310 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
311 struct e1000_vfta * shadow_vfta =
312 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
314 pci_dev = eth_dev->pci_dev;
315 eth_dev->dev_ops = ð_igb_ops;
316 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
317 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
319 /* for secondary processes, we don't initialise any further as primary
320 * has already done this work. Only check we don't need a different
322 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
323 if (eth_dev->data->scattered_rx)
324 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
328 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
330 igb_identify_hardware(eth_dev);
331 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
336 e1000_get_bus_info(hw);
339 hw->phy.autoneg_wait_to_complete = 0;
340 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
343 if (hw->phy.media_type == e1000_media_type_copper) {
344 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
345 hw->phy.disable_polarity_correction = 0;
346 hw->phy.ms_type = e1000_ms_hw_default;
350 * Start from a known state, this is important in reading the nvm
355 /* Make sure we have a good EEPROM before we read from it */
356 if (e1000_validate_nvm_checksum(hw) < 0) {
358 * Some PCI-E parts fail the first check due to
359 * the link being in sleep state, call it again,
360 * if it fails a second time its a real issue.
362 if (e1000_validate_nvm_checksum(hw) < 0) {
363 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
369 /* Read the permanent MAC address out of the EEPROM */
370 if (e1000_read_mac_addr(hw) != 0) {
371 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
376 /* Allocate memory for storing MAC addresses */
377 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
378 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
379 if (eth_dev->data->mac_addrs == NULL) {
380 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
381 "store MAC addresses",
382 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
387 /* Copy the permanent MAC address */
388 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
390 /* initialize the vfta */
391 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
393 /* Now initialize the hardware */
394 if (igb_hardware_init(hw) != 0) {
395 PMD_INIT_LOG(ERR, "Hardware initialization failed");
396 rte_free(eth_dev->data->mac_addrs);
397 eth_dev->data->mac_addrs = NULL;
401 hw->mac.get_link_status = 1;
403 /* Indicate SOL/IDER usage */
404 if (e1000_check_reset_block(hw) < 0) {
405 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
409 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
410 eth_dev->data->port_id, pci_dev->id.vendor_id,
411 pci_dev->id.device_id);
413 rte_intr_callback_register(&(pci_dev->intr_handle),
414 eth_igb_interrupt_handler, (void *)eth_dev);
416 /* enable uio intr after callback register */
417 rte_intr_enable(&(pci_dev->intr_handle));
419 /* enable support intr */
420 igb_intr_enable(eth_dev);
425 igb_hw_control_release(hw);
431 * Virtual Function device init
434 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
435 struct rte_eth_dev *eth_dev)
437 struct rte_pci_device *pci_dev;
438 struct e1000_hw *hw =
439 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
442 PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
444 eth_dev->dev_ops = &igbvf_eth_dev_ops;
445 pci_dev = eth_dev->pci_dev;
447 hw->device_id = pci_dev->id.device_id;
448 hw->vendor_id = pci_dev->id.vendor_id;
449 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
451 /* Initialize the shared code */
452 diag = e1000_setup_init_funcs(hw, TRUE);
454 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
459 /* init_mailbox_params */
460 hw->mbx.ops.init_params(hw);
462 /* Disable the interrupts for VF */
463 igbvf_intr_disable(hw);
465 diag = hw->mac.ops.reset_hw(hw);
467 /* Allocate memory for storing MAC addresses */
468 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
469 hw->mac.rar_entry_count, 0);
470 if (eth_dev->data->mac_addrs == NULL) {
472 "Failed to allocate %d bytes needed to store MAC "
474 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
477 /* Copy the permanent MAC address */
478 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
479 ð_dev->data->mac_addrs[0]);
481 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
483 eth_dev->data->port_id, pci_dev->id.vendor_id,
484 pci_dev->id.device_id,
490 static struct eth_driver rte_igb_pmd = {
492 .name = "rte_igb_pmd",
493 .id_table = pci_id_igb_map,
494 #ifdef RTE_EAL_UNBIND_PORTS
495 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
498 .eth_dev_init = eth_igb_dev_init,
499 .dev_private_size = sizeof(struct e1000_adapter),
503 * virtual function driver struct
505 static struct eth_driver rte_igbvf_pmd = {
507 .name = "rte_igbvf_pmd",
508 .id_table = pci_id_igbvf_map,
509 #ifdef RTE_EAL_UNBIND_PORTS
510 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
513 .eth_dev_init = eth_igbvf_dev_init,
514 .dev_private_size = sizeof(struct e1000_adapter),
518 rte_igb_pmd_init(void)
520 rte_eth_driver_register(&rte_igb_pmd);
525 * VF Driver initialization routine.
526 * Invoked one at EAL init time.
527 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
530 rte_igbvf_pmd_init(void)
532 DEBUGFUNC("rte_igbvf_pmd_init");
534 rte_eth_driver_register(&rte_igbvf_pmd);
539 eth_igb_configure(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
544 PMD_INIT_LOG(DEBUG, ">>");
546 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
548 PMD_INIT_LOG(DEBUG, "<<");
554 eth_igb_start(struct rte_eth_dev *dev)
556 struct e1000_hw *hw =
557 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
560 PMD_INIT_LOG(DEBUG, ">>");
562 /* Power up the phy. Needed to make the link go Up */
563 e1000_power_up_phy(hw);
566 * Packet Buffer Allocation (PBA)
567 * Writing PBA sets the receive portion of the buffer
568 * the remainder is used for the transmit buffer.
570 if (hw->mac.type == e1000_82575) {
573 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
574 E1000_WRITE_REG(hw, E1000_PBA, pba);
577 /* Put the address into the Receive Address Array */
578 e1000_rar_set(hw, hw->mac.addr, 0);
580 /* Initialize the hardware */
581 if (igb_hardware_init(hw)) {
582 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
586 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
588 /* Configure for OS presence */
589 igb_init_manageability(hw);
591 eth_igb_tx_init(dev);
593 /* This can fail when allocating mbufs for descriptor rings */
594 ret = eth_igb_rx_init(dev);
596 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
597 igb_dev_clear_queues(dev);
601 e1000_clear_hw_cntrs_base_generic(hw);
604 * VLAN Offload Settings
606 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
607 ETH_VLAN_EXTEND_MASK;
608 eth_igb_vlan_offload_set(dev, mask);
611 * Configure the Interrupt Moderation register (EITR) with the maximum
612 * possible value (0xFFFF) to minimize "System Partial Write" issued by
613 * spurious [DMA] memory updates of RX and TX ring descriptors.
615 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
616 * spurious memory updates per second should be expected.
617 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
619 * Because interrupts are not used at all, the MSI-X is not activated
620 * and interrupt moderation is controlled by EITR[0].
622 * Note that having [almost] disabled memory updates of RX and TX ring
623 * descriptors through the Interrupt Moderation mechanism, memory
624 * updates of ring descriptors are now moderated by the configurable
625 * value of Write-Back Threshold registers.
627 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
628 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
631 /* Enable all RX & TX queues in the IVAR registers */
632 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
633 for (i = 0; i < 8; i++)
634 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
636 /* Configure EITR with the maximum possible value (0xFFFF) */
637 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
640 /* Setup link speed and duplex */
641 switch (dev->data->dev_conf.link_speed) {
642 case ETH_LINK_SPEED_AUTONEG:
643 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
644 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
645 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
646 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
647 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
648 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
650 goto error_invalid_config;
652 case ETH_LINK_SPEED_10:
653 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
654 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
655 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
656 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
657 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
658 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
660 goto error_invalid_config;
662 case ETH_LINK_SPEED_100:
663 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
664 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
665 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
666 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
667 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
668 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
670 goto error_invalid_config;
672 case ETH_LINK_SPEED_1000:
673 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
674 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
675 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
677 goto error_invalid_config;
679 case ETH_LINK_SPEED_10000:
681 goto error_invalid_config;
683 e1000_setup_link(hw);
685 /* check if lsc interrupt feature is enabled */
686 if (dev->data->dev_conf.intr_conf.lsc != 0)
687 ret = eth_igb_lsc_interrupt_setup(dev);
689 /* resume enabled intr since hw reset */
690 igb_intr_enable(dev);
692 PMD_INIT_LOG(DEBUG, "<<");
696 error_invalid_config:
697 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
698 dev->data->dev_conf.link_speed,
699 dev->data->dev_conf.link_duplex, dev->data->port_id);
700 igb_dev_clear_queues(dev);
704 /*********************************************************************
706 * This routine disables all traffic on the adapter by issuing a
707 * global reset on the MAC.
709 **********************************************************************/
711 eth_igb_stop(struct rte_eth_dev *dev)
713 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
714 struct rte_eth_link link;
716 igb_intr_disable(hw);
718 E1000_WRITE_REG(hw, E1000_WUC, 0);
720 /* Power down the phy. Needed to make the link go Down */
721 e1000_power_down_phy(hw);
723 igb_dev_clear_queues(dev);
725 /* clear the recorded link status */
726 memset(&link, 0, sizeof(link));
727 rte_igb_dev_atomic_write_link_status(dev, &link);
731 eth_igb_close(struct rte_eth_dev *dev)
733 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
734 struct rte_eth_link link;
737 e1000_phy_hw_reset(hw);
738 igb_release_manageability(hw);
739 igb_hw_control_release(hw);
741 igb_dev_clear_queues(dev);
743 memset(&link, 0, sizeof(link));
744 rte_igb_dev_atomic_write_link_status(dev, &link);
748 igb_get_rx_buffer_size(struct e1000_hw *hw)
750 uint32_t rx_buf_size;
751 if (hw->mac.type == e1000_82576) {
752 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
753 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
754 /* PBS needs to be translated according to a lookup table */
755 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
756 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
757 rx_buf_size = (rx_buf_size << 10);
758 } else if (hw->mac.type == e1000_i210) {
759 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
761 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
767 /*********************************************************************
769 * Initialize the hardware
771 **********************************************************************/
773 igb_hardware_init(struct e1000_hw *hw)
775 uint32_t rx_buf_size;
778 /* Let the firmware know the OS is in control */
779 igb_hw_control_acquire(hw);
782 * These parameters control the automatic generation (Tx) and
783 * response (Rx) to Ethernet PAUSE frames.
784 * - High water mark should allow for at least two standard size (1518)
785 * frames to be received after sending an XOFF.
786 * - Low water mark works best when it is very near the high water mark.
787 * This allows the receiver to restart by sending XON when it has
788 * drained a bit. Here we use an arbitary value of 1500 which will
789 * restart after one full frame is pulled from the buffer. There
790 * could be several smaller frames in the buffer and if so they will
791 * not trigger the XON until their total number reduces the buffer
793 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
795 rx_buf_size = igb_get_rx_buffer_size(hw);
797 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
798 hw->fc.low_water = hw->fc.high_water - 1500;
799 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
802 /* Set Flow control, use the tunable location if sane */
803 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
804 hw->fc.requested_mode = igb_fc_setting;
806 hw->fc.requested_mode = e1000_fc_none;
808 /* Issue a global reset */
810 E1000_WRITE_REG(hw, E1000_WUC, 0);
812 diag = e1000_init_hw(hw);
816 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
817 e1000_get_phy_info(hw);
818 e1000_check_for_link(hw);
823 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
825 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
827 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
828 struct e1000_hw_stats *stats =
829 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
832 if(hw->phy.media_type == e1000_media_type_copper ||
833 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
835 E1000_READ_REG(hw,E1000_SYMERRS);
836 stats->sec += E1000_READ_REG(hw, E1000_SEC);
839 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
840 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
841 stats->scc += E1000_READ_REG(hw, E1000_SCC);
842 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
844 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
845 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
846 stats->colc += E1000_READ_REG(hw, E1000_COLC);
847 stats->dc += E1000_READ_REG(hw, E1000_DC);
848 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
849 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
850 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
852 ** For watchdog management we need to know if we have been
853 ** paused during the last interval, so capture that here.
855 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
856 stats->xoffrxc += pause_frames;
857 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
858 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
859 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
860 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
861 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
862 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
863 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
864 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
865 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
866 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
867 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
868 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
870 /* For the 64-bit byte counters the low dword must be read first. */
871 /* Both registers clear on the read of the high dword */
873 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
874 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
875 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
876 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
878 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
879 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
880 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
881 stats->roc += E1000_READ_REG(hw, E1000_ROC);
882 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
884 stats->tor += E1000_READ_REG(hw, E1000_TORH);
885 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
887 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
888 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
889 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
890 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
891 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
892 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
893 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
894 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
895 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
896 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
898 /* Interrupt Counts */
900 stats->iac += E1000_READ_REG(hw, E1000_IAC);
901 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
902 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
903 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
904 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
905 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
906 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
907 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
908 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
910 /* Host to Card Statistics */
912 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
913 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
914 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
915 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
916 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
917 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
918 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
919 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
920 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
921 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
922 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
923 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
924 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
925 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
927 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
928 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
929 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
930 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
931 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
932 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
934 if (rte_stats == NULL)
938 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
939 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
942 rte_stats->oerrors = stats->ecol + stats->latecol;
944 rte_stats->ipackets = stats->gprc;
945 rte_stats->opackets = stats->gptc;
946 rte_stats->ibytes = stats->gorc;
947 rte_stats->obytes = stats->gotc;
951 eth_igb_stats_reset(struct rte_eth_dev *dev)
953 struct e1000_hw_stats *hw_stats =
954 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
956 /* HW registers are cleared on read */
957 eth_igb_stats_get(dev, NULL);
959 /* Reset software totals */
960 memset(hw_stats, 0, sizeof(*hw_stats));
964 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
966 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
967 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
968 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
970 /* Good Rx packets, include VF loopback */
971 UPDATE_VF_STAT(E1000_VFGPRC,
972 hw_stats->last_gprc, hw_stats->gprc);
974 /* Good Rx octets, include VF loopback */
975 UPDATE_VF_STAT(E1000_VFGORC,
976 hw_stats->last_gorc, hw_stats->gorc);
978 /* Good Tx packets, include VF loopback */
979 UPDATE_VF_STAT(E1000_VFGPTC,
980 hw_stats->last_gptc, hw_stats->gptc);
982 /* Good Tx octets, include VF loopback */
983 UPDATE_VF_STAT(E1000_VFGOTC,
984 hw_stats->last_gotc, hw_stats->gotc);
986 /* Rx Multicst packets */
987 UPDATE_VF_STAT(E1000_VFMPRC,
988 hw_stats->last_mprc, hw_stats->mprc);
990 /* Good Rx loopback packets */
991 UPDATE_VF_STAT(E1000_VFGPRLBC,
992 hw_stats->last_gprlbc, hw_stats->gprlbc);
994 /* Good Rx loopback octets */
995 UPDATE_VF_STAT(E1000_VFGORLBC,
996 hw_stats->last_gorlbc, hw_stats->gorlbc);
998 /* Good Tx loopback packets */
999 UPDATE_VF_STAT(E1000_VFGPTLBC,
1000 hw_stats->last_gptlbc, hw_stats->gptlbc);
1002 /* Good Tx loopback octets */
1003 UPDATE_VF_STAT(E1000_VFGOTLBC,
1004 hw_stats->last_gotlbc, hw_stats->gotlbc);
1006 if (rte_stats == NULL)
1009 memset(rte_stats, 0, sizeof(*rte_stats));
1010 rte_stats->ipackets = hw_stats->gprc;
1011 rte_stats->ibytes = hw_stats->gorc;
1012 rte_stats->opackets = hw_stats->gptc;
1013 rte_stats->obytes = hw_stats->gotc;
1014 rte_stats->imcasts = hw_stats->mprc;
1015 rte_stats->ilbpackets = hw_stats->gprlbc;
1016 rte_stats->ilbbytes = hw_stats->gorlbc;
1017 rte_stats->olbpackets = hw_stats->gptlbc;
1018 rte_stats->olbbytes = hw_stats->gotlbc;
1023 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1025 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1026 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1028 /* Sync HW register to the last stats */
1029 eth_igbvf_stats_get(dev, NULL);
1031 /* reset HW current stats*/
1032 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1033 offsetof(struct e1000_vf_stats, gprc));
1038 eth_igb_infos_get(struct rte_eth_dev *dev,
1039 struct rte_eth_dev_info *dev_info)
1041 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1044 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1045 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1047 switch (hw->mac.type) {
1049 dev_info->max_rx_queues = 4;
1050 dev_info->max_tx_queues = 4;
1054 dev_info->max_rx_queues = 16;
1055 dev_info->max_tx_queues = 16;
1059 dev_info->max_rx_queues = 8;
1060 dev_info->max_tx_queues = 8;
1064 dev_info->max_rx_queues = 8;
1065 dev_info->max_tx_queues = 8;
1069 dev_info->max_rx_queues = 4;
1070 dev_info->max_tx_queues = 4;
1074 dev_info->max_rx_queues = 2;
1075 dev_info->max_tx_queues = 2;
1078 case e1000_vfadapt_i350:
1079 dev_info->max_rx_queues = 1;
1080 dev_info->max_tx_queues = 1;
1084 /* Should not happen */
1085 dev_info->max_rx_queues = 0;
1086 dev_info->max_tx_queues = 0;
1090 /* return 0 means link status changed, -1 means not changed */
1092 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1094 struct e1000_hw *hw =
1095 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1096 struct rte_eth_link link, old;
1097 int link_check, count;
1100 hw->mac.get_link_status = 1;
1102 /* possible wait-to-complete in up to 9 seconds */
1103 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1104 /* Read the real link status */
1105 switch (hw->phy.media_type) {
1106 case e1000_media_type_copper:
1107 /* Do the work to read phy */
1108 e1000_check_for_link(hw);
1109 link_check = !hw->mac.get_link_status;
1112 case e1000_media_type_fiber:
1113 e1000_check_for_link(hw);
1114 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1118 case e1000_media_type_internal_serdes:
1119 e1000_check_for_link(hw);
1120 link_check = hw->mac.serdes_has_link;
1123 /* VF device is type_unknown */
1124 case e1000_media_type_unknown:
1125 eth_igbvf_link_update(hw);
1126 link_check = !hw->mac.get_link_status;
1132 if (link_check || wait_to_complete == 0)
1134 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1136 memset(&link, 0, sizeof(link));
1137 rte_igb_dev_atomic_read_link_status(dev, &link);
1140 /* Now we check if a transition has happened */
1142 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1144 link.link_status = 1;
1145 } else if (!link_check) {
1146 link.link_speed = 0;
1147 link.link_duplex = 0;
1148 link.link_status = 0;
1150 rte_igb_dev_atomic_write_link_status(dev, &link);
1153 if (old.link_status == link.link_status)
1161 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1162 * For ASF and Pass Through versions of f/w this means
1163 * that the driver is loaded.
1166 igb_hw_control_acquire(struct e1000_hw *hw)
1170 /* Let firmware know the driver has taken over */
1171 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1172 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1176 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1177 * For ASF and Pass Through versions of f/w this means that the
1178 * driver is no longer loaded.
1181 igb_hw_control_release(struct e1000_hw *hw)
1185 /* Let firmware taken over control of h/w */
1186 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1187 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1188 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1192 * Bit of a misnomer, what this really means is
1193 * to enable OS management of the system... aka
1194 * to disable special hardware management features.
1197 igb_init_manageability(struct e1000_hw *hw)
1199 if (e1000_enable_mng_pass_thru(hw)) {
1200 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1201 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1203 /* disable hardware interception of ARP */
1204 manc &= ~(E1000_MANC_ARP_EN);
1206 /* enable receiving management packets to the host */
1207 manc |= E1000_MANC_EN_MNG2HOST;
1208 manc2h |= 1 << 5; /* Mng Port 623 */
1209 manc2h |= 1 << 6; /* Mng Port 664 */
1210 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1211 E1000_WRITE_REG(hw, E1000_MANC, manc);
1216 igb_release_manageability(struct e1000_hw *hw)
1218 if (e1000_enable_mng_pass_thru(hw)) {
1219 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1221 manc |= E1000_MANC_ARP_EN;
1222 manc &= ~E1000_MANC_EN_MNG2HOST;
1224 E1000_WRITE_REG(hw, E1000_MANC, manc);
1229 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1231 struct e1000_hw *hw =
1232 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1235 rctl = E1000_READ_REG(hw, E1000_RCTL);
1236 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1237 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1241 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1243 struct e1000_hw *hw =
1244 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247 rctl = E1000_READ_REG(hw, E1000_RCTL);
1248 rctl &= (~E1000_RCTL_UPE);
1249 if (dev->data->all_multicast == 1)
1250 rctl |= E1000_RCTL_MPE;
1252 rctl &= (~E1000_RCTL_MPE);
1253 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1257 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1259 struct e1000_hw *hw =
1260 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263 rctl = E1000_READ_REG(hw, E1000_RCTL);
1264 rctl |= E1000_RCTL_MPE;
1265 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1269 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1271 struct e1000_hw *hw =
1272 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275 if (dev->data->promiscuous == 1)
1276 return; /* must remain in all_multicast mode */
1277 rctl = E1000_READ_REG(hw, E1000_RCTL);
1278 rctl &= (~E1000_RCTL_MPE);
1279 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1283 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1285 struct e1000_hw *hw =
1286 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287 struct e1000_vfta * shadow_vfta =
1288 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1293 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1294 E1000_VFTA_ENTRY_MASK);
1295 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1296 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1301 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1303 /* update local VFTA copy */
1304 shadow_vfta->vfta[vid_idx] = vfta;
1310 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1312 struct e1000_hw *hw =
1313 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1314 uint32_t reg = ETHER_TYPE_VLAN ;
1316 reg |= (tpid << 16);
1317 E1000_WRITE_REG(hw, E1000_VET, reg);
1321 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1323 struct e1000_hw *hw =
1324 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327 /* Filter Table Disable */
1328 reg = E1000_READ_REG(hw, E1000_RCTL);
1329 reg &= ~E1000_RCTL_CFIEN;
1330 reg &= ~E1000_RCTL_VFE;
1331 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1335 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1337 struct e1000_hw *hw =
1338 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1339 struct e1000_vfta * shadow_vfta =
1340 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1344 /* Filter Table Enable, CFI not used for packet acceptance */
1345 reg = E1000_READ_REG(hw, E1000_RCTL);
1346 reg &= ~E1000_RCTL_CFIEN;
1347 reg |= E1000_RCTL_VFE;
1348 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1350 /* restore VFTA table */
1351 for (i = 0; i < IGB_VFTA_SIZE; i++)
1352 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1356 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1358 struct e1000_hw *hw =
1359 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362 /* VLAN Mode Disable */
1363 reg = E1000_READ_REG(hw, E1000_CTRL);
1364 reg &= ~E1000_CTRL_VME;
1365 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1369 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1371 struct e1000_hw *hw =
1372 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375 /* VLAN Mode Enable */
1376 reg = E1000_READ_REG(hw, E1000_CTRL);
1377 reg |= E1000_CTRL_VME;
1378 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1382 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1384 struct e1000_hw *hw =
1385 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388 /* CTRL_EXT: Extended VLAN */
1389 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1390 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1391 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1393 /* Update maximum packet length */
1394 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1395 E1000_WRITE_REG(hw, E1000_RLPML,
1396 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1401 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1403 struct e1000_hw *hw =
1404 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407 /* CTRL_EXT: Extended VLAN */
1408 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1409 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1410 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1412 /* Update maximum packet length */
1413 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1414 E1000_WRITE_REG(hw, E1000_RLPML,
1415 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1420 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1422 if(mask & ETH_VLAN_STRIP_MASK){
1423 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1424 igb_vlan_hw_strip_enable(dev);
1426 igb_vlan_hw_strip_disable(dev);
1429 if(mask & ETH_VLAN_FILTER_MASK){
1430 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1431 igb_vlan_hw_filter_enable(dev);
1433 igb_vlan_hw_filter_disable(dev);
1436 if(mask & ETH_VLAN_EXTEND_MASK){
1437 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1438 igb_vlan_hw_extend_enable(dev);
1440 igb_vlan_hw_extend_disable(dev);
1446 * It enables the interrupt mask and then enable the interrupt.
1449 * Pointer to struct rte_eth_dev.
1452 * - On success, zero.
1453 * - On failure, a negative value.
1456 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1458 struct e1000_interrupt *intr =
1459 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1461 intr->mask |= E1000_ICR_LSC;
1467 * It reads ICR and gets interrupt causes, check it and set a bit flag
1468 * to update link status.
1471 * Pointer to struct rte_eth_dev.
1474 * - On success, zero.
1475 * - On failure, a negative value.
1478 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1481 struct e1000_hw *hw =
1482 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483 struct e1000_interrupt *intr =
1484 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1486 igb_intr_disable(hw);
1488 /* read-on-clear nic registers here */
1489 icr = E1000_READ_REG(hw, E1000_ICR);
1492 if (icr & E1000_ICR_LSC) {
1493 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1500 * It executes link_update after knowing an interrupt is prsent.
1503 * Pointer to struct rte_eth_dev.
1506 * - On success, zero.
1507 * - On failure, a negative value.
1510 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1512 struct e1000_hw *hw =
1513 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1514 struct e1000_interrupt *intr =
1515 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1516 uint32_t tctl, rctl;
1517 struct rte_eth_link link;
1521 igb_intr_enable(dev);
1522 rte_intr_enable(&(dev->pci_dev->intr_handle));
1524 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1525 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1527 /* set get_link_status to check register later */
1528 hw->mac.get_link_status = 1;
1529 ret = eth_igb_link_update(dev, 0);
1531 /* check if link has changed */
1535 memset(&link, 0, sizeof(link));
1536 rte_igb_dev_atomic_read_link_status(dev, &link);
1537 if (link.link_status) {
1539 " Port %d: Link Up - speed %u Mbps - %s\n",
1540 dev->data->port_id, (unsigned)link.link_speed,
1541 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1542 "full-duplex" : "half-duplex");
1544 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1545 dev->data->port_id);
1547 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1548 dev->pci_dev->addr.domain,
1549 dev->pci_dev->addr.bus,
1550 dev->pci_dev->addr.devid,
1551 dev->pci_dev->addr.function);
1552 tctl = E1000_READ_REG(hw, E1000_TCTL);
1553 rctl = E1000_READ_REG(hw, E1000_RCTL);
1554 if (link.link_status) {
1556 tctl |= E1000_TCTL_EN;
1557 rctl |= E1000_RCTL_EN;
1560 tctl &= ~E1000_TCTL_EN;
1561 rctl &= ~E1000_RCTL_EN;
1563 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1564 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1565 E1000_WRITE_FLUSH(hw);
1566 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1573 * Interrupt handler which shall be registered at first.
1576 * Pointer to interrupt handle.
1578 * The address of parameter (struct rte_eth_dev *) regsitered before.
1584 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1587 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1589 eth_igb_interrupt_get_status(dev);
1590 eth_igb_interrupt_action(dev);
1594 eth_igb_led_on(struct rte_eth_dev *dev)
1596 struct e1000_hw *hw;
1598 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1603 eth_igb_led_off(struct rte_eth_dev *dev)
1605 struct e1000_hw *hw;
1607 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1612 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1614 struct e1000_hw *hw;
1616 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1622 uint32_t rx_buf_size;
1623 uint32_t max_high_water;
1625 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626 rx_buf_size = igb_get_rx_buffer_size(hw);
1627 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1629 /* At least reserve one Ethernet frame for watermark */
1630 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1631 if ((fc_conf->high_water > max_high_water) ||
1632 (fc_conf->high_water < fc_conf->low_water)) {
1633 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1634 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1638 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1639 hw->fc.pause_time = fc_conf->pause_time;
1640 hw->fc.high_water = fc_conf->high_water;
1641 hw->fc.low_water = fc_conf->low_water;
1642 hw->fc.send_xon = fc_conf->send_xon;
1644 err = e1000_setup_link_generic(hw);
1645 if (err == E1000_SUCCESS) {
1649 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1654 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1655 uint32_t index, __rte_unused uint32_t pool)
1657 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1663 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1665 uint8_t addr[ETHER_ADDR_LEN];
1666 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668 memset(addr, 0, sizeof(addr));
1670 e1000_rar_set(hw, addr, index);
1674 * Virtual Function operations
1677 igbvf_intr_disable(struct e1000_hw *hw)
1679 PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1681 /* Clear interrupt mask to stop from interrupts being generated */
1682 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1684 E1000_WRITE_FLUSH(hw);
1688 igbvf_stop_adapter(struct rte_eth_dev *dev)
1692 struct rte_eth_dev_info dev_info;
1693 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695 memset(&dev_info, 0, sizeof(dev_info));
1696 eth_igb_infos_get(dev, &dev_info);
1698 /* Clear interrupt mask to stop from interrupts being generated */
1699 igbvf_intr_disable(hw);
1701 /* Clear any pending interrupts, flush previous writes */
1702 E1000_READ_REG(hw, E1000_EICR);
1704 /* Disable the transmit unit. Each queue must be disabled. */
1705 for (i = 0; i < dev_info.max_tx_queues; i++)
1706 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1708 /* Disable the receive unit by stopping each queue */
1709 for (i = 0; i < dev_info.max_rx_queues; i++) {
1710 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1711 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1712 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1713 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1717 /* flush all queues disables */
1718 E1000_WRITE_FLUSH(hw);
1722 static int eth_igbvf_link_update(struct e1000_hw *hw)
1724 struct e1000_mbx_info *mbx = &hw->mbx;
1725 struct e1000_mac_info *mac = &hw->mac;
1726 int ret_val = E1000_SUCCESS;
1728 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1731 * We only want to run this if there has been a rst asserted.
1732 * in this case that could mean a link change, device reset,
1733 * or a virtual function reset
1736 /* If we were hit with a reset or timeout drop the link */
1737 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1738 mac->get_link_status = TRUE;
1740 if (!mac->get_link_status)
1743 /* if link status is down no point in checking to see if pf is up */
1744 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1747 /* if we passed all the tests above then the link is up and we no
1748 * longer need to check for link */
1749 mac->get_link_status = FALSE;
1757 igbvf_dev_configure(struct rte_eth_dev *dev)
1759 struct rte_eth_conf* conf = &dev->data->dev_conf;
1761 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1762 dev->data->port_id);
1765 * VF has no ability to enable/disable HW CRC
1766 * Keep the persistent behavior the same as Host PF
1768 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1769 if (!conf->rxmode.hw_strip_crc) {
1770 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1771 conf->rxmode.hw_strip_crc = 1;
1774 if (conf->rxmode.hw_strip_crc) {
1775 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1776 conf->rxmode.hw_strip_crc = 0;
1784 igbvf_dev_start(struct rte_eth_dev *dev)
1786 struct e1000_hw *hw =
1787 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1790 PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1792 hw->mac.ops.reset_hw(hw);
1795 igbvf_set_vfta_all(dev,1);
1797 eth_igbvf_tx_init(dev);
1799 /* This can fail when allocating mbufs for descriptor rings */
1800 ret = eth_igbvf_rx_init(dev);
1802 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1803 igb_dev_clear_queues(dev);
1811 igbvf_dev_stop(struct rte_eth_dev *dev)
1813 PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1815 igbvf_stop_adapter(dev);
1818 * Clear what we set, but we still keep shadow_vfta to
1819 * restore after device starts
1821 igbvf_set_vfta_all(dev,0);
1823 igb_dev_clear_queues(dev);
1827 igbvf_dev_close(struct rte_eth_dev *dev)
1829 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831 PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1835 igbvf_dev_stop(dev);
1838 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1840 struct e1000_mbx_info *mbx = &hw->mbx;
1843 /* After set vlan, vlan strip will also be enabled in igb driver*/
1844 msgbuf[0] = E1000_VF_SET_VLAN;
1846 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1848 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1850 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1853 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1855 struct e1000_hw *hw =
1856 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 struct e1000_vfta * shadow_vfta =
1858 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1859 int i = 0, j = 0, vfta = 0, mask = 1;
1861 for (i = 0; i < IGB_VFTA_SIZE; i++){
1862 vfta = shadow_vfta->vfta[i];
1865 for (j = 0; j < 32; j++){
1868 (uint16_t)((i<<5)+j), on);
1877 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1879 struct e1000_hw *hw =
1880 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881 struct e1000_vfta * shadow_vfta =
1882 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1883 uint32_t vid_idx = 0;
1884 uint32_t vid_bit = 0;
1887 PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1889 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1890 ret = igbvf_set_vfta(hw, vlan_id, !!on);
1892 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1895 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1896 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1898 /*Save what we set and retore it after device reset*/
1900 shadow_vfta->vfta[vid_idx] |= vid_bit;
1902 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1908 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
1909 struct rte_eth_rss_reta *reta_conf)
1913 struct e1000_hw *hw =
1914 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 * Update Redirection Table RETA[n],n=0...31,The redirection table has
1918 * 128-entries in 32 registers
1920 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1921 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
1922 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1924 mask = (uint8_t)((reta_conf->mask_hi >>
1925 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
1928 /* If all 4 entries were set,don't need read RETA register */
1930 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
1932 for (j = 0; j < 4; j++) {
1933 if (mask & (0x1 << j)) {
1935 reta &= ~(0xFF << 8 * j);
1936 reta |= reta_conf->reta[i + j] << 8 * j;
1939 E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
1947 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
1948 struct rte_eth_rss_reta *reta_conf)
1952 struct e1000_hw *hw =
1953 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1956 * Read Redirection Table RETA[n],n=0...31,The redirection table has
1957 * 128-entries in 32 registers
1959 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1960 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
1961 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1963 mask = (uint8_t)((reta_conf->mask_hi >>
1964 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
1967 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
1968 for (j = 0; j < 4; j++) {
1969 if (mask & (0x1 << j))
1970 reta_conf->reta[i + j] =
1971 (uint8_t)((reta >> 8 * j) & 0xFF);