4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
64 #define IGB_DEFAULT_RX_PTHRESH 8
65 #define IGB_DEFAULT_RX_HTHRESH 8
66 #define IGB_DEFAULT_RX_WTHRESH 0
68 #define IGB_DEFAULT_TX_PTHRESH 32
69 #define IGB_DEFAULT_TX_HTHRESH 0
70 #define IGB_DEFAULT_TX_WTHRESH 0
72 static int eth_igb_configure(struct rte_eth_dev *dev);
73 static int eth_igb_start(struct rte_eth_dev *dev);
74 static void eth_igb_stop(struct rte_eth_dev *dev);
75 static void eth_igb_close(struct rte_eth_dev *dev);
76 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
77 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
78 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
79 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
80 static int eth_igb_link_update(struct rte_eth_dev *dev,
81 int wait_to_complete);
82 static void eth_igb_stats_get(struct rte_eth_dev *dev,
83 struct rte_eth_stats *rte_stats);
84 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
85 static void eth_igb_infos_get(struct rte_eth_dev *dev,
86 struct rte_eth_dev_info *dev_info);
87 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
88 struct rte_eth_dev_info *dev_info);
89 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
90 struct rte_eth_fc_conf *fc_conf);
91 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
92 struct rte_eth_fc_conf *fc_conf);
93 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
94 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
95 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
96 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
98 static int igb_hardware_init(struct e1000_hw *hw);
99 static void igb_hw_control_acquire(struct e1000_hw *hw);
100 static void igb_hw_control_release(struct e1000_hw *hw);
101 static void igb_init_manageability(struct e1000_hw *hw);
102 static void igb_release_manageability(struct e1000_hw *hw);
104 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
106 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
107 uint16_t vlan_id, int on);
108 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
109 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
111 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
112 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
113 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
114 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
115 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
116 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
118 static int eth_igb_led_on(struct rte_eth_dev *dev);
119 static int eth_igb_led_off(struct rte_eth_dev *dev);
121 static void igb_intr_disable(struct e1000_hw *hw);
122 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
123 static void eth_igb_rar_set(struct rte_eth_dev *dev,
124 struct ether_addr *mac_addr,
125 uint32_t index, uint32_t pool);
126 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
128 static void igbvf_intr_disable(struct e1000_hw *hw);
129 static int igbvf_dev_configure(struct rte_eth_dev *dev);
130 static int igbvf_dev_start(struct rte_eth_dev *dev);
131 static void igbvf_dev_stop(struct rte_eth_dev *dev);
132 static void igbvf_dev_close(struct rte_eth_dev *dev);
133 static int eth_igbvf_link_update(struct e1000_hw *hw);
134 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
135 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
136 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
137 uint16_t vlan_id, int on);
138 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
139 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
140 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
141 struct rte_eth_rss_reta *reta_conf);
142 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta *reta_conf);
145 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
146 struct rte_syn_filter *filter, uint16_t rx_queue);
147 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
148 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
149 struct rte_syn_filter *filter, uint16_t *rx_queue);
150 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
152 struct rte_ethertype_filter *filter, uint16_t rx_queue);
153 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
155 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
157 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
158 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
160 struct rte_2tuple_filter *filter, uint16_t rx_queue);
161 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
163 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
165 struct rte_2tuple_filter *filter, uint16_t *rx_queue);
166 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
168 struct rte_flex_filter *filter, uint16_t rx_queue);
169 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
171 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
173 struct rte_flex_filter *filter, uint16_t *rx_queue);
174 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
176 struct rte_5tuple_filter *filter, uint16_t rx_queue);
177 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
179 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
181 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
184 * Define VF Stats MACRO for Non "cleared on read" register
186 #define UPDATE_VF_STAT(reg, last, cur) \
188 u32 latest = E1000_READ_REG(hw, reg); \
189 cur += latest - last; \
194 #define IGB_FC_PAUSE_TIME 0x0680
195 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
196 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
198 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
200 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
203 * The set of PCI devices this driver supports
205 static struct rte_pci_id pci_id_igb_map[] = {
207 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
208 #include "rte_pci_dev_ids.h"
214 * The set of PCI devices this driver supports (for 82576&I350 VF)
216 static struct rte_pci_id pci_id_igbvf_map[] = {
218 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
219 #include "rte_pci_dev_ids.h"
224 static struct eth_dev_ops eth_igb_ops = {
225 .dev_configure = eth_igb_configure,
226 .dev_start = eth_igb_start,
227 .dev_stop = eth_igb_stop,
228 .dev_close = eth_igb_close,
229 .promiscuous_enable = eth_igb_promiscuous_enable,
230 .promiscuous_disable = eth_igb_promiscuous_disable,
231 .allmulticast_enable = eth_igb_allmulticast_enable,
232 .allmulticast_disable = eth_igb_allmulticast_disable,
233 .link_update = eth_igb_link_update,
234 .stats_get = eth_igb_stats_get,
235 .stats_reset = eth_igb_stats_reset,
236 .dev_infos_get = eth_igb_infos_get,
237 .mtu_set = eth_igb_mtu_set,
238 .vlan_filter_set = eth_igb_vlan_filter_set,
239 .vlan_tpid_set = eth_igb_vlan_tpid_set,
240 .vlan_offload_set = eth_igb_vlan_offload_set,
241 .rx_queue_setup = eth_igb_rx_queue_setup,
242 .rx_queue_release = eth_igb_rx_queue_release,
243 .rx_queue_count = eth_igb_rx_queue_count,
244 .rx_descriptor_done = eth_igb_rx_descriptor_done,
245 .tx_queue_setup = eth_igb_tx_queue_setup,
246 .tx_queue_release = eth_igb_tx_queue_release,
247 .dev_led_on = eth_igb_led_on,
248 .dev_led_off = eth_igb_led_off,
249 .flow_ctrl_get = eth_igb_flow_ctrl_get,
250 .flow_ctrl_set = eth_igb_flow_ctrl_set,
251 .mac_addr_add = eth_igb_rar_set,
252 .mac_addr_remove = eth_igb_rar_clear,
253 .reta_update = eth_igb_rss_reta_update,
254 .reta_query = eth_igb_rss_reta_query,
255 .rss_hash_update = eth_igb_rss_hash_update,
256 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
257 .add_syn_filter = eth_igb_add_syn_filter,
258 .remove_syn_filter = eth_igb_remove_syn_filter,
259 .get_syn_filter = eth_igb_get_syn_filter,
260 .add_ethertype_filter = eth_igb_add_ethertype_filter,
261 .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
262 .get_ethertype_filter = eth_igb_get_ethertype_filter,
263 .add_2tuple_filter = eth_igb_add_2tuple_filter,
264 .remove_2tuple_filter = eth_igb_remove_2tuple_filter,
265 .get_2tuple_filter = eth_igb_get_2tuple_filter,
266 .add_flex_filter = eth_igb_add_flex_filter,
267 .remove_flex_filter = eth_igb_remove_flex_filter,
268 .get_flex_filter = eth_igb_get_flex_filter,
269 .add_5tuple_filter = eth_igb_add_5tuple_filter,
270 .remove_5tuple_filter = eth_igb_remove_5tuple_filter,
271 .get_5tuple_filter = eth_igb_get_5tuple_filter,
275 * dev_ops for virtual function, bare necessities for basic vf
276 * operation have been implemented
278 static struct eth_dev_ops igbvf_eth_dev_ops = {
279 .dev_configure = igbvf_dev_configure,
280 .dev_start = igbvf_dev_start,
281 .dev_stop = igbvf_dev_stop,
282 .dev_close = igbvf_dev_close,
283 .link_update = eth_igb_link_update,
284 .stats_get = eth_igbvf_stats_get,
285 .stats_reset = eth_igbvf_stats_reset,
286 .vlan_filter_set = igbvf_vlan_filter_set,
287 .dev_infos_get = eth_igbvf_infos_get,
288 .rx_queue_setup = eth_igb_rx_queue_setup,
289 .rx_queue_release = eth_igb_rx_queue_release,
290 .tx_queue_setup = eth_igb_tx_queue_setup,
291 .tx_queue_release = eth_igb_tx_queue_release,
295 * Atomically reads the link status information from global
296 * structure rte_eth_dev.
299 * - Pointer to the structure rte_eth_dev to read from.
300 * - Pointer to the buffer to be saved with the link status.
303 * - On success, zero.
304 * - On failure, negative value.
307 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
308 struct rte_eth_link *link)
310 struct rte_eth_link *dst = link;
311 struct rte_eth_link *src = &(dev->data->dev_link);
313 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
314 *(uint64_t *)src) == 0)
321 * Atomically writes the link status information into global
322 * structure rte_eth_dev.
325 * - Pointer to the structure rte_eth_dev to read from.
326 * - Pointer to the buffer to be saved with the link status.
329 * - On success, zero.
330 * - On failure, negative value.
333 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
334 struct rte_eth_link *link)
336 struct rte_eth_link *dst = &(dev->data->dev_link);
337 struct rte_eth_link *src = link;
339 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
340 *(uint64_t *)src) == 0)
347 igb_intr_enable(struct rte_eth_dev *dev)
349 struct e1000_interrupt *intr =
350 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
351 struct e1000_hw *hw =
352 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
354 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
355 E1000_WRITE_FLUSH(hw);
359 igb_intr_disable(struct e1000_hw *hw)
361 E1000_WRITE_REG(hw, E1000_IMC, ~0);
362 E1000_WRITE_FLUSH(hw);
365 static inline int32_t
366 igb_pf_reset_hw(struct e1000_hw *hw)
371 status = e1000_reset_hw(hw);
373 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
374 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
375 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
376 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
377 E1000_WRITE_FLUSH(hw);
383 igb_identify_hardware(struct rte_eth_dev *dev)
385 struct e1000_hw *hw =
386 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
388 hw->vendor_id = dev->pci_dev->id.vendor_id;
389 hw->device_id = dev->pci_dev->id.device_id;
390 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
391 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
393 e1000_set_mac_type(hw);
395 /* need to check if it is a vf device below */
399 igb_reset_swfw_lock(struct e1000_hw *hw)
404 * Do mac ops initialization manually here, since we will need
405 * some function pointers set by this call.
407 ret_val = e1000_init_mac_params(hw);
412 * SMBI lock should not fail in this early stage. If this is the case,
413 * it is due to an improper exit of the application.
414 * So force the release of the faulty lock.
416 if (e1000_get_hw_semaphore_generic(hw) < 0) {
417 PMD_DRV_LOG(DEBUG, "SMBI lock released");
419 e1000_put_hw_semaphore_generic(hw);
421 if (hw->mac.ops.acquire_swfw_sync != NULL) {
425 * Phy lock should not fail in this early stage. If this is the case,
426 * it is due to an improper exit of the application.
427 * So force the release of the faulty lock.
429 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
430 if (hw->bus.func > E1000_FUNC_1)
432 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
433 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
436 hw->mac.ops.release_swfw_sync(hw, mask);
439 * This one is more tricky since it is common to all ports; but
440 * swfw_sync retries last long enough (1s) to be almost sure that if
441 * lock can not be taken it is due to an improper lock of the
444 mask = E1000_SWFW_EEP_SM;
445 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
446 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
448 hw->mac.ops.release_swfw_sync(hw, mask);
451 return E1000_SUCCESS;
455 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
456 struct rte_eth_dev *eth_dev)
459 struct rte_pci_device *pci_dev;
460 struct e1000_hw *hw =
461 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
462 struct e1000_vfta * shadow_vfta =
463 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
466 pci_dev = eth_dev->pci_dev;
467 eth_dev->dev_ops = ð_igb_ops;
468 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
469 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
471 /* for secondary processes, we don't initialise any further as primary
472 * has already done this work. Only check we don't need a different
474 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
475 if (eth_dev->data->scattered_rx)
476 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
480 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
482 igb_identify_hardware(eth_dev);
483 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
488 e1000_get_bus_info(hw);
490 /* Reset any pending lock */
491 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
496 /* Finish initialization */
497 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
503 hw->phy.autoneg_wait_to_complete = 0;
504 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
507 if (hw->phy.media_type == e1000_media_type_copper) {
508 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
509 hw->phy.disable_polarity_correction = 0;
510 hw->phy.ms_type = e1000_ms_hw_default;
514 * Start from a known state, this is important in reading the nvm
519 /* Make sure we have a good EEPROM before we read from it */
520 if (e1000_validate_nvm_checksum(hw) < 0) {
522 * Some PCI-E parts fail the first check due to
523 * the link being in sleep state, call it again,
524 * if it fails a second time its a real issue.
526 if (e1000_validate_nvm_checksum(hw) < 0) {
527 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
533 /* Read the permanent MAC address out of the EEPROM */
534 if (e1000_read_mac_addr(hw) != 0) {
535 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
540 /* Allocate memory for storing MAC addresses */
541 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
542 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
543 if (eth_dev->data->mac_addrs == NULL) {
544 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
545 "store MAC addresses",
546 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
551 /* Copy the permanent MAC address */
552 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
554 /* initialize the vfta */
555 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
557 /* Now initialize the hardware */
558 if (igb_hardware_init(hw) != 0) {
559 PMD_INIT_LOG(ERR, "Hardware initialization failed");
560 rte_free(eth_dev->data->mac_addrs);
561 eth_dev->data->mac_addrs = NULL;
565 hw->mac.get_link_status = 1;
567 /* Indicate SOL/IDER usage */
568 if (e1000_check_reset_block(hw) < 0) {
569 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
573 /* initialize PF if max_vfs not zero */
574 igb_pf_host_init(eth_dev);
576 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
577 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
578 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
579 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
580 E1000_WRITE_FLUSH(hw);
582 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
583 eth_dev->data->port_id, pci_dev->id.vendor_id,
584 pci_dev->id.device_id);
586 rte_intr_callback_register(&(pci_dev->intr_handle),
587 eth_igb_interrupt_handler, (void *)eth_dev);
589 /* enable uio intr after callback register */
590 rte_intr_enable(&(pci_dev->intr_handle));
592 /* enable support intr */
593 igb_intr_enable(eth_dev);
598 igb_hw_control_release(hw);
604 * Virtual Function device init
607 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
608 struct rte_eth_dev *eth_dev)
610 struct rte_pci_device *pci_dev;
611 struct e1000_hw *hw =
612 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
615 PMD_INIT_FUNC_TRACE();
617 eth_dev->dev_ops = &igbvf_eth_dev_ops;
618 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
619 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
621 /* for secondary processes, we don't initialise any further as primary
622 * has already done this work. Only check we don't need a different
624 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
625 if (eth_dev->data->scattered_rx)
626 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
630 pci_dev = eth_dev->pci_dev;
632 hw->device_id = pci_dev->id.device_id;
633 hw->vendor_id = pci_dev->id.vendor_id;
634 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
636 /* Initialize the shared code (base driver) */
637 diag = e1000_setup_init_funcs(hw, TRUE);
639 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
644 /* init_mailbox_params */
645 hw->mbx.ops.init_params(hw);
647 /* Disable the interrupts for VF */
648 igbvf_intr_disable(hw);
650 diag = hw->mac.ops.reset_hw(hw);
652 /* Allocate memory for storing MAC addresses */
653 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
654 hw->mac.rar_entry_count, 0);
655 if (eth_dev->data->mac_addrs == NULL) {
657 "Failed to allocate %d bytes needed to store MAC "
659 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
663 /* Copy the permanent MAC address */
664 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
665 ð_dev->data->mac_addrs[0]);
667 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
669 eth_dev->data->port_id, pci_dev->id.vendor_id,
670 pci_dev->id.device_id, "igb_mac_82576_vf");
675 static struct eth_driver rte_igb_pmd = {
677 .name = "rte_igb_pmd",
678 .id_table = pci_id_igb_map,
679 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
681 .eth_dev_init = eth_igb_dev_init,
682 .dev_private_size = sizeof(struct e1000_adapter),
686 * virtual function driver struct
688 static struct eth_driver rte_igbvf_pmd = {
690 .name = "rte_igbvf_pmd",
691 .id_table = pci_id_igbvf_map,
692 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
694 .eth_dev_init = eth_igbvf_dev_init,
695 .dev_private_size = sizeof(struct e1000_adapter),
699 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
701 rte_eth_driver_register(&rte_igb_pmd);
706 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
708 struct e1000_hw *hw =
709 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
710 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
711 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
712 rctl |= E1000_RCTL_VFE;
713 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
717 * VF Driver initialization routine.
718 * Invoked one at EAL init time.
719 * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
722 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
724 PMD_INIT_FUNC_TRACE();
726 rte_eth_driver_register(&rte_igbvf_pmd);
731 eth_igb_configure(struct rte_eth_dev *dev)
733 struct e1000_interrupt *intr =
734 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
736 PMD_INIT_FUNC_TRACE();
737 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
738 PMD_INIT_FUNC_TRACE();
744 eth_igb_start(struct rte_eth_dev *dev)
746 struct e1000_hw *hw =
747 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
751 PMD_INIT_FUNC_TRACE();
753 /* Power up the phy. Needed to make the link go Up */
754 e1000_power_up_phy(hw);
757 * Packet Buffer Allocation (PBA)
758 * Writing PBA sets the receive portion of the buffer
759 * the remainder is used for the transmit buffer.
761 if (hw->mac.type == e1000_82575) {
764 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
765 E1000_WRITE_REG(hw, E1000_PBA, pba);
768 /* Put the address into the Receive Address Array */
769 e1000_rar_set(hw, hw->mac.addr, 0);
771 /* Initialize the hardware */
772 if (igb_hardware_init(hw)) {
773 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
777 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
779 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
780 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
781 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
782 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
783 E1000_WRITE_FLUSH(hw);
785 /* configure PF module if SRIOV enabled */
786 igb_pf_host_configure(dev);
788 /* Configure for OS presence */
789 igb_init_manageability(hw);
791 eth_igb_tx_init(dev);
793 /* This can fail when allocating mbufs for descriptor rings */
794 ret = eth_igb_rx_init(dev);
796 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
797 igb_dev_clear_queues(dev);
801 e1000_clear_hw_cntrs_base_generic(hw);
804 * VLAN Offload Settings
806 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
807 ETH_VLAN_EXTEND_MASK;
808 eth_igb_vlan_offload_set(dev, mask);
810 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
811 /* Enable VLAN filter since VMDq always use VLAN filter */
812 igb_vmdq_vlan_hw_filter_enable(dev);
816 * Configure the Interrupt Moderation register (EITR) with the maximum
817 * possible value (0xFFFF) to minimize "System Partial Write" issued by
818 * spurious [DMA] memory updates of RX and TX ring descriptors.
820 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
821 * spurious memory updates per second should be expected.
822 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
824 * Because interrupts are not used at all, the MSI-X is not activated
825 * and interrupt moderation is controlled by EITR[0].
827 * Note that having [almost] disabled memory updates of RX and TX ring
828 * descriptors through the Interrupt Moderation mechanism, memory
829 * updates of ring descriptors are now moderated by the configurable
830 * value of Write-Back Threshold registers.
832 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
833 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
834 (hw->mac.type == e1000_i211)) {
837 /* Enable all RX & TX queues in the IVAR registers */
838 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
839 for (i = 0; i < 8; i++)
840 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
842 /* Configure EITR with the maximum possible value (0xFFFF) */
843 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
846 /* Setup link speed and duplex */
847 switch (dev->data->dev_conf.link_speed) {
848 case ETH_LINK_SPEED_AUTONEG:
849 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
850 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
851 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
852 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
853 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
854 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
856 goto error_invalid_config;
858 case ETH_LINK_SPEED_10:
859 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
860 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
861 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
862 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
863 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
864 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
866 goto error_invalid_config;
868 case ETH_LINK_SPEED_100:
869 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
870 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
871 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
872 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
873 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
874 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
876 goto error_invalid_config;
878 case ETH_LINK_SPEED_1000:
879 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
880 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
881 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
883 goto error_invalid_config;
885 case ETH_LINK_SPEED_10000:
887 goto error_invalid_config;
889 e1000_setup_link(hw);
891 /* check if lsc interrupt feature is enabled */
892 if (dev->data->dev_conf.intr_conf.lsc != 0)
893 ret = eth_igb_lsc_interrupt_setup(dev);
895 /* resume enabled intr since hw reset */
896 igb_intr_enable(dev);
898 PMD_INIT_LOG(DEBUG, "<<");
902 error_invalid_config:
903 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
904 dev->data->dev_conf.link_speed,
905 dev->data->dev_conf.link_duplex, dev->data->port_id);
906 igb_dev_clear_queues(dev);
910 /*********************************************************************
912 * This routine disables all traffic on the adapter by issuing a
913 * global reset on the MAC.
915 **********************************************************************/
917 eth_igb_stop(struct rte_eth_dev *dev)
919 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
920 struct rte_eth_link link;
922 igb_intr_disable(hw);
924 E1000_WRITE_REG(hw, E1000_WUC, 0);
926 /* Set bit for Go Link disconnect */
927 if (hw->mac.type >= e1000_82580) {
930 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
931 phpm_reg |= E1000_82580_PM_GO_LINKD;
932 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
935 /* Power down the phy. Needed to make the link go Down */
936 e1000_power_down_phy(hw);
938 igb_dev_clear_queues(dev);
940 /* clear the recorded link status */
941 memset(&link, 0, sizeof(link));
942 rte_igb_dev_atomic_write_link_status(dev, &link);
946 eth_igb_close(struct rte_eth_dev *dev)
948 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
949 struct rte_eth_link link;
952 e1000_phy_hw_reset(hw);
953 igb_release_manageability(hw);
954 igb_hw_control_release(hw);
956 /* Clear bit for Go Link disconnect */
957 if (hw->mac.type >= e1000_82580) {
960 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
961 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
962 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
965 igb_dev_clear_queues(dev);
967 memset(&link, 0, sizeof(link));
968 rte_igb_dev_atomic_write_link_status(dev, &link);
972 igb_get_rx_buffer_size(struct e1000_hw *hw)
974 uint32_t rx_buf_size;
975 if (hw->mac.type == e1000_82576) {
976 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
977 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
978 /* PBS needs to be translated according to a lookup table */
979 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
980 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
981 rx_buf_size = (rx_buf_size << 10);
982 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
983 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
985 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
991 /*********************************************************************
993 * Initialize the hardware
995 **********************************************************************/
997 igb_hardware_init(struct e1000_hw *hw)
999 uint32_t rx_buf_size;
1002 /* Let the firmware know the OS is in control */
1003 igb_hw_control_acquire(hw);
1006 * These parameters control the automatic generation (Tx) and
1007 * response (Rx) to Ethernet PAUSE frames.
1008 * - High water mark should allow for at least two standard size (1518)
1009 * frames to be received after sending an XOFF.
1010 * - Low water mark works best when it is very near the high water mark.
1011 * This allows the receiver to restart by sending XON when it has
1012 * drained a bit. Here we use an arbitrary value of 1500 which will
1013 * restart after one full frame is pulled from the buffer. There
1014 * could be several smaller frames in the buffer and if so they will
1015 * not trigger the XON until their total number reduces the buffer
1017 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1019 rx_buf_size = igb_get_rx_buffer_size(hw);
1021 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1022 hw->fc.low_water = hw->fc.high_water - 1500;
1023 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1024 hw->fc.send_xon = 1;
1026 /* Set Flow control, use the tunable location if sane */
1027 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1028 hw->fc.requested_mode = igb_fc_setting;
1030 hw->fc.requested_mode = e1000_fc_none;
1032 /* Issue a global reset */
1033 igb_pf_reset_hw(hw);
1034 E1000_WRITE_REG(hw, E1000_WUC, 0);
1036 diag = e1000_init_hw(hw);
1040 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1041 e1000_get_phy_info(hw);
1042 e1000_check_for_link(hw);
1047 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1049 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1051 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052 struct e1000_hw_stats *stats =
1053 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1056 if(hw->phy.media_type == e1000_media_type_copper ||
1057 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1059 E1000_READ_REG(hw,E1000_SYMERRS);
1060 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1063 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1064 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1065 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1066 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1068 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1069 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1070 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1071 stats->dc += E1000_READ_REG(hw, E1000_DC);
1072 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1073 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1074 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1076 ** For watchdog management we need to know if we have been
1077 ** paused during the last interval, so capture that here.
1079 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1080 stats->xoffrxc += pause_frames;
1081 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1082 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1083 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1084 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1085 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1086 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1087 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1088 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1089 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1090 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1091 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1092 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1094 /* For the 64-bit byte counters the low dword must be read first. */
1095 /* Both registers clear on the read of the high dword */
1097 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1098 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1099 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1100 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1102 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1103 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1104 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1105 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1106 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1108 stats->tor += E1000_READ_REG(hw, E1000_TORH);
1109 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1111 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1112 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1113 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1114 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1115 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1116 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1117 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1118 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1119 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1120 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1122 /* Interrupt Counts */
1124 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1125 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1126 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1127 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1128 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1129 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1130 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1131 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1132 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1134 /* Host to Card Statistics */
1136 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1137 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1138 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1139 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1140 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1141 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1142 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1143 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1144 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1145 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1146 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1147 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1148 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1149 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1151 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1152 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1153 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1154 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1155 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1156 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1158 if (rte_stats == NULL)
1162 rte_stats->ibadcrc = stats->crcerrs;
1163 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1164 rte_stats->imissed = stats->mpc;
1165 rte_stats->ierrors = rte_stats->ibadcrc +
1166 rte_stats->ibadlen +
1167 rte_stats->imissed +
1168 stats->rxerrc + stats->algnerrc + stats->cexterr;
1171 rte_stats->oerrors = stats->ecol + stats->latecol;
1173 /* XON/XOFF pause frames */
1174 rte_stats->tx_pause_xon = stats->xontxc;
1175 rte_stats->rx_pause_xon = stats->xonrxc;
1176 rte_stats->tx_pause_xoff = stats->xofftxc;
1177 rte_stats->rx_pause_xoff = stats->xoffrxc;
1179 rte_stats->ipackets = stats->gprc;
1180 rte_stats->opackets = stats->gptc;
1181 rte_stats->ibytes = stats->gorc;
1182 rte_stats->obytes = stats->gotc;
1186 eth_igb_stats_reset(struct rte_eth_dev *dev)
1188 struct e1000_hw_stats *hw_stats =
1189 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1191 /* HW registers are cleared on read */
1192 eth_igb_stats_get(dev, NULL);
1194 /* Reset software totals */
1195 memset(hw_stats, 0, sizeof(*hw_stats));
1199 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1201 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1203 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1205 /* Good Rx packets, include VF loopback */
1206 UPDATE_VF_STAT(E1000_VFGPRC,
1207 hw_stats->last_gprc, hw_stats->gprc);
1209 /* Good Rx octets, include VF loopback */
1210 UPDATE_VF_STAT(E1000_VFGORC,
1211 hw_stats->last_gorc, hw_stats->gorc);
1213 /* Good Tx packets, include VF loopback */
1214 UPDATE_VF_STAT(E1000_VFGPTC,
1215 hw_stats->last_gptc, hw_stats->gptc);
1217 /* Good Tx octets, include VF loopback */
1218 UPDATE_VF_STAT(E1000_VFGOTC,
1219 hw_stats->last_gotc, hw_stats->gotc);
1221 /* Rx Multicst packets */
1222 UPDATE_VF_STAT(E1000_VFMPRC,
1223 hw_stats->last_mprc, hw_stats->mprc);
1225 /* Good Rx loopback packets */
1226 UPDATE_VF_STAT(E1000_VFGPRLBC,
1227 hw_stats->last_gprlbc, hw_stats->gprlbc);
1229 /* Good Rx loopback octets */
1230 UPDATE_VF_STAT(E1000_VFGORLBC,
1231 hw_stats->last_gorlbc, hw_stats->gorlbc);
1233 /* Good Tx loopback packets */
1234 UPDATE_VF_STAT(E1000_VFGPTLBC,
1235 hw_stats->last_gptlbc, hw_stats->gptlbc);
1237 /* Good Tx loopback octets */
1238 UPDATE_VF_STAT(E1000_VFGOTLBC,
1239 hw_stats->last_gotlbc, hw_stats->gotlbc);
1241 if (rte_stats == NULL)
1244 memset(rte_stats, 0, sizeof(*rte_stats));
1245 rte_stats->ipackets = hw_stats->gprc;
1246 rte_stats->ibytes = hw_stats->gorc;
1247 rte_stats->opackets = hw_stats->gptc;
1248 rte_stats->obytes = hw_stats->gotc;
1249 rte_stats->imcasts = hw_stats->mprc;
1250 rte_stats->ilbpackets = hw_stats->gprlbc;
1251 rte_stats->ilbbytes = hw_stats->gorlbc;
1252 rte_stats->olbpackets = hw_stats->gptlbc;
1253 rte_stats->olbbytes = hw_stats->gotlbc;
1258 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1260 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1261 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1263 /* Sync HW register to the last stats */
1264 eth_igbvf_stats_get(dev, NULL);
1266 /* reset HW current stats*/
1267 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1268 offsetof(struct e1000_vf_stats, gprc));
1273 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1275 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1278 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1279 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1280 dev_info->rx_offload_capa =
1281 DEV_RX_OFFLOAD_VLAN_STRIP |
1282 DEV_RX_OFFLOAD_IPV4_CKSUM |
1283 DEV_RX_OFFLOAD_UDP_CKSUM |
1284 DEV_RX_OFFLOAD_TCP_CKSUM;
1285 dev_info->tx_offload_capa =
1286 DEV_TX_OFFLOAD_VLAN_INSERT |
1287 DEV_TX_OFFLOAD_IPV4_CKSUM |
1288 DEV_TX_OFFLOAD_UDP_CKSUM |
1289 DEV_TX_OFFLOAD_TCP_CKSUM |
1290 DEV_TX_OFFLOAD_SCTP_CKSUM;
1292 switch (hw->mac.type) {
1294 dev_info->max_rx_queues = 4;
1295 dev_info->max_tx_queues = 4;
1296 dev_info->max_vmdq_pools = 0;
1300 dev_info->max_rx_queues = 16;
1301 dev_info->max_tx_queues = 16;
1302 dev_info->max_vmdq_pools = ETH_8_POOLS;
1303 dev_info->vmdq_queue_num = 16;
1307 dev_info->max_rx_queues = 8;
1308 dev_info->max_tx_queues = 8;
1309 dev_info->max_vmdq_pools = ETH_8_POOLS;
1310 dev_info->vmdq_queue_num = 8;
1314 dev_info->max_rx_queues = 8;
1315 dev_info->max_tx_queues = 8;
1316 dev_info->max_vmdq_pools = ETH_8_POOLS;
1317 dev_info->vmdq_queue_num = 8;
1321 dev_info->max_rx_queues = 8;
1322 dev_info->max_tx_queues = 8;
1326 dev_info->max_rx_queues = 4;
1327 dev_info->max_tx_queues = 4;
1328 dev_info->max_vmdq_pools = 0;
1332 dev_info->max_rx_queues = 2;
1333 dev_info->max_tx_queues = 2;
1334 dev_info->max_vmdq_pools = 0;
1338 /* Should not happen */
1341 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1343 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1345 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1346 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1347 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1349 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1353 dev_info->default_txconf = (struct rte_eth_txconf) {
1355 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1356 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1357 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1364 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1366 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1369 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1370 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1371 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1372 DEV_RX_OFFLOAD_IPV4_CKSUM |
1373 DEV_RX_OFFLOAD_UDP_CKSUM |
1374 DEV_RX_OFFLOAD_TCP_CKSUM;
1375 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1376 DEV_TX_OFFLOAD_IPV4_CKSUM |
1377 DEV_TX_OFFLOAD_UDP_CKSUM |
1378 DEV_TX_OFFLOAD_TCP_CKSUM |
1379 DEV_TX_OFFLOAD_SCTP_CKSUM;
1380 switch (hw->mac.type) {
1382 dev_info->max_rx_queues = 2;
1383 dev_info->max_tx_queues = 2;
1385 case e1000_vfadapt_i350:
1386 dev_info->max_rx_queues = 1;
1387 dev_info->max_tx_queues = 1;
1390 /* Should not happen */
1394 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1396 .pthresh = IGB_DEFAULT_RX_PTHRESH,
1397 .hthresh = IGB_DEFAULT_RX_HTHRESH,
1398 .wthresh = IGB_DEFAULT_RX_WTHRESH,
1400 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1404 dev_info->default_txconf = (struct rte_eth_txconf) {
1406 .pthresh = IGB_DEFAULT_TX_PTHRESH,
1407 .hthresh = IGB_DEFAULT_TX_HTHRESH,
1408 .wthresh = IGB_DEFAULT_TX_WTHRESH,
1414 /* return 0 means link status changed, -1 means not changed */
1416 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1418 struct e1000_hw *hw =
1419 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420 struct rte_eth_link link, old;
1421 int link_check, count;
1424 hw->mac.get_link_status = 1;
1426 /* possible wait-to-complete in up to 9 seconds */
1427 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1428 /* Read the real link status */
1429 switch (hw->phy.media_type) {
1430 case e1000_media_type_copper:
1431 /* Do the work to read phy */
1432 e1000_check_for_link(hw);
1433 link_check = !hw->mac.get_link_status;
1436 case e1000_media_type_fiber:
1437 e1000_check_for_link(hw);
1438 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1442 case e1000_media_type_internal_serdes:
1443 e1000_check_for_link(hw);
1444 link_check = hw->mac.serdes_has_link;
1447 /* VF device is type_unknown */
1448 case e1000_media_type_unknown:
1449 eth_igbvf_link_update(hw);
1450 link_check = !hw->mac.get_link_status;
1456 if (link_check || wait_to_complete == 0)
1458 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1460 memset(&link, 0, sizeof(link));
1461 rte_igb_dev_atomic_read_link_status(dev, &link);
1464 /* Now we check if a transition has happened */
1466 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1468 link.link_status = 1;
1469 } else if (!link_check) {
1470 link.link_speed = 0;
1471 link.link_duplex = 0;
1472 link.link_status = 0;
1474 rte_igb_dev_atomic_write_link_status(dev, &link);
1477 if (old.link_status == link.link_status)
1485 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1486 * For ASF and Pass Through versions of f/w this means
1487 * that the driver is loaded.
1490 igb_hw_control_acquire(struct e1000_hw *hw)
1494 /* Let firmware know the driver has taken over */
1495 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1496 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1500 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1501 * For ASF and Pass Through versions of f/w this means that the
1502 * driver is no longer loaded.
1505 igb_hw_control_release(struct e1000_hw *hw)
1509 /* Let firmware taken over control of h/w */
1510 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1511 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1512 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1516 * Bit of a misnomer, what this really means is
1517 * to enable OS management of the system... aka
1518 * to disable special hardware management features.
1521 igb_init_manageability(struct e1000_hw *hw)
1523 if (e1000_enable_mng_pass_thru(hw)) {
1524 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1525 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1527 /* disable hardware interception of ARP */
1528 manc &= ~(E1000_MANC_ARP_EN);
1530 /* enable receiving management packets to the host */
1531 manc |= E1000_MANC_EN_MNG2HOST;
1532 manc2h |= 1 << 5; /* Mng Port 623 */
1533 manc2h |= 1 << 6; /* Mng Port 664 */
1534 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1535 E1000_WRITE_REG(hw, E1000_MANC, manc);
1540 igb_release_manageability(struct e1000_hw *hw)
1542 if (e1000_enable_mng_pass_thru(hw)) {
1543 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1545 manc |= E1000_MANC_ARP_EN;
1546 manc &= ~E1000_MANC_EN_MNG2HOST;
1548 E1000_WRITE_REG(hw, E1000_MANC, manc);
1553 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1555 struct e1000_hw *hw =
1556 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559 rctl = E1000_READ_REG(hw, E1000_RCTL);
1560 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1561 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1565 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1567 struct e1000_hw *hw =
1568 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571 rctl = E1000_READ_REG(hw, E1000_RCTL);
1572 rctl &= (~E1000_RCTL_UPE);
1573 if (dev->data->all_multicast == 1)
1574 rctl |= E1000_RCTL_MPE;
1576 rctl &= (~E1000_RCTL_MPE);
1577 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1581 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1583 struct e1000_hw *hw =
1584 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587 rctl = E1000_READ_REG(hw, E1000_RCTL);
1588 rctl |= E1000_RCTL_MPE;
1589 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1593 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1595 struct e1000_hw *hw =
1596 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599 if (dev->data->promiscuous == 1)
1600 return; /* must remain in all_multicast mode */
1601 rctl = E1000_READ_REG(hw, E1000_RCTL);
1602 rctl &= (~E1000_RCTL_MPE);
1603 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1607 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1609 struct e1000_hw *hw =
1610 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611 struct e1000_vfta * shadow_vfta =
1612 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1617 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1618 E1000_VFTA_ENTRY_MASK);
1619 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1620 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1625 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1627 /* update local VFTA copy */
1628 shadow_vfta->vfta[vid_idx] = vfta;
1634 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1636 struct e1000_hw *hw =
1637 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638 uint32_t reg = ETHER_TYPE_VLAN ;
1640 reg |= (tpid << 16);
1641 E1000_WRITE_REG(hw, E1000_VET, reg);
1645 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1647 struct e1000_hw *hw =
1648 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651 /* Filter Table Disable */
1652 reg = E1000_READ_REG(hw, E1000_RCTL);
1653 reg &= ~E1000_RCTL_CFIEN;
1654 reg &= ~E1000_RCTL_VFE;
1655 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1659 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1661 struct e1000_hw *hw =
1662 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 struct e1000_vfta * shadow_vfta =
1664 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1668 /* Filter Table Enable, CFI not used for packet acceptance */
1669 reg = E1000_READ_REG(hw, E1000_RCTL);
1670 reg &= ~E1000_RCTL_CFIEN;
1671 reg |= E1000_RCTL_VFE;
1672 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1674 /* restore VFTA table */
1675 for (i = 0; i < IGB_VFTA_SIZE; i++)
1676 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1680 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1682 struct e1000_hw *hw =
1683 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686 /* VLAN Mode Disable */
1687 reg = E1000_READ_REG(hw, E1000_CTRL);
1688 reg &= ~E1000_CTRL_VME;
1689 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1693 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1695 struct e1000_hw *hw =
1696 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699 /* VLAN Mode Enable */
1700 reg = E1000_READ_REG(hw, E1000_CTRL);
1701 reg |= E1000_CTRL_VME;
1702 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1706 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1708 struct e1000_hw *hw =
1709 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712 /* CTRL_EXT: Extended VLAN */
1713 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1714 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1715 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1717 /* Update maximum packet length */
1718 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1719 E1000_WRITE_REG(hw, E1000_RLPML,
1720 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1725 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1727 struct e1000_hw *hw =
1728 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1731 /* CTRL_EXT: Extended VLAN */
1732 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1733 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1734 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1736 /* Update maximum packet length */
1737 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1738 E1000_WRITE_REG(hw, E1000_RLPML,
1739 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1744 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1746 if(mask & ETH_VLAN_STRIP_MASK){
1747 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1748 igb_vlan_hw_strip_enable(dev);
1750 igb_vlan_hw_strip_disable(dev);
1753 if(mask & ETH_VLAN_FILTER_MASK){
1754 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1755 igb_vlan_hw_filter_enable(dev);
1757 igb_vlan_hw_filter_disable(dev);
1760 if(mask & ETH_VLAN_EXTEND_MASK){
1761 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1762 igb_vlan_hw_extend_enable(dev);
1764 igb_vlan_hw_extend_disable(dev);
1770 * It enables the interrupt mask and then enable the interrupt.
1773 * Pointer to struct rte_eth_dev.
1776 * - On success, zero.
1777 * - On failure, a negative value.
1780 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1782 struct e1000_interrupt *intr =
1783 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1785 intr->mask |= E1000_ICR_LSC;
1791 * It reads ICR and gets interrupt causes, check it and set a bit flag
1792 * to update link status.
1795 * Pointer to struct rte_eth_dev.
1798 * - On success, zero.
1799 * - On failure, a negative value.
1802 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1805 struct e1000_hw *hw =
1806 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807 struct e1000_interrupt *intr =
1808 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1810 igb_intr_disable(hw);
1812 /* read-on-clear nic registers here */
1813 icr = E1000_READ_REG(hw, E1000_ICR);
1816 if (icr & E1000_ICR_LSC) {
1817 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1820 if (icr & E1000_ICR_VMMB)
1821 intr->flags |= E1000_FLAG_MAILBOX;
1827 * It executes link_update after knowing an interrupt is prsent.
1830 * Pointer to struct rte_eth_dev.
1833 * - On success, zero.
1834 * - On failure, a negative value.
1837 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1839 struct e1000_hw *hw =
1840 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841 struct e1000_interrupt *intr =
1842 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1843 uint32_t tctl, rctl;
1844 struct rte_eth_link link;
1847 if (intr->flags & E1000_FLAG_MAILBOX) {
1848 igb_pf_mbx_process(dev);
1849 intr->flags &= ~E1000_FLAG_MAILBOX;
1852 igb_intr_enable(dev);
1853 rte_intr_enable(&(dev->pci_dev->intr_handle));
1855 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1856 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1858 /* set get_link_status to check register later */
1859 hw->mac.get_link_status = 1;
1860 ret = eth_igb_link_update(dev, 0);
1862 /* check if link has changed */
1866 memset(&link, 0, sizeof(link));
1867 rte_igb_dev_atomic_read_link_status(dev, &link);
1868 if (link.link_status) {
1870 " Port %d: Link Up - speed %u Mbps - %s",
1872 (unsigned)link.link_speed,
1873 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1874 "full-duplex" : "half-duplex");
1876 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1877 dev->data->port_id);
1879 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1880 dev->pci_dev->addr.domain,
1881 dev->pci_dev->addr.bus,
1882 dev->pci_dev->addr.devid,
1883 dev->pci_dev->addr.function);
1884 tctl = E1000_READ_REG(hw, E1000_TCTL);
1885 rctl = E1000_READ_REG(hw, E1000_RCTL);
1886 if (link.link_status) {
1888 tctl |= E1000_TCTL_EN;
1889 rctl |= E1000_RCTL_EN;
1892 tctl &= ~E1000_TCTL_EN;
1893 rctl &= ~E1000_RCTL_EN;
1895 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1896 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1897 E1000_WRITE_FLUSH(hw);
1898 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1905 * Interrupt handler which shall be registered at first.
1908 * Pointer to interrupt handle.
1910 * The address of parameter (struct rte_eth_dev *) regsitered before.
1916 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1919 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1921 eth_igb_interrupt_get_status(dev);
1922 eth_igb_interrupt_action(dev);
1926 eth_igb_led_on(struct rte_eth_dev *dev)
1928 struct e1000_hw *hw;
1930 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1935 eth_igb_led_off(struct rte_eth_dev *dev)
1937 struct e1000_hw *hw;
1939 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1944 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1946 struct e1000_hw *hw;
1951 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952 fc_conf->pause_time = hw->fc.pause_time;
1953 fc_conf->high_water = hw->fc.high_water;
1954 fc_conf->low_water = hw->fc.low_water;
1955 fc_conf->send_xon = hw->fc.send_xon;
1956 fc_conf->autoneg = hw->mac.autoneg;
1959 * Return rx_pause and tx_pause status according to actual setting of
1960 * the TFCE and RFCE bits in the CTRL register.
1962 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1963 if (ctrl & E1000_CTRL_TFCE)
1968 if (ctrl & E1000_CTRL_RFCE)
1973 if (rx_pause && tx_pause)
1974 fc_conf->mode = RTE_FC_FULL;
1976 fc_conf->mode = RTE_FC_RX_PAUSE;
1978 fc_conf->mode = RTE_FC_TX_PAUSE;
1980 fc_conf->mode = RTE_FC_NONE;
1986 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1988 struct e1000_hw *hw;
1990 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1996 uint32_t rx_buf_size;
1997 uint32_t max_high_water;
2000 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001 if (fc_conf->autoneg != hw->mac.autoneg)
2003 rx_buf_size = igb_get_rx_buffer_size(hw);
2004 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2006 /* At least reserve one Ethernet frame for watermark */
2007 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2008 if ((fc_conf->high_water > max_high_water) ||
2009 (fc_conf->high_water < fc_conf->low_water)) {
2010 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2011 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2015 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2016 hw->fc.pause_time = fc_conf->pause_time;
2017 hw->fc.high_water = fc_conf->high_water;
2018 hw->fc.low_water = fc_conf->low_water;
2019 hw->fc.send_xon = fc_conf->send_xon;
2021 err = e1000_setup_link_generic(hw);
2022 if (err == E1000_SUCCESS) {
2024 /* check if we want to forward MAC frames - driver doesn't have native
2025 * capability to do that, so we'll write the registers ourselves */
2027 rctl = E1000_READ_REG(hw, E1000_RCTL);
2029 /* set or clear MFLCN.PMCF bit depending on configuration */
2030 if (fc_conf->mac_ctrl_frame_fwd != 0)
2031 rctl |= E1000_RCTL_PMCF;
2033 rctl &= ~E1000_RCTL_PMCF;
2035 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2036 E1000_WRITE_FLUSH(hw);
2041 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2045 #define E1000_RAH_POOLSEL_SHIFT (18)
2047 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2048 uint32_t index, __rte_unused uint32_t pool)
2050 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2054 rah = E1000_READ_REG(hw, E1000_RAH(index));
2055 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2056 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2060 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2062 uint8_t addr[ETHER_ADDR_LEN];
2063 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 memset(addr, 0, sizeof(addr));
2067 e1000_rar_set(hw, addr, index);
2071 * Virtual Function operations
2074 igbvf_intr_disable(struct e1000_hw *hw)
2076 PMD_INIT_FUNC_TRACE();
2078 /* Clear interrupt mask to stop from interrupts being generated */
2079 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2081 E1000_WRITE_FLUSH(hw);
2085 igbvf_stop_adapter(struct rte_eth_dev *dev)
2089 struct rte_eth_dev_info dev_info;
2090 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092 memset(&dev_info, 0, sizeof(dev_info));
2093 eth_igbvf_infos_get(dev, &dev_info);
2095 /* Clear interrupt mask to stop from interrupts being generated */
2096 igbvf_intr_disable(hw);
2098 /* Clear any pending interrupts, flush previous writes */
2099 E1000_READ_REG(hw, E1000_EICR);
2101 /* Disable the transmit unit. Each queue must be disabled. */
2102 for (i = 0; i < dev_info.max_tx_queues; i++)
2103 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2105 /* Disable the receive unit by stopping each queue */
2106 for (i = 0; i < dev_info.max_rx_queues; i++) {
2107 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2108 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2109 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2110 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2114 /* flush all queues disables */
2115 E1000_WRITE_FLUSH(hw);
2119 static int eth_igbvf_link_update(struct e1000_hw *hw)
2121 struct e1000_mbx_info *mbx = &hw->mbx;
2122 struct e1000_mac_info *mac = &hw->mac;
2123 int ret_val = E1000_SUCCESS;
2125 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2128 * We only want to run this if there has been a rst asserted.
2129 * in this case that could mean a link change, device reset,
2130 * or a virtual function reset
2133 /* If we were hit with a reset or timeout drop the link */
2134 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2135 mac->get_link_status = TRUE;
2137 if (!mac->get_link_status)
2140 /* if link status is down no point in checking to see if pf is up */
2141 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2144 /* if we passed all the tests above then the link is up and we no
2145 * longer need to check for link */
2146 mac->get_link_status = FALSE;
2154 igbvf_dev_configure(struct rte_eth_dev *dev)
2156 struct rte_eth_conf* conf = &dev->data->dev_conf;
2158 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2159 dev->data->port_id);
2162 * VF has no ability to enable/disable HW CRC
2163 * Keep the persistent behavior the same as Host PF
2165 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2166 if (!conf->rxmode.hw_strip_crc) {
2167 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2168 conf->rxmode.hw_strip_crc = 1;
2171 if (conf->rxmode.hw_strip_crc) {
2172 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2173 conf->rxmode.hw_strip_crc = 0;
2181 igbvf_dev_start(struct rte_eth_dev *dev)
2183 struct e1000_hw *hw =
2184 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187 PMD_INIT_FUNC_TRACE();
2189 hw->mac.ops.reset_hw(hw);
2192 igbvf_set_vfta_all(dev,1);
2194 eth_igbvf_tx_init(dev);
2196 /* This can fail when allocating mbufs for descriptor rings */
2197 ret = eth_igbvf_rx_init(dev);
2199 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2200 igb_dev_clear_queues(dev);
2208 igbvf_dev_stop(struct rte_eth_dev *dev)
2210 PMD_INIT_FUNC_TRACE();
2212 igbvf_stop_adapter(dev);
2215 * Clear what we set, but we still keep shadow_vfta to
2216 * restore after device starts
2218 igbvf_set_vfta_all(dev,0);
2220 igb_dev_clear_queues(dev);
2224 igbvf_dev_close(struct rte_eth_dev *dev)
2226 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228 PMD_INIT_FUNC_TRACE();
2232 igbvf_dev_stop(dev);
2235 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2237 struct e1000_mbx_info *mbx = &hw->mbx;
2240 /* After set vlan, vlan strip will also be enabled in igb driver*/
2241 msgbuf[0] = E1000_VF_SET_VLAN;
2243 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2245 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2247 return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2250 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2252 struct e1000_hw *hw =
2253 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254 struct e1000_vfta * shadow_vfta =
2255 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2256 int i = 0, j = 0, vfta = 0, mask = 1;
2258 for (i = 0; i < IGB_VFTA_SIZE; i++){
2259 vfta = shadow_vfta->vfta[i];
2262 for (j = 0; j < 32; j++){
2265 (uint16_t)((i<<5)+j), on);
2274 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2276 struct e1000_hw *hw =
2277 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278 struct e1000_vfta * shadow_vfta =
2279 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2280 uint32_t vid_idx = 0;
2281 uint32_t vid_bit = 0;
2284 PMD_INIT_FUNC_TRACE();
2286 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2287 ret = igbvf_set_vfta(hw, vlan_id, !!on);
2289 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2292 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2293 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2295 /*Save what we set and retore it after device reset*/
2297 shadow_vfta->vfta[vid_idx] |= vid_bit;
2299 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2305 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2306 struct rte_eth_rss_reta *reta_conf)
2310 struct e1000_hw *hw =
2311 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2315 * 128-entries in 32 registers
2317 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2318 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2319 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2321 mask = (uint8_t)((reta_conf->mask_hi >>
2322 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2325 /* If all 4 entries were set,don't need read RETA register */
2327 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2329 for (j = 0; j < 4; j++) {
2330 if (mask & (0x1 << j)) {
2332 reta &= ~(0xFF << 8 * j);
2333 reta |= reta_conf->reta[i + j] << 8 * j;
2336 E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2344 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2345 struct rte_eth_rss_reta *reta_conf)
2349 struct e1000_hw *hw =
2350 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2354 * 128-entries in 32 registers
2356 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2357 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2358 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2360 mask = (uint8_t)((reta_conf->mask_hi >>
2361 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2364 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2365 for (j = 0; j < 4; j++) {
2366 if (mask & (0x1 << j))
2367 reta_conf->reta[i + j] =
2368 (uint8_t)((reta >> 8 * j) & 0xFF);
2376 #define MAC_TYPE_FILTER_SUP(type) do {\
2377 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2378 (type) != e1000_82576)\
2383 * add the syn filter
2386 * dev: Pointer to struct rte_eth_dev.
2387 * filter: ponter to the filter that will be added.
2388 * rx_queue: the queue id the filter assigned to.
2391 * - On success, zero.
2392 * - On failure, a negative value.
2395 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2396 struct rte_syn_filter *filter, uint16_t rx_queue)
2398 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399 uint32_t synqf, rfctl;
2401 MAC_TYPE_FILTER_SUP(hw->mac.type);
2403 if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2406 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2407 if (synqf & E1000_SYN_FILTER_ENABLE)
2410 synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2411 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2413 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2414 if (filter->hig_pri)
2415 rfctl |= E1000_RFCTL_SYNQFP;
2417 rfctl &= ~E1000_RFCTL_SYNQFP;
2419 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2420 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2425 * remove the syn filter
2428 * dev: Pointer to struct rte_eth_dev.
2431 * - On success, zero.
2432 * - On failure, a negative value.
2435 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2437 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439 MAC_TYPE_FILTER_SUP(hw->mac.type);
2441 E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2446 * get the syn filter's info
2449 * dev: Pointer to struct rte_eth_dev.
2450 * filter: ponter to the filter that returns.
2451 * *rx_queue: pointer to the queue id the filter assigned to.
2454 * - On success, zero.
2455 * - On failure, a negative value.
2458 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2459 struct rte_syn_filter *filter, uint16_t *rx_queue)
2461 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462 uint32_t synqf, rfctl;
2464 MAC_TYPE_FILTER_SUP(hw->mac.type);
2465 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2466 if (synqf & E1000_SYN_FILTER_ENABLE) {
2467 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2468 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2469 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2470 E1000_SYN_FILTER_QUEUE_SHIFT);
2477 * add an ethertype filter
2480 * dev: Pointer to struct rte_eth_dev.
2481 * index: the index the filter allocates.
2482 * filter: ponter to the filter that will be added.
2483 * rx_queue: the queue id the filter assigned to.
2486 * - On success, zero.
2487 * - On failure, a negative value.
2490 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2491 struct rte_ethertype_filter *filter, uint16_t rx_queue)
2493 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496 MAC_TYPE_FILTER_SUP(hw->mac.type);
2498 if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2501 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2502 if (etqf & E1000_ETQF_FILTER_ENABLE)
2503 return -EINVAL; /* filter index is in use. */
2507 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2508 etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2509 etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2511 if (filter->priority_en) {
2512 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2513 " in E1000.", filter->priority);
2517 E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2522 * remove an ethertype filter
2525 * dev: Pointer to struct rte_eth_dev.
2526 * index: the index the filter allocates.
2529 * - On success, zero.
2530 * - On failure, a negative value.
2533 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2535 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 MAC_TYPE_FILTER_SUP(hw->mac.type);
2539 if (index >= E1000_MAX_ETQF_FILTERS)
2542 E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2547 * get an ethertype filter
2550 * dev: Pointer to struct rte_eth_dev.
2551 * index: the index the filter allocates.
2552 * filter: ponter to the filter that will be gotten.
2553 * *rx_queue: the ponited of the queue id the filter assigned to.
2556 * - On success, zero.
2557 * - On failure, a negative value.
2560 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2561 struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2563 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2566 MAC_TYPE_FILTER_SUP(hw->mac.type);
2568 if (index >= E1000_MAX_ETQF_FILTERS)
2571 etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2572 if (etqf & E1000_ETQF_FILTER_ENABLE) {
2573 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2574 filter->priority_en = 0;
2575 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2581 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
2582 if ((type) != e1000_82580 && (type) != e1000_i350)\
2587 * add a 2tuple filter
2590 * dev: Pointer to struct rte_eth_dev.
2591 * index: the index the filter allocates.
2592 * filter: ponter to the filter that will be added.
2593 * rx_queue: the queue id the filter assigned to.
2596 * - On success, zero.
2597 * - On failure, a negative value.
2600 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2601 struct rte_2tuple_filter *filter, uint16_t rx_queue)
2603 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604 uint32_t ttqf, imir = 0;
2605 uint32_t imir_ext = 0;
2607 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2609 if (index >= E1000_MAX_TTQF_FILTERS ||
2610 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2611 filter->priority > E1000_2TUPLE_MAX_PRI)
2612 return -EINVAL; /* filter index is out of range. */
2613 if (filter->tcp_flags > TCP_FLAG_ALL)
2614 return -EINVAL; /* flags is invalid. */
2616 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2617 if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2618 return -EINVAL; /* filter index is in use. */
2620 imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2621 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2622 imir |= E1000_IMIR_PORT_BP;
2624 imir &= ~E1000_IMIR_PORT_BP;
2626 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2629 ttqf |= E1000_TTQF_QUEUE_ENABLE;
2630 ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2631 ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2632 if (filter->protocol_mask == 1)
2633 ttqf |= E1000_TTQF_MASK_ENABLE;
2635 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2637 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2638 /* tcp flags bits setting. */
2639 if (filter->tcp_flags & TCP_FLAG_ALL) {
2640 if (filter->tcp_flags & TCP_UGR_FLAG)
2641 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2642 if (filter->tcp_flags & TCP_ACK_FLAG)
2643 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2644 if (filter->tcp_flags & TCP_PSH_FLAG)
2645 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2646 if (filter->tcp_flags & TCP_RST_FLAG)
2647 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2648 if (filter->tcp_flags & TCP_SYN_FLAG)
2649 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2650 if (filter->tcp_flags & TCP_FIN_FLAG)
2651 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2652 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2654 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2655 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2656 E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2657 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2662 * remove a 2tuple filter
2665 * dev: Pointer to struct rte_eth_dev.
2666 * index: the index the filter allocates.
2669 * - On success, zero.
2670 * - On failure, a negative value.
2673 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2676 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2680 if (index >= E1000_MAX_TTQF_FILTERS)
2681 return -EINVAL; /* filter index is out of range */
2683 E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2684 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2685 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2690 * get a 2tuple filter
2693 * dev: Pointer to struct rte_eth_dev.
2694 * index: the index the filter allocates.
2695 * filter: ponter to the filter that returns.
2696 * *rx_queue: pointer of the queue id the filter assigned to.
2699 * - On success, zero.
2700 * - On failure, a negative value.
2703 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2704 struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2706 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707 uint32_t imir, ttqf, imir_ext;
2709 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2711 if (index >= E1000_MAX_TTQF_FILTERS)
2712 return -EINVAL; /* filter index is out of range. */
2714 ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2715 if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2716 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2717 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2718 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2719 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2720 E1000_TTQF_QUEUE_SHIFT;
2721 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2722 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2723 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2724 E1000_IMIR_PRIORITY_SHIFT;
2726 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2727 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2728 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2729 filter->tcp_flags |= TCP_UGR_FLAG;
2730 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2731 filter->tcp_flags |= TCP_ACK_FLAG;
2732 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2733 filter->tcp_flags |= TCP_PSH_FLAG;
2734 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2735 filter->tcp_flags |= TCP_RST_FLAG;
2736 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2737 filter->tcp_flags |= TCP_SYN_FLAG;
2738 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2739 filter->tcp_flags |= TCP_FIN_FLAG;
2741 filter->tcp_flags = 0;
2751 * dev: Pointer to struct rte_eth_dev.
2752 * index: the index the filter allocates.
2753 * filter: ponter to the filter that will be added.
2754 * rx_queue: the queue id the filter assigned to.
2757 * - On success, zero.
2758 * - On failure, a negative value.
2761 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2762 struct rte_flex_filter *filter, uint16_t rx_queue)
2764 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765 uint32_t wufc, en_bits = 0;
2766 uint32_t queueing = 0;
2767 uint32_t reg_off = 0;
2770 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2772 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2773 return -EINVAL; /* filter index is out of range. */
2775 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2776 filter->len % 8 != 0 ||
2777 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2780 wufc = E1000_READ_REG(hw, E1000_WUFC);
2781 en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2782 if ((wufc & en_bits) == en_bits)
2783 return -EINVAL; /* the filter is in use. */
2785 E1000_WRITE_REG(hw, E1000_WUFC,
2786 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2789 if (index < E1000_MAX_FHFT)
2790 reg_off = E1000_FHFT(index);
2792 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2794 for (i = 0; i < 16; i++) {
2795 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2796 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2797 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2798 (uint32_t)filter->mask[i]);
2801 queueing |= filter->len |
2802 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2803 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2804 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2809 * remove a flex filter
2812 * dev: Pointer to struct rte_eth_dev.
2813 * index: the index the filter allocates.
2816 * - On success, zero.
2817 * - On failure, a negative value.
2820 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2823 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824 uint32_t wufc, reg_off = 0;
2827 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2829 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2830 return -EINVAL; /* filter index is out of range. */
2832 wufc = E1000_READ_REG(hw, E1000_WUFC);
2833 E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2835 if (index < E1000_MAX_FHFT)
2836 reg_off = E1000_FHFT(index);
2838 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2840 for (i = 0; i < 64; i++)
2841 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2849 * dev: Pointer to struct rte_eth_dev.
2850 * index: the index the filter allocates.
2851 * filter: ponter to the filter that returns.
2852 * *rx_queue: the pointer of the queue id the filter assigned to.
2855 * - On success, zero.
2856 * - On failure, a negative value.
2859 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2860 struct rte_flex_filter *filter, uint16_t *rx_queue)
2862 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863 uint32_t wufc, queueing, wufc_en = 0;
2866 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2868 if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2869 return -EINVAL; /* filter index is out of range. */
2871 wufc = E1000_READ_REG(hw, E1000_WUFC);
2872 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2874 if ((wufc & wufc_en) == wufc_en) {
2875 uint32_t reg_off = 0;
2877 if (index < E1000_MAX_FHFT)
2878 reg_off = E1000_FHFT(index);
2880 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2882 for (i = 0; i < 16; i++, j = i * 2) {
2884 E1000_READ_REG(hw, reg_off + i*4*4);
2885 filter->dwords[j+1] =
2886 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2888 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2890 queueing = E1000_READ_REG(hw,
2891 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2892 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2893 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2894 E1000_FHFT_QUEUEING_PRIO_SHIFT;
2895 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2896 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2903 * add a 5tuple filter
2906 * dev: Pointer to struct rte_eth_dev.
2907 * index: the index the filter allocates.
2908 * filter: ponter to the filter that will be added.
2909 * rx_queue: the queue id the filter assigned to.
2912 * - On success, zero.
2913 * - On failure, a negative value.
2916 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2917 struct rte_5tuple_filter *filter, uint16_t rx_queue)
2919 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920 uint32_t ftqf, spqf = 0;
2922 uint32_t imir_ext = 0;
2924 if (hw->mac.type != e1000_82576)
2927 if (index >= E1000_MAX_FTQF_FILTERS ||
2928 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2929 return -EINVAL; /* filter index is out of range. */
2931 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2932 if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2933 return -EINVAL; /* filter index is in use. */
2936 ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2937 if (filter->src_ip_mask == 1) /* 1b means not compare. */
2938 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2939 if (filter->dst_ip_mask == 1)
2940 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2941 if (filter->src_port_mask == 1)
2942 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2943 if (filter->protocol_mask == 1)
2944 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2945 ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2946 ftqf |= E1000_FTQF_VF_MASK_EN;
2947 ftqf |= E1000_FTQF_QUEUE_ENABLE;
2948 E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2949 E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2950 E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2952 spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2953 E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2955 imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2956 if (filter->dst_port_mask == 1) /* 1b means not compare. */
2957 imir |= E1000_IMIR_PORT_BP;
2959 imir &= ~E1000_IMIR_PORT_BP;
2960 imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2962 imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2963 /* tcp flags bits setting. */
2964 if (filter->tcp_flags & TCP_FLAG_ALL) {
2965 if (filter->tcp_flags & TCP_UGR_FLAG)
2966 imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2967 if (filter->tcp_flags & TCP_ACK_FLAG)
2968 imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2969 if (filter->tcp_flags & TCP_PSH_FLAG)
2970 imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2971 if (filter->tcp_flags & TCP_RST_FLAG)
2972 imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2973 if (filter->tcp_flags & TCP_SYN_FLAG)
2974 imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2975 if (filter->tcp_flags & TCP_FIN_FLAG)
2976 imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2978 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2979 E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2980 E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2985 * remove a 5tuple filter
2988 * dev: Pointer to struct rte_eth_dev.
2989 * index: the index the filter allocates
2992 * - On success, zero.
2993 * - On failure, a negative value.
2996 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2999 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001 if (hw->mac.type != e1000_82576)
3004 if (index >= E1000_MAX_FTQF_FILTERS)
3005 return -EINVAL; /* filter index is out of range. */
3007 E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
3008 E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
3009 E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
3010 E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
3011 E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
3012 E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
3017 * get a 5tuple filter
3020 * dev: Pointer to struct rte_eth_dev.
3021 * index: the index the filter allocates
3022 * filter: ponter to the filter that returns
3023 * *rx_queue: pointer of the queue id the filter assigned to
3026 * - On success, zero.
3027 * - On failure, a negative value.
3030 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3031 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3033 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034 uint32_t spqf, ftqf, imir, imir_ext;
3036 if (hw->mac.type != e1000_82576)
3039 if (index >= E1000_MAX_FTQF_FILTERS)
3040 return -EINVAL; /* filter index is out of range. */
3042 ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
3043 if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
3044 filter->src_ip_mask =
3045 (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3046 filter->dst_ip_mask =
3047 (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3048 filter->src_port_mask =
3049 (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3050 filter->protocol_mask =
3051 (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3053 (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
3054 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
3055 E1000_FTQF_QUEUE_SHIFT);
3057 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
3058 filter->src_port = spqf & E1000_SPQF_SRCPORT;
3060 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
3061 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
3063 imir = E1000_READ_REG(hw, E1000_IMIR(index));
3064 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
3065 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
3066 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
3067 E1000_IMIR_PRIORITY_SHIFT;
3069 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
3070 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
3071 if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
3072 filter->tcp_flags |= TCP_UGR_FLAG;
3073 if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
3074 filter->tcp_flags |= TCP_ACK_FLAG;
3075 if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
3076 filter->tcp_flags |= TCP_PSH_FLAG;
3077 if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
3078 filter->tcp_flags |= TCP_RST_FLAG;
3079 if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3080 filter->tcp_flags |= TCP_SYN_FLAG;
3081 if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3082 filter->tcp_flags |= TCP_FIN_FLAG;
3084 filter->tcp_flags = 0;
3091 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3094 struct e1000_hw *hw;
3095 struct rte_eth_dev_info dev_info;
3096 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3099 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3101 #ifdef RTE_LIBRTE_82571_SUPPORT
3102 /* XXX: not bigger than max_rx_pktlen */
3103 if (hw->mac.type == e1000_82571)
3106 eth_igb_infos_get(dev, &dev_info);
3108 /* check that mtu is within the allowed range */
3109 if ((mtu < ETHER_MIN_MTU) ||
3110 (frame_size > dev_info.max_rx_pktlen))
3113 /* refuse mtu that requires the support of scattered packets when this
3114 * feature has not been enabled before. */
3115 if (!dev->data->scattered_rx &&
3116 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3119 rctl = E1000_READ_REG(hw, E1000_RCTL);
3121 /* switch to jumbo mode if needed */
3122 if (frame_size > ETHER_MAX_LEN) {
3123 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3124 rctl |= E1000_RCTL_LPE;
3126 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3127 rctl &= ~E1000_RCTL_LPE;
3129 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3131 /* update max frame size */
3132 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3134 E1000_WRITE_REG(hw, E1000_RLPML,
3135 dev->data->dev_conf.rxmode.max_rx_pkt_len);
3140 static struct rte_driver pmd_igb_drv = {
3142 .init = rte_igb_pmd_init,
3145 static struct rte_driver pmd_igbvf_drv = {
3147 .init = rte_igbvf_pmd_init,
3150 PMD_REGISTER_DRIVER(pmd_igb_drv);
3151 PMD_REGISTER_DRIVER(pmd_igbvf_drv);