lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q,
  61                 uint16_t nb_tx_q);
  62 static int  eth_igb_start(struct rte_eth_dev *dev);
  63 static void eth_igb_stop(struct rte_eth_dev *dev);
  64 static void eth_igb_close(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  66 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  68 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  69 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  70                                 int wait_to_complete);
  71 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  72                                 struct rte_eth_stats *rte_stats);
  73 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  74 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_dev_info *dev_info);
  76 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  77                                 struct rte_eth_fc_conf *fc_conf);
  78 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  80 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  81 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  82                                                         void *param);
  83 static int  igb_hardware_init(struct e1000_hw *hw);
  84 static void igb_hw_control_acquire(struct e1000_hw *hw);
  85 static void igb_hw_control_release(struct e1000_hw *hw);
  86 static void igb_init_manageability(struct e1000_hw *hw);
  87 static void igb_release_manageability(struct e1000_hw *hw);
  88
  89 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  90                 uint16_t vlan_id, int on);
  91 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  92 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  93
  94 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  99 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 100
 101 static int eth_igb_led_on(struct rte_eth_dev *dev);
 102 static int eth_igb_led_off(struct rte_eth_dev *dev);
 103
 104 static void igb_intr_disable(struct e1000_hw *hw);
 105 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 106 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 107                 struct ether_addr *mac_addr,
 108                 uint32_t index, uint32_t pool);
 109 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 110
 111 static void igbvf_intr_disable(struct e1000_hw *hw);
 112 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 113 static int igbvf_dev_start(struct rte_eth_dev *dev);
 114 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 115 static void igbvf_dev_close(struct rte_eth_dev *dev);
 116 static int eth_igbvf_link_update(struct e1000_hw *hw);
 117 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 118 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 119 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 120                 uint16_t vlan_id, int on);
 121 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 122 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 123
 124 /*
 125  * Define VF Stats MACRO for Non "cleared on read" register
 126  */
 127 #define UPDATE_VF_STAT(reg, last, cur)            \
 128 {                                                 \
 129         u32 latest = E1000_READ_REG(hw, reg);     \
 130         cur += latest - last;                     \
 131         last = latest;                            \
 132 }
 133
 134
 135 #define IGB_FC_PAUSE_TIME 0x0680
 136 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 137 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 138
 139 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 140
 141 /*
 142  * The set of PCI devices this driver supports
 143  */
 144 static struct rte_pci_id pci_id_igb_map[] = {
 145
 146 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 147 #include "rte_pci_dev_ids.h"
 148
 149 {.device_id = 0},
 150 };
 151
 152 /*
 153  * The set of PCI devices this driver supports (for 82576&I350 VF)
 154  */
 155 static struct rte_pci_id pci_id_igbvf_map[] = {
 156
 157 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 158 #include "rte_pci_dev_ids.h"
 159
 160 {.device_id = 0},
 161 };
 162
 163 static struct eth_dev_ops eth_igb_ops = {
 164         .dev_configure        = eth_igb_configure,
 165         .dev_start            = eth_igb_start,
 166         .dev_stop             = eth_igb_stop,
 167         .dev_close            = eth_igb_close,
 168         .promiscuous_enable   = eth_igb_promiscuous_enable,
 169         .promiscuous_disable  = eth_igb_promiscuous_disable,
 170         .allmulticast_enable  = eth_igb_allmulticast_enable,
 171         .allmulticast_disable = eth_igb_allmulticast_disable,
 172         .link_update          = eth_igb_link_update,
 173         .stats_get            = eth_igb_stats_get,
 174         .stats_reset          = eth_igb_stats_reset,
 175         .dev_infos_get        = eth_igb_infos_get,
 176         .vlan_filter_set      = eth_igb_vlan_filter_set,
 177         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 178         .vlan_offload_set     = eth_igb_vlan_offload_set,
 179         .rx_queue_setup       = eth_igb_rx_queue_setup,
 180         .tx_queue_setup       = eth_igb_tx_queue_setup,
 181         .dev_led_on           = eth_igb_led_on,
 182         .dev_led_off          = eth_igb_led_off,
 183         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 184         .mac_addr_add         = eth_igb_rar_set,
 185         .mac_addr_remove      = eth_igb_rar_clear,
 186 };
 187
 188 /*
 189  * dev_ops for virtual function, bare necessities for basic vf
 190  * operation have been implemented
 191  */
 192 static struct eth_dev_ops igbvf_eth_dev_ops = {
 193         .dev_configure        = igbvf_dev_configure,
 194         .dev_start            = igbvf_dev_start,
 195         .dev_stop             = igbvf_dev_stop,
 196         .dev_close            = igbvf_dev_close,
 197         .link_update          = eth_igb_link_update,
 198         .stats_get            = eth_igbvf_stats_get,
 199         .stats_reset          = eth_igbvf_stats_reset,
 200         .vlan_filter_set      = igbvf_vlan_filter_set,
 201         .dev_infos_get        = eth_igb_infos_get,
 202         .rx_queue_setup       = eth_igb_rx_queue_setup,
 203         .rx_queue_release     = eth_igb_rx_queue_release,
 204         .tx_queue_setup       = eth_igb_tx_queue_setup,
 205         .tx_queue_release     = eth_igb_tx_queue_release,
 206 };
 207
 208 /**
 209  * Atomically reads the link status information from global
 210  * structure rte_eth_dev.
 211  *
 212  * @param dev
 213  *   - Pointer to the structure rte_eth_dev to read from.
 214  *   - Pointer to the buffer to be saved with the link status.
 215  *
 216  * @return
 217  *   - On success, zero.
 218  *   - On failure, negative value.
 219  */
 220 static inline int
 221 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 222                                 struct rte_eth_link *link)
 223 {
 224         struct rte_eth_link *dst = link;
 225         struct rte_eth_link *src = &(dev->data->dev_link);
 226
 227         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 228                                         *(uint64_t *)src) == 0)
 229                 return -1;
 230
 231         return 0;
 232 }
 233
 234 /**
 235  * Atomically writes the link status information into global
 236  * structure rte_eth_dev.
 237  *
 238  * @param dev
 239  *   - Pointer to the structure rte_eth_dev to read from.
 240  *   - Pointer to the buffer to be saved with the link status.
 241  *
 242  * @return
 243  *   - On success, zero.
 244  *   - On failure, negative value.
 245  */
 246 static inline int
 247 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 248                                 struct rte_eth_link *link)
 249 {
 250         struct rte_eth_link *dst = &(dev->data->dev_link);
 251         struct rte_eth_link *src = link;
 252
 253         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 254                                         *(uint64_t *)src) == 0)
 255                 return -1;
 256
 257         return 0;
 258 }
 259
 260 static void
 261 igb_identify_hardware(struct rte_eth_dev *dev)
 262 {
 263         struct e1000_hw *hw =
 264                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 265
 266         hw->vendor_id = dev->pci_dev->id.vendor_id;
 267         hw->device_id = dev->pci_dev->id.device_id;
 268         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 269         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 270
 271         e1000_set_mac_type(hw);
 272
 273         /* need to check if it is a vf device below */
 274 }
 275
 276 static int
 277 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 278                    struct rte_eth_dev *eth_dev)
 279 {
 280         int error = 0;
 281         struct rte_pci_device *pci_dev;
 282         struct e1000_hw *hw =
 283                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 284         struct e1000_vfta * shadow_vfta =
 285                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 286
 287         pci_dev = eth_dev->pci_dev;
 288         eth_dev->dev_ops = &eth_igb_ops;
 289         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 290         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 291
 292         /* for secondary processes, we don't initialise any further as primary
 293          * has already done this work. Only check we don't need a different
 294          * RX function */
 295         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 296                 if (eth_dev->data->scattered_rx)
 297                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 298                 return 0;
 299         }
 300
 301         hw->hw_addr= (void *)pci_dev->mem_resource.addr;
 302
 303         igb_identify_hardware(eth_dev);
 304
 305         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 306                 error = -EIO;
 307                 goto err_late;
 308         }
 309
 310         e1000_get_bus_info(hw);
 311
 312         hw->mac.autoneg = 1;
 313         hw->phy.autoneg_wait_to_complete = 0;
 314         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 315
 316         /* Copper options */
 317         if (hw->phy.media_type == e1000_media_type_copper) {
 318                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 319                 hw->phy.disable_polarity_correction = 0;
 320                 hw->phy.ms_type = e1000_ms_hw_default;
 321         }
 322
 323         /*
 324          * Start from a known state, this is important in reading the nvm
 325          * and mac from that.
 326          */
 327         e1000_reset_hw(hw);
 328
 329         /* Make sure we have a good EEPROM before we read from it */
 330         if (e1000_validate_nvm_checksum(hw) < 0) {
 331                 /*
 332                  * Some PCI-E parts fail the first check due to
 333                  * the link being in sleep state, call it again,
 334                  * if it fails a second time its a real issue.
 335                  */
 336                 if (e1000_validate_nvm_checksum(hw) < 0) {
 337                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 338                         error = -EIO;
 339                         goto err_late;
 340                 }
 341         }
 342
 343         /* Read the permanent MAC address out of the EEPROM */
 344         if (e1000_read_mac_addr(hw) != 0) {
 345                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 346                 error = -EIO;
 347                 goto err_late;
 348         }
 349
 350         /* Allocate memory for storing MAC addresses */
 351         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 352                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 353         if (eth_dev->data->mac_addrs == NULL) {
 354                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 355                                                 "store MAC addresses",
 356                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 357                 error = -ENOMEM;
 358                 goto err_late;
 359         }
 360
 361         /* Copy the permanent MAC address */
 362         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 363
 364         /* initialize the vfta */
 365         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 366
 367         /* Now initialize the hardware */
 368         if (igb_hardware_init(hw) != 0) {
 369                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 370                 rte_free(eth_dev->data->mac_addrs);
 371                 eth_dev->data->mac_addrs = NULL;
 372                 error = -ENODEV;
 373                 goto err_late;
 374         }
 375         hw->mac.get_link_status = 1;
 376
 377         /* Indicate SOL/IDER usage */
 378         if (e1000_check_reset_block(hw) < 0) {
 379                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 380                                         "SOL/IDER session");
 381         }
 382
 383         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 384                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 385                      pci_dev->id.device_id);
 386
 387         rte_intr_callback_register(&(pci_dev->intr_handle),
 388                 eth_igb_interrupt_handler, (void *)eth_dev);
 389
 390         return 0;
 391
 392 err_late:
 393         igb_hw_control_release(hw);
 394
 395         return (error);
 396 }
 397
 398 /*
 399  * Virtual Function device init
 400  */
 401 static int
 402 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 403                 struct rte_eth_dev *eth_dev)
 404 {
 405         struct rte_pci_device *pci_dev;
 406         struct e1000_hw *hw =
 407                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 408         int diag;
 409
 410         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 411
 412         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 413         pci_dev = eth_dev->pci_dev;
 414
 415         hw->device_id = pci_dev->id.device_id;
 416         hw->vendor_id = pci_dev->id.vendor_id;
 417         hw->hw_addr = (void *)pci_dev->mem_resource.addr;
 418
 419         /* Initialize the shared code */
 420         diag = e1000_setup_init_funcs(hw, TRUE);
 421         if (diag != 0) {
 422                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 423                         diag);
 424                 return -EIO;
 425         }
 426
 427         /* init_mailbox_params */
 428         hw->mbx.ops.init_params(hw);
 429
 430         /* Disable the interrupts for VF */
 431         igbvf_intr_disable(hw);
 432
 433         diag = hw->mac.ops.reset_hw(hw);
 434
 435         /* Allocate memory for storing MAC addresses */
 436         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 437                 hw->mac.rar_entry_count, 0);
 438         if (eth_dev->data->mac_addrs == NULL) {
 439                 PMD_INIT_LOG(ERR,
 440                         "Failed to allocate %d bytes needed to store MAC "
 441                         "addresses",
 442                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 443                 return -ENOMEM;
 444         }
 445         /* Copy the permanent MAC address */
 446         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 447                         &eth_dev->data->mac_addrs[0]);
 448
 449         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 450                         "mac.type=%s\n",
 451                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 452                         pci_dev->id.device_id,
 453                         "igb_mac_82576_vf");
 454
 455         return 0;
 456 }
 457
 458 static struct eth_driver rte_igb_pmd = {
 459         {
 460                 .name = "rte_igb_pmd",
 461                 .id_table = pci_id_igb_map,
 462                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 463         },
 464         .eth_dev_init = eth_igb_dev_init,
 465         .dev_private_size = sizeof(struct e1000_adapter),
 466 };
 467
 468 /*
 469  * virtual function driver struct
 470  */
 471 static struct eth_driver rte_igbvf_pmd = {
 472         {
 473                 .name = "rte_igbvf_pmd",
 474                 .id_table = pci_id_igbvf_map,
 475                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 476         },
 477         .eth_dev_init = eth_igbvf_dev_init,
 478         .dev_private_size = sizeof(struct e1000_adapter),
 479 };
 480
 481 int
 482 rte_igb_pmd_init(void)
 483 {
 484         rte_eth_driver_register(&rte_igb_pmd);
 485         return 0;
 486 }
 487
 488 /*
 489  * VF Driver initialization routine.
 490  * Invoked one at EAL init time.
 491  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 492  */
 493 int
 494 rte_igbvf_pmd_init(void)
 495 {
 496         DEBUGFUNC("rte_igbvf_pmd_init");
 497
 498         rte_eth_driver_register(&rte_igbvf_pmd);
 499         return (0);
 500 }
 501
 502 static int
 503 eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q)
 504 {
 505         struct e1000_interrupt *intr =
 506                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 507         int diag;
 508
 509         PMD_INIT_LOG(DEBUG, ">>");
 510
 511         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 512
 513         /* Allocate the array of pointers to RX structures */
 514         diag = igb_dev_rx_queue_alloc(dev, nb_rx_q);
 515         if (diag != 0) {
 516                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 517                                         " pointers to RX queues failed",
 518                                         dev->data->port_id, nb_rx_q);
 519                 return diag;
 520         }
 521
 522         /* Allocate the array of pointers to TX structures */
 523         diag = igb_dev_tx_queue_alloc(dev, nb_tx_q);
 524         if (diag != 0) {
 525                 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
 526                                         " pointers to TX queues failed",
 527                                         dev->data->port_id, nb_tx_q);
 528
 529                 return diag;
 530         }
 531
 532         PMD_INIT_LOG(DEBUG, "<<");
 533
 534         return (0);
 535 }
 536
 537 static int
 538 eth_igb_start(struct rte_eth_dev *dev)
 539 {
 540         struct e1000_hw *hw =
 541                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 542         int ret, i;
 543
 544         PMD_INIT_LOG(DEBUG, ">>");
 545
 546         igb_intr_disable(hw);
 547
 548         /* Power up the phy. Needed to make the link go Up */
 549         e1000_power_up_phy(hw);
 550
 551         /*
 552          * Packet Buffer Allocation (PBA)
 553          * Writing PBA sets the receive portion of the buffer
 554          * the remainder is used for the transmit buffer.
 555          */
 556         if (hw->mac.type == e1000_82575) {
 557                 uint32_t pba;
 558
 559                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 560                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 561         }
 562
 563         /* Put the address into the Receive Address Array */
 564         e1000_rar_set(hw, hw->mac.addr, 0);
 565
 566         /* Initialize the hardware */
 567         if (igb_hardware_init(hw)) {
 568                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 569                 return (-1);
 570         }
 571
 572         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 573
 574         /* Configure for OS presence */
 575         igb_init_manageability(hw);
 576
 577         eth_igb_tx_init(dev);
 578
 579         /* This can fail when allocating mbufs for descriptor rings */
 580         ret = eth_igb_rx_init(dev);
 581         if (ret) {
 582                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 583                 return ret;
 584         }
 585
 586         e1000_clear_hw_cntrs_base_generic(hw);
 587
 588         /*
 589          * VLAN Offload Settings
 590          */
 591         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 592                         ETH_VLAN_EXTEND_MASK;
 593         eth_igb_vlan_offload_set(dev, mask);
 594
 595         /*
 596          * Configure the Interrupt Moderation register (EITR) with the maximum
 597          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 598          * spurious [DMA] memory updates of RX and TX ring descriptors.
 599          *
 600          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 601          * spurious memory updates per second should be expected.
 602          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 603          *
 604          * Because interrupts are not used at all, the MSI-X is not activated
 605          * and interrupt moderation is controlled by EITR[0].
 606          *
 607          * Note that having [almost] disabled memory updates of RX and TX ring
 608          * descriptors through the Interrupt Moderation mechanism, memory
 609          * updates of ring descriptors are now moderated by the configurable
 610          * value of Write-Back Threshold registers.
 611          */
 612         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 613                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 614                 uint32_t ivar;
 615
 616                 /* Enable all RX & TX queues in the IVAR registers */
 617                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 618                 for (i = 0; i < 8; i++)
 619                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 620
 621                 /* Configure EITR with the maximum possible value (0xFFFF) */
 622                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 623         }
 624
 625         /* Setup link speed and duplex */
 626         switch (dev->data->dev_conf.link_speed) {
 627         case ETH_LINK_SPEED_AUTONEG:
 628                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 629                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 630                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 631                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 632                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 633                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 634                 else
 635                         goto error_invalid_config;
 636                 break;
 637         case ETH_LINK_SPEED_10:
 638                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 639                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 640                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 641                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 642                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 643                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 644                 else
 645                         goto error_invalid_config;
 646                 break;
 647         case ETH_LINK_SPEED_100:
 648                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 649                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 650                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 651                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 652                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 653                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 654                 else
 655                         goto error_invalid_config;
 656                 break;
 657         case ETH_LINK_SPEED_1000:
 658                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 659                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 660                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 661                 else
 662                         goto error_invalid_config;
 663                 break;
 664         case ETH_LINK_SPEED_10000:
 665         default:
 666                 goto error_invalid_config;
 667         }
 668         e1000_setup_link(hw);
 669
 670         /* check if lsc interrupt feature is enabled */
 671         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 672                 ret = eth_igb_interrupt_setup(dev);
 673                 if (ret) {
 674                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 675                         igb_dev_clear_queues(dev);
 676                         return ret;
 677                 }
 678         }
 679
 680         PMD_INIT_LOG(DEBUG, "<<");
 681
 682         return (0);
 683
 684 error_invalid_config:
 685         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 686                         dev->data->dev_conf.link_speed,
 687                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 688         return -1;
 689 }
 690
 691 /*********************************************************************
 692  *
 693  *  This routine disables all traffic on the adapter by issuing a
 694  *  global reset on the MAC.
 695  *
 696  **********************************************************************/
 697 static void
 698 eth_igb_stop(struct rte_eth_dev *dev)
 699 {
 700         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 701         struct rte_eth_link link;
 702
 703         igb_intr_disable(hw);
 704         e1000_reset_hw(hw);
 705         E1000_WRITE_REG(hw, E1000_WUC, 0);
 706
 707         /* Power down the phy. Needed to make the link go Down */
 708         e1000_power_down_phy(hw);
 709
 710         igb_dev_clear_queues(dev);
 711
 712         /* clear the recorded link status */
 713         memset(&link, 0, sizeof(link));
 714         rte_igb_dev_atomic_write_link_status(dev, &link);
 715 }
 716
 717 static void
 718 eth_igb_close(struct rte_eth_dev *dev)
 719 {
 720         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 721         struct rte_eth_link link;
 722
 723         eth_igb_stop(dev);
 724         e1000_phy_hw_reset(hw);
 725         igb_release_manageability(hw);
 726         igb_hw_control_release(hw);
 727
 728         igb_dev_clear_queues(dev);
 729
 730         memset(&link, 0, sizeof(link));
 731         rte_igb_dev_atomic_write_link_status(dev, &link);
 732 }
 733
 734 static int
 735 igb_get_rx_buffer_size(struct e1000_hw *hw)
 736 {
 737         uint32_t rx_buf_size;
 738         if (hw->mac.type == e1000_82576) {
 739                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 740         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 741                 /* PBS needs to be translated according to a lookup table */
 742                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 743                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 744                 rx_buf_size = (rx_buf_size << 10);
 745         } else if (hw->mac.type == e1000_i210) {
 746                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 747         } else {
 748                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 749         }
 750
 751         return rx_buf_size;
 752 }
 753
 754 /*********************************************************************
 755  *
 756  *  Initialize the hardware
 757  *
 758  **********************************************************************/
 759 static int
 760 igb_hardware_init(struct e1000_hw *hw)
 761 {
 762         uint32_t rx_buf_size;
 763         int diag;
 764
 765         /* Let the firmware know the OS is in control */
 766         igb_hw_control_acquire(hw);
 767
 768         /*
 769          * These parameters control the automatic generation (Tx) and
 770          * response (Rx) to Ethernet PAUSE frames.
 771          * - High water mark should allow for at least two standard size (1518)
 772          *   frames to be received after sending an XOFF.
 773          * - Low water mark works best when it is very near the high water mark.
 774          *   This allows the receiver to restart by sending XON when it has
 775          *   drained a bit. Here we use an arbitary value of 1500 which will
 776          *   restart after one full frame is pulled from the buffer. There
 777          *   could be several smaller frames in the buffer and if so they will
 778          *   not trigger the XON until their total number reduces the buffer
 779          *   by 1500.
 780          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 781          */
 782         rx_buf_size = igb_get_rx_buffer_size(hw);
 783
 784         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 785         hw->fc.low_water = hw->fc.high_water - 1500;
 786         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 787         hw->fc.send_xon = 1;
 788
 789         /* Set Flow control, use the tunable location if sane */
 790         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 791                 hw->fc.requested_mode = igb_fc_setting;
 792         else
 793                 hw->fc.requested_mode = e1000_fc_none;
 794
 795         /* Issue a global reset */
 796         e1000_reset_hw(hw);
 797         E1000_WRITE_REG(hw, E1000_WUC, 0);
 798
 799         diag = e1000_init_hw(hw);
 800         if (diag < 0)
 801                 return (diag);
 802
 803         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 804         e1000_get_phy_info(hw);
 805         e1000_check_for_link(hw);
 806
 807         return (0);
 808 }
 809
 810 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 811 static void
 812 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 813 {
 814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 815         struct e1000_hw_stats *stats =
 816                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 817         int pause_frames;
 818
 819         if(hw->phy.media_type == e1000_media_type_copper ||
 820             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 821                 stats->symerrs +=
 822                     E1000_READ_REG(hw,E1000_SYMERRS);
 823                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 824         }
 825
 826         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 827         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 828         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 829         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 830
 831         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 832         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 833         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 834         stats->dc += E1000_READ_REG(hw, E1000_DC);
 835         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 836         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 837         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 838         /*
 839         ** For watchdog management we need to know if we have been
 840         ** paused during the last interval, so capture that here.
 841         */
 842         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 843         stats->xoffrxc += pause_frames;
 844         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 845         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 846         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 847         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 848         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 849         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 850         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 851         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 852         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 853         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 854         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 855         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 856
 857         /* For the 64-bit byte counters the low dword must be read first. */
 858         /* Both registers clear on the read of the high dword */
 859
 860         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 861         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 862         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 863         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 864
 865         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 866         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 867         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 868         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 869         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 870
 871         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 872         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 873
 874         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 875         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 876         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 877         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 878         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 879         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 880         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 881         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 882         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 883         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 884
 885         /* Interrupt Counts */
 886
 887         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 888         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 889         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 890         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 891         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 892         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 893         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 894         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 895         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 896
 897         /* Host to Card Statistics */
 898
 899         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 900         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 901         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 902         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 903         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 904         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 905         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 906         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 907         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 908         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 909         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 910         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 911         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 912         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 913
 914         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 915         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 916         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 917         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 918         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 919         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 920
 921         if (rte_stats == NULL)
 922                 return;
 923
 924         /* Rx Errors */
 925         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 926             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 927
 928         /* Tx Errors */
 929         rte_stats->oerrors = stats->ecol + stats->latecol;
 930
 931         rte_stats->ipackets = stats->gprc;
 932         rte_stats->opackets = stats->gptc;
 933         rte_stats->ibytes   = stats->gorc;
 934         rte_stats->obytes   = stats->gotc;
 935 }
 936
 937 static void
 938 eth_igb_stats_reset(struct rte_eth_dev *dev)
 939 {
 940         struct e1000_hw_stats *hw_stats =
 941                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 942
 943         /* HW registers are cleared on read */
 944         eth_igb_stats_get(dev, NULL);
 945
 946         /* Reset software totals */
 947         memset(hw_stats, 0, sizeof(*hw_stats));
 948 }
 949
 950 static void
 951 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 952 {
 953         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 954         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 955                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 956
 957         /* Good Rx packets, include VF loopback */
 958         UPDATE_VF_STAT(E1000_VFGPRC,
 959             hw_stats->last_gprc, hw_stats->gprc);
 960
 961         /* Good Rx octets, include VF loopback */
 962         UPDATE_VF_STAT(E1000_VFGORC,
 963             hw_stats->last_gorc, hw_stats->gorc);
 964
 965         /* Good Tx packets, include VF loopback */
 966         UPDATE_VF_STAT(E1000_VFGPTC,
 967             hw_stats->last_gptc, hw_stats->gptc);
 968
 969         /* Good Tx octets, include VF loopback */
 970         UPDATE_VF_STAT(E1000_VFGOTC,
 971             hw_stats->last_gotc, hw_stats->gotc);
 972
 973         /* Rx Multicst packets */
 974         UPDATE_VF_STAT(E1000_VFMPRC,
 975             hw_stats->last_mprc, hw_stats->mprc);
 976
 977         /* Good Rx loopback packets */
 978         UPDATE_VF_STAT(E1000_VFGPRLBC,
 979             hw_stats->last_gprlbc, hw_stats->gprlbc);
 980
 981         /* Good Rx loopback octets */
 982         UPDATE_VF_STAT(E1000_VFGORLBC,
 983             hw_stats->last_gorlbc, hw_stats->gorlbc);
 984
 985         /* Good Tx loopback packets */
 986         UPDATE_VF_STAT(E1000_VFGPTLBC,
 987             hw_stats->last_gptlbc, hw_stats->gptlbc);
 988
 989         /* Good Tx loopback octets */
 990         UPDATE_VF_STAT(E1000_VFGOTLBC,
 991             hw_stats->last_gotlbc, hw_stats->gotlbc);
 992
 993         if (rte_stats == NULL)
 994                 return;
 995
 996         memset(rte_stats, 0, sizeof(*rte_stats));
 997         rte_stats->ipackets = hw_stats->gprc;
 998         rte_stats->ibytes = hw_stats->gorc;
 999         rte_stats->opackets = hw_stats->gptc;
1000         rte_stats->obytes = hw_stats->gotc;
1001         rte_stats->imcasts = hw_stats->mprc;
1002         rte_stats->ilbpackets = hw_stats->gprlbc;
1003         rte_stats->ilbbytes = hw_stats->gorlbc;
1004         rte_stats->olbpackets = hw_stats->gptlbc;
1005         rte_stats->olbbytes = hw_stats->gotlbc;
1006
1007 }
1008
1009 static void
1010 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1011 {
1012         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1013                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1014
1015         /* Sync HW register to the last stats */
1016         eth_igbvf_stats_get(dev, NULL);
1017
1018         /* reset HW current stats*/
1019         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1020                offsetof(struct e1000_vf_stats, gprc));
1021
1022 }
1023
1024 static void
1025 eth_igb_infos_get(struct rte_eth_dev *dev,
1026                     struct rte_eth_dev_info *dev_info)
1027 {
1028         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029
1030         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1031         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1032         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1033
1034         switch (hw->mac.type) {
1035         case e1000_82575:
1036                 dev_info->max_rx_queues = 4;
1037                 dev_info->max_tx_queues = 4;
1038                 break;
1039
1040         case e1000_82576:
1041                 dev_info->max_rx_queues = 16;
1042                 dev_info->max_tx_queues = 16;
1043                 break;
1044
1045         case e1000_82580:
1046                 dev_info->max_rx_queues = 8;
1047                 dev_info->max_tx_queues = 8;
1048                 break;
1049
1050         case e1000_i350:
1051                 dev_info->max_rx_queues = 8;
1052                 dev_info->max_tx_queues = 8;
1053                 break;
1054
1055         case e1000_i210:
1056                 dev_info->max_rx_queues = 4;
1057                 dev_info->max_tx_queues = 4;
1058                 break;
1059
1060         case e1000_vfadapt:
1061                 dev_info->max_rx_queues = 2;
1062                 dev_info->max_tx_queues = 2;
1063                 break;
1064
1065         case e1000_vfadapt_i350:
1066                 dev_info->max_rx_queues = 1;
1067                 dev_info->max_tx_queues = 1;
1068                 break;
1069
1070         default:
1071                 /* Should not happen */
1072                 dev_info->max_rx_queues = 0;
1073                 dev_info->max_tx_queues = 0;
1074         }
1075 }
1076
1077 /* return 0 means link status changed, -1 means not changed */
1078 static int
1079 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1080 {
1081         struct e1000_hw *hw =
1082                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1083         struct rte_eth_link link, old;
1084         int link_check, count;
1085
1086         link_check = 0;
1087         hw->mac.get_link_status = 1;
1088
1089         /* possible wait-to-complete in up to 9 seconds */
1090         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1091                 /* Read the real link status */
1092                 switch (hw->phy.media_type) {
1093                 case e1000_media_type_copper:
1094                         /* Do the work to read phy */
1095                         e1000_check_for_link(hw);
1096                         link_check = !hw->mac.get_link_status;
1097                         break;
1098
1099                 case e1000_media_type_fiber:
1100                         e1000_check_for_link(hw);
1101                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1102                                       E1000_STATUS_LU);
1103                         break;
1104
1105                 case e1000_media_type_internal_serdes:
1106                         e1000_check_for_link(hw);
1107                         link_check = hw->mac.serdes_has_link;
1108                         break;
1109
1110                 /* VF device is type_unknown */
1111                 case e1000_media_type_unknown:
1112                         eth_igbvf_link_update(hw);
1113                         link_check = !hw->mac.get_link_status;
1114                         break;
1115
1116                 default:
1117                         break;
1118                 }
1119                 if (link_check || wait_to_complete == 0)
1120                         break;
1121                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1122         }
1123         memset(&link, 0, sizeof(link));
1124         rte_igb_dev_atomic_read_link_status(dev, &link);
1125         old = link;
1126
1127         /* Now we check if a transition has happened */
1128         if (link_check) {
1129                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1130                                           &link.link_duplex);
1131                 link.link_status = 1;
1132         } else if (!link_check) {
1133                 link.link_speed = 0;
1134                 link.link_duplex = 0;
1135                 link.link_status = 0;
1136         }
1137         rte_igb_dev_atomic_write_link_status(dev, &link);
1138
1139         /* not changed */
1140         if (old.link_status == link.link_status)
1141                 return -1;
1142
1143         /* changed */
1144         return 0;
1145 }
1146
1147 /*
1148  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1149  * For ASF and Pass Through versions of f/w this means
1150  * that the driver is loaded.
1151  */
1152 static void
1153 igb_hw_control_acquire(struct e1000_hw *hw)
1154 {
1155         uint32_t ctrl_ext;
1156
1157         /* Let firmware know the driver has taken over */
1158         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1159         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1160 }
1161
1162 /*
1163  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1164  * For ASF and Pass Through versions of f/w this means that the
1165  * driver is no longer loaded.
1166  */
1167 static void
1168 igb_hw_control_release(struct e1000_hw *hw)
1169 {
1170         uint32_t ctrl_ext;
1171
1172         /* Let firmware taken over control of h/w */
1173         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1174         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1175                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1176 }
1177
1178 /*
1179  * Bit of a misnomer, what this really means is
1180  * to enable OS management of the system... aka
1181  * to disable special hardware management features.
1182  */
1183 static void
1184 igb_init_manageability(struct e1000_hw *hw)
1185 {
1186         if (e1000_enable_mng_pass_thru(hw)) {
1187                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1188                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1189
1190                 /* disable hardware interception of ARP */
1191                 manc &= ~(E1000_MANC_ARP_EN);
1192
1193                 /* enable receiving management packets to the host */
1194                 manc |= E1000_MANC_EN_MNG2HOST;
1195                 manc2h |= 1 << 5;  /* Mng Port 623 */
1196                 manc2h |= 1 << 6;  /* Mng Port 664 */
1197                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1198                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1199         }
1200 }
1201
1202 static void
1203 igb_release_manageability(struct e1000_hw *hw)
1204 {
1205         if (e1000_enable_mng_pass_thru(hw)) {
1206                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1207
1208                 manc |= E1000_MANC_ARP_EN;
1209                 manc &= ~E1000_MANC_EN_MNG2HOST;
1210
1211                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1212         }
1213 }
1214
1215 static void
1216 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1217 {
1218         struct e1000_hw *hw =
1219                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1220         uint32_t rctl;
1221
1222         rctl = E1000_READ_REG(hw, E1000_RCTL);
1223         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1224         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1225 }
1226
1227 static void
1228 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1229 {
1230         struct e1000_hw *hw =
1231                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         uint32_t rctl;
1233
1234         rctl = E1000_READ_REG(hw, E1000_RCTL);
1235         rctl &= (~E1000_RCTL_UPE);
1236         if (dev->data->all_multicast == 1)
1237                 rctl |= E1000_RCTL_MPE;
1238         else
1239                 rctl &= (~E1000_RCTL_MPE);
1240         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1241 }
1242
1243 static void
1244 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1245 {
1246         struct e1000_hw *hw =
1247                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         uint32_t rctl;
1249
1250         rctl = E1000_READ_REG(hw, E1000_RCTL);
1251         rctl |= E1000_RCTL_MPE;
1252         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1253 }
1254
1255 static void
1256 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1257 {
1258         struct e1000_hw *hw =
1259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         uint32_t rctl;
1261
1262         if (dev->data->promiscuous == 1)
1263                 return; /* must remain in all_multicast mode */
1264         rctl = E1000_READ_REG(hw, E1000_RCTL);
1265         rctl &= (~E1000_RCTL_MPE);
1266         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1267 }
1268
1269 static int
1270 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1271 {
1272         struct e1000_hw *hw =
1273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         struct e1000_vfta * shadow_vfta =
1275                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1276         uint32_t vfta;
1277         uint32_t vid_idx;
1278         uint32_t vid_bit;
1279
1280         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1281                               E1000_VFTA_ENTRY_MASK);
1282         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1283         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1284         if (on)
1285                 vfta |= vid_bit;
1286         else
1287                 vfta &= ~vid_bit;
1288         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1289
1290         /* update local VFTA copy */
1291         shadow_vfta->vfta[vid_idx] = vfta;
1292
1293         return 0;
1294 }
1295
1296 static void
1297 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1298 {
1299         struct e1000_hw *hw =
1300                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301         uint32_t reg = ETHER_TYPE_VLAN ;
1302
1303         reg |= (tpid << 16);
1304         E1000_WRITE_REG(hw, E1000_VET, reg);
1305 }
1306
1307 static void
1308 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1309 {
1310         struct e1000_hw *hw =
1311                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312         uint32_t reg;
1313
1314         /* Filter Table Disable */
1315         reg = E1000_READ_REG(hw, E1000_RCTL);
1316         reg &= ~E1000_RCTL_CFIEN;
1317         reg &= ~E1000_RCTL_VFE;
1318         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1319 }
1320
1321 static void
1322 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1323 {
1324         struct e1000_hw *hw =
1325                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         struct e1000_vfta * shadow_vfta =
1327                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1328         uint32_t reg;
1329         int i;
1330
1331         /* Filter Table Enable, CFI not used for packet acceptance */
1332         reg = E1000_READ_REG(hw, E1000_RCTL);
1333         reg &= ~E1000_RCTL_CFIEN;
1334         reg |= E1000_RCTL_VFE;
1335         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1336
1337         /* restore VFTA table */
1338         for (i = 0; i < IGB_VFTA_SIZE; i++)
1339                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1340 }
1341
1342 static void
1343 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1344 {
1345         struct e1000_hw *hw =
1346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         uint32_t reg;
1348
1349         /* VLAN Mode Disable */
1350         reg = E1000_READ_REG(hw, E1000_CTRL);
1351         reg &= ~E1000_CTRL_VME;
1352         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1353
1354         /* Update maximum frame size */
1355         E1000_WRITE_REG(hw, E1000_RLPML,
1356                 dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE);
1357 }
1358
1359 static void
1360 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1361 {
1362         struct e1000_hw *hw =
1363                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364         uint32_t reg;
1365
1366         /* VLAN Mode Enable */
1367         reg = E1000_READ_REG(hw, E1000_CTRL);
1368         reg |= E1000_CTRL_VME;
1369         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1370
1371         /* Update maximum frame size */
1372         E1000_WRITE_REG(hw, E1000_RLPML,
1373                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1374
1375 }
1376
1377 static void
1378 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1379 {
1380         struct e1000_hw *hw =
1381                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1382         uint32_t reg;
1383
1384         /* CTRL_EXT: Extended VLAN */
1385         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1386         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1387         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1388
1389 }
1390
1391 static void
1392 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1393 {
1394         struct e1000_hw *hw =
1395                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         uint32_t reg;
1397
1398         /* CTRL_EXT: Extended VLAN */
1399         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1400         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1401         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1402 }
1403
1404 static void
1405 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1406 {
1407         if(mask & ETH_VLAN_STRIP_MASK){
1408                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1409                         igb_vlan_hw_strip_enable(dev);
1410                 else
1411                         igb_vlan_hw_strip_disable(dev);
1412         }
1413
1414         if(mask & ETH_VLAN_FILTER_MASK){
1415                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1416                         igb_vlan_hw_filter_enable(dev);
1417                 else
1418                         igb_vlan_hw_filter_disable(dev);
1419         }
1420
1421         if(mask & ETH_VLAN_EXTEND_MASK){
1422                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1423                         igb_vlan_hw_extend_enable(dev);
1424                 else
1425                         igb_vlan_hw_extend_disable(dev);
1426         }
1427 }
1428
1429 static void
1430 igb_intr_disable(struct e1000_hw *hw)
1431 {
1432         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1433         E1000_WRITE_FLUSH(hw);
1434 }
1435
1436 /**
1437  * It enables the interrupt mask and then enable the interrupt.
1438  *
1439  * @param dev
1440  *  Pointer to struct rte_eth_dev.
1441  *
1442  * @return
1443  *  - On success, zero.
1444  *  - On failure, a negative value.
1445  */
1446 static int
1447 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1448 {
1449         struct e1000_hw *hw =
1450                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451
1452         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1453         E1000_WRITE_FLUSH(hw);
1454         rte_intr_enable(&(dev->pci_dev->intr_handle));
1455
1456         return 0;
1457 }
1458
1459 /*
1460  * It reads ICR and gets interrupt causes, check it and set a bit flag
1461  * to update link status.
1462  *
1463  * @param dev
1464  *  Pointer to struct rte_eth_dev.
1465  *
1466  * @return
1467  *  - On success, zero.
1468  *  - On failure, a negative value.
1469  */
1470 static int
1471 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1472 {
1473         uint32_t icr;
1474         struct e1000_hw *hw =
1475                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1476         struct e1000_interrupt *intr =
1477                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1478
1479         /* read-on-clear nic registers here */
1480         icr = E1000_READ_REG(hw, E1000_ICR);
1481         if (icr & E1000_ICR_LSC) {
1482                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1483         }
1484
1485         return 0;
1486 }
1487
1488 /*
1489  * It executes link_update after knowing an interrupt is prsent.
1490  *
1491  * @param dev
1492  *  Pointer to struct rte_eth_dev.
1493  *
1494  * @return
1495  *  - On success, zero.
1496  *  - On failure, a negative value.
1497  */
1498 static int
1499 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1500 {
1501         struct e1000_hw *hw =
1502                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503         struct e1000_interrupt *intr =
1504                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1505         uint32_t tctl, rctl;
1506         struct rte_eth_link link;
1507         int ret;
1508
1509         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1510                 return -1;
1511
1512         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1513         rte_intr_enable(&(dev->pci_dev->intr_handle));
1514
1515         /* set get_link_status to check register later */
1516         hw->mac.get_link_status = 1;
1517         ret = eth_igb_link_update(dev, 0);
1518
1519         /* check if link has changed */
1520         if (ret < 0)
1521                 return 0;
1522
1523         memset(&link, 0, sizeof(link));
1524         rte_igb_dev_atomic_read_link_status(dev, &link);
1525         if (link.link_status) {
1526                 PMD_INIT_LOG(INFO,
1527                         " Port %d: Link Up - speed %u Mbps - %s\n",
1528                         dev->data->port_id, (unsigned)link.link_speed,
1529                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1530                                 "full-duplex" : "half-duplex");
1531         } else {
1532                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1533                                         dev->data->port_id);
1534         }
1535         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1536                                 dev->pci_dev->addr.domain,
1537                                 dev->pci_dev->addr.bus,
1538                                 dev->pci_dev->addr.devid,
1539                                 dev->pci_dev->addr.function);
1540         tctl = E1000_READ_REG(hw, E1000_TCTL);
1541         rctl = E1000_READ_REG(hw, E1000_RCTL);
1542         if (link.link_status) {
1543                 /* enable Tx/Rx */
1544                 tctl |= E1000_TCTL_EN;
1545                 rctl |= E1000_RCTL_EN;
1546         } else {
1547                 /* disable Tx/Rx */
1548                 tctl &= ~E1000_TCTL_EN;
1549                 rctl &= ~E1000_RCTL_EN;
1550         }
1551         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1552         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1553         E1000_WRITE_FLUSH(hw);
1554
1555         return 0;
1556 }
1557
1558 /**
1559  * Interrupt handler which shall be registered at first.
1560  *
1561  * @param handle
1562  *  Pointer to interrupt handle.
1563  * @param param
1564  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1565  *
1566  * @return
1567  *  void
1568  */
1569 static void
1570 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
1571 {
1572         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1573
1574         eth_igb_interrupt_get_status(dev);
1575         eth_igb_interrupt_action(dev);
1576         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1577 }
1578
1579 static int
1580 eth_igb_led_on(struct rte_eth_dev *dev)
1581 {
1582         struct e1000_hw *hw;
1583
1584         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1586 }
1587
1588 static int
1589 eth_igb_led_off(struct rte_eth_dev *dev)
1590 {
1591         struct e1000_hw *hw;
1592
1593         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1594         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1595 }
1596
1597 static int
1598 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1599 {
1600         struct e1000_hw *hw;
1601         int err;
1602         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1603                 e1000_fc_none,
1604                 e1000_fc_rx_pause,
1605                 e1000_fc_tx_pause,
1606                 e1000_fc_full
1607         };
1608         uint32_t rx_buf_size;
1609         uint32_t max_high_water;
1610
1611         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612         rx_buf_size = igb_get_rx_buffer_size(hw);
1613         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1614
1615         /* At least reserve one Ethernet frame for watermark */
1616         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1617         if ((fc_conf->high_water > max_high_water) ||
1618                 (fc_conf->high_water < fc_conf->low_water)) {
1619                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1620                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1621                 return (-EINVAL);
1622         }
1623
1624         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1625         hw->fc.pause_time     = fc_conf->pause_time;
1626         hw->fc.high_water     = fc_conf->high_water;
1627         hw->fc.low_water      = fc_conf->low_water;
1628         hw->fc.send_xon       = fc_conf->send_xon;
1629
1630         err = e1000_setup_link_generic(hw);
1631         if (err == E1000_SUCCESS) {
1632                 return 0;
1633         }
1634
1635         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1636         return (-EIO);
1637 }
1638
1639 static void
1640 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1641                 uint32_t index, __rte_unused uint32_t pool)
1642 {
1643         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644
1645         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1646 }
1647
1648 static void
1649 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1650 {
1651         uint8_t addr[ETHER_ADDR_LEN];
1652         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653
1654         memset(addr, 0, sizeof(addr));
1655
1656         e1000_rar_set(hw, addr, index);
1657 }
1658
1659 /*
1660  * Virtual Function operations
1661  */
1662 static void
1663 igbvf_intr_disable(struct e1000_hw *hw)
1664 {
1665         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1666
1667         /* Clear interrupt mask to stop from interrupts being generated */
1668         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1669
1670         E1000_WRITE_FLUSH(hw);
1671 }
1672
1673 static void
1674 igbvf_stop_adapter(struct rte_eth_dev *dev)
1675 {
1676         u32 reg_val;
1677         u16 i;
1678         struct rte_eth_dev_info dev_info;
1679         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680
1681         memset(&dev_info, 0, sizeof(dev_info));
1682         eth_igb_infos_get(dev, &dev_info);
1683
1684         /* Clear interrupt mask to stop from interrupts being generated */
1685         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1686
1687         /* Clear any pending interrupts, flush previous writes */
1688         E1000_READ_REG(hw, E1000_EICR);
1689
1690         /* Disable the transmit unit.  Each queue must be disabled. */
1691         for (i = 0; i < dev_info.max_tx_queues; i++)
1692                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1693
1694         /* Disable the receive unit by stopping each queue */
1695         for (i = 0; i < dev_info.max_rx_queues; i++) {
1696                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1697                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1698                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1699                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1700                         ;
1701         }
1702
1703         /* flush all queues disables */
1704         E1000_WRITE_FLUSH(hw);
1705         msec_delay(2);
1706 }
1707
1708 static int eth_igbvf_link_update(struct e1000_hw *hw)
1709 {
1710         struct e1000_mbx_info *mbx = &hw->mbx;
1711         struct e1000_mac_info *mac = &hw->mac;
1712         int ret_val = E1000_SUCCESS;
1713
1714         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1715
1716         /*
1717          * We only want to run this if there has been a rst asserted.
1718          * in this case that could mean a link change, device reset,
1719          * or a virtual function reset
1720          */
1721
1722         /* If we were hit with a reset or timeout drop the link */
1723         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1724                 mac->get_link_status = TRUE;
1725
1726         if (!mac->get_link_status)
1727                 goto out;
1728
1729         /* if link status is down no point in checking to see if pf is up */
1730         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1731                 goto out;
1732
1733         /* if we passed all the tests above then the link is up and we no
1734          * longer need to check for link */
1735         mac->get_link_status = FALSE;
1736
1737 out:
1738         return ret_val;
1739 }
1740
1741
1742 static int
1743 igbvf_dev_configure(struct rte_eth_dev *dev)
1744 {
1745         struct rte_eth_conf* conf = &dev->data->dev_conf;
1746
1747         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1748                 dev->data->port_id);
1749
1750         /*
1751          * VF has no ability to enable/disable HW CRC
1752          * Keep the persistent behavior the same as Host PF
1753          */
1754 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1755         if (!conf->rxmode.hw_strip_crc) {
1756                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1757                 conf->rxmode.hw_strip_crc = 1;
1758         }
1759 #else
1760         if (conf->rxmode.hw_strip_crc) {
1761                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1762                 conf->rxmode.hw_strip_crc = 0;
1763         }
1764 #endif
1765
1766         return 0;
1767 }
1768
1769 static int
1770 igbvf_dev_start(struct rte_eth_dev *dev)
1771 {
1772         int ret;
1773
1774         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1775
1776         /* Set all vfta */
1777         igbvf_set_vfta_all(dev,1);
1778
1779         eth_igbvf_tx_init(dev);
1780
1781         /* This can fail when allocating mbufs for descriptor rings */
1782         ret = eth_igbvf_rx_init(dev);
1783         if (ret) {
1784                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1785                 igb_dev_clear_queues(dev);
1786                 return ret;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static void
1793 igbvf_dev_stop(struct rte_eth_dev *dev)
1794 {
1795         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1796
1797         igbvf_stop_adapter(dev);
1798
1799         /*
1800           * Clear what we set, but we still keep shadow_vfta to
1801           * restore after device starts
1802           */
1803         igbvf_set_vfta_all(dev,0);
1804
1805         igb_dev_clear_queues(dev);
1806 }
1807
1808 static void
1809 igbvf_dev_close(struct rte_eth_dev *dev)
1810 {
1811         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812
1813         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1814
1815         e1000_reset_hw(hw);
1816
1817         igbvf_dev_stop(dev);
1818 }
1819
1820 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1821 {
1822         struct e1000_mbx_info *mbx = &hw->mbx;
1823         uint32_t msgbuf[2];
1824
1825         /* After set vlan, vlan strip will also be enabled in igb driver*/
1826         msgbuf[0] = E1000_VF_SET_VLAN;
1827         msgbuf[1] = vid;
1828         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1829         if (on)
1830                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1831
1832         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1833 }
1834
1835 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1836 {
1837         struct e1000_hw *hw =
1838                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839         struct e1000_vfta * shadow_vfta =
1840                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1841         int i = 0, j = 0, vfta = 0, mask = 1;
1842
1843         for (i = 0; i < IGB_VFTA_SIZE; i++){
1844                 vfta = shadow_vfta->vfta[i];
1845                 if(vfta){
1846                         mask = 1;
1847                         for (j = 0; j < 32; j++){
1848                                 if(vfta & mask)
1849                                         igbvf_set_vfta(hw, (i<<5)+j, on);
1850                                 mask<<=1;
1851                         }
1852                 }
1853         }
1854
1855 }
1856
1857 static int
1858 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1859 {
1860         struct e1000_hw *hw =
1861                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         struct e1000_vfta * shadow_vfta =
1863                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1864         uint32_t vid_idx = 0;
1865         uint32_t vid_bit = 0;
1866         int ret = 0;
1867
1868         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1869
1870         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1871         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1872         if(ret){
1873                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1874                 return ret;
1875         }
1876         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1877         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1878
1879         /*Save what we set and retore it after device reset*/
1880         if (on)
1881                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1882         else
1883                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1884
1885         return 0;
1886 }
1887