lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  81                                                         void *param);
  82 static int  igb_hardware_init(struct e1000_hw *hw);
  83 static void igb_hw_control_acquire(struct e1000_hw *hw);
  84 static void igb_hw_control_release(struct e1000_hw *hw);
  85 static void igb_init_manageability(struct e1000_hw *hw);
  86 static void igb_release_manageability(struct e1000_hw *hw);
  87
  88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  89                 uint16_t vlan_id, int on);
  90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  92
  93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  99
 100 static int eth_igb_led_on(struct rte_eth_dev *dev);
 101 static int eth_igb_led_off(struct rte_eth_dev *dev);
 102
 103 static void igb_intr_disable(struct e1000_hw *hw);
 104 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 106                 struct ether_addr *mac_addr,
 107                 uint32_t index, uint32_t pool);
 108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 109
 110 static void igbvf_intr_disable(struct e1000_hw *hw);
 111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 112 static int igbvf_dev_start(struct rte_eth_dev *dev);
 113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 114 static void igbvf_dev_close(struct rte_eth_dev *dev);
 115 static int eth_igbvf_link_update(struct e1000_hw *hw);
 116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 119                 uint16_t vlan_id, int on);
 120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 122 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 123                  struct rte_eth_rss_reta *reta_conf);
 124 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 125                 struct rte_eth_rss_reta *reta_conf);
 126
 127 /*
 128  * Define VF Stats MACRO for Non "cleared on read" register
 129  */
 130 #define UPDATE_VF_STAT(reg, last, cur)            \
 131 {                                                 \
 132         u32 latest = E1000_READ_REG(hw, reg);     \
 133         cur += latest - last;                     \
 134         last = latest;                            \
 135 }
 136
 137
 138 #define IGB_FC_PAUSE_TIME 0x0680
 139 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 140 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 141
 142 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 143
 144 /*
 145  * The set of PCI devices this driver supports
 146  */
 147 static struct rte_pci_id pci_id_igb_map[] = {
 148
 149 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 150 #include "rte_pci_dev_ids.h"
 151
 152 {.device_id = 0},
 153 };
 154
 155 /*
 156  * The set of PCI devices this driver supports (for 82576&I350 VF)
 157  */
 158 static struct rte_pci_id pci_id_igbvf_map[] = {
 159
 160 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 161 #include "rte_pci_dev_ids.h"
 162
 163 {.device_id = 0},
 164 };
 165
 166 static struct eth_dev_ops eth_igb_ops = {
 167         .dev_configure        = eth_igb_configure,
 168         .dev_start            = eth_igb_start,
 169         .dev_stop             = eth_igb_stop,
 170         .dev_close            = eth_igb_close,
 171         .promiscuous_enable   = eth_igb_promiscuous_enable,
 172         .promiscuous_disable  = eth_igb_promiscuous_disable,
 173         .allmulticast_enable  = eth_igb_allmulticast_enable,
 174         .allmulticast_disable = eth_igb_allmulticast_disable,
 175         .link_update          = eth_igb_link_update,
 176         .stats_get            = eth_igb_stats_get,
 177         .stats_reset          = eth_igb_stats_reset,
 178         .dev_infos_get        = eth_igb_infos_get,
 179         .vlan_filter_set      = eth_igb_vlan_filter_set,
 180         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 181         .vlan_offload_set     = eth_igb_vlan_offload_set,
 182         .rx_queue_setup       = eth_igb_rx_queue_setup,
 183         .rx_queue_release     = eth_igb_rx_queue_release,
 184         .tx_queue_setup       = eth_igb_tx_queue_setup,
 185         .tx_queue_release     = eth_igb_tx_queue_release,
 186         .dev_led_on           = eth_igb_led_on,
 187         .dev_led_off          = eth_igb_led_off,
 188         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 189         .mac_addr_add         = eth_igb_rar_set,
 190         .mac_addr_remove      = eth_igb_rar_clear,
 191         .reta_update          = eth_igb_rss_reta_update,
 192         .reta_query           = eth_igb_rss_reta_query,
 193 };
 194
 195 /*
 196  * dev_ops for virtual function, bare necessities for basic vf
 197  * operation have been implemented
 198  */
 199 static struct eth_dev_ops igbvf_eth_dev_ops = {
 200         .dev_configure        = igbvf_dev_configure,
 201         .dev_start            = igbvf_dev_start,
 202         .dev_stop             = igbvf_dev_stop,
 203         .dev_close            = igbvf_dev_close,
 204         .link_update          = eth_igb_link_update,
 205         .stats_get            = eth_igbvf_stats_get,
 206         .stats_reset          = eth_igbvf_stats_reset,
 207         .vlan_filter_set      = igbvf_vlan_filter_set,
 208         .dev_infos_get        = eth_igb_infos_get,
 209         .rx_queue_setup       = eth_igb_rx_queue_setup,
 210         .rx_queue_release     = eth_igb_rx_queue_release,
 211         .tx_queue_setup       = eth_igb_tx_queue_setup,
 212         .tx_queue_release     = eth_igb_tx_queue_release,
 213 };
 214
 215 /**
 216  * Atomically reads the link status information from global
 217  * structure rte_eth_dev.
 218  *
 219  * @param dev
 220  *   - Pointer to the structure rte_eth_dev to read from.
 221  *   - Pointer to the buffer to be saved with the link status.
 222  *
 223  * @return
 224  *   - On success, zero.
 225  *   - On failure, negative value.
 226  */
 227 static inline int
 228 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 229                                 struct rte_eth_link *link)
 230 {
 231         struct rte_eth_link *dst = link;
 232         struct rte_eth_link *src = &(dev->data->dev_link);
 233
 234         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 235                                         *(uint64_t *)src) == 0)
 236                 return -1;
 237
 238         return 0;
 239 }
 240
 241 /**
 242  * Atomically writes the link status information into global
 243  * structure rte_eth_dev.
 244  *
 245  * @param dev
 246  *   - Pointer to the structure rte_eth_dev to read from.
 247  *   - Pointer to the buffer to be saved with the link status.
 248  *
 249  * @return
 250  *   - On success, zero.
 251  *   - On failure, negative value.
 252  */
 253 static inline int
 254 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 255                                 struct rte_eth_link *link)
 256 {
 257         struct rte_eth_link *dst = &(dev->data->dev_link);
 258         struct rte_eth_link *src = link;
 259
 260         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 261                                         *(uint64_t *)src) == 0)
 262                 return -1;
 263
 264         return 0;
 265 }
 266
 267 static inline void
 268 igb_intr_enable(struct rte_eth_dev *dev)
 269 {
 270         struct e1000_interrupt *intr =
 271                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 272         struct e1000_hw *hw =
 273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 274
 275         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 276         E1000_WRITE_FLUSH(hw);
 277 }
 278
 279 static void
 280 igb_intr_disable(struct e1000_hw *hw)
 281 {
 282         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 283         E1000_WRITE_FLUSH(hw);
 284 }
 285
 286 static void
 287 igb_identify_hardware(struct rte_eth_dev *dev)
 288 {
 289         struct e1000_hw *hw =
 290                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 291
 292         hw->vendor_id = dev->pci_dev->id.vendor_id;
 293         hw->device_id = dev->pci_dev->id.device_id;
 294         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 295         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 296
 297         e1000_set_mac_type(hw);
 298
 299         /* need to check if it is a vf device below */
 300 }
 301
 302 static int
 303 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 304                    struct rte_eth_dev *eth_dev)
 305 {
 306         int error = 0;
 307         struct rte_pci_device *pci_dev;
 308         struct e1000_hw *hw =
 309                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 310         struct e1000_vfta * shadow_vfta =
 311                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 312
 313         pci_dev = eth_dev->pci_dev;
 314         eth_dev->dev_ops = &eth_igb_ops;
 315         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 316         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 317
 318         /* for secondary processes, we don't initialise any further as primary
 319          * has already done this work. Only check we don't need a different
 320          * RX function */
 321         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 322                 if (eth_dev->data->scattered_rx)
 323                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 324                 return 0;
 325         }
 326
 327         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 328
 329         igb_identify_hardware(eth_dev);
 330         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 331                 error = -EIO;
 332                 goto err_late;
 333         }
 334
 335         e1000_get_bus_info(hw);
 336
 337         hw->mac.autoneg = 1;
 338         hw->phy.autoneg_wait_to_complete = 0;
 339         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 340
 341         /* Copper options */
 342         if (hw->phy.media_type == e1000_media_type_copper) {
 343                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 344                 hw->phy.disable_polarity_correction = 0;
 345                 hw->phy.ms_type = e1000_ms_hw_default;
 346         }
 347
 348         /*
 349          * Start from a known state, this is important in reading the nvm
 350          * and mac from that.
 351          */
 352         e1000_reset_hw(hw);
 353
 354         /* Make sure we have a good EEPROM before we read from it */
 355         if (e1000_validate_nvm_checksum(hw) < 0) {
 356                 /*
 357                  * Some PCI-E parts fail the first check due to
 358                  * the link being in sleep state, call it again,
 359                  * if it fails a second time its a real issue.
 360                  */
 361                 if (e1000_validate_nvm_checksum(hw) < 0) {
 362                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 363                         error = -EIO;
 364                         goto err_late;
 365                 }
 366         }
 367
 368         /* Read the permanent MAC address out of the EEPROM */
 369         if (e1000_read_mac_addr(hw) != 0) {
 370                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 371                 error = -EIO;
 372                 goto err_late;
 373         }
 374
 375         /* Allocate memory for storing MAC addresses */
 376         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 377                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 378         if (eth_dev->data->mac_addrs == NULL) {
 379                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 380                                                 "store MAC addresses",
 381                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 382                 error = -ENOMEM;
 383                 goto err_late;
 384         }
 385
 386         /* Copy the permanent MAC address */
 387         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 388
 389         /* initialize the vfta */
 390         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 391
 392         /* Now initialize the hardware */
 393         if (igb_hardware_init(hw) != 0) {
 394                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 395                 rte_free(eth_dev->data->mac_addrs);
 396                 eth_dev->data->mac_addrs = NULL;
 397                 error = -ENODEV;
 398                 goto err_late;
 399         }
 400         hw->mac.get_link_status = 1;
 401
 402         /* Indicate SOL/IDER usage */
 403         if (e1000_check_reset_block(hw) < 0) {
 404                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 405                                         "SOL/IDER session");
 406         }
 407
 408         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 409                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 410                      pci_dev->id.device_id);
 411
 412         rte_intr_callback_register(&(pci_dev->intr_handle),
 413                 eth_igb_interrupt_handler, (void *)eth_dev);
 414
 415         /* enable uio intr after callback register */
 416         rte_intr_enable(&(pci_dev->intr_handle));
 417
 418         /* enable support intr */
 419         igb_intr_enable(eth_dev);
 420
 421         return 0;
 422
 423 err_late:
 424         igb_hw_control_release(hw);
 425
 426         return (error);
 427 }
 428
 429 /*
 430  * Virtual Function device init
 431  */
 432 static int
 433 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 434                 struct rte_eth_dev *eth_dev)
 435 {
 436         struct rte_pci_device *pci_dev;
 437         struct e1000_hw *hw =
 438                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 439         int diag;
 440
 441         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 442
 443         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 444         pci_dev = eth_dev->pci_dev;
 445
 446         hw->device_id = pci_dev->id.device_id;
 447         hw->vendor_id = pci_dev->id.vendor_id;
 448         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 449
 450         /* Initialize the shared code */
 451         diag = e1000_setup_init_funcs(hw, TRUE);
 452         if (diag != 0) {
 453                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 454                         diag);
 455                 return -EIO;
 456         }
 457
 458         /* init_mailbox_params */
 459         hw->mbx.ops.init_params(hw);
 460
 461         /* Disable the interrupts for VF */
 462         igbvf_intr_disable(hw);
 463
 464         diag = hw->mac.ops.reset_hw(hw);
 465
 466         /* Allocate memory for storing MAC addresses */
 467         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 468                 hw->mac.rar_entry_count, 0);
 469         if (eth_dev->data->mac_addrs == NULL) {
 470                 PMD_INIT_LOG(ERR,
 471                         "Failed to allocate %d bytes needed to store MAC "
 472                         "addresses",
 473                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 474                 return -ENOMEM;
 475         }
 476         /* Copy the permanent MAC address */
 477         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 478                         &eth_dev->data->mac_addrs[0]);
 479
 480         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 481                         "mac.type=%s\n",
 482                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 483                         pci_dev->id.device_id,
 484                         "igb_mac_82576_vf");
 485
 486         return 0;
 487 }
 488
 489 static struct eth_driver rte_igb_pmd = {
 490         {
 491                 .name = "rte_igb_pmd",
 492                 .id_table = pci_id_igb_map,
 493 #ifdef RTE_EAL_UNBIND_PORTS
 494                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 495 #endif
 496         },
 497         .eth_dev_init = eth_igb_dev_init,
 498         .dev_private_size = sizeof(struct e1000_adapter),
 499 };
 500
 501 /*
 502  * virtual function driver struct
 503  */
 504 static struct eth_driver rte_igbvf_pmd = {
 505         {
 506                 .name = "rte_igbvf_pmd",
 507                 .id_table = pci_id_igbvf_map,
 508 #ifdef RTE_EAL_UNBIND_PORTS
 509                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 510 #endif
 511         },
 512         .eth_dev_init = eth_igbvf_dev_init,
 513         .dev_private_size = sizeof(struct e1000_adapter),
 514 };
 515
 516 int
 517 rte_igb_pmd_init(void)
 518 {
 519         rte_eth_driver_register(&rte_igb_pmd);
 520         return 0;
 521 }
 522
 523 /*
 524  * VF Driver initialization routine.
 525  * Invoked one at EAL init time.
 526  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 527  */
 528 int
 529 rte_igbvf_pmd_init(void)
 530 {
 531         DEBUGFUNC("rte_igbvf_pmd_init");
 532
 533         rte_eth_driver_register(&rte_igbvf_pmd);
 534         return (0);
 535 }
 536
 537 static int
 538 eth_igb_configure(struct rte_eth_dev *dev)
 539 {
 540         struct e1000_interrupt *intr =
 541                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 542
 543         PMD_INIT_LOG(DEBUG, ">>");
 544
 545         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 546
 547         PMD_INIT_LOG(DEBUG, "<<");
 548
 549         return (0);
 550 }
 551
 552 static int
 553 eth_igb_start(struct rte_eth_dev *dev)
 554 {
 555         struct e1000_hw *hw =
 556                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 557         int ret, i, mask;
 558
 559         PMD_INIT_LOG(DEBUG, ">>");
 560
 561         /* Power up the phy. Needed to make the link go Up */
 562         e1000_power_up_phy(hw);
 563
 564         /*
 565          * Packet Buffer Allocation (PBA)
 566          * Writing PBA sets the receive portion of the buffer
 567          * the remainder is used for the transmit buffer.
 568          */
 569         if (hw->mac.type == e1000_82575) {
 570                 uint32_t pba;
 571
 572                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 573                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 574         }
 575
 576         /* Put the address into the Receive Address Array */
 577         e1000_rar_set(hw, hw->mac.addr, 0);
 578
 579         /* Initialize the hardware */
 580         if (igb_hardware_init(hw)) {
 581                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 582                 return (-EIO);
 583         }
 584
 585         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 586
 587         /* Configure for OS presence */
 588         igb_init_manageability(hw);
 589
 590         eth_igb_tx_init(dev);
 591
 592         /* This can fail when allocating mbufs for descriptor rings */
 593         ret = eth_igb_rx_init(dev);
 594         if (ret) {
 595                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 596                 igb_dev_clear_queues(dev);
 597                 return ret;
 598         }
 599
 600         e1000_clear_hw_cntrs_base_generic(hw);
 601
 602         /*
 603          * VLAN Offload Settings
 604          */
 605         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 606                         ETH_VLAN_EXTEND_MASK;
 607         eth_igb_vlan_offload_set(dev, mask);
 608
 609         /*
 610          * Configure the Interrupt Moderation register (EITR) with the maximum
 611          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 612          * spurious [DMA] memory updates of RX and TX ring descriptors.
 613          *
 614          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 615          * spurious memory updates per second should be expected.
 616          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 617          *
 618          * Because interrupts are not used at all, the MSI-X is not activated
 619          * and interrupt moderation is controlled by EITR[0].
 620          *
 621          * Note that having [almost] disabled memory updates of RX and TX ring
 622          * descriptors through the Interrupt Moderation mechanism, memory
 623          * updates of ring descriptors are now moderated by the configurable
 624          * value of Write-Back Threshold registers.
 625          */
 626         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 627                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 628                 uint32_t ivar;
 629
 630                 /* Enable all RX & TX queues in the IVAR registers */
 631                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 632                 for (i = 0; i < 8; i++)
 633                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 634
 635                 /* Configure EITR with the maximum possible value (0xFFFF) */
 636                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 637         }
 638
 639         /* Setup link speed and duplex */
 640         switch (dev->data->dev_conf.link_speed) {
 641         case ETH_LINK_SPEED_AUTONEG:
 642                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 643                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 644                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 645                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 646                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 647                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 648                 else
 649                         goto error_invalid_config;
 650                 break;
 651         case ETH_LINK_SPEED_10:
 652                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 653                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 654                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 655                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 656                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 657                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 658                 else
 659                         goto error_invalid_config;
 660                 break;
 661         case ETH_LINK_SPEED_100:
 662                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 663                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 664                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 665                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 666                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 667                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 668                 else
 669                         goto error_invalid_config;
 670                 break;
 671         case ETH_LINK_SPEED_1000:
 672                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 673                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 674                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 675                 else
 676                         goto error_invalid_config;
 677                 break;
 678         case ETH_LINK_SPEED_10000:
 679         default:
 680                 goto error_invalid_config;
 681         }
 682         e1000_setup_link(hw);
 683
 684         /* check if lsc interrupt feature is enabled */
 685         if (dev->data->dev_conf.intr_conf.lsc != 0)
 686                 ret = eth_igb_lsc_interrupt_setup(dev);
 687
 688         /* resume enabled intr since hw reset */
 689         igb_intr_enable(dev);
 690
 691         PMD_INIT_LOG(DEBUG, "<<");
 692
 693         return (0);
 694
 695 error_invalid_config:
 696         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 697                         dev->data->dev_conf.link_speed,
 698                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 699         igb_dev_clear_queues(dev);
 700         return (-EINVAL);
 701 }
 702
 703 /*********************************************************************
 704  *
 705  *  This routine disables all traffic on the adapter by issuing a
 706  *  global reset on the MAC.
 707  *
 708  **********************************************************************/
 709 static void
 710 eth_igb_stop(struct rte_eth_dev *dev)
 711 {
 712         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 713         struct rte_eth_link link;
 714
 715         igb_intr_disable(hw);
 716         e1000_reset_hw(hw);
 717         E1000_WRITE_REG(hw, E1000_WUC, 0);
 718
 719         /* Power down the phy. Needed to make the link go Down */
 720         e1000_power_down_phy(hw);
 721
 722         igb_dev_clear_queues(dev);
 723
 724         /* clear the recorded link status */
 725         memset(&link, 0, sizeof(link));
 726         rte_igb_dev_atomic_write_link_status(dev, &link);
 727 }
 728
 729 static void
 730 eth_igb_close(struct rte_eth_dev *dev)
 731 {
 732         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 733         struct rte_eth_link link;
 734
 735         eth_igb_stop(dev);
 736         e1000_phy_hw_reset(hw);
 737         igb_release_manageability(hw);
 738         igb_hw_control_release(hw);
 739
 740         igb_dev_clear_queues(dev);
 741
 742         memset(&link, 0, sizeof(link));
 743         rte_igb_dev_atomic_write_link_status(dev, &link);
 744 }
 745
 746 static int
 747 igb_get_rx_buffer_size(struct e1000_hw *hw)
 748 {
 749         uint32_t rx_buf_size;
 750         if (hw->mac.type == e1000_82576) {
 751                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 752         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 753                 /* PBS needs to be translated according to a lookup table */
 754                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 755                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 756                 rx_buf_size = (rx_buf_size << 10);
 757         } else if (hw->mac.type == e1000_i210) {
 758                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 759         } else {
 760                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 761         }
 762
 763         return rx_buf_size;
 764 }
 765
 766 /*********************************************************************
 767  *
 768  *  Initialize the hardware
 769  *
 770  **********************************************************************/
 771 static int
 772 igb_hardware_init(struct e1000_hw *hw)
 773 {
 774         uint32_t rx_buf_size;
 775         int diag;
 776
 777         /* Let the firmware know the OS is in control */
 778         igb_hw_control_acquire(hw);
 779
 780         /*
 781          * These parameters control the automatic generation (Tx) and
 782          * response (Rx) to Ethernet PAUSE frames.
 783          * - High water mark should allow for at least two standard size (1518)
 784          *   frames to be received after sending an XOFF.
 785          * - Low water mark works best when it is very near the high water mark.
 786          *   This allows the receiver to restart by sending XON when it has
 787          *   drained a bit. Here we use an arbitary value of 1500 which will
 788          *   restart after one full frame is pulled from the buffer. There
 789          *   could be several smaller frames in the buffer and if so they will
 790          *   not trigger the XON until their total number reduces the buffer
 791          *   by 1500.
 792          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 793          */
 794         rx_buf_size = igb_get_rx_buffer_size(hw);
 795
 796         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 797         hw->fc.low_water = hw->fc.high_water - 1500;
 798         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 799         hw->fc.send_xon = 1;
 800
 801         /* Set Flow control, use the tunable location if sane */
 802         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 803                 hw->fc.requested_mode = igb_fc_setting;
 804         else
 805                 hw->fc.requested_mode = e1000_fc_none;
 806
 807         /* Issue a global reset */
 808         e1000_reset_hw(hw);
 809         E1000_WRITE_REG(hw, E1000_WUC, 0);
 810
 811         diag = e1000_init_hw(hw);
 812         if (diag < 0)
 813                 return (diag);
 814
 815         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 816         e1000_get_phy_info(hw);
 817         e1000_check_for_link(hw);
 818
 819         return (0);
 820 }
 821
 822 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 823 static void
 824 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 825 {
 826         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 827         struct e1000_hw_stats *stats =
 828                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 829         int pause_frames;
 830
 831         if(hw->phy.media_type == e1000_media_type_copper ||
 832             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 833                 stats->symerrs +=
 834                     E1000_READ_REG(hw,E1000_SYMERRS);
 835                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 836         }
 837
 838         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 839         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 840         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 841         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 842
 843         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 844         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 845         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 846         stats->dc += E1000_READ_REG(hw, E1000_DC);
 847         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 848         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 849         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 850         /*
 851         ** For watchdog management we need to know if we have been
 852         ** paused during the last interval, so capture that here.
 853         */
 854         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 855         stats->xoffrxc += pause_frames;
 856         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 857         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 858         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 859         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 860         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 861         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 862         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 863         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 864         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 865         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 866         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 867         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 868
 869         /* For the 64-bit byte counters the low dword must be read first. */
 870         /* Both registers clear on the read of the high dword */
 871
 872         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 873         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 874         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 875         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 876
 877         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 878         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 879         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 880         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 881         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 882
 883         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 884         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 885
 886         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 887         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 888         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 889         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 890         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 891         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 892         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 893         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 894         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 895         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 896
 897         /* Interrupt Counts */
 898
 899         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 900         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 901         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 902         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 903         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 904         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 905         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 906         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 907         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 908
 909         /* Host to Card Statistics */
 910
 911         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 912         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 913         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 914         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 915         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 916         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 917         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 918         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 919         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 920         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 921         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 922         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 923         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 924         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 925
 926         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 927         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 928         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 929         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 930         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 931         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 932
 933         if (rte_stats == NULL)
 934                 return;
 935
 936         /* Rx Errors */
 937         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 938             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 939
 940         /* Tx Errors */
 941         rte_stats->oerrors = stats->ecol + stats->latecol;
 942
 943         rte_stats->ipackets = stats->gprc;
 944         rte_stats->opackets = stats->gptc;
 945         rte_stats->ibytes   = stats->gorc;
 946         rte_stats->obytes   = stats->gotc;
 947 }
 948
 949 static void
 950 eth_igb_stats_reset(struct rte_eth_dev *dev)
 951 {
 952         struct e1000_hw_stats *hw_stats =
 953                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 954
 955         /* HW registers are cleared on read */
 956         eth_igb_stats_get(dev, NULL);
 957
 958         /* Reset software totals */
 959         memset(hw_stats, 0, sizeof(*hw_stats));
 960 }
 961
 962 static void
 963 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 964 {
 965         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 967                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 968
 969         /* Good Rx packets, include VF loopback */
 970         UPDATE_VF_STAT(E1000_VFGPRC,
 971             hw_stats->last_gprc, hw_stats->gprc);
 972
 973         /* Good Rx octets, include VF loopback */
 974         UPDATE_VF_STAT(E1000_VFGORC,
 975             hw_stats->last_gorc, hw_stats->gorc);
 976
 977         /* Good Tx packets, include VF loopback */
 978         UPDATE_VF_STAT(E1000_VFGPTC,
 979             hw_stats->last_gptc, hw_stats->gptc);
 980
 981         /* Good Tx octets, include VF loopback */
 982         UPDATE_VF_STAT(E1000_VFGOTC,
 983             hw_stats->last_gotc, hw_stats->gotc);
 984
 985         /* Rx Multicst packets */
 986         UPDATE_VF_STAT(E1000_VFMPRC,
 987             hw_stats->last_mprc, hw_stats->mprc);
 988
 989         /* Good Rx loopback packets */
 990         UPDATE_VF_STAT(E1000_VFGPRLBC,
 991             hw_stats->last_gprlbc, hw_stats->gprlbc);
 992
 993         /* Good Rx loopback octets */
 994         UPDATE_VF_STAT(E1000_VFGORLBC,
 995             hw_stats->last_gorlbc, hw_stats->gorlbc);
 996
 997         /* Good Tx loopback packets */
 998         UPDATE_VF_STAT(E1000_VFGPTLBC,
 999             hw_stats->last_gptlbc, hw_stats->gptlbc);
1000
1001         /* Good Tx loopback octets */
1002         UPDATE_VF_STAT(E1000_VFGOTLBC,
1003             hw_stats->last_gotlbc, hw_stats->gotlbc);
1004
1005         if (rte_stats == NULL)
1006                 return;
1007
1008         memset(rte_stats, 0, sizeof(*rte_stats));
1009         rte_stats->ipackets = hw_stats->gprc;
1010         rte_stats->ibytes = hw_stats->gorc;
1011         rte_stats->opackets = hw_stats->gptc;
1012         rte_stats->obytes = hw_stats->gotc;
1013         rte_stats->imcasts = hw_stats->mprc;
1014         rte_stats->ilbpackets = hw_stats->gprlbc;
1015         rte_stats->ilbbytes = hw_stats->gorlbc;
1016         rte_stats->olbpackets = hw_stats->gptlbc;
1017         rte_stats->olbbytes = hw_stats->gotlbc;
1018
1019 }
1020
1021 static void
1022 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1023 {
1024         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1025                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1026
1027         /* Sync HW register to the last stats */
1028         eth_igbvf_stats_get(dev, NULL);
1029
1030         /* reset HW current stats*/
1031         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1032                offsetof(struct e1000_vf_stats, gprc));
1033
1034 }
1035
1036 static void
1037 eth_igb_infos_get(struct rte_eth_dev *dev,
1038                     struct rte_eth_dev_info *dev_info)
1039 {
1040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1041
1042         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1043         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1044         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1045
1046         switch (hw->mac.type) {
1047         case e1000_82575:
1048                 dev_info->max_rx_queues = 4;
1049                 dev_info->max_tx_queues = 4;
1050                 break;
1051
1052         case e1000_82576:
1053                 dev_info->max_rx_queues = 16;
1054                 dev_info->max_tx_queues = 16;
1055                 break;
1056
1057         case e1000_82580:
1058                 dev_info->max_rx_queues = 8;
1059                 dev_info->max_tx_queues = 8;
1060                 break;
1061
1062         case e1000_i350:
1063                 dev_info->max_rx_queues = 8;
1064                 dev_info->max_tx_queues = 8;
1065                 break;
1066
1067         case e1000_i210:
1068                 dev_info->max_rx_queues = 4;
1069                 dev_info->max_tx_queues = 4;
1070                 break;
1071
1072         case e1000_vfadapt:
1073                 dev_info->max_rx_queues = 2;
1074                 dev_info->max_tx_queues = 2;
1075                 break;
1076
1077         case e1000_vfadapt_i350:
1078                 dev_info->max_rx_queues = 1;
1079                 dev_info->max_tx_queues = 1;
1080                 break;
1081
1082         default:
1083                 /* Should not happen */
1084                 dev_info->max_rx_queues = 0;
1085                 dev_info->max_tx_queues = 0;
1086         }
1087 }
1088
1089 /* return 0 means link status changed, -1 means not changed */
1090 static int
1091 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1092 {
1093         struct e1000_hw *hw =
1094                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1095         struct rte_eth_link link, old;
1096         int link_check, count;
1097
1098         link_check = 0;
1099         hw->mac.get_link_status = 1;
1100
1101         /* possible wait-to-complete in up to 9 seconds */
1102         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1103                 /* Read the real link status */
1104                 switch (hw->phy.media_type) {
1105                 case e1000_media_type_copper:
1106                         /* Do the work to read phy */
1107                         e1000_check_for_link(hw);
1108                         link_check = !hw->mac.get_link_status;
1109                         break;
1110
1111                 case e1000_media_type_fiber:
1112                         e1000_check_for_link(hw);
1113                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1114                                       E1000_STATUS_LU);
1115                         break;
1116
1117                 case e1000_media_type_internal_serdes:
1118                         e1000_check_for_link(hw);
1119                         link_check = hw->mac.serdes_has_link;
1120                         break;
1121
1122                 /* VF device is type_unknown */
1123                 case e1000_media_type_unknown:
1124                         eth_igbvf_link_update(hw);
1125                         link_check = !hw->mac.get_link_status;
1126                         break;
1127
1128                 default:
1129                         break;
1130                 }
1131                 if (link_check || wait_to_complete == 0)
1132                         break;
1133                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1134         }
1135         memset(&link, 0, sizeof(link));
1136         rte_igb_dev_atomic_read_link_status(dev, &link);
1137         old = link;
1138
1139         /* Now we check if a transition has happened */
1140         if (link_check) {
1141                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1142                                           &link.link_duplex);
1143                 link.link_status = 1;
1144         } else if (!link_check) {
1145                 link.link_speed = 0;
1146                 link.link_duplex = 0;
1147                 link.link_status = 0;
1148         }
1149         rte_igb_dev_atomic_write_link_status(dev, &link);
1150
1151         /* not changed */
1152         if (old.link_status == link.link_status)
1153                 return -1;
1154
1155         /* changed */
1156         return 0;
1157 }
1158
1159 /*
1160  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1161  * For ASF and Pass Through versions of f/w this means
1162  * that the driver is loaded.
1163  */
1164 static void
1165 igb_hw_control_acquire(struct e1000_hw *hw)
1166 {
1167         uint32_t ctrl_ext;
1168
1169         /* Let firmware know the driver has taken over */
1170         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1171         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1172 }
1173
1174 /*
1175  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1176  * For ASF and Pass Through versions of f/w this means that the
1177  * driver is no longer loaded.
1178  */
1179 static void
1180 igb_hw_control_release(struct e1000_hw *hw)
1181 {
1182         uint32_t ctrl_ext;
1183
1184         /* Let firmware taken over control of h/w */
1185         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1186         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1187                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1188 }
1189
1190 /*
1191  * Bit of a misnomer, what this really means is
1192  * to enable OS management of the system... aka
1193  * to disable special hardware management features.
1194  */
1195 static void
1196 igb_init_manageability(struct e1000_hw *hw)
1197 {
1198         if (e1000_enable_mng_pass_thru(hw)) {
1199                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1200                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1201
1202                 /* disable hardware interception of ARP */
1203                 manc &= ~(E1000_MANC_ARP_EN);
1204
1205                 /* enable receiving management packets to the host */
1206                 manc |= E1000_MANC_EN_MNG2HOST;
1207                 manc2h |= 1 << 5;  /* Mng Port 623 */
1208                 manc2h |= 1 << 6;  /* Mng Port 664 */
1209                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1210                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1211         }
1212 }
1213
1214 static void
1215 igb_release_manageability(struct e1000_hw *hw)
1216 {
1217         if (e1000_enable_mng_pass_thru(hw)) {
1218                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1219
1220                 manc |= E1000_MANC_ARP_EN;
1221                 manc &= ~E1000_MANC_EN_MNG2HOST;
1222
1223                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1224         }
1225 }
1226
1227 static void
1228 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1229 {
1230         struct e1000_hw *hw =
1231                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         uint32_t rctl;
1233
1234         rctl = E1000_READ_REG(hw, E1000_RCTL);
1235         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1236         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1237 }
1238
1239 static void
1240 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1241 {
1242         struct e1000_hw *hw =
1243                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244         uint32_t rctl;
1245
1246         rctl = E1000_READ_REG(hw, E1000_RCTL);
1247         rctl &= (~E1000_RCTL_UPE);
1248         if (dev->data->all_multicast == 1)
1249                 rctl |= E1000_RCTL_MPE;
1250         else
1251                 rctl &= (~E1000_RCTL_MPE);
1252         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1253 }
1254
1255 static void
1256 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1257 {
1258         struct e1000_hw *hw =
1259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         uint32_t rctl;
1261
1262         rctl = E1000_READ_REG(hw, E1000_RCTL);
1263         rctl |= E1000_RCTL_MPE;
1264         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1265 }
1266
1267 static void
1268 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1269 {
1270         struct e1000_hw *hw =
1271                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1272         uint32_t rctl;
1273
1274         if (dev->data->promiscuous == 1)
1275                 return; /* must remain in all_multicast mode */
1276         rctl = E1000_READ_REG(hw, E1000_RCTL);
1277         rctl &= (~E1000_RCTL_MPE);
1278         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1279 }
1280
1281 static int
1282 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1283 {
1284         struct e1000_hw *hw =
1285                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1286         struct e1000_vfta * shadow_vfta =
1287                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1288         uint32_t vfta;
1289         uint32_t vid_idx;
1290         uint32_t vid_bit;
1291
1292         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1293                               E1000_VFTA_ENTRY_MASK);
1294         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1295         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1296         if (on)
1297                 vfta |= vid_bit;
1298         else
1299                 vfta &= ~vid_bit;
1300         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1301
1302         /* update local VFTA copy */
1303         shadow_vfta->vfta[vid_idx] = vfta;
1304
1305         return 0;
1306 }
1307
1308 static void
1309 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1310 {
1311         struct e1000_hw *hw =
1312                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313         uint32_t reg = ETHER_TYPE_VLAN ;
1314
1315         reg |= (tpid << 16);
1316         E1000_WRITE_REG(hw, E1000_VET, reg);
1317 }
1318
1319 static void
1320 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1321 {
1322         struct e1000_hw *hw =
1323                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         uint32_t reg;
1325
1326         /* Filter Table Disable */
1327         reg = E1000_READ_REG(hw, E1000_RCTL);
1328         reg &= ~E1000_RCTL_CFIEN;
1329         reg &= ~E1000_RCTL_VFE;
1330         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1331 }
1332
1333 static void
1334 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1335 {
1336         struct e1000_hw *hw =
1337                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338         struct e1000_vfta * shadow_vfta =
1339                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1340         uint32_t reg;
1341         int i;
1342
1343         /* Filter Table Enable, CFI not used for packet acceptance */
1344         reg = E1000_READ_REG(hw, E1000_RCTL);
1345         reg &= ~E1000_RCTL_CFIEN;
1346         reg |= E1000_RCTL_VFE;
1347         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1348
1349         /* restore VFTA table */
1350         for (i = 0; i < IGB_VFTA_SIZE; i++)
1351                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1352 }
1353
1354 static void
1355 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1356 {
1357         struct e1000_hw *hw =
1358                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359         uint32_t reg;
1360
1361         /* VLAN Mode Disable */
1362         reg = E1000_READ_REG(hw, E1000_CTRL);
1363         reg &= ~E1000_CTRL_VME;
1364         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1365
1366         /* Update maximum frame size */
1367         E1000_WRITE_REG(hw, E1000_RLPML,
1368                 dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE);
1369 }
1370
1371 static void
1372 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1373 {
1374         struct e1000_hw *hw =
1375                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         uint32_t reg;
1377
1378         /* VLAN Mode Enable */
1379         reg = E1000_READ_REG(hw, E1000_CTRL);
1380         reg |= E1000_CTRL_VME;
1381         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1382
1383         /* Update maximum frame size */
1384         E1000_WRITE_REG(hw, E1000_RLPML,
1385                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1386
1387 }
1388
1389 static void
1390 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1391 {
1392         struct e1000_hw *hw =
1393                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394         uint32_t reg;
1395
1396         /* CTRL_EXT: Extended VLAN */
1397         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1398         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1399         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1400
1401 }
1402
1403 static void
1404 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1405 {
1406         struct e1000_hw *hw =
1407                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408         uint32_t reg;
1409
1410         /* CTRL_EXT: Extended VLAN */
1411         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1412         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1413         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1414 }
1415
1416 static void
1417 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1418 {
1419         if(mask & ETH_VLAN_STRIP_MASK){
1420                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1421                         igb_vlan_hw_strip_enable(dev);
1422                 else
1423                         igb_vlan_hw_strip_disable(dev);
1424         }
1425
1426         if(mask & ETH_VLAN_FILTER_MASK){
1427                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1428                         igb_vlan_hw_filter_enable(dev);
1429                 else
1430                         igb_vlan_hw_filter_disable(dev);
1431         }
1432
1433         if(mask & ETH_VLAN_EXTEND_MASK){
1434                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1435                         igb_vlan_hw_extend_enable(dev);
1436                 else
1437                         igb_vlan_hw_extend_disable(dev);
1438         }
1439 }
1440
1441
1442 /**
1443  * It enables the interrupt mask and then enable the interrupt.
1444  *
1445  * @param dev
1446  *  Pointer to struct rte_eth_dev.
1447  *
1448  * @return
1449  *  - On success, zero.
1450  *  - On failure, a negative value.
1451  */
1452 static int
1453 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1454 {
1455         struct e1000_interrupt *intr =
1456                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1457
1458         intr->mask |= E1000_ICR_LSC;
1459
1460         return 0;
1461 }
1462
1463 /*
1464  * It reads ICR and gets interrupt causes, check it and set a bit flag
1465  * to update link status.
1466  *
1467  * @param dev
1468  *  Pointer to struct rte_eth_dev.
1469  *
1470  * @return
1471  *  - On success, zero.
1472  *  - On failure, a negative value.
1473  */
1474 static int
1475 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1476 {
1477         uint32_t icr;
1478         struct e1000_hw *hw =
1479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480         struct e1000_interrupt *intr =
1481                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1482
1483         igb_intr_disable(hw);
1484
1485         /* read-on-clear nic registers here */
1486         icr = E1000_READ_REG(hw, E1000_ICR);
1487
1488         intr->flags = 0;
1489         if (icr & E1000_ICR_LSC) {
1490                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1491         }
1492
1493         return 0;
1494 }
1495
1496 /*
1497  * It executes link_update after knowing an interrupt is prsent.
1498  *
1499  * @param dev
1500  *  Pointer to struct rte_eth_dev.
1501  *
1502  * @return
1503  *  - On success, zero.
1504  *  - On failure, a negative value.
1505  */
1506 static int
1507 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1508 {
1509         struct e1000_hw *hw =
1510                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511         struct e1000_interrupt *intr =
1512                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1513         uint32_t tctl, rctl;
1514         struct rte_eth_link link;
1515         int ret;
1516
1517
1518         igb_intr_enable(dev);
1519         rte_intr_enable(&(dev->pci_dev->intr_handle));
1520
1521         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1522                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1523
1524                 /* set get_link_status to check register later */
1525                 hw->mac.get_link_status = 1;
1526                 ret = eth_igb_link_update(dev, 0);
1527
1528                 /* check if link has changed */
1529                 if (ret < 0)
1530                         return 0;
1531
1532                 memset(&link, 0, sizeof(link));
1533                 rte_igb_dev_atomic_read_link_status(dev, &link);
1534                 if (link.link_status) {
1535                         PMD_INIT_LOG(INFO,
1536                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1537                                 dev->data->port_id, (unsigned)link.link_speed,
1538                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1539                                         "full-duplex" : "half-duplex");
1540                 } else {
1541                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1542                                                 dev->data->port_id);
1543                 }
1544                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1545                                         dev->pci_dev->addr.domain,
1546                                         dev->pci_dev->addr.bus,
1547                                         dev->pci_dev->addr.devid,
1548                                         dev->pci_dev->addr.function);
1549                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1550                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1551                 if (link.link_status) {
1552                         /* enable Tx/Rx */
1553                         tctl |= E1000_TCTL_EN;
1554                         rctl |= E1000_RCTL_EN;
1555                 } else {
1556                         /* disable Tx/Rx */
1557                         tctl &= ~E1000_TCTL_EN;
1558                         rctl &= ~E1000_RCTL_EN;
1559                 }
1560                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1561                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1562                 E1000_WRITE_FLUSH(hw);
1563                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1564         }
1565
1566         return 0;
1567 }
1568
1569 /**
1570  * Interrupt handler which shall be registered at first.
1571  *
1572  * @param handle
1573  *  Pointer to interrupt handle.
1574  * @param param
1575  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1576  *
1577  * @return
1578  *  void
1579  */
1580 static void
1581 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1582                                                         void *param)
1583 {
1584         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1585
1586         eth_igb_interrupt_get_status(dev);
1587         eth_igb_interrupt_action(dev);
1588 }
1589
1590 static int
1591 eth_igb_led_on(struct rte_eth_dev *dev)
1592 {
1593         struct e1000_hw *hw;
1594
1595         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1597 }
1598
1599 static int
1600 eth_igb_led_off(struct rte_eth_dev *dev)
1601 {
1602         struct e1000_hw *hw;
1603
1604         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1606 }
1607
1608 static int
1609 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1610 {
1611         struct e1000_hw *hw;
1612         int err;
1613         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1614                 e1000_fc_none,
1615                 e1000_fc_rx_pause,
1616                 e1000_fc_tx_pause,
1617                 e1000_fc_full
1618         };
1619         uint32_t rx_buf_size;
1620         uint32_t max_high_water;
1621
1622         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         rx_buf_size = igb_get_rx_buffer_size(hw);
1624         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1625
1626         /* At least reserve one Ethernet frame for watermark */
1627         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1628         if ((fc_conf->high_water > max_high_water) ||
1629                 (fc_conf->high_water < fc_conf->low_water)) {
1630                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1631                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1632                 return (-EINVAL);
1633         }
1634
1635         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1636         hw->fc.pause_time     = fc_conf->pause_time;
1637         hw->fc.high_water     = fc_conf->high_water;
1638         hw->fc.low_water      = fc_conf->low_water;
1639         hw->fc.send_xon       = fc_conf->send_xon;
1640
1641         err = e1000_setup_link_generic(hw);
1642         if (err == E1000_SUCCESS) {
1643                 return 0;
1644         }
1645
1646         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1647         return (-EIO);
1648 }
1649
1650 static void
1651 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1652                 uint32_t index, __rte_unused uint32_t pool)
1653 {
1654         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655
1656         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1657 }
1658
1659 static void
1660 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1661 {
1662         uint8_t addr[ETHER_ADDR_LEN];
1663         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664
1665         memset(addr, 0, sizeof(addr));
1666
1667         e1000_rar_set(hw, addr, index);
1668 }
1669
1670 /*
1671  * Virtual Function operations
1672  */
1673 static void
1674 igbvf_intr_disable(struct e1000_hw *hw)
1675 {
1676         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1677
1678         /* Clear interrupt mask to stop from interrupts being generated */
1679         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1680
1681         E1000_WRITE_FLUSH(hw);
1682 }
1683
1684 static void
1685 igbvf_stop_adapter(struct rte_eth_dev *dev)
1686 {
1687         u32 reg_val;
1688         u16 i;
1689         struct rte_eth_dev_info dev_info;
1690         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691
1692         memset(&dev_info, 0, sizeof(dev_info));
1693         eth_igb_infos_get(dev, &dev_info);
1694
1695         /* Clear interrupt mask to stop from interrupts being generated */
1696         igbvf_intr_disable(hw);
1697
1698         /* Clear any pending interrupts, flush previous writes */
1699         E1000_READ_REG(hw, E1000_EICR);
1700
1701         /* Disable the transmit unit.  Each queue must be disabled. */
1702         for (i = 0; i < dev_info.max_tx_queues; i++)
1703                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1704
1705         /* Disable the receive unit by stopping each queue */
1706         for (i = 0; i < dev_info.max_rx_queues; i++) {
1707                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1708                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1709                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1710                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1711                         ;
1712         }
1713
1714         /* flush all queues disables */
1715         E1000_WRITE_FLUSH(hw);
1716         msec_delay(2);
1717 }
1718
1719 static int eth_igbvf_link_update(struct e1000_hw *hw)
1720 {
1721         struct e1000_mbx_info *mbx = &hw->mbx;
1722         struct e1000_mac_info *mac = &hw->mac;
1723         int ret_val = E1000_SUCCESS;
1724
1725         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1726
1727         /*
1728          * We only want to run this if there has been a rst asserted.
1729          * in this case that could mean a link change, device reset,
1730          * or a virtual function reset
1731          */
1732
1733         /* If we were hit with a reset or timeout drop the link */
1734         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1735                 mac->get_link_status = TRUE;
1736
1737         if (!mac->get_link_status)
1738                 goto out;
1739
1740         /* if link status is down no point in checking to see if pf is up */
1741         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1742                 goto out;
1743
1744         /* if we passed all the tests above then the link is up and we no
1745          * longer need to check for link */
1746         mac->get_link_status = FALSE;
1747
1748 out:
1749         return ret_val;
1750 }
1751
1752
1753 static int
1754 igbvf_dev_configure(struct rte_eth_dev *dev)
1755 {
1756         struct rte_eth_conf* conf = &dev->data->dev_conf;
1757
1758         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1759                 dev->data->port_id);
1760
1761         /*
1762          * VF has no ability to enable/disable HW CRC
1763          * Keep the persistent behavior the same as Host PF
1764          */
1765 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1766         if (!conf->rxmode.hw_strip_crc) {
1767                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1768                 conf->rxmode.hw_strip_crc = 1;
1769         }
1770 #else
1771         if (conf->rxmode.hw_strip_crc) {
1772                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1773                 conf->rxmode.hw_strip_crc = 0;
1774         }
1775 #endif
1776
1777         return 0;
1778 }
1779
1780 static int
1781 igbvf_dev_start(struct rte_eth_dev *dev)
1782 {
1783         struct e1000_hw *hw =
1784                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1785         int ret;
1786
1787         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1788
1789         hw->mac.ops.reset_hw(hw);
1790
1791         /* Set all vfta */
1792         igbvf_set_vfta_all(dev,1);
1793
1794         eth_igbvf_tx_init(dev);
1795
1796         /* This can fail when allocating mbufs for descriptor rings */
1797         ret = eth_igbvf_rx_init(dev);
1798         if (ret) {
1799                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1800                 igb_dev_clear_queues(dev);
1801                 return ret;
1802         }
1803
1804         return 0;
1805 }
1806
1807 static void
1808 igbvf_dev_stop(struct rte_eth_dev *dev)
1809 {
1810         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1811
1812         igbvf_stop_adapter(dev);
1813
1814         /*
1815           * Clear what we set, but we still keep shadow_vfta to
1816           * restore after device starts
1817           */
1818         igbvf_set_vfta_all(dev,0);
1819
1820         igb_dev_clear_queues(dev);
1821 }
1822
1823 static void
1824 igbvf_dev_close(struct rte_eth_dev *dev)
1825 {
1826         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827
1828         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1829
1830         e1000_reset_hw(hw);
1831
1832         igbvf_dev_stop(dev);
1833 }
1834
1835 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1836 {
1837         struct e1000_mbx_info *mbx = &hw->mbx;
1838         uint32_t msgbuf[2];
1839
1840         /* After set vlan, vlan strip will also be enabled in igb driver*/
1841         msgbuf[0] = E1000_VF_SET_VLAN;
1842         msgbuf[1] = vid;
1843         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1844         if (on)
1845                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1846
1847         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1848 }
1849
1850 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1851 {
1852         struct e1000_hw *hw =
1853                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         struct e1000_vfta * shadow_vfta =
1855                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1856         int i = 0, j = 0, vfta = 0, mask = 1;
1857
1858         for (i = 0; i < IGB_VFTA_SIZE; i++){
1859                 vfta = shadow_vfta->vfta[i];
1860                 if(vfta){
1861                         mask = 1;
1862                         for (j = 0; j < 32; j++){
1863                                 if(vfta & mask)
1864                                         igbvf_set_vfta(hw,
1865                                                 (uint16_t)((i<<5)+j), on);
1866                                 mask<<=1;
1867                         }
1868                 }
1869         }
1870
1871 }
1872
1873 static int
1874 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1875 {
1876         struct e1000_hw *hw =
1877                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1878         struct e1000_vfta * shadow_vfta =
1879                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1880         uint32_t vid_idx = 0;
1881         uint32_t vid_bit = 0;
1882         int ret = 0;
1883
1884         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1885
1886         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1887         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1888         if(ret){
1889                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1890                 return ret;
1891         }
1892         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1893         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1894
1895         /*Save what we set and retore it after device reset*/
1896         if (on)
1897                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1898         else
1899                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1900
1901         return 0;
1902 }
1903
1904 static int
1905 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
1906                                 struct rte_eth_rss_reta *reta_conf)
1907 {
1908         uint8_t i,j,mask;
1909         uint32_t reta;
1910         struct e1000_hw *hw =
1911                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912
1913         /*
1914          * Update Redirection Table RETA[n],n=0...31,The redirection table has
1915          * 128-entries in 32 registers
1916          */
1917         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1918                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
1919                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1920                 else
1921                         mask = (uint8_t)((reta_conf->mask_hi >>
1922                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
1923                 if (mask != 0) {
1924                         reta = 0;
1925                         /* If all 4 entries were set,don't need read RETA register */
1926                         if (mask != 0xF)
1927                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
1928
1929                         for (j = 0; j < 4; j++) {
1930                                 if (mask & (0x1 << j)) {
1931                                         if (mask != 0xF)
1932                                                 reta &= ~(0xFF << 8 * j);
1933                                         reta |= reta_conf->reta[i + j] << 8 * j;
1934                                 }
1935                         }
1936                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
1937                 }
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int
1944 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
1945                                 struct rte_eth_rss_reta *reta_conf)
1946 {
1947         uint8_t i,j,mask;
1948         uint32_t reta;
1949         struct e1000_hw *hw =
1950                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951
1952         /*
1953          * Read Redirection Table RETA[n],n=0...31,The redirection table has
1954          * 128-entries in 32 registers
1955          */
1956         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1957                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
1958                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1959                 else
1960                         mask = (uint8_t)((reta_conf->mask_hi >>
1961                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
1962
1963                 if (mask != 0) {
1964                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
1965                         for (j = 0; j < 4; j++) {
1966                                 if (mask & (0x1 << j))
1967                                         reta_conf->reta[i + j] =
1968                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
1969                         }
1970                 }
1971         }
1972
1973         return 0;
1974 }