4 * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_interrupts.h>
45 #include <rte_debug.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_memcpy.h>
50 #include <rte_malloc.h>
51 #include <rte_random.h>
53 #include "e1000/e1000_defines.h"
54 #include "e1000/e1000_regs.h"
55 #include "e1000/e1000_hw.h"
56 #include "e1000_ethdev.h"
59 void eth_random_addr(uint8_t *addr)
61 uint64_t rand = rte_rand();
62 uint8_t *p = (uint8_t*)&rand;
64 rte_memcpy(addr, p, ETHER_ADDR_LEN);
65 addr[0] &= 0xfe; /* clear multicast bit */
66 addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
69 static inline uint16_t
70 dev_num_vf(struct rte_eth_dev *eth_dev)
72 return eth_dev->pci_dev->max_vfs;
76 int igb_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
78 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
79 struct e1000_vf_info *vfinfo =
80 *E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
83 for (vfn = 0; vfn < vf_num; vfn++) {
84 eth_random_addr(vf_mac_addr);
85 /* keep the random address as default */
86 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
94 igb_mb_intr_setup(struct rte_eth_dev *dev)
96 struct e1000_interrupt *intr =
97 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
99 intr->mask |= E1000_ICR_VMMB;
104 void igb_pf_host_init(struct rte_eth_dev *eth_dev)
106 struct e1000_vf_info **vfinfo =
107 E1000_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
108 struct e1000_hw *hw =
109 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
113 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
114 if (0 == (vf_num = dev_num_vf(eth_dev)))
117 if (hw->mac.type == e1000_i350)
119 else if(hw->mac.type == e1000_82576)
120 /* per datasheet, it should be 2, but 1 seems correct */
125 *vfinfo = rte_zmalloc("vf_info", sizeof(struct e1000_vf_info) * vf_num, 0);
127 rte_panic("Cannot allocate memory for private VF data\n");
129 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_8_POOLS;
130 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
131 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
132 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
134 igb_vf_perm_addr_gen(eth_dev, vf_num);
136 /* set mb interrupt mask */
137 igb_mb_intr_setup(eth_dev);
142 #define E1000_RAH_POOLSEL_SHIFT (18)
143 int igb_pf_host_configure(struct rte_eth_dev *eth_dev)
147 struct e1000_hw *hw =
148 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
153 if (0 == (vf_num = dev_num_vf(eth_dev)))
156 /* enable VMDq and set the default pool for PF */
157 vtctl = E1000_READ_REG(hw, E1000_VT_CTL);
158 vtctl &= ~E1000_VT_CTL_DEFAULT_POOL_MASK;
159 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
160 << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
161 vtctl |= E1000_VT_CTL_VM_REPL_EN;
162 E1000_WRITE_REG(hw, E1000_VT_CTL, vtctl);
164 /* Enable pools reserved to PF only */
165 E1000_WRITE_REG(hw, E1000_VFRE, (~0) << vf_num);
166 E1000_WRITE_REG(hw, E1000_VFTE, (~0) << vf_num);
168 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
169 if (hw->mac.type == e1000_i350)
170 E1000_WRITE_REG(hw, E1000_TXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
172 E1000_WRITE_REG(hw, E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
174 /* clear VMDq map to perment rar 0 */
175 rah = E1000_READ_REG(hw, E1000_RAH(0));
176 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
177 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
179 /* clear VMDq map to scan rar 32 */
180 rah = E1000_READ_REG(hw, E1000_RAH(hw->mac.rar_entry_count));
181 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
182 E1000_WRITE_REG(hw, E1000_RAH(hw->mac.rar_entry_count), rah);
184 /* set VMDq map to default PF pool */
185 rah = E1000_READ_REG(hw, E1000_RAH(0));
186 rah |= (0x1 << (RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx +
187 E1000_RAH_POOLSEL_SHIFT));
188 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
191 * enable vlan filtering and allow all vlan tags through
193 vlanctrl = E1000_READ_REG(hw, E1000_RCTL);
194 vlanctrl |= E1000_RCTL_VFE ; /* enable vlan filters */
195 E1000_WRITE_REG(hw, E1000_RCTL, vlanctrl);
197 /* VFTA - enable all vlan filters */
198 for (i = 0; i < IGB_VFTA_SIZE; i++) {
199 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, 0xFFFFFFFF);
202 /* Enable/Disable MAC Anti-Spoofing */
203 e1000_vmdq_set_anti_spoofing_pf(hw, FALSE, vf_num);
209 set_rx_mode(struct rte_eth_dev *dev)
211 struct rte_eth_dev_data *dev_data =
212 (struct rte_eth_dev_data*)dev->data->dev_private;
213 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
214 uint32_t fctrl, vmolr = E1000_VMOLR_BAM | E1000_VMOLR_AUPE;
215 uint16_t vfn = dev_num_vf(dev);
217 /* Check for Promiscuous and All Multicast modes */
218 fctrl = E1000_READ_REG(hw, E1000_RCTL);
220 /* set all bits that we expect to always be set */
221 fctrl &= ~E1000_RCTL_SBP; /* disable store-bad-packets */
222 fctrl |= E1000_RCTL_BAM;;
224 /* clear the bits we are changing the status of */
225 fctrl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
227 if (dev_data->promiscuous) {
228 fctrl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
229 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
231 if (dev_data->all_multicast) {
232 fctrl |= E1000_RCTL_MPE;
233 vmolr |= E1000_VMOLR_MPME;
235 vmolr |= E1000_VMOLR_ROMPE;
239 if ((hw->mac.type == e1000_82576) ||
240 (hw->mac.type == e1000_i350)) {
241 vmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) &
242 ~(E1000_VMOLR_MPME | E1000_VMOLR_ROMPE |
244 E1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);
247 E1000_WRITE_REG(hw, E1000_RCTL, fctrl);
251 igb_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
253 struct e1000_hw *hw =
254 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
255 struct e1000_vf_info *vfinfo =
256 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
257 uint32_t vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));
259 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE |
260 E1000_VMOLR_BAM | E1000_VMOLR_AUPE);
261 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);
263 E1000_WRITE_REG(hw, E1000_VMVIR(vf), 0);
265 /* reset multicast table array for vf */
266 vfinfo[vf].num_vf_mc_hashes = 0;
273 igb_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
275 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
278 /* enable transmit and receive for vf */
279 reg = E1000_READ_REG(hw, E1000_VFTE);
280 reg |= (reg | (1 << vf));
281 E1000_WRITE_REG(hw, E1000_VFTE, reg);
283 reg = E1000_READ_REG(hw, E1000_VFRE);
284 reg |= (reg | (1 << vf));
285 E1000_WRITE_REG(hw, E1000_VFRE, reg);
287 igb_vf_reset_event(dev, vf);
291 igb_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
293 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
294 struct e1000_vf_info *vfinfo =
295 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
296 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
297 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
298 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
301 igb_vf_reset_msg(dev, vf);
303 hw->mac.ops.rar_set(hw, vf_mac, rar_entry);
304 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry));
305 rah |= (0x1 << (vf + E1000_RAH_POOLSEL_SHIFT));
306 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);
308 /* reply to reset with ack and vf mac address */
309 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
310 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
311 e1000_write_mbx(hw, msgbuf, 3, vf);
317 igb_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
319 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
320 struct e1000_vf_info *vfinfo =
321 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
322 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
323 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
325 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
326 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
327 hw->mac.ops.rar_set(hw, new_mac, rar_entry);
334 igb_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
340 int entries = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >>
341 E1000_VT_MSGINFO_SHIFT;
342 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
343 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
344 struct e1000_vf_info *vfinfo =
345 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
347 /* only so many hash values supported */
348 entries = RTE_MIN(entries, E1000_MAX_VF_MC_ENTRIES);
351 * salt away the number of multi cast addresses assigned
352 * to this VF for later use to restore when the PF multi cast
355 vfinfo->num_vf_mc_hashes = (uint16_t)entries;
358 * VFs are limited to using the MTA hash table for their multicast
361 for (i = 0; i < entries; i++) {
362 vfinfo->vf_mc_hashes[i] = hash_list[i];
365 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
366 vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F;
367 vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F;
368 mta_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, vector_reg);
369 mta_reg |= (1 << vector_bit);
370 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, vector_reg, mta_reg);
377 igb_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
380 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
381 struct e1000_vf_info *vfinfo =
382 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
383 uint32_t vid_idx, vid_bit, vfta;
385 add = (msgbuf[0] & E1000_VT_MSGINFO_MASK)
386 >> E1000_VT_MSGINFO_SHIFT;
387 vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
390 vfinfo[vf].vlan_count++;
391 else if (vfinfo[vf].vlan_count)
392 vfinfo[vf].vlan_count--;
394 vid_idx = (uint32_t)((vid >> E1000_VFTA_ENTRY_SHIFT) &
395 E1000_VFTA_ENTRY_MASK);
396 vid_bit = (uint32_t)(1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
397 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
403 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
404 E1000_WRITE_FLUSH(hw);
410 igb_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
412 uint16_t mbx_size = E1000_VFMAILBOX_SIZE;
413 uint32_t msgbuf[E1000_VFMAILBOX_SIZE];
415 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
417 retval = e1000_read_mbx(hw, msgbuf, mbx_size, vf);
419 RTE_LOG(ERR, PMD, "Error mbx recv msg from VF %d\n", vf);
423 /* do nothing with the message already processed */
424 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
427 /* flush the ack before we write any messages back */
428 E1000_WRITE_FLUSH(hw);
430 /* perform VF reset */
431 if (msgbuf[0] == E1000_VF_RESET) {
432 return igb_vf_reset(dev, vf, msgbuf);
435 /* check & process VF to PF mailbox message */
436 switch ((msgbuf[0] & 0xFFFF)) {
437 case E1000_VF_SET_MAC_ADDR:
438 retval = igb_vf_set_mac_addr(dev, vf, msgbuf);
440 case E1000_VF_SET_MULTICAST:
441 retval = igb_vf_set_multicast(dev, vf, msgbuf);
443 case E1000_VF_SET_VLAN:
444 retval = igb_vf_set_vlan(dev, vf, msgbuf);
447 RTE_LOG(DEBUG, PMD, "Unhandled Msg %8.8x\n", (unsigned) msgbuf[0]);
448 retval = E1000_ERR_MBX;
452 /* response the VF according to the message process result */
454 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
456 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
458 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
460 e1000_write_mbx(hw, msgbuf, 1, vf);
466 igb_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
468 uint32_t msg = E1000_VT_MSGTYPE_NACK;
469 struct e1000_hw *hw =
470 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
472 e1000_write_mbx(hw, &msg, 1, vf);
475 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev)
478 struct e1000_hw *hw =
479 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
481 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
482 /* check & process vf function level reset */
483 if (!e1000_check_for_rst(hw, vf))
484 igb_vf_reset_event(eth_dev, vf);
486 /* check & process vf mailbox messages */
487 if (!e1000_check_for_msg(hw, vf))
488 igb_rcv_msg_from_vf(eth_dev, vf);
490 /* check & process acks from vf */
491 if (!e1000_check_for_ack(hw, vf))
492 igb_rcv_ack_from_vf(eth_dev, vf);