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35 #include <sys/queue.h>
46 #include <rte_interrupts.h>
47 #include <rte_byteorder.h>
48 #include <rte_common.h>
50 #include <rte_debug.h>
52 #include <rte_memory.h>
53 #include <rte_memcpy.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
56 #include <rte_tailq.h>
58 #include <rte_per_lcore.h>
59 #include <rte_lcore.h>
60 #include <rte_atomic.h>
61 #include <rte_branch_prediction.h>
63 #include <rte_mempool.h>
64 #include <rte_malloc.h>
66 #include <rte_ether.h>
67 #include <rte_ethdev.h>
68 #include <rte_prefetch.h>
72 #include <rte_string_fns.h>
74 #include "e1000_logs.h"
75 #include "e1000/e1000_api.h"
76 #include "e1000_ethdev.h"
78 static inline struct rte_mbuf *
79 rte_rxmbuf_alloc(struct rte_mempool *mp)
83 m = __rte_mbuf_raw_alloc(mp);
84 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
88 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
89 (uint64_t) ((mb)->buf_physaddr + \
90 (uint64_t) ((char *)((mb)->pkt.data) - \
91 (char *)(mb)->buf_addr))
93 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
94 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
97 * Structure associated with each descriptor of the RX ring of a RX queue.
100 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
104 * Structure associated with each descriptor of the TX ring of a TX queue.
106 struct igb_tx_entry {
107 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
108 uint16_t next_id; /**< Index of next descriptor in ring. */
109 uint16_t last_id; /**< Index of last scattered descriptor. */
113 * Structure associated with each RX queue.
115 struct igb_rx_queue {
116 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
117 volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
118 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
119 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
120 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
121 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
122 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
123 uint16_t nb_rx_desc; /**< number of RX descriptors. */
124 uint16_t rx_tail; /**< current value of RDT register. */
125 uint16_t nb_rx_hold; /**< number of held free RX desc. */
126 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
127 uint16_t queue_id; /**< RX queue index. */
128 uint8_t port_id; /**< Device port identifier. */
129 uint8_t pthresh; /**< Prefetch threshold register. */
130 uint8_t hthresh; /**< Host threshold register. */
131 uint8_t wthresh; /**< Write-back threshold register. */
132 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
133 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
137 * Hardware context number
139 enum igb_advctx_num {
140 IGB_CTX_0 = 0, /**< CTX0 */
141 IGB_CTX_1 = 1, /**< CTX1 */
142 IGB_CTX_NUM = 2, /**< CTX_NUM */
146 * Strucutre to check if new context need be built
148 struct igb_advctx_info {
149 uint16_t flags; /**< ol_flags related to context build. */
150 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
151 union rte_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */
155 * Structure associated with each TX queue.
157 struct igb_tx_queue {
158 volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
159 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
160 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
161 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
162 uint32_t txd_type; /**< Device-specific TXD type */
163 uint16_t nb_tx_desc; /**< number of TX descriptors. */
164 uint16_t tx_tail; /**< Current value of TDT register. */
166 /**< Index of first used TX descriptor. */
167 uint16_t queue_id; /**< TX queue index. */
168 uint8_t port_id; /**< Device port identifier. */
169 uint8_t pthresh; /**< Prefetch threshold register. */
170 uint8_t hthresh; /**< Host threshold register. */
171 uint8_t wthresh; /**< Write-back threshold register. */
173 /**< Current used hardware descriptor. */
175 /**< Start context position for transmit queue. */
176 struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
177 /**< Hardware context history.*/
181 #define RTE_PMD_USE_PREFETCH
184 #ifdef RTE_PMD_USE_PREFETCH
185 #define rte_igb_prefetch(p) rte_prefetch0(p)
187 #define rte_igb_prefetch(p) do {} while(0)
190 #ifdef RTE_PMD_PACKET_PREFETCH
191 #define rte_packet_prefetch(p) rte_prefetch1(p)
193 #define rte_packet_prefetch(p) do {} while(0)
196 /*********************************************************************
200 **********************************************************************/
203 * Advanced context descriptor are almost same between igb/ixgbe
204 * This is a separate function, looking for optimization opportunity here
205 * Rework required to go with the pre-defined values.
209 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
210 volatile struct e1000_adv_tx_context_desc *ctx_txd,
211 uint16_t ol_flags, uint32_t vlan_macip_lens)
213 uint32_t type_tucmd_mlhl;
214 uint32_t mss_l4len_idx;
215 uint32_t ctx_idx, ctx_curr;
218 ctx_curr = txq->ctx_curr;
219 ctx_idx = ctx_curr + txq->ctx_start;
224 if (ol_flags & PKT_TX_VLAN_PKT) {
225 cmp_mask |= TX_VLAN_CMP_MASK;
228 if (ol_flags & PKT_TX_IP_CKSUM) {
229 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
230 cmp_mask |= TX_MAC_LEN_CMP_MASK;
233 /* Specify which HW CTX to upload. */
234 mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
235 switch (ol_flags & PKT_TX_L4_MASK) {
236 case PKT_TX_UDP_CKSUM:
237 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
238 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
239 mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
240 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
242 case PKT_TX_TCP_CKSUM:
243 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
244 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
245 mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
246 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
248 case PKT_TX_SCTP_CKSUM:
249 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
250 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
251 mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
252 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
255 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
256 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
260 txq->ctx_cache[ctx_curr].flags = ol_flags;
261 txq->ctx_cache[ctx_curr].cmp_mask = cmp_mask;
262 txq->ctx_cache[ctx_curr].vlan_macip_lens.data =
263 vlan_macip_lens & cmp_mask;
265 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
266 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
267 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
268 ctx_txd->seqnum_seed = 0;
272 * Check which hardware context can be used. Use the existing match
273 * or create a new context descriptor.
275 static inline uint32_t
276 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
277 uint32_t vlan_macip_lens)
279 /* If match with the current context */
280 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
281 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
282 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
283 return txq->ctx_curr;
286 /* If match with the second context */
288 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
289 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
290 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
291 return txq->ctx_curr;
294 /* Mismatch, use the previous context */
295 return (IGB_CTX_NUM);
298 static inline uint32_t
299 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
301 static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
302 static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
305 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
306 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
310 static inline uint32_t
311 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
313 static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
314 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
318 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
321 struct igb_tx_queue *txq;
322 struct igb_tx_entry *sw_ring;
323 struct igb_tx_entry *txe, *txn;
324 volatile union e1000_adv_tx_desc *txr;
325 volatile union e1000_adv_tx_desc *txd;
326 struct rte_mbuf *tx_pkt;
327 struct rte_mbuf *m_seg;
328 uint64_t buf_dma_addr;
329 uint32_t olinfo_status;
330 uint32_t cmd_type_len;
339 uint32_t new_ctx = 0;
341 uint32_t vlan_macip_lens;
344 sw_ring = txq->sw_ring;
346 tx_id = txq->tx_tail;
347 txe = &sw_ring[tx_id];
349 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
351 pkt_len = tx_pkt->pkt.pkt_len;
353 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
356 * The number of descriptors that must be allocated for a
357 * packet is the number of segments of that packet, plus 1
358 * Context Descriptor for the VLAN Tag Identifier, if any.
359 * Determine the last TX descriptor to allocate in the TX ring
360 * for the packet, starting from the current position (tx_id)
363 tx_last = (uint16_t) (tx_id + tx_pkt->pkt.nb_segs - 1);
365 ol_flags = tx_pkt->ol_flags;
366 vlan_macip_lens = tx_pkt->pkt.vlan_macip.data;
367 tx_ol_req = (ol_flags & PKT_TX_OFFLOAD_MASK);
369 /* If a Context Descriptor need be built . */
371 ctx = what_advctx_update(txq, tx_ol_req,
373 /* Only allocate context descriptor if required*/
374 new_ctx = (ctx == IGB_CTX_NUM);
376 tx_last = (uint16_t) (tx_last + new_ctx);
378 if (tx_last >= txq->nb_tx_desc)
379 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
381 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
382 " tx_first=%u tx_last=%u\n",
383 (unsigned) txq->port_id,
384 (unsigned) txq->queue_id,
390 * Check if there are enough free descriptors in the TX ring
391 * to transmit the next packet.
392 * This operation is based on the two following rules:
394 * 1- Only check that the last needed TX descriptor can be
395 * allocated (by construction, if that descriptor is free,
396 * all intermediate ones are also free).
398 * For this purpose, the index of the last TX descriptor
399 * used for a packet (the "last descriptor" of a packet)
400 * is recorded in the TX entries (the last one included)
401 * that are associated with all TX descriptors allocated
404 * 2- Avoid to allocate the last free TX descriptor of the
405 * ring, in order to never set the TDT register with the
406 * same value stored in parallel by the NIC in the TDH
407 * register, which makes the TX engine of the NIC enter
408 * in a deadlock situation.
410 * By extension, avoid to allocate a free descriptor that
411 * belongs to the last set of free descriptors allocated
412 * to the same packet previously transmitted.
416 * The "last descriptor" of the previously sent packet, if any,
417 * which used the last descriptor to allocate.
419 tx_end = sw_ring[tx_last].last_id;
422 * The next descriptor following that "last descriptor" in the
425 tx_end = sw_ring[tx_end].next_id;
428 * The "last descriptor" associated with that next descriptor.
430 tx_end = sw_ring[tx_end].last_id;
433 * Check that this descriptor is free.
435 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
442 * Set common flags of all TX Data Descriptors.
444 * The following bits must be set in all Data Descriptors:
445 * - E1000_ADVTXD_DTYP_DATA
446 * - E1000_ADVTXD_DCMD_DEXT
448 * The following bits must be set in the first Data Descriptor
449 * and are ignored in the other ones:
450 * - E1000_ADVTXD_DCMD_IFCS
451 * - E1000_ADVTXD_MAC_1588
452 * - E1000_ADVTXD_DCMD_VLE
454 * The following bits must only be set in the last Data
456 * - E1000_TXD_CMD_EOP
458 * The following bits can be set in any Data Descriptor, but
459 * are only set in the last Data Descriptor:
462 cmd_type_len = txq->txd_type |
463 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
464 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
465 #if defined(RTE_LIBRTE_IEEE1588)
466 if (ol_flags & PKT_TX_IEEE1588_TMST)
467 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
470 /* Setup TX Advanced context descriptor if required */
472 volatile struct e1000_adv_tx_context_desc *
475 ctx_txd = (volatile struct
476 e1000_adv_tx_context_desc *)
479 txn = &sw_ring[txe->next_id];
480 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
482 if (txe->mbuf != NULL) {
483 rte_pktmbuf_free_seg(txe->mbuf);
487 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
490 txe->last_id = tx_last;
491 tx_id = txe->next_id;
495 /* Setup the TX Advanced Data Descriptor */
496 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
497 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
498 olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
503 txn = &sw_ring[txe->next_id];
506 if (txe->mbuf != NULL)
507 rte_pktmbuf_free_seg(txe->mbuf);
511 * Set up transmit descriptor.
513 slen = (uint16_t) m_seg->pkt.data_len;
514 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
515 txd->read.buffer_addr =
516 rte_cpu_to_le_64(buf_dma_addr);
517 txd->read.cmd_type_len =
518 rte_cpu_to_le_32(cmd_type_len | slen);
519 txd->read.olinfo_status =
520 rte_cpu_to_le_32(olinfo_status);
521 txe->last_id = tx_last;
522 tx_id = txe->next_id;
524 m_seg = m_seg->pkt.next;
525 } while (m_seg != NULL);
528 * The last packet data descriptor needs End Of Packet (EOP)
529 * and Report Status (RS).
531 txd->read.cmd_type_len |=
532 rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
538 * Set the Transmit Descriptor Tail (TDT).
540 E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
541 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
542 (unsigned) txq->port_id, (unsigned) txq->queue_id,
543 (unsigned) tx_id, (unsigned) nb_tx);
544 txq->tx_tail = tx_id;
549 /*********************************************************************
553 **********************************************************************/
554 static inline uint16_t
555 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
559 static uint16_t ip_pkt_types_map[16] = {
560 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
561 PKT_RX_IPV6_HDR, 0, 0, 0,
562 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
563 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
566 #if defined(RTE_LIBRTE_IEEE1588)
567 static uint32_t ip_pkt_etqf_map[8] = {
568 0, 0, 0, PKT_RX_IEEE1588_PTP,
572 pkt_flags = (uint16_t) (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ?
573 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
574 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
576 pkt_flags = (uint16_t) (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ? 0 :
577 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
579 return pkt_flags | (uint16_t) (((hl_tp_rs & 0x0F) == 0) ? 0 :
583 static inline uint16_t
584 rx_desc_status_to_pkt_flags(uint32_t rx_status)
588 /* Check if VLAN present */
589 pkt_flags = (uint16_t) (rx_status & E1000_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
591 #if defined(RTE_LIBRTE_IEEE1588)
592 if (rx_status & E1000_RXD_STAT_TMST)
593 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
598 static inline uint16_t
599 rx_desc_error_to_pkt_flags(uint32_t rx_status)
602 * Bit 30: IPE, IPv4 checksum error
603 * Bit 29: L4I, L4I integrity error
606 static uint16_t error_to_pkt_flags_map[4] = {
607 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
608 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
610 return error_to_pkt_flags_map[(rx_status >>
611 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
615 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
618 struct igb_rx_queue *rxq;
619 volatile union e1000_adv_rx_desc *rx_ring;
620 volatile union e1000_adv_rx_desc *rxdp;
621 struct igb_rx_entry *sw_ring;
622 struct igb_rx_entry *rxe;
623 struct rte_mbuf *rxm;
624 struct rte_mbuf *nmb;
625 union e1000_adv_rx_desc rxd;
628 uint32_t hlen_type_rss;
638 rx_id = rxq->rx_tail;
639 rx_ring = rxq->rx_ring;
640 sw_ring = rxq->sw_ring;
641 while (nb_rx < nb_pkts) {
643 * The order of operations here is important as the DD status
644 * bit must not be read after any other descriptor fields.
645 * rx_ring and rxdp are pointing to volatile data so the order
646 * of accesses cannot be reordered by the compiler. If they were
647 * not volatile, they could be reordered which could lead to
648 * using invalid descriptor fields when read from rxd.
650 rxdp = &rx_ring[rx_id];
651 staterr = rxdp->wb.upper.status_error;
652 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
659 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
660 * likely to be invalid and to be dropped by the various
661 * validation checks performed by the network stack.
663 * Allocate a new mbuf to replenish the RX ring descriptor.
664 * If the allocation fails:
665 * - arrange for that RX descriptor to be the first one
666 * being parsed the next time the receive function is
667 * invoked [on the same queue].
669 * - Stop parsing the RX ring and return immediately.
671 * This policy do not drop the packet received in the RX
672 * descriptor for which the allocation of a new mbuf failed.
673 * Thus, it allows that packet to be later retrieved if
674 * mbuf have been freed in the mean time.
675 * As a side effect, holding RX descriptors instead of
676 * systematically giving them back to the NIC may lead to
677 * RX ring exhaustion situations.
678 * However, the NIC can gracefully prevent such situations
679 * to happen by sending specific "back-pressure" flow control
680 * frames to its peer(s).
682 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
683 "staterr=0x%x pkt_len=%u\n",
684 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
685 (unsigned) rx_id, (unsigned) staterr,
686 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
688 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
690 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
691 "queue_id=%u\n", (unsigned) rxq->port_id,
692 (unsigned) rxq->queue_id);
693 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
698 rxe = &sw_ring[rx_id];
700 if (rx_id == rxq->nb_rx_desc)
703 /* Prefetch next mbuf while processing current one. */
704 rte_igb_prefetch(sw_ring[rx_id].mbuf);
707 * When next RX descriptor is on a cache-line boundary,
708 * prefetch the next 4 RX descriptors and the next 8 pointers
711 if ((rx_id & 0x3) == 0) {
712 rte_igb_prefetch(&rx_ring[rx_id]);
713 rte_igb_prefetch(&sw_ring[rx_id]);
719 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
720 rxdp->read.hdr_addr = dma_addr;
721 rxdp->read.pkt_addr = dma_addr;
724 * Initialize the returned mbuf.
725 * 1) setup generic mbuf fields:
726 * - number of segments,
729 * - RX port identifier.
730 * 2) integrate hardware offload data, if any:
732 * - IP checksum flag,
733 * - VLAN TCI, if any,
736 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
738 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
739 rte_packet_prefetch(rxm->pkt.data);
740 rxm->pkt.nb_segs = 1;
741 rxm->pkt.next = NULL;
742 rxm->pkt.pkt_len = pkt_len;
743 rxm->pkt.data_len = pkt_len;
744 rxm->pkt.in_port = rxq->port_id;
746 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
747 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
748 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
749 rxm->pkt.vlan_macip.f.vlan_tci =
750 rte_le_to_cpu_16(rxd.wb.upper.vlan);
752 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
753 pkt_flags = (pkt_flags |
754 rx_desc_status_to_pkt_flags(staterr));
755 pkt_flags = (pkt_flags |
756 rx_desc_error_to_pkt_flags(staterr));
757 rxm->ol_flags = pkt_flags;
760 * Store the mbuf address into the next entry of the array
761 * of returned packets.
763 rx_pkts[nb_rx++] = rxm;
765 rxq->rx_tail = rx_id;
768 * If the number of free RX descriptors is greater than the RX free
769 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
771 * Update the RDT with the value of the last processed RX descriptor
772 * minus 1, to guarantee that the RDT register is never equal to the
773 * RDH register, which creates a "full" ring situtation from the
774 * hardware point of view...
776 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
777 if (nb_hold > rxq->rx_free_thresh) {
778 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
779 "nb_hold=%u nb_rx=%u\n",
780 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
781 (unsigned) rx_id, (unsigned) nb_hold,
783 rx_id = (uint16_t) ((rx_id == 0) ?
784 (rxq->nb_rx_desc - 1) : (rx_id - 1));
785 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
788 rxq->nb_rx_hold = nb_hold;
793 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
796 struct igb_rx_queue *rxq;
797 volatile union e1000_adv_rx_desc *rx_ring;
798 volatile union e1000_adv_rx_desc *rxdp;
799 struct igb_rx_entry *sw_ring;
800 struct igb_rx_entry *rxe;
801 struct rte_mbuf *first_seg;
802 struct rte_mbuf *last_seg;
803 struct rte_mbuf *rxm;
804 struct rte_mbuf *nmb;
805 union e1000_adv_rx_desc rxd;
806 uint64_t dma; /* Physical address of mbuf data buffer */
808 uint32_t hlen_type_rss;
818 rx_id = rxq->rx_tail;
819 rx_ring = rxq->rx_ring;
820 sw_ring = rxq->sw_ring;
823 * Retrieve RX context of current packet, if any.
825 first_seg = rxq->pkt_first_seg;
826 last_seg = rxq->pkt_last_seg;
828 while (nb_rx < nb_pkts) {
831 * The order of operations here is important as the DD status
832 * bit must not be read after any other descriptor fields.
833 * rx_ring and rxdp are pointing to volatile data so the order
834 * of accesses cannot be reordered by the compiler. If they were
835 * not volatile, they could be reordered which could lead to
836 * using invalid descriptor fields when read from rxd.
838 rxdp = &rx_ring[rx_id];
839 staterr = rxdp->wb.upper.status_error;
840 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
847 * Allocate a new mbuf to replenish the RX ring descriptor.
848 * If the allocation fails:
849 * - arrange for that RX descriptor to be the first one
850 * being parsed the next time the receive function is
851 * invoked [on the same queue].
853 * - Stop parsing the RX ring and return immediately.
855 * This policy does not drop the packet received in the RX
856 * descriptor for which the allocation of a new mbuf failed.
857 * Thus, it allows that packet to be later retrieved if
858 * mbuf have been freed in the mean time.
859 * As a side effect, holding RX descriptors instead of
860 * systematically giving them back to the NIC may lead to
861 * RX ring exhaustion situations.
862 * However, the NIC can gracefully prevent such situations
863 * to happen by sending specific "back-pressure" flow control
864 * frames to its peer(s).
866 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
867 "staterr=0x%x data_len=%u\n",
868 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
869 (unsigned) rx_id, (unsigned) staterr,
870 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
872 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
874 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
875 "queue_id=%u\n", (unsigned) rxq->port_id,
876 (unsigned) rxq->queue_id);
877 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
882 rxe = &sw_ring[rx_id];
884 if (rx_id == rxq->nb_rx_desc)
887 /* Prefetch next mbuf while processing current one. */
888 rte_igb_prefetch(sw_ring[rx_id].mbuf);
891 * When next RX descriptor is on a cache-line boundary,
892 * prefetch the next 4 RX descriptors and the next 8 pointers
895 if ((rx_id & 0x3) == 0) {
896 rte_igb_prefetch(&rx_ring[rx_id]);
897 rte_igb_prefetch(&sw_ring[rx_id]);
901 * Update RX descriptor with the physical address of the new
902 * data buffer of the new allocated mbuf.
906 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
907 rxdp->read.pkt_addr = dma;
908 rxdp->read.hdr_addr = dma;
911 * Set data length & data buffer address of mbuf.
913 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
914 rxm->pkt.data_len = data_len;
915 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
918 * If this is the first buffer of the received packet,
919 * set the pointer to the first mbuf of the packet and
920 * initialize its context.
921 * Otherwise, update the total length and the number of segments
922 * of the current scattered packet, and update the pointer to
923 * the last mbuf of the current packet.
925 if (first_seg == NULL) {
927 first_seg->pkt.pkt_len = data_len;
928 first_seg->pkt.nb_segs = 1;
930 first_seg->pkt.pkt_len += data_len;
931 first_seg->pkt.nb_segs++;
932 last_seg->pkt.next = rxm;
936 * If this is not the last buffer of the received packet,
937 * update the pointer to the last mbuf of the current scattered
938 * packet and continue to parse the RX ring.
940 if (! (staterr & E1000_RXD_STAT_EOP)) {
946 * This is the last buffer of the received packet.
947 * If the CRC is not stripped by the hardware:
948 * - Subtract the CRC length from the total packet length.
949 * - If the last buffer only contains the whole CRC or a part
950 * of it, free the mbuf associated to the last buffer.
951 * If part of the CRC is also contained in the previous
952 * mbuf, subtract the length of that CRC part from the
953 * data length of the previous mbuf.
955 rxm->pkt.next = NULL;
956 if (unlikely(rxq->crc_len > 0)) {
957 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
958 if (data_len <= ETHER_CRC_LEN) {
959 rte_pktmbuf_free_seg(rxm);
960 first_seg->pkt.nb_segs--;
961 last_seg->pkt.data_len = (uint16_t)
962 (last_seg->pkt.data_len -
963 (ETHER_CRC_LEN - data_len));
964 last_seg->pkt.next = NULL;
967 (uint16_t) (data_len - ETHER_CRC_LEN);
971 * Initialize the first mbuf of the returned packet:
972 * - RX port identifier,
973 * - hardware offload data, if any:
975 * - IP checksum flag,
976 * - VLAN TCI, if any,
979 first_seg->pkt.in_port = rxq->port_id;
980 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
983 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
984 * set in the pkt_flags field.
986 first_seg->pkt.vlan_macip.f.vlan_tci =
987 rte_le_to_cpu_16(rxd.wb.upper.vlan);
988 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
989 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
990 pkt_flags = (pkt_flags | rx_desc_status_to_pkt_flags(staterr));
991 pkt_flags = (pkt_flags | rx_desc_error_to_pkt_flags(staterr));
992 first_seg->ol_flags = pkt_flags;
994 /* Prefetch data of first segment, if configured to do so. */
995 rte_packet_prefetch(first_seg->pkt.data);
998 * Store the mbuf address into the next entry of the array
999 * of returned packets.
1001 rx_pkts[nb_rx++] = first_seg;
1004 * Setup receipt context for a new packet.
1010 * Record index of the next RX descriptor to probe.
1012 rxq->rx_tail = rx_id;
1015 * Save receive context.
1017 rxq->pkt_first_seg = first_seg;
1018 rxq->pkt_last_seg = last_seg;
1021 * If the number of free RX descriptors is greater than the RX free
1022 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1024 * Update the RDT with the value of the last processed RX descriptor
1025 * minus 1, to guarantee that the RDT register is never equal to the
1026 * RDH register, which creates a "full" ring situtation from the
1027 * hardware point of view...
1029 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1030 if (nb_hold > rxq->rx_free_thresh) {
1031 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1032 "nb_hold=%u nb_rx=%u\n",
1033 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1034 (unsigned) rx_id, (unsigned) nb_hold,
1036 rx_id = (uint16_t) ((rx_id == 0) ?
1037 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1038 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1041 rxq->nb_rx_hold = nb_hold;
1046 * Rings setup and release.
1048 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1049 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
1050 * This will also optimize cache line size effect.
1051 * H/W supports up to cache line size 128.
1053 #define IGB_ALIGN 128
1056 * Maximum number of Ring Descriptors.
1058 * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1059 * desscriptors should meet the following condition:
1060 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1062 #define IGB_MIN_RING_DESC 32
1063 #define IGB_MAX_RING_DESC 4096
1065 static const struct rte_memzone *
1066 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1067 uint16_t queue_id, uint32_t ring_size, int socket_id)
1069 char z_name[RTE_MEMZONE_NAMESIZE];
1070 const struct rte_memzone *mz;
1072 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1073 dev->driver->pci_drv.name, ring_name,
1074 dev->data->port_id, queue_id);
1075 mz = rte_memzone_lookup(z_name);
1079 return rte_memzone_reserve_aligned(z_name, (uint64_t)ring_size,
1080 socket_id, 0, IGB_ALIGN);
1084 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1088 if (txq->sw_ring != NULL) {
1089 for (i = 0; i < txq->nb_tx_desc; i++) {
1090 if (txq->sw_ring[i].mbuf != NULL) {
1091 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1092 txq->sw_ring[i].mbuf = NULL;
1099 igb_tx_queue_release(struct igb_tx_queue *txq)
1102 igb_tx_queue_release_mbufs(txq);
1103 rte_free(txq->sw_ring);
1109 eth_igb_tx_queue_release(void *txq)
1111 igb_tx_queue_release(txq);
1115 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1120 memset((void*)&txq->ctx_cache, 0,
1121 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1125 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1127 struct igb_tx_entry *txe = txq->sw_ring;
1130 struct e1000_hw *hw;
1132 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1133 size = sizeof(union e1000_adv_tx_desc) * txq->nb_tx_desc;
1134 /* Zero out HW ring memory */
1135 for (i = 0; i < size; i++) {
1136 ((volatile char *)txq->tx_ring)[i] = 0;
1139 /* Initialize ring entries */
1140 prev = txq->nb_tx_desc - 1;
1141 for (i = 0; i < txq->nb_tx_desc; i++) {
1142 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1144 txd->wb.status = E1000_TXD_STAT_DD;
1147 txe[prev].next_id = i;
1151 txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1152 /* 82575 specific, each tx queue will use 2 hw contexts */
1153 if (hw->mac.type == e1000_82575)
1154 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1156 igb_reset_tx_queue_stat(txq);
1160 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1163 unsigned int socket_id,
1164 const struct rte_eth_txconf *tx_conf)
1166 const struct rte_memzone *tz;
1167 struct igb_tx_queue *txq;
1168 struct e1000_hw *hw;
1171 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1174 * Validate number of transmit descriptors.
1175 * It must not exceed hardware maximum, and must be multiple
1178 if (((nb_desc * sizeof(union e1000_adv_tx_desc)) % IGB_ALIGN) != 0 ||
1179 (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1184 * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1187 if (tx_conf->tx_free_thresh != 0)
1188 RTE_LOG(WARNING, PMD,
1189 "The tx_free_thresh parameter is not "
1190 "used for the 1G driver.\n");
1191 if (tx_conf->tx_rs_thresh != 0)
1192 RTE_LOG(WARNING, PMD,
1193 "The tx_rs_thresh parameter is not "
1194 "used for the 1G driver.\n");
1195 if (tx_conf->tx_thresh.wthresh == 0)
1196 RTE_LOG(WARNING, PMD,
1197 "To improve 1G driver performance, consider setting "
1198 "the TX WTHRESH value to 4, 8, or 16.\n");
1200 /* Free memory prior to re-allocation if needed */
1201 if (dev->data->tx_queues[queue_idx] != NULL)
1202 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1204 /* First allocate the tx queue data structure */
1205 txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1211 * Allocate TX ring hardware descriptors. A memzone large enough to
1212 * handle the maximum ring size is allocated in order to allow for
1213 * resizing in later calls to the queue setup function.
1215 size = sizeof(union e1000_adv_tx_desc) * IGB_MAX_RING_DESC;
1216 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1219 igb_tx_queue_release(txq);
1223 txq->nb_tx_desc = nb_desc;
1224 txq->pthresh = tx_conf->tx_thresh.pthresh;
1225 txq->hthresh = tx_conf->tx_thresh.hthresh;
1226 txq->wthresh = tx_conf->tx_thresh.wthresh;
1227 txq->queue_id = queue_idx;
1228 txq->port_id = dev->data->port_id;
1230 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
1231 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1232 txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1234 /* Allocate software ring */
1235 txq->sw_ring = rte_zmalloc("txq->sw_ring",
1236 sizeof(struct igb_tx_entry) * nb_desc,
1238 if (txq->sw_ring == NULL) {
1239 igb_tx_queue_release(txq);
1242 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1243 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1245 igb_reset_tx_queue(txq, dev);
1246 dev->tx_pkt_burst = eth_igb_xmit_pkts;
1247 dev->data->tx_queues[queue_idx] = txq;
1253 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1257 if (rxq->sw_ring != NULL) {
1258 for (i = 0; i < rxq->nb_rx_desc; i++) {
1259 if (rxq->sw_ring[i].mbuf != NULL) {
1260 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1261 rxq->sw_ring[i].mbuf = NULL;
1268 igb_rx_queue_release(struct igb_rx_queue *rxq)
1271 igb_rx_queue_release_mbufs(rxq);
1272 rte_free(rxq->sw_ring);
1278 eth_igb_rx_queue_release(void *rxq)
1280 igb_rx_queue_release(rxq);
1284 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1289 /* Zero out HW ring memory */
1290 size = sizeof(union e1000_adv_rx_desc) * rxq->nb_rx_desc;
1291 for (i = 0; i < size; i++) {
1292 ((volatile char *)rxq->rx_ring)[i] = 0;
1296 rxq->pkt_first_seg = NULL;
1297 rxq->pkt_last_seg = NULL;
1301 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1304 unsigned int socket_id,
1305 const struct rte_eth_rxconf *rx_conf,
1306 struct rte_mempool *mp)
1308 const struct rte_memzone *rz;
1309 struct igb_rx_queue *rxq;
1310 struct e1000_hw *hw;
1313 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 * Validate number of receive descriptors.
1317 * It must not exceed hardware maximum, and must be multiple
1320 if (((nb_desc * sizeof(union e1000_adv_rx_desc)) % IGB_ALIGN) != 0 ||
1321 (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1325 /* Free memory prior to re-allocation if needed */
1326 if (dev->data->rx_queues[queue_idx] != NULL) {
1327 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1328 dev->data->rx_queues[queue_idx] = NULL;
1331 /* First allocate the RX queue data structure. */
1332 rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1337 rxq->nb_rx_desc = nb_desc;
1338 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1339 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1340 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1341 rxq->drop_en = rx_conf->rx_drop_en;
1342 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1343 rxq->queue_id = queue_idx;
1344 rxq->port_id = dev->data->port_id;
1345 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1349 * Allocate RX ring hardware descriptors. A memzone large enough to
1350 * handle the maximum ring size is allocated in order to allow for
1351 * resizing in later calls to the queue setup function.
1353 size = sizeof(union e1000_adv_rx_desc) * IGB_MAX_RING_DESC;
1354 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx, size, socket_id);
1356 igb_rx_queue_release(rxq);
1359 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
1360 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1361 rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1363 /* Allocate software ring. */
1364 rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1365 sizeof(struct igb_rx_entry) * nb_desc,
1367 if (rxq->sw_ring == NULL) {
1368 igb_rx_queue_release(rxq);
1371 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1372 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1374 dev->data->rx_queues[queue_idx] = rxq;
1375 igb_reset_rx_queue(rxq);
1381 igb_dev_clear_queues(struct rte_eth_dev *dev)
1384 struct igb_tx_queue *txq;
1385 struct igb_rx_queue *rxq;
1387 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1388 txq = dev->data->tx_queues[i];
1390 igb_tx_queue_release_mbufs(txq);
1391 igb_reset_tx_queue(txq, dev);
1395 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1396 rxq = dev->data->rx_queues[i];
1398 igb_rx_queue_release_mbufs(rxq);
1399 igb_reset_rx_queue(rxq);
1405 * Receive Side Scaling (RSS).
1406 * See section 7.1.1.7 in the following document:
1407 * "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1410 * The source and destination IP addresses of the IP header and the source and
1411 * destination ports of TCP/UDP headers, if any, of received packets are hashed
1412 * against a configurable random key to compute a 32-bit RSS hash result.
1413 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1414 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
1415 * RSS output index which is used as the RX queue index where to store the
1417 * The following output is supplied in the RX write-back descriptor:
1418 * - 32-bit result of the Microsoft RSS hash function,
1419 * - 4-bit RSS type field.
1423 * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1424 * Used as the default key.
1426 static uint8_t rss_intel_key[40] = {
1427 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1428 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1429 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1430 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1431 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1435 igb_rss_disable(struct rte_eth_dev *dev)
1437 struct e1000_hw *hw;
1440 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441 mrqc = E1000_READ_REG(hw, E1000_MRQC);
1442 mrqc &= ~E1000_MRQC_ENABLE_MASK;
1443 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1447 igb_rss_configure(struct rte_eth_dev *dev)
1449 struct e1000_hw *hw;
1457 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
1460 if (rss_hf == 0) /* Disable RSS. */ {
1461 igb_rss_disable(dev);
1464 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
1465 if (hash_key == NULL)
1466 hash_key = rss_intel_key; /* Default hash key. */
1468 /* Fill in RSS hash key. */
1469 for (i = 0; i < 10; i++) {
1470 rss_key = hash_key[(i * 4)];
1471 rss_key |= hash_key[(i * 4) + 1] << 8;
1472 rss_key |= hash_key[(i * 4) + 2] << 16;
1473 rss_key |= hash_key[(i * 4) + 3] << 24;
1474 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1477 /* Fill in redirection table. */
1478 shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1479 for (i = 0; i < 128; i++) {
1486 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1487 i % dev->data->nb_rx_queues : 0);
1488 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1490 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1493 /* Set configured hashing functions in MRQC register. */
1494 mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1495 if (rss_hf & ETH_RSS_IPV4)
1496 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1497 if (rss_hf & ETH_RSS_IPV4_TCP)
1498 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1499 if (rss_hf & ETH_RSS_IPV6)
1500 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1501 if (rss_hf & ETH_RSS_IPV6_EX)
1502 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1503 if (rss_hf & ETH_RSS_IPV6_TCP)
1504 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1505 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1506 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1507 if (rss_hf & ETH_RSS_IPV4_UDP)
1508 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1509 if (rss_hf & ETH_RSS_IPV6_UDP)
1510 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1511 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1512 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1513 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1516 /*********************************************************************
1518 * Enable receive unit.
1520 **********************************************************************/
1523 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1525 struct igb_rx_entry *rxe = rxq->sw_ring;
1529 /* Initialize software ring entries. */
1530 for (i = 0; i < rxq->nb_rx_desc; i++) {
1531 volatile union e1000_adv_rx_desc *rxd;
1532 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1535 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1536 "queue_id=%hu\n", rxq->queue_id);
1537 igb_rx_queue_release(rxq);
1541 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
1542 rxd = &rxq->rx_ring[i];
1543 rxd->read.hdr_addr = dma_addr;
1544 rxd->read.pkt_addr = dma_addr;
1552 eth_igb_rx_init(struct rte_eth_dev *dev)
1554 struct e1000_hw *hw;
1555 struct igb_rx_queue *rxq;
1556 struct rte_pktmbuf_pool_private *mbp_priv;
1561 uint16_t rctl_bsize;
1565 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569 * Make sure receives are disabled while setting
1570 * up the descriptor ring.
1572 rctl = E1000_READ_REG(hw, E1000_RCTL);
1573 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1576 * Configure support of jumbo frames, if any.
1578 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1579 rctl |= E1000_RCTL_LPE;
1581 /* Set maximum packet length. */
1582 E1000_WRITE_REG(hw, E1000_RLPML,
1583 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1585 rctl &= ~E1000_RCTL_LPE;
1587 /* Configure and enable each RX queue. */
1589 dev->rx_pkt_burst = eth_igb_recv_pkts;
1590 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1594 rxq = dev->data->rx_queues[i];
1596 /* Allocate buffers for descriptor rings and set up queue */
1597 ret = igb_alloc_rx_queue_mbufs(rxq);
1602 * Reset crc_len in case it was changed after queue setup by a
1606 (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1609 bus_addr = rxq->rx_ring_phys_addr;
1610 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1612 sizeof(union e1000_adv_rx_desc));
1613 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1614 (uint32_t)(bus_addr >> 32));
1615 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1617 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1620 * Configure RX buffer size.
1622 mbp_priv = (struct rte_pktmbuf_pool_private *)
1623 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
1624 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
1625 RTE_PKTMBUF_HEADROOM);
1626 if (buf_size >= 1024) {
1628 * Configure the BSIZEPACKET field of the SRRCTL
1629 * register of the queue.
1630 * Value is in 1 KB resolution, from 1 KB to 127 KB.
1631 * If this field is equal to 0b, then RCTL.BSIZE
1632 * determines the RX packet buffer size.
1634 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
1635 E1000_SRRCTL_BSIZEPKT_MASK);
1636 buf_size = (uint16_t) ((srrctl &
1637 E1000_SRRCTL_BSIZEPKT_MASK) <<
1638 E1000_SRRCTL_BSIZEPKT_SHIFT);
1640 if (dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE
1642 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1643 dev->data->scattered_rx = 1;
1647 * Use BSIZE field of the device RCTL register.
1649 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
1650 rctl_bsize = buf_size;
1651 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1652 dev->data->scattered_rx = 1;
1655 /* Set if packets are dropped when no descriptors available */
1657 srrctl |= E1000_SRRCTL_DROP_EN;
1659 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
1661 /* Enable this RX queue. */
1662 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
1663 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1664 rxdctl &= 0xFFF00000;
1665 rxdctl |= (rxq->pthresh & 0x1F);
1666 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
1667 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
1668 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1672 * Setup BSIZE field of RCTL register, if needed.
1673 * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
1674 * register, since the code above configures the SRRCTL register of
1675 * the RX queue in such a case.
1676 * All configurable sizes are:
1677 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1678 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1679 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1680 * 2048: rctl |= E1000_RCTL_SZ_2048;
1681 * 1024: rctl |= E1000_RCTL_SZ_1024;
1682 * 512: rctl |= E1000_RCTL_SZ_512;
1683 * 256: rctl |= E1000_RCTL_SZ_256;
1685 if (rctl_bsize > 0) {
1686 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
1687 rctl |= E1000_RCTL_SZ_512;
1688 else /* 256 <= buf_size < 512 - use 256 */
1689 rctl |= E1000_RCTL_SZ_256;
1693 * Configure RSS if device configured with multiple RX queues.
1695 if (dev->data->nb_rx_queues > 1)
1696 igb_rss_configure(dev);
1698 igb_rss_disable(dev);
1701 * Setup the Checksum Register.
1702 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1704 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1705 rxcsum |= E1000_RXCSUM_PCSD;
1707 /* Enable both L3/L4 rx checksum offload */
1708 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
1709 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
1711 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
1712 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1714 /* Setup the Receive Control Register. */
1715 if (dev->data->dev_conf.rxmode.hw_strip_crc) {
1716 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1718 /* set STRCRC bit in all queues for Powerville/Springville */
1719 if (hw->mac.type == e1000_i350 || hw->mac.type == e1000_i210) {
1720 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1721 uint32_t dvmolr = E1000_READ_REG(hw,
1723 dvmolr |= E1000_DVMOLR_STRCRC;
1724 E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr);
1728 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1730 /* clear STRCRC bit in all queues for Powerville/Springville */
1731 if (hw->mac.type == e1000_i350 || hw->mac.type == e1000_i210) {
1732 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1733 uint32_t dvmolr = E1000_READ_REG(hw,
1735 dvmolr &= ~E1000_DVMOLR_STRCRC;
1736 E1000_WRITE_REG(hw, E1000_DVMOLR(i), dvmolr);
1741 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1742 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1743 E1000_RCTL_RDMTS_HALF |
1744 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1746 /* Make sure VLAN Filters are off. */
1747 rctl &= ~E1000_RCTL_VFE;
1748 /* Don't store bad packets. */
1749 rctl &= ~E1000_RCTL_SBP;
1751 /* Enable Receives. */
1752 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1755 * Setup the HW Rx Head and Tail Descriptor Pointers.
1756 * This needs to be done after enable.
1758 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1759 rxq = dev->data->rx_queues[i];
1760 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1761 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1767 /*********************************************************************
1769 * Enable transmit unit.
1771 **********************************************************************/
1773 eth_igb_tx_init(struct rte_eth_dev *dev)
1775 struct e1000_hw *hw;
1776 struct igb_tx_queue *txq;
1781 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783 /* Setup the Base and Length of the Tx Descriptor Rings. */
1784 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1786 txq = dev->data->tx_queues[i];
1787 bus_addr = txq->tx_ring_phys_addr;
1789 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1791 sizeof(union e1000_adv_tx_desc));
1792 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1793 (uint32_t)(bus_addr >> 32));
1794 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1796 /* Setup the HW Tx Head and Tail descriptor pointers. */
1797 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1798 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1800 /* Setup Transmit threshold registers. */
1801 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1802 txdctl |= txq->pthresh & 0x1F;
1803 txdctl |= ((txq->hthresh & 0x1F) << 8);
1804 txdctl |= ((txq->wthresh & 0x1F) << 16);
1805 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1806 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1809 /* Program the Transmit Control Register. */
1810 tctl = E1000_READ_REG(hw, E1000_TCTL);
1811 tctl &= ~E1000_TCTL_CT;
1812 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1813 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1815 e1000_config_collision_dist(hw);
1817 /* This write will effectively turn on the transmit unit. */
1818 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1821 /*********************************************************************
1823 * Enable VF receive unit.
1825 **********************************************************************/
1827 eth_igbvf_rx_init(struct rte_eth_dev *dev)
1829 struct e1000_hw *hw;
1830 struct igb_rx_queue *rxq;
1831 struct rte_pktmbuf_pool_private *mbp_priv;
1834 uint16_t rctl_bsize;
1838 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840 /* Configure and enable each RX queue. */
1842 dev->rx_pkt_burst = eth_igb_recv_pkts;
1843 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1847 rxq = dev->data->rx_queues[i];
1849 /* Allocate buffers for descriptor rings and set up queue */
1850 ret = igb_alloc_rx_queue_mbufs(rxq);
1854 bus_addr = rxq->rx_ring_phys_addr;
1855 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1857 sizeof(union e1000_adv_rx_desc));
1858 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1859 (uint32_t)(bus_addr >> 32));
1860 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1862 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1865 * Configure RX buffer size.
1867 mbp_priv = (struct rte_pktmbuf_pool_private *)
1868 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
1869 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
1870 RTE_PKTMBUF_HEADROOM);
1871 if (buf_size >= 1024) {
1873 * Configure the BSIZEPACKET field of the SRRCTL
1874 * register of the queue.
1875 * Value is in 1 KB resolution, from 1 KB to 127 KB.
1876 * If this field is equal to 0b, then RCTL.BSIZE
1877 * determines the RX packet buffer size.
1879 srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
1880 E1000_SRRCTL_BSIZEPKT_MASK);
1881 buf_size = (uint16_t) ((srrctl &
1882 E1000_SRRCTL_BSIZEPKT_MASK) <<
1883 E1000_SRRCTL_BSIZEPKT_SHIFT);
1885 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size){
1886 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1887 dev->data->scattered_rx = 1;
1891 * Use BSIZE field of the device RCTL register.
1893 if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
1894 rctl_bsize = buf_size;
1895 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1896 dev->data->scattered_rx = 1;
1899 /* Set if packets are dropped when no descriptors available */
1901 srrctl |= E1000_SRRCTL_DROP_EN;
1903 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
1905 /* Enable this RX queue. */
1906 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
1907 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1908 rxdctl &= 0xFFF00000;
1909 rxdctl |= (rxq->pthresh & 0x1F);
1910 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
1911 if (hw->mac.type == e1000_82576) {
1913 * Workaround of 82576 VF Erratum
1914 * force set WTHRESH to 1
1915 * to avoid Write-Back not triggered sometimes
1918 PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !\n");
1921 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
1922 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1926 * Setup the HW Rx Head and Tail Descriptor Pointers.
1927 * This needs to be done after enable.
1929 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1930 rxq = dev->data->rx_queues[i];
1931 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1932 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1938 /*********************************************************************
1940 * Enable VF transmit unit.
1942 **********************************************************************/
1944 eth_igbvf_tx_init(struct rte_eth_dev *dev)
1946 struct e1000_hw *hw;
1947 struct igb_tx_queue *txq;
1951 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953 /* Setup the Base and Length of the Tx Descriptor Rings. */
1954 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1957 txq = dev->data->tx_queues[i];
1958 bus_addr = txq->tx_ring_phys_addr;
1959 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1961 sizeof(union e1000_adv_tx_desc));
1962 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1963 (uint32_t)(bus_addr >> 32));
1964 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1966 /* Setup the HW Tx Head and Tail descriptor pointers. */
1967 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1968 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1970 /* Setup Transmit threshold registers. */
1971 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1972 txdctl |= txq->pthresh & 0x1F;
1973 txdctl |= ((txq->hthresh & 0x1F) << 8);
1974 if (hw->mac.type == e1000_82576) {
1976 * Workaround of 82576 VF Erratum
1977 * force set WTHRESH to 1
1978 * to avoid Write-Back not triggered sometimes
1981 PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !\n");
1984 txdctl |= ((txq->wthresh & 0x1F) << 16);
1985 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1986 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);