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39 #include <rte_mempool.h>
40 #include <rte_malloc.h>
41 #include <rte_spinlock.h>
42 #include "fm10k_logs.h"
43 #include "base/fm10k_type.h"
45 /* descriptor ring base addresses must be aligned to the following */
46 #define FM10K_ALIGN_RX_DESC 128
47 #define FM10K_ALIGN_TX_DESC 128
49 /* The maximum packet size that FM10K supports */
50 #define FM10K_MAX_PKT_SIZE (15 * 1024)
52 /* Minimum size of RX buffer FM10K supported */
53 #define FM10K_MIN_RX_BUF_SIZE 256
55 /* The maximum of SRIOV VFs per port supported */
56 #define FM10K_MAX_VF_NUM 64
58 /* number of descriptors must be a multiple of the following */
59 #define FM10K_MULT_RX_DESC FM10K_REQ_RX_DESCRIPTOR_MULTIPLE
60 #define FM10K_MULT_TX_DESC FM10K_REQ_TX_DESCRIPTOR_MULTIPLE
62 /* maximum size of descriptor rings */
63 #define FM10K_MAX_RX_RING_SZ (512 * 1024)
64 #define FM10K_MAX_TX_RING_SZ (512 * 1024)
66 /* minimum and maximum number of descriptors in a ring */
67 #define FM10K_MIN_RX_DESC 32
68 #define FM10K_MIN_TX_DESC 32
69 #define FM10K_MAX_RX_DESC (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))
70 #define FM10K_MAX_TX_DESC (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))
73 * byte aligment for HW RX data buffer
74 * Datasheet requires RX buffer addresses shall either be 512-byte aligned or
75 * be 8-byte aligned but without crossing host memory pages (4KB alignment
76 * boundaries). Satisfy first option.
78 #define FM10K_RX_DATABUF_ALIGN 512
81 * threshold default, min, max, and divisor constraints
82 * the configured values must satisfy the following:
86 #define FM10K_RX_FREE_THRESH_DEFAULT(rxq) 32
87 #define FM10K_RX_FREE_THRESH_MIN(rxq) 1
88 #define FM10K_RX_FREE_THRESH_MAX(rxq) ((rxq)->nb_desc - 1)
89 #define FM10K_RX_FREE_THRESH_DIV(rxq) ((rxq)->nb_desc)
91 #define FM10K_TX_FREE_THRESH_DEFAULT(txq) 32
92 #define FM10K_TX_FREE_THRESH_MIN(txq) 1
93 #define FM10K_TX_FREE_THRESH_MAX(txq) ((txq)->nb_desc - 3)
94 #define FM10K_TX_FREE_THRESH_DIV(txq) 0
96 #define FM10K_DEFAULT_RX_PTHRESH 8
97 #define FM10K_DEFAULT_RX_HTHRESH 8
98 #define FM10K_DEFAULT_RX_WTHRESH 0
100 #define FM10K_DEFAULT_TX_PTHRESH 32
101 #define FM10K_DEFAULT_TX_HTHRESH 0
102 #define FM10K_DEFAULT_TX_WTHRESH 0
104 #define FM10K_TX_RS_THRESH_DEFAULT(txq) 32
105 #define FM10K_TX_RS_THRESH_MIN(txq) 1
106 #define FM10K_TX_RS_THRESH_MAX(txq) \
107 RTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)
108 #define FM10K_TX_RS_THRESH_DIV(txq) ((txq)->nb_desc)
110 #define FM10K_VLAN_TAG_SIZE 4
112 struct fm10k_dev_info {
113 volatile uint32_t enable;
114 volatile uint32_t glort;
115 /* Protect the mailbox to avoid race condition */
116 rte_spinlock_t mbx_lock;
120 * Structure to store private data for each driver instance.
122 struct fm10k_adapter {
124 struct fm10k_hw_stats stats;
125 struct fm10k_dev_info info;
128 #define FM10K_DEV_PRIVATE_TO_HW(adapter) \
129 (&((struct fm10k_adapter *)adapter)->hw)
131 #define FM10K_DEV_PRIVATE_TO_STATS(adapter) \
132 (&((struct fm10k_adapter *)adapter)->stats)
134 #define FM10K_DEV_PRIVATE_TO_INFO(adapter) \
135 (&((struct fm10k_adapter *)adapter)->info)
137 #define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \
138 (&(((struct fm10k_adapter *)adapter)->info.mbx_lock))
140 struct fm10k_rx_queue {
141 struct rte_mempool *mp;
142 struct rte_mbuf **sw_ring;
143 volatile union fm10k_rx_desc *hw_ring;
144 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
145 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
146 uint64_t hw_ring_phys_addr;
149 uint16_t next_trigger;
150 uint16_t alloc_thresh;
151 volatile uint32_t *tail_ptr;
156 uint8_t rx_deferred_start; /**< don't start this queue in dev start. */
160 * a FIFO is used to track which descriptors have their RS bit set for Tx
161 * queues which are configured to allow multiple descriptors per packet
170 struct fm10k_tx_queue {
171 struct rte_mbuf **sw_ring;
172 struct fm10k_tx_desc *hw_ring;
173 uint64_t hw_ring_phys_addr;
174 struct fifo rs_tracker;
179 uint16_t free_trigger;
180 uint16_t free_thresh;
182 volatile uint32_t *tail_ptr;
185 uint8_t tx_deferred_start; /** < don't start this queue in dev start. */
189 #define MBUF_DMA_ADDR(mb) \
190 ((uint64_t) ((mb)->buf_physaddr + (mb)->data_off))
192 /* enforce 512B alignment on default Rx DMA addresses */
193 #define MBUF_DMA_ADDR_DEFAULT(mb) \
194 ((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM), 512))
196 static inline void fifo_reset(struct fifo *fifo, uint32_t len)
198 fifo->head = fifo->tail = fifo->list;
199 fifo->endp = fifo->list + len;
202 static inline void fifo_insert(struct fifo *fifo, uint16_t val)
205 if (++fifo->head == fifo->endp)
206 fifo->head = fifo->list;
209 /* do not worry about list being empty since we only check it once we know
210 * we have used enough descriptors to set the RS bit at least once */
211 static inline uint16_t fifo_peek(struct fifo *fifo)
216 static inline uint16_t fifo_remove(struct fifo *fifo)
220 if (++fifo->tail == fifo->endp)
221 fifo->tail = fifo->list;